我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 _$ u6 u# _7 F. c# b5 z2 T
input mcasp_ahclkx, |4 u; @6 h D
input mcasp_aclkx,
$ @% p" C7 w; u. A- F( Qinput axr0,1 ~( O0 w: ~( [! \$ X" C c5 a* }9 h
6 D& A" V* U3 c6 ]9 G/ ]6 s: J B5 Goutput mcasp_afsr,. _' l* M0 h/ Y
output mcasp_ahclkr,
( ?1 w4 u+ }* Loutput mcasp_aclkr,
8 g% u0 L* p( R7 v- T0 P" Routput axr1,* A& O. J$ G; u- \
assign mcasp_afsr = mcasp_afsx;
- f \; c4 R* k, g+ \' tassign mcasp_aclkr = mcasp_aclkx;6 ~: K/ w8 S# z+ z% e
assign mcasp_ahclkr = mcasp_ahclkx;' N* n8 }: A- p. O+ X4 s) _
assign axr1 = axr0;
8 @; I$ G/ k4 J" J
( o4 P% L; u' Y& P! ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 j9 K9 M6 v: h
static void McASPI2SConfigure(void)
" W5 K- E o2 N& p9 S{
1 V: X0 \( N2 X; b- e- ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 |5 I8 E# a( B/ z3 Y' X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% z3 V" U0 ?: G; n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 x' J5 r0 t" D$ H: E2 J O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: e+ W0 c, @2 {5 w0 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," y& z. L+ D$ n: F j
MCASP_RX_MODE_DMA);
2 }0 J4 U6 G4 ?: q6 ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( _6 `6 n6 N% l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* s- K! X; Y( w. F6 k0 ?' z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
\9 |! m' S# j" i9 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* R/ Z+ B z$ O1 l! Y4 P9 N; p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 U$ `5 }8 V: o4 F4 S1 D2 C; _4 uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' i5 Z" R3 F K2 ~$ h# N9 z* L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( O' w- ]8 A0 U4 q1 V" ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, H; M# R2 \# k5 a. J2 bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 \- A ]9 Z4 G
0x00, 0xFF); /* configure the clock for transmitter */
( ~; Y* w$ B) mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, H& c( e5 A' rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ R/ j' }( b8 y( v: EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 \) |" P- l* s/ Y7 E" r
0x00, 0xFF);
) O( `* U( H" U/ O, E$ ?
% ~. B7 y- a' [9 m% W; _9 v) m( A/* Enable synchronization of RX and TX sections */ ; R1 q f+ \' M* {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 S! ]4 h5 G* gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 T2 H4 g# R/ _3 N+ zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% x. V3 U y* D- n( I$ S** Set the serializers, Currently only one serializer is set as
1 m, R- }; U% F# m: P# E0 F# s9 _** transmitter and one serializer as receiver.) I0 d, k- L8 s( {# N& r6 g
*/
; s) x$ Y. L0 X3 HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 b% v% _) k2 G, ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 C* }% B- K8 I
** Configure the McASP pins 8 d8 G7 @' \. g. o0 g8 Q1 m
** Input - Frame Sync, Clock and Serializer Rx
0 f" g( @/ U1 n** Output - Serializer Tx is connected to the input of the codec . m+ e; h7 B' h( R, _5 s3 d4 }1 g+ J) N
*/, M6 p4 A8 i% ~: q" J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( k7 K. X- j; ^. s8 r! W& Y9 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 ]# _8 g0 n/ I% {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& R( r( s! k! f7 `
| MCASP_PIN_ACLKX
1 V7 D; Y4 {* f( j" w( x| MCASP_PIN_AHCLKX
8 r) i+ l4 P) I/ A8 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, _' f8 h3 L2 o/ NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 }8 N" s. K2 D# h
| MCASP_TX_CLKFAIL , a# L9 t9 t' T+ D+ G
| MCASP_TX_SYNCERROR7 V( \. F, E) |* `" G& R8 x" h- R" E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 N/ d6 j, \) s2 n7 C| MCASP_RX_CLKFAIL
) e- ^% k$ E, c4 L x| MCASP_RX_SYNCERROR , V( i. c1 j6 n$ v
| MCASP_RX_OVERRUN);
- U+ V1 {$ z: b5 Q. |} static void I2SDataTxRxActivate(void)
' R% v1 ^9 a* y- e{
* D" h2 W2 A5 F# o0 c+ U( e# ]9 r' ~/* Start the clocks */% m* B3 [$ P) _7 [" N! S1 w. D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 f* K, X* @! v' N7 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, C/ q, r6 m: t* z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ w* f' H1 A; r M: ]- E
EDMA3_TRIG_MODE_EVENT);
4 O! o- L% ]! D" q; ]* n( }9 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + l8 C8 f& R$ R* L. |$ t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 s$ t3 Z; v4 O& h( oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) ^6 w- j+ Z" e' u! g6 w0 Q4 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! {9 ]% I/ p$ [6 s- u$ r$ W, Z: m( k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
o* y8 o, n$ i* n. g, [% E! HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 C; g% ]# b4 ~5 P5 gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! s8 a/ h! z2 A; v7 l
}
+ w) K! E+ X# {0 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 s" ~8 ?- m, N" W- s0 h |