我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; x4 s( B+ p8 V6 v$ K& o, Zinput mcasp_ahclkx,5 ^! ~, U/ Q1 O
input mcasp_aclkx,* R# N, V1 E. x2 X, C7 p0 m
input axr0,
; k+ f( e0 u6 X
. I) _' m3 x4 b0 Coutput mcasp_afsr,. @8 p4 H7 y% g4 P1 H
output mcasp_ahclkr,
, ~! {7 X( s& X r& i4 d7 k: joutput mcasp_aclkr,; X ?* Y4 l7 b5 q- A+ o" X
output axr1,
$ d& C, k: p# e# v2 d assign mcasp_afsr = mcasp_afsx;" F: A' W. ~# n
assign mcasp_aclkr = mcasp_aclkx;
, t* a* @. H7 H* X& H# ?- J1 `assign mcasp_ahclkr = mcasp_ahclkx;
W5 |3 [1 I3 x$ A1 u: r8 Bassign axr1 = axr0; 5 I: v# A% _8 ?# Y; b8 g, A) j
, ~0 k7 `9 z- |. S) H4 P, ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & @3 U# r4 ~ K9 g6 m" N. \$ {, S
static void McASPI2SConfigure(void)$ g# d3 m5 o7 _$ A4 j0 M
{ [) r$ k; g9 I' o6 d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' x, u0 D- X% |8 @ v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 C3 E5 g% r) C5 U; @- q Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" G2 D" i# A+ N# _6 M BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 i1 d- x, [$ T0 N' d; Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ L P$ F1 p" x6 C" `( w1 [
MCASP_RX_MODE_DMA); W# l1 R. r* J7 F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ u2 j4 ]' \6 d; p2 H EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 F; z) E. |$ ~( F) m- k; o* d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 V8 s- s) Z9 x3 f) |# w3 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); L; H; {* t$ M: M6 ?3 h, @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ h: E" h: P- S# J0 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* M+ R+ ?* T) y# a% K" \, e4 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 k* v& I& {1 Q8 S0 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 W+ M% ~/ T+ g( u' U6 M5 r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ b/ d$ s6 P3 Z. c) t0x00, 0xFF); /* configure the clock for transmitter */; P2 C+ p+ T, @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ R" \4 n0 ?1 j4 O) M3 h# C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; j) {- M: q. ]1 j" `" TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: s& o! c! ^" a0 ?& T3 c9 v+ n
0x00, 0xFF);- w1 W- h: `' Z. m. x
1 ?" Y4 E( @$ X/* Enable synchronization of RX and TX sections */ ! z) a/ x* l6 g* Z+ K! z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& W. H0 d! ~4 R4 r" l& z* yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 C" l$ |; x+ y! b& }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( Q L/ J/ N2 I' Y5 f$ l** Set the serializers, Currently only one serializer is set as1 q+ ?# J% a8 E& c! G7 ~$ y
** transmitter and one serializer as receiver.
' n z" X6 g- I2 ?5 _( L+ u*// g; X5 T* n+ Q; H' r1 G7 i' I, z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 `* K0 ^+ U! R9 [$ `6 U0 h. C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# f C/ Y5 g, I! O6 C** Configure the McASP pins . m, @" H9 \) j6 i
** Input - Frame Sync, Clock and Serializer Rx
* e( e7 s' D+ a; R0 Y** Output - Serializer Tx is connected to the input of the codec ( B8 {9 J) `" z. O) t
*/
: `* c0 X9 q* H: iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 x% S' q5 n/ h# P% |/ LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, j' x/ ~; y; j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 {9 d+ W, T$ f/ j9 g& m5 ]
| MCASP_PIN_ACLKX9 P0 A* G2 }- [' D1 s8 w
| MCASP_PIN_AHCLKX
/ T4 p2 V( }4 C4 o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ B2 |0 P0 Y( W& }4 W) jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 Y5 i7 q5 h5 w+ s5 I% x( ~5 D5 W| MCASP_TX_CLKFAIL
0 p5 d, |2 R& {/ W9 L9 _' h| MCASP_TX_SYNCERROR, e' n9 L0 ]5 B6 P+ C, [2 n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 Q9 \' p! g' X; K+ A| MCASP_RX_CLKFAIL
! L( ^. P/ k5 `* ~4 B* G2 w| MCASP_RX_SYNCERROR , s/ y! d) ]. W& e- W" O
| MCASP_RX_OVERRUN);: k7 P2 C. V; `. Q7 V
} static void I2SDataTxRxActivate(void)
8 J* C. k* ^4 F+ z/ d3 Y9 S{- T* a; m$ U8 N$ x8 g( Q
/* Start the clocks */; s3 @& P2 J( [4 E; b" T! ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. m$ I9 P+ D5 L& g8 o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, H7 E4 r" X# JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- O( Z n" q0 F. S
EDMA3_TRIG_MODE_EVENT);6 o' O) \1 T# g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % w4 X" [, a$ n2 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ e. o5 [0 p8 g3 g* g) @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 J- q4 J [8 x& E# P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 D8 P0 @9 t/ |7 u7 {$ z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- K. N$ Y) @" }8 y! aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 M r( G1 T( W0 P( D) S4 T# h& h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. S1 K1 N2 v/ ~6 u, Q) I
} 6 J4 Y* z% l( |6 S9 s/ S3 I5 f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) V' l: {5 L: _* d: F+ i
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