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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ v8 M* w( D' ~: T
input mcasp_ahclkx,
) e2 t( R# h$ k. S) Dinput mcasp_aclkx,
! r' Q0 _4 o/ f( O1 \input axr0,4 k1 |; q) G# y. h9 b; l! ]/ `8 \
$ U3 I O) Q8 p/ {2 k% foutput mcasp_afsr,5 d$ `" ~, M% W
output mcasp_ahclkr,
. u$ l0 R3 v8 W) r4 w' \/ ?; e) boutput mcasp_aclkr,* D& t- x7 S; B4 x5 ]9 g4 ^* @' u
output axr1,' [% o% n/ t( k/ r2 p. C
assign mcasp_afsr = mcasp_afsx;; v3 e2 g) c4 {8 `
assign mcasp_aclkr = mcasp_aclkx;) T J- S8 }' x6 l5 @# d! k
assign mcasp_ahclkr = mcasp_ahclkx;! p0 C7 r4 P" t0 u5 Z
assign axr1 = axr0;
% O4 e. h$ D* ?
. i/ E8 Z% O1 z: {+ ^/ Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, m0 M& p) {- f: Z- |! \* W/ o! estatic void McASPI2SConfigure(void)
5 ~8 t& g" \9 P8 k! {% x: K- A. S{, z6 I; u/ i; p4 j, T4 B7 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. T, q0 @7 W/ s4 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: f, U6 |+ B( _* ^8 A5 `) F7 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 k1 n; n& u. v0 f5 V! i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( B' A8 `5 W& F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ Q- O& n2 i/ t" n' U
MCASP_RX_MODE_DMA);
1 q# u$ ?4 h7 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- e5 V! j- t0 m% N" d+ FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, j u1 I2 A- H, a- M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% J- p. ?" z# W! P5 U2 K; QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 ~# a) E) x6 e3 @. R- IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % t9 F S! }4 h: P2 Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# t# I% L3 K8 Z4 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 J# q% R0 E# w7 l6 yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 W5 Q* d& c( hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ z" e3 h5 V4 W" ~3 i, J0x00, 0xFF); /* configure the clock for transmitter */6 R2 u, ]4 l% m& Q+ T5 i$ z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; A" L! K7 t. t1 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 F8 f1 J* r7 W2 M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& ~# r0 F6 e! b) o, s# s0x00, 0xFF);
! y1 b( P0 m; P1 h3 }) Q8 u+ b" Q5 j# A9 C1 \
/* Enable synchronization of RX and TX sections */
# O# {) J7 E- ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: l1 b3 ?- E0 }" NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( {7 T) l5 }$ J: Z+ o. r+ X+ CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 s' G! X4 O! E/ C7 W** Set the serializers, Currently only one serializer is set as
4 e8 s7 Q' b! L4 X Z4 O** transmitter and one serializer as receiver.
! q; ~" ]- i1 a7 O( B*/
- x2 T' F* n/ Q4 V, u4 J7 T9 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& Y" i8 ^6 [/ O( e1 e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 W/ x7 S) ?8 f9 i+ J5 b
** Configure the McASP pins
! h2 ]0 {. y" _ ]1 F, X* r8 `** Input - Frame Sync, Clock and Serializer Rx2 _2 w4 d3 N; F0 n0 y
** Output - Serializer Tx is connected to the input of the codec 3 w5 V/ B/ K4 f( m9 R
*/
' b! S& H5 m4 Z& ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 t! U/ ^! R9 K$ `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); j5 e# w1 _# f4 M9 f4 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 I( V5 `* R! F| MCASP_PIN_ACLKX
) K/ X+ P q5 u| MCASP_PIN_AHCLKX
2 b' I5 `8 E5 \$ c& G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; c# M+ z+ [% G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 C) L4 t( f' o0 g) B9 D| MCASP_TX_CLKFAIL 7 W+ u: c7 H. s% s* r4 G$ W) b
| MCASP_TX_SYNCERROR
' v; G7 Q9 m+ i! F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 R) i$ A; J% Z| MCASP_RX_CLKFAIL
8 J# R, T3 I1 ~| MCASP_RX_SYNCERROR
0 L# @9 G3 N5 ~6 e) q% G| MCASP_RX_OVERRUN);/ T8 ?3 v) V' a! z7 x
} static void I2SDataTxRxActivate(void)
3 K; a F2 [& p. ]( P/ Z/ a( W, K{ e4 u; M& I3 C# }+ ~. ^
/* Start the clocks */
x" [; n1 z- o' E8 Q+ mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 M2 y% S6 r* o6 I) C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 F* N" B7 g+ `" i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( J+ M! D8 Z* N* n8 ]
EDMA3_TRIG_MODE_EVENT);
( F8 z) d9 Z4 \8 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 [, e, e$ E! k& mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) o, H( B' `% R$ UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; K* W5 Q) @* A }- u6 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" D* {0 ?& K) n( B; N9 F- O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. o# i! F* ]1 C6 V: y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ N$ R& x- ]7 ~) ]) y9 t) A& }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 T* i8 M' _1 e1 e. j' N6 t: B6 M
}
2 A2 }9 t S- E2 g( y/ M7 L! _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; o1 s" w- Q2 v% c
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