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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 _2 b- h) a) M3 |" A7 j
input mcasp_ahclkx,
( v- c" Q. b. [5 Einput mcasp_aclkx,# ~4 v; c) i1 m: c2 @' D
input axr0,
4 N, A% R. Q" R# }2 E/ m" m
7 a- h; @: `; t3 Voutput mcasp_afsr,
7 i* `: Y- F; v% Youtput mcasp_ahclkr,- j. x( X/ L& X/ t/ j( b- h9 v( r
output mcasp_aclkr,
" t/ A T- @; ` _output axr1,: b2 I, A! q3 ^& O
assign mcasp_afsr = mcasp_afsx;% J9 q; w) I: d7 k
assign mcasp_aclkr = mcasp_aclkx;! a( c3 J7 o) `, G2 l6 t3 P p
assign mcasp_ahclkr = mcasp_ahclkx;! i" s& Y' k2 |) c( R. {1 v" W
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 S* p# e. v; `+ o. c+ p! istatic void McASPI2SConfigure(void)6 Y* f Q. Q+ m3 M
{# A- S3 \6 M) r) e! `/ y' i# E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' l5 f. q8 Q) N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( a5 Q# B( v' X' t) O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& A" g3 a; [& R0 T1 l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 N f; ^: l6 e* Q0 Z. `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. x' H! n$ ~5 L' G' dMCASP_RX_MODE_DMA);$ E: ^( O; Y2 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. I# _' \3 G# r6 _# J$ m, B' [3 hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ s" D& w& Q G6 B/ y. eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; N$ E9 S0 A* @" i- vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& l" p' Z6 h$ P. O, k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " N6 m$ |. ?- n! j) j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% V: F2 ]- k% v& w( y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 y4 l V3 @ T4 b: HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 _" _* e: K# ~1 C6 o: TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- y5 G- a- n5 ^) ?& s1 p1 `: _- \/ m( h
0x00, 0xFF); /* configure the clock for transmitter */# B/ C- q( I; x j% m9 k! k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: ]3 n% n; S' h- Z9 g7 k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ n/ l7 J. J# ?' n( l/ IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ X; a' S E8 r5 E8 A q9 Y6 [
0x00, 0xFF);! @% s3 m% K0 t/ c- r
$ ?: L- V3 I/ ?; H" K/* Enable synchronization of RX and TX sections */ / z7 E$ v9 g2 J# S1 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; Y7 e/ ^5 ^. ]& X% ] AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 N% l. `/ s7 W7 u5 J; ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- X2 r. c7 L2 d6 |! E- X1 _** Set the serializers, Currently only one serializer is set as
* o/ N" A1 Z: w3 I7 Q** transmitter and one serializer as receiver.# `; {' @5 `+ T7 w, D
*/$ h/ H9 Q2 K% C. ]; S$ }* c2 E, t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; e& ^; b, |6 p; ^2 w6 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% j) ^# t |4 y3 Y% d% `* U** Configure the McASP pins 6 u; N S, u) F/ q6 b% j
** Input - Frame Sync, Clock and Serializer Rx
" Z4 ?! L7 X0 o** Output - Serializer Tx is connected to the input of the codec % u1 R+ ^4 E# W3 _4 @. }- Q7 J% l
*/4 Z5 }% Y. x# f/ ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* J/ I7 I- u, q, h6 m0 v6 tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% M( O7 b% r5 h5 ~9 E* M; YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 N o, g. y6 j5 x: h& i
| MCASP_PIN_ACLKX% l1 f( b2 {1 N! Q8 c
| MCASP_PIN_AHCLKX
( v8 f' y9 x, E( b7 Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- w3 G, E2 x% l6 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ ~, c( l3 k9 ~
| MCASP_TX_CLKFAIL 3 G4 k$ M2 |2 u, R' I
| MCASP_TX_SYNCERROR7 N" c2 T! a4 Q8 J( ^! S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , r8 |3 U* L$ E
| MCASP_RX_CLKFAIL$ F p) ~ T# Q7 K Q
| MCASP_RX_SYNCERROR
* v' L) `! X) i| MCASP_RX_OVERRUN);
( M/ o( W0 N( a2 z: v) H/ ~} static void I2SDataTxRxActivate(void)' T; x2 _4 F. M2 V( @ \
{6 X. X: _$ u6 g" U5 E/ t& r$ j9 J' @
/* Start the clocks */% N2 l+ F( f* h3 q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 X" L7 }& W4 H. Y' i1 i; h- ?0 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 X" D6 E# P1 g, |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 L& H! i8 M( i/ E& S- N. |% hEDMA3_TRIG_MODE_EVENT);4 Z/ I( O2 T3 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 { s1 s# a: \2 I7 |& @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" G: Q& f+ h, v: ?$ h9 ]) t, VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 ?0 A* w; Q$ p+ ^) J0 E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( x( l: p; @$ ]" h- gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ ?4 \; l6 T# x$ I. v k8 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 V* `9 y: L/ v2 G' e, XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, t$ j0 i5 f+ s} * J1 d# [5 Z9 C B T' s' c+ [# s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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