|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% `5 `7 K2 B( X6 p# {- A4 {
input mcasp_ahclkx,
* \' @0 W$ k- i6 I0 kinput mcasp_aclkx,: @. {" v5 j6 A+ \ g+ l
input axr0,
" q8 ~( _$ g2 P+ a( ?
6 d0 `9 Y( N8 q6 }: w% [1 c5 doutput mcasp_afsr,) h& h7 ~$ E( n$ ], E Q* g) M" l
output mcasp_ahclkr,
% V. h+ e/ Y" e- n3 voutput mcasp_aclkr,
% L Z2 p( d& }7 j! B- ooutput axr1,
+ `* y& \2 M& ^2 T assign mcasp_afsr = mcasp_afsx;( j4 j0 U9 G% _
assign mcasp_aclkr = mcasp_aclkx;, N: S7 u9 _1 M1 C2 s
assign mcasp_ahclkr = mcasp_ahclkx;. ?" |: ]8 L, a, ?, J7 L
assign axr1 = axr0;
5 o6 a, H7 N0 k# `
0 X6 T% [% r0 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; b5 b; W9 ?7 U4 v f% v; |
static void McASPI2SConfigure(void)0 J- a% G9 J% E0 o5 N
{
0 m6 }4 m! d2 r, rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 \6 Y9 Y7 {5 U! d. t, i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 C# s& D' i: d/ @' u2 GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) z2 e0 J$ Q' x7 q: ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- ~1 T: m- T2 H2 w. @: w( G0 ~- i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 f0 ]1 r( P+ }' m' LMCASP_RX_MODE_DMA);& i" T# n# z' Y, Z, B, s3 B7 ]0 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: N8 F3 Q- W4 A) aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: ]4 [; |/ V( |$ z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 @; t% {3 K: q2 d" g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( c/ t0 N1 ~7 D% r1 _* n! ?: ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 i. \, x" Q5 K( P9 U: P5 A! EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ ^" V2 `$ q8 A. N# I% ]/ `1 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ Y7 s" a1 G# K/ R5 h! c0 O1 TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 E3 n# d$ Q. E0 S6 {2 B- lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 W; {: ]0 r: e7 X: u
0x00, 0xFF); /* configure the clock for transmitter */
+ a$ R2 T. H ?1 `! uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# H% F- E4 j8 M+ ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 g8 @" A$ Y4 P' Q1 T4 Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( }! z* T f4 a: P+ v! G# \& l0x00, 0xFF);
, E9 S/ g$ H+ k8 E5 T# ~0 l% R3 |5 [3 @0 E- C4 t# r
/* Enable synchronization of RX and TX sections */ # ?) ?8 K' e8 L$ [/ y6 E9 O- _& L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 z3 I) D: [0 I/ ^1 N* CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' S) y9 u) n; Q5 }( d6 mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. a. ]0 r( R- M, r/ e- p g
** Set the serializers, Currently only one serializer is set as$ K* h/ c8 F+ ?0 T
** transmitter and one serializer as receiver.8 u7 D0 t+ F1 h' {$ t; |+ B$ Y0 i
*/6 s/ K* d* ^3 J, }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' u6 l P; B+ T8 X7 I3 q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, \8 k2 H1 A0 v1 w** Configure the McASP pins ( q/ j* S) k; { a- l! Z* [! ?
** Input - Frame Sync, Clock and Serializer Rx
; l6 W# n) N2 X5 u3 u6 N** Output - Serializer Tx is connected to the input of the codec ' w; L& d3 b% L
*/
& [! ?& [, h+ g$ uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); |- c$ v- H" R! j. o5 q' s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) B) ~7 R/ D/ a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 @/ g$ u% T9 p' G: d| MCASP_PIN_ACLKX9 q6 U% B& l9 M3 q
| MCASP_PIN_AHCLKX* z, W( u5 I$ b4 g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" E* E \% n1 tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# A1 @4 V- u- A6 x; B| MCASP_TX_CLKFAIL
% W6 a7 n% A8 R| MCASP_TX_SYNCERROR
% d( {& |- W( ?. \; T+ _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% ~1 c. I4 j, h1 r9 J% R7 t. T| MCASP_RX_CLKFAIL
$ ^6 C* x' W" F: [1 C" c| MCASP_RX_SYNCERROR ( e) q. l9 K) h: W* a
| MCASP_RX_OVERRUN);
/ [3 t1 ^3 l1 Z1 X1 \& _0 E} static void I2SDataTxRxActivate(void)+ f. y: L# M$ j' j* v: Q/ W
{
) G/ }3 e5 s; N8 q/* Start the clocks */6 y$ r K, J' L8 L% L) ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 d6 h, @" Q. G# i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 |# y! a S$ W4 |9 d8 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. N* J* U: |* e9 a& D K. A7 k
EDMA3_TRIG_MODE_EVENT);/ E6 O% k+ ~! z G! N, }1 w( J6 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" ]) `$ s+ C8 s( T+ K6 k1 ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 z. M) \1 J1 M* \! V( w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) M$ n4 Y# j2 p# j# c/ d" QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 v/ |! ]$ _3 p. r7 l" h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% L R' w* g' F4 y) h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 U7 [: m2 e/ Y3 h( u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) b. T; R* v, W4 }: w3 p( k
} ( h( ^& A: i* Y/ ^& a3 N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- n) k5 q6 {" c: w9 n |