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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, F2 [. v# s. u* Q5 ^8 C) F$ T w
input mcasp_ahclkx,4 p3 {1 p. b3 G- L* m" w
input mcasp_aclkx,
9 C) N. m8 [6 v7 R9 dinput axr0,$ O; {3 |- e% L
# u5 r0 U3 N! V, F6 `output mcasp_afsr,! M$ Q" j$ g: t q7 V' t; q, g/ C
output mcasp_ahclkr,
& I2 r6 s# ?9 q( youtput mcasp_aclkr,
9 U- X1 z/ i9 [/ f6 Y' C) poutput axr1,$ S& X: f6 s4 M* B
assign mcasp_afsr = mcasp_afsx;
( g# |1 I x* J+ Nassign mcasp_aclkr = mcasp_aclkx;3 s( H1 B' w4 D7 L+ }: Q
assign mcasp_ahclkr = mcasp_ahclkx;
2 T% e# M Q! f( n3 S; d2 ?4 hassign axr1 = axr0; ) |, g+ v' C- y' n0 h9 o/ t/ O3 R
3 f$ x6 Z. v5 q8 Y+ Y4 x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 E b) i7 g0 g' |3 y& M L+ t
static void McASPI2SConfigure(void)7 a: h, z( e2 Y" g" G* R+ i
{
/ d% H1 I2 S; h' n& z" O% Q5 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, {; O/ [) Y2 I, b7 UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- F7 ]$ W& x' K( _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 n( l0 E/ u# U* n; Y6 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ F. P* c2 o# U# {* Y; F7 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* D5 z$ h/ C1 x3 a
MCASP_RX_MODE_DMA);4 t' j6 d M, p4 n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- h1 r" D5 A% p- G' F4 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 k$ f0 p/ N* NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 G# ?: I+ H1 g2 P% b" ^1 Q/ u2 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ x7 X. {% c+ y( V" \3 HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' `5 `0 ~6 t* q9 @( F" x; N8 IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// g; L/ a! E* n& r7 g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& L \2 \0 s t2 X) | mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 J" E! m+ `/ H& R2 i: e( p; q3 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 |+ j1 V3 C/ b3 i1 S0x00, 0xFF); /* configure the clock for transmitter */# R+ o- l& ?1 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ @) O* @+ j# J5 F/ \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + ^7 z9 P! x; X! T7 U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ t2 o9 O w" m
0x00, 0xFF);
! X# N: a P m6 _( I
. A& t* {0 H& ?7 R/* Enable synchronization of RX and TX sections */
; M4 p" n2 s0 l! J- z* WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ M2 s1 p/ X) d& jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& f% u& ^0 {* A' QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 @. p$ N# i- H/ E; L7 a
** Set the serializers, Currently only one serializer is set as
x' t! K) y* k7 e3 O** transmitter and one serializer as receiver.. ]4 N' p! {, |' g) G1 P. p6 o
*/
* {3 |0 `3 \3 y! d, kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- j/ `6 Q: e0 ?7 l5 s6 g" u0 Q+ PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 P8 n% y9 i3 n
** Configure the McASP pins \( R) T+ p9 j
** Input - Frame Sync, Clock and Serializer Rx
. x5 x( @2 |: V1 S! M** Output - Serializer Tx is connected to the input of the codec
- a* R% A: L: r3 L& m8 v*// T. x+ L" @/ I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ ~7 @5 f! t/ u0 p0 p- j2 z/ u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 s( a8 g+ `% c7 }" ~- B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( o" z3 b9 d4 f. w4 H' o' Q% S || MCASP_PIN_ACLKX
) J3 U a- D# v) \+ `* u| MCASP_PIN_AHCLKX
5 F0 Z. H. p. `9 I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 j5 L5 j( _3 K' ^) P: {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # H1 T' f# Y, g9 p
| MCASP_TX_CLKFAIL 2 m2 V* v c9 z1 ?; a
| MCASP_TX_SYNCERROR# y( ?* _1 F/ b7 V" K2 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - }: l# ^) \7 E/ B' j( m2 P* j
| MCASP_RX_CLKFAIL d. s0 a6 C- ?+ v0 |- i
| MCASP_RX_SYNCERROR
; Y' P0 u' x) U7 b1 t6 c| MCASP_RX_OVERRUN);
$ k- m3 u5 E3 Q* [+ ?} static void I2SDataTxRxActivate(void)$ H& `. D% Y8 a6 L/ s2 `! p7 l
{# D. Q9 @! Y3 n$ o& K
/* Start the clocks */% }& M3 Z2 O; O5 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% V& S! h! U( u) H% u! iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* C) }5 y: p0 \4 J; L' p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," b" k# R+ [( O* Z% j4 }5 H
EDMA3_TRIG_MODE_EVENT);
% Q0 S& a- N4 \7 @, IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 R; B7 t8 c. _. UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 n7 @" f. b1 A* y% A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- @' A! I8 d, Y4 u& P9 C( w$ l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& D5 M6 ] G5 c. I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 m- B+ g) Z! i+ _5 J0 c7 T6 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% a5 V; D- _8 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* ?% B" a* X; i I8 G( t
}
F$ k/ Z2 }2 A4 n5 e7 P6 e$ A, v% O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 A! L6 P+ u2 W( u7 B, j' e( \$ g
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