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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ I, h8 c) \0 D `# f8 k+ [$ X
input mcasp_ahclkx,
, w" \8 G* f+ g7 T6 uinput mcasp_aclkx,4 y) T4 g) w" f( A8 e# R
input axr0,/ d/ {4 H* R; R7 v) a
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output mcasp_afsr,& g9 }8 O& ]. o2 p& z- G
output mcasp_ahclkr,. U, _3 F3 A, X3 B5 F
output mcasp_aclkr,2 H# u; |* b/ F
output axr1,
+ e' S* J& N+ `; {4 J$ ~( B assign mcasp_afsr = mcasp_afsx;' w* T' p k. J
assign mcasp_aclkr = mcasp_aclkx;
1 s6 s7 G- s) L- P0 G. d! T: Wassign mcasp_ahclkr = mcasp_ahclkx; Z8 l1 u; K( c+ X
assign axr1 = axr0; ' r0 ?9 N- y2 E& h
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 W% @# J; _# B6 K. `3 {static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ g+ ]2 A/ J- u, {8 ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. D# G% G6 L7 }/ N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* W3 U! v/ Q- E- s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
c; J) ^$ `/ S5 U3 v, n9 q2 lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! e, \ q5 T6 R( AMCASP_RX_MODE_DMA);
( q' p5 ^1 @5 C5 l* |- hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, m ?6 k3 R) c+ s; T b/ j9 h$ w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: S: r! E, m6 N4 M& GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 ]! A6 n$ _( fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% W; I+ v2 Y: Y. R8 E' zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 F. q# \3 B( \3 S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% R3 x: B1 ^5 R4 k' n, }- {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% z- U4 o. p- fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* v" X9 U9 R( Y1 w! GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 n: g: G# ^+ C+ d% R# F. e" t0x00, 0xFF); /* configure the clock for transmitter */
# p% J/ C7 T+ ]0 H: Y; o4 Z7 lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 M; v. K. E& b: @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; z. c- j* U5 Y' L: z. ^9 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% n. v0 g! w a2 m% x& p; r0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
9 O( H0 X( g2 |# |% ^4 b' h9 _, YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 p( v3 w# g+ G- [4 qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; j$ w5 ]$ @/ ?! W8 W, @% xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 ^8 Y: {% }. x I0 S4 h** Set the serializers, Currently only one serializer is set as5 \" s) t4 j: L8 N/ W, l
** transmitter and one serializer as receiver.$ \" A+ G3 B, S9 Q5 X
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# a, I9 b8 q) m4 ?+ cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 Y( r& L8 C% W3 j$ X) [. y0 S+ z8 Z) _
** Configure the McASP pins
( i+ {1 e; i/ e6 q2 g2 i+ f** Input - Frame Sync, Clock and Serializer Rx
2 V s7 p* K5 x! m** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ P* N8 E+ B& }. D5 u+ gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 k* K1 }9 i' T4 O9 @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 {5 j! D X3 T T' U| MCASP_PIN_ACLKX
~) R0 \! u( C| MCASP_PIN_AHCLKX& x0 D: _, a8 @; r9 o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& H# j) X I& r/ V+ m5 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' `& H- v" b6 J; m
| MCASP_TX_CLKFAIL , q2 p$ r6 {4 X( k
| MCASP_TX_SYNCERROR
. [' j: \0 P* {: |2 ~1 K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " K6 g8 I' }2 a6 }
| MCASP_RX_CLKFAIL# d- b* v2 O2 K- T: r* [
| MCASP_RX_SYNCERROR . v) h7 ?& s' a
| MCASP_RX_OVERRUN);
+ a. z0 Y& W# }} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
3 n9 v' o: B eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' m" c3 z+ k5 ~5 n1 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 ~1 @2 J, H% r9 D$ _( }2 t1 i! M! B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& N( C% [6 g+ e! e& gEDMA3_TRIG_MODE_EVENT);$ r3 _ r* f5 x& P4 t5 c3 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 g9 q2 H0 Y/ N$ g* ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( E. P) h5 S5 [6 T# a$ Q+ b" FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 X- B }* O. b3 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- ^4 T7 {5 w8 h. awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- x/ t# ?5 b% {6 r0 }9 t2 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 @3 Q1 d7 J3 C4 z" A6 a5 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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) N1 I) _6 Z+ b- v+ u) f0 ?" T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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