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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. k `# |; H3 G9 b& l8 h" minput mcasp_ahclkx,
) ]+ f" |( h8 @" J5 c+ T& cinput mcasp_aclkx,/ x) }# v9 C) S9 r( T. H" u) D
input axr0,
6 t, W# c; @$ {9 t. Z; \: q7 j' s2 t9 {0 t
9 n f% q6 e" a( G- \9 Q' Y: T" Eoutput mcasp_afsr,5 ]- @5 F1 _3 m) y
output mcasp_ahclkr,$ b1 i+ @2 S7 m4 m, x9 Z
output mcasp_aclkr,; n2 Q0 } k0 E; c3 z
output axr1,
7 K; W q1 E! x) {( |2 B' Z" o: R assign mcasp_afsr = mcasp_afsx;$ }2 V4 |" x; i' j
assign mcasp_aclkr = mcasp_aclkx;
4 G' K! Y: O8 I M5 z4 `" ]. kassign mcasp_ahclkr = mcasp_ahclkx;
; c3 [6 k6 W, i+ B% Yassign axr1 = axr0;
% O5 E; l# |- u6 Z% ]" J% E
- f" I. B9 ]4 j% ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 A5 E6 q' q# P
static void McASPI2SConfigure(void)
% W {( }4 a, s. I{, F8 f8 `9 _0 R$ a# k- y1 s2 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; H4 V4 W: X! n$ @+ ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 F' s8 C* X# aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* o. Z- W4 t" H% t. ^* E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 X& S* o4 ]: S( \+ M/ wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
k' i3 U4 d* ]) V- H. CMCASP_RX_MODE_DMA);
/ k3 w5 ^9 x& w- d9 o% FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 |% |6 w9 F( c3 f3 ?0 T$ R, AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, L, j* j! r; e4 }9 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # p, Z+ k0 V5 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" `: z: O) h5 Z1 L+ AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; Y5 A# ]8 I- R! d0 iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ ~# L w5 U' f+ ^2 TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. m* \+ J/ e% h0 [. `( v$ kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 A! D; J, l9 T# N" R1 ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( n+ d8 C0 }3 z# {* u# M' c N/ ?
0x00, 0xFF); /* configure the clock for transmitter */
- }, t3 @0 E/ D3 V0 J$ E% UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. @: B3 ~' s) l, Z( fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ p* T Z& q1 b+ r/ EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- v! M* _4 Y! x* e7 J
0x00, 0xFF);" D# {' Y/ H8 u- @/ Z- C
; B4 z7 }" _ P( e; ?/ ^
/* Enable synchronization of RX and TX sections */
5 O: q# S2 O* k; n$ V1 I& M+ @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- N3 s% p7 @& S2 r* w1 _1 qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 i& A' C% N7 z8 q; B6 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 Y! O" l0 ], [7 Y: n** Set the serializers, Currently only one serializer is set as! m* Q* B+ j( x% N
** transmitter and one serializer as receiver.
! |- o$ i; {, N: M*/
3 [" A; r& t/ Q: h6 L5 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( |6 A. a/ B6 r3 B0 @/ ^+ p' RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 c I( z& V; o" i2 H** Configure the McASP pins 2 K1 a+ A( |4 C& _, h
** Input - Frame Sync, Clock and Serializer Rx. h+ z9 V/ L% N7 X* @
** Output - Serializer Tx is connected to the input of the codec
4 G2 x9 y/ D7 v2 ~*/# d; b5 b1 X4 X6 C+ I8 Y B: K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 Z4 R- K% G0 K$ \1 K' k5 f K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( S4 B; Y# l& D" _0 CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( p& Q( y/ A8 u. {9 c, j- N
| MCASP_PIN_ACLKX
2 i5 |' e" F) l, D9 H- P| MCASP_PIN_AHCLKX# \! r/ U7 {+ S2 P, F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. w- Q4 X& U3 i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ f3 a) n+ E# O+ I: t3 d& R| MCASP_TX_CLKFAIL
) c) w) \4 P4 k3 T| MCASP_TX_SYNCERROR3 T. m) k; r, [1 m/ Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " V! y. Q& W* j
| MCASP_RX_CLKFAIL
+ Y% q+ g" P7 d& S4 e# v| MCASP_RX_SYNCERROR
* @+ u; M e7 o5 {* B8 @; m| MCASP_RX_OVERRUN);
O7 y+ p) M* o0 H5 u# d) U} static void I2SDataTxRxActivate(void). D; F! s3 e- S: c+ ?
{
9 h2 c7 C4 Z) M9 S2 x. J0 }# ^/* Start the clocks */ X6 U4 @# u$ o: A0 z M% r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! e* d6 T) a4 A+ \( B1 j- IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( c1 x" X! d% H0 A7 U% G: n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( C8 B! s) ^+ R" R- |6 A' d
EDMA3_TRIG_MODE_EVENT);) {1 M) o0 O/ n: D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 [! [& I1 V _, U {9 Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
e! D6 e% @) a/ B! n# R5 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* K8 _& |; U3 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 }( E; t2 n8 C$ X$ f: L7 [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 c. z3 Z- j! ~* _# S9 O9 QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% V( z9 O" ^% [2 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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