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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( [3 [: a' p a! Finput mcasp_ahclkx, R+ S8 \# l8 f9 V7 s5 D
input mcasp_aclkx,
/ O- ~ `1 n* q6 ainput axr0, p# j# ~/ R" W7 U1 C
+ n9 L" L6 c) t3 w+ ]" u
output mcasp_afsr,+ E0 U% c5 ]5 Q
output mcasp_ahclkr,, i4 i8 f+ `1 R
output mcasp_aclkr,
& n5 _ ~3 V% houtput axr1,' I! U: I W5 Y9 i0 g4 l# ?6 y, }
assign mcasp_afsr = mcasp_afsx;. d" L" P* q5 ` P& B
assign mcasp_aclkr = mcasp_aclkx;
8 o8 {* Y' o) F: wassign mcasp_ahclkr = mcasp_ahclkx;! K% G! y1 y6 y0 R5 R# k0 y
assign axr1 = axr0;
! \9 ~2 b( i4 o) j. \! _7 T4 [7 D. u# l% {4 t6 J4 ]4 X) F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + E7 f* @ J' T
static void McASPI2SConfigure(void)
& V- v- W# y, u/ X{
: z( a0 b/ H7 G( x! r8 t6 EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ m( \( g& p" z' o* w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 K- T; @& Z) {8 g; ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; Y* I- O1 o; w& M& E" C+ dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. C7 L% E& y! V2 M* o$ S CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 N" @& H% K1 P, eMCASP_RX_MODE_DMA);
9 t: B9 u3 n, u1 oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& @6 i+ l( }7 ?7 n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, Z# J; }8 B# F0 P5 Q7 N9 s/ @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % S: j% h- T& q3 S6 b) d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, Z3 t# B8 c9 @ k; eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- n1 n# {& {: I ^$ |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 K. {2 I ?* ]( @. GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* a" G/ b: M! F; C2 hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * q+ @2 }: a7 N* X4 h* A& K! K, R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* t, ?" [$ z, ^( d- |/ {$ J
0x00, 0xFF); /* configure the clock for transmitter */
5 @! R$ d) @7 a: J2 S4 aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 X, J3 K/ t$ {& o6 ]7 l9 fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ J% Y6 Z, F" k* EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 [1 a, O" Z$ P- G3 s0x00, 0xFF);
- x% J/ \, u% ^: w2 w
# o! Q2 V. F7 O/ T4 i2 \% D/* Enable synchronization of RX and TX sections */ # E# F: {. Y7 M" y9 ]3 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 V& p8 ~* p8 h! Z3 M: h' f- e# b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* O2 @5 [& K% Y! X) GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 G/ y) B# Q" r! A" \** Set the serializers, Currently only one serializer is set as0 U: y$ ?0 \5 n$ i* H
** transmitter and one serializer as receiver.3 [% v$ ?- C* |: M! Z! n; G
*/9 I( L7 I5 l, r9 `! m0 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ r1 {+ p$ ]/ g/ b& C; VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& g0 F5 W3 U3 [) v! f** Configure the McASP pins
4 V9 d2 w. N) @2 h** Input - Frame Sync, Clock and Serializer Rx
# x$ b2 w) K# `" }5 o! l' y** Output - Serializer Tx is connected to the input of the codec
2 o9 k6 |7 V9 e1 E5 M+ ?*/) d; U) A1 Y7 X# U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( c9 f w5 K/ b$ q0 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 ^& w* [5 L, |* P0 c7 tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 i" c( B+ s3 E8 Q. X8 c: j- X) q| MCASP_PIN_ACLKX. C/ C/ y5 _4 k9 X R
| MCASP_PIN_AHCLKX+ B3 f$ ^. Z. x! U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 P4 k) x* x6 c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR E6 H; a0 _7 q
| MCASP_TX_CLKFAIL
4 p" ^+ H6 o- ]' W| MCASP_TX_SYNCERROR4 t5 c8 h, s$ H9 b# A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- N! [/ a9 f* M. Q| MCASP_RX_CLKFAIL; c+ \$ U& Q) n8 L
| MCASP_RX_SYNCERROR
0 E% u g% f0 j, [0 q) K6 ?| MCASP_RX_OVERRUN);" v/ }( c% t/ w& g
} static void I2SDataTxRxActivate(void)
- j0 |/ E4 L6 g" }8 e" c{- H" S2 z1 m8 S7 O
/* Start the clocks */
; n; y. V8 L1 D4 v5 w0 u) rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 u C Z7 P# F- T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 K( m5 O+ h L4 B/ ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
|# q* y. d Q8 x9 {$ Q( L/ ~5 v GEDMA3_TRIG_MODE_EVENT);+ d$ s8 Y# _# m5 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / G q7 m' e6 Q9 H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& v$ R+ \8 z4 P+ {$ C& l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 L6 ]( [2 I7 q5 } y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! r: D$ m2 Q5 \. L- H) G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) M5 Q: @+ `8 }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- \$ \6 ^- y7 R1 E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. @2 y0 l) X5 j8 K4 d$ C} ( k3 J( C- E n7 v7 {2 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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