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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' S9 P5 }# F& L- H8 ]3 `
input mcasp_ahclkx,! i, l- }( i8 h. J1 H6 h4 O
input mcasp_aclkx,
; f. k) V' d& W! r1 i) x$ sinput axr0,% J& Y4 J6 |; @: A& s
3 d9 |0 u: B& ^
output mcasp_afsr,7 A0 z. M: r! i9 n2 U
output mcasp_ahclkr,
( s3 ?. b% Y2 Z3 Loutput mcasp_aclkr,
1 Y" Z: A3 b7 k7 ~% zoutput axr1,
0 i/ @& R! Y* f7 J* p assign mcasp_afsr = mcasp_afsx;
0 @: v* }- A3 @( J! Z+ Yassign mcasp_aclkr = mcasp_aclkx;+ j1 S; x9 J b; W
assign mcasp_ahclkr = mcasp_ahclkx;0 w( V% l4 Z* ]/ a- ?/ g
assign axr1 = axr0;
# { l. o: h$ u; C" R# B t" f* _2 A
: S4 r8 Y& Y z4 O! S3 \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
E) f4 S# i" {- Fstatic void McASPI2SConfigure(void)7 X; ]0 x" Q( y+ |2 R
{6 g$ a( \" H" B$ T; b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* ? o/ r% ]" z3 H0 i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" f. [& ^* c' |) F9 ~0 y9 WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, w' ?0 K! T8 E( W1 A& v. [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ {- W, ]+ D8 I: b: o2 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ `. r4 k0 m# E" N
MCASP_RX_MODE_DMA);
) @' Y4 v3 b4 n6 @" J- n# |4 C1 cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 I, i8 x! a7 A% u/ v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 k+ A2 X$ Q b8 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, q: [" v2 y( R# M* Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 p$ W3 ^& x; ~& f$ n! y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, \. g1 M5 `1 r2 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* X. M2 x7 T, R# R8 Q: yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); _" T7 H/ |: L* c+ I/ F# N4 v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! @" Q+ V O6 h' D2 k) Q4 ]! N N+ TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' D- Q8 ?8 S% y2 G/ M! E3 E0x00, 0xFF); /* configure the clock for transmitter */
$ `9 o1 [' E8 G7 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 E+ q) t k0 q# @' e- a2 C3 @' JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 L- d: Q- x$ X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 Q6 t% Y6 {) I. S- X% Y
0x00, 0xFF);
) n4 `8 c( L; x0 o h6 s
1 B, O& s) ^/ v" L0 o$ F$ T/* Enable synchronization of RX and TX sections */ 9 H0 m5 K$ m% d2 k. h+ P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 ^; b5 v' _+ U& O& D8 X) ?" w! }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; X6 ?+ _, N: E. W V# cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: J$ r* H t; x** Set the serializers, Currently only one serializer is set as
+ E3 ^) J+ C- F1 Y9 S h** transmitter and one serializer as receiver.( @+ ? t" l* v% A
*/
1 i% g1 u# Y4 V& cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& D$ d+ ~, b4 q2 _, E& y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 j4 O% h3 k! V3 _$ A
** Configure the McASP pins
+ E$ j3 R4 W/ L) N** Input - Frame Sync, Clock and Serializer Rx
7 f7 d1 V1 F V6 @( ^" k) ~** Output - Serializer Tx is connected to the input of the codec " G% }/ m2 e U& I8 X3 D" [
*/
* _/ q' N# d6 O$ W$ I# ]; hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% v, `( P* A( P: IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ z' O2 v3 w9 h, c1 V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" L- H, B8 ?5 w$ x/ f# q0 l
| MCASP_PIN_ACLKX
# K5 K4 J) R( G7 q' e. R$ P| MCASP_PIN_AHCLKX
) J0 e& X. h! r5 C: K, X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# n0 ~5 f# h- ?, r1 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 a8 T \+ B2 W" u( s| MCASP_TX_CLKFAIL 6 ?+ G# X% }- F8 z8 g" Y8 p
| MCASP_TX_SYNCERROR
, f1 M5 S+ Z3 L" v) S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 Z9 u% n) h) {6 |( ]
| MCASP_RX_CLKFAIL9 N; {* B$ m2 v& P) v6 c. _. l+ J
| MCASP_RX_SYNCERROR
0 m$ Z; J( a/ z7 Y| MCASP_RX_OVERRUN);+ M5 y! Z" m8 O6 s1 ?; E- C
} static void I2SDataTxRxActivate(void)
/ x1 A1 E& c' r8 Z. q) o{
" N' A( I" U' i6 N) w/* Start the clocks */
* [$ U$ }. D9 {+ G3 n2 C) TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% M" T( T3 i' H4 _- a4 T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& Q$ }4 O* f* U( `* P% R8 d. F0 n& CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# V0 q9 J8 j; jEDMA3_TRIG_MODE_EVENT);9 y7 x( v- {5 n: y% v) X7 ~" w1 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 y1 r$ w1 l6 G; u% {6 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ a6 ]& b7 h6 d8 g' W" nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 `6 y6 @! e' H: k3 r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% ^, y: [, g, i: E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% {; g ?* d1 ]7 r2 t9 B3 \, uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 X; f$ S# N; RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 z& d9 h0 _& t' I V8 i} - L7 C4 z" o: K1 K- @, W' E" G/ f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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