|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) W7 V! N" N7 k2 [ X
input mcasp_ahclkx,
. c+ `) z6 w' a% M6 winput mcasp_aclkx,& u8 W5 C) Q. E; ^2 o5 O. f( r/ F* W
input axr0,
% D- ~/ v: V& c; X7 D Z4 k! W5 O( m) H
output mcasp_afsr,: X+ u$ H+ K6 Q% [
output mcasp_ahclkr,
6 B9 H ` G' H% R2 N! i+ B9 R6 I y8 ]output mcasp_aclkr,. V8 o& Z5 j: s6 F' r9 B* E8 X6 n; T
output axr1,
: N0 S, o$ U1 x assign mcasp_afsr = mcasp_afsx;: e- n; H7 U$ C" P, [/ k2 t) Q3 x
assign mcasp_aclkr = mcasp_aclkx;
) x+ B# ^* i2 F+ F) Vassign mcasp_ahclkr = mcasp_ahclkx;# D* W9 w- Z7 m6 u+ ?8 h# |
assign axr1 = axr0; & b8 U2 v9 [5 K5 J. D, }# m
& [% W- _# c+ n A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % B' z& M" B/ j
static void McASPI2SConfigure(void), r" m4 R- D5 O4 p- O
{+ i5 t5 B/ F( J4 N; S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ Y% K+ ?% K" ?- i6 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 j8 D v0 K1 D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 W3 Q1 ~3 [' {) Y) D8 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ v/ F. ]. k- a4 p4 G2 h, r$ DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 t8 o+ G8 q* H. v7 `. ~
MCASP_RX_MODE_DMA);( o1 [- `/ H6 k% x' G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( p" k t3 j. ^% ^) V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 c: d' k6 N5 i4 q+ u5 A6 T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 E, ^$ a6 U, s3 K. ~; A: Y4 s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 a: R1 C* H3 I: v x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 e; M) H7 k2 i/ G; q7 C- N8 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. d' x; R+ d7 _/ cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! M0 G# M: y/ H( f$ AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , i/ p4 w# _" O% A9 u* [+ u# b0 k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' U$ p- F3 z( e3 S9 d: q0x00, 0xFF); /* configure the clock for transmitter */- m- y+ \' j& F8 A; V7 y3 i3 _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. [6 A- w7 w. x# ^" x: [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % w8 g2 s! Q) A% q# K- h) d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! {$ v1 Z% y/ J7 |9 `
0x00, 0xFF);
5 B h M, [- `- h6 x! n
3 Q. q* y% t( b$ f, I4 G6 I/* Enable synchronization of RX and TX sections */ 7 T0 e) z& O" c* W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" A( n4 x4 x& l' ? m1 t0 \5 k0 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); m7 w& i: l3 j' z! e# m+ S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 D" N' v8 K8 r7 P6 e** Set the serializers, Currently only one serializer is set as
$ _+ I: |5 ], M+ A3 Y, F T** transmitter and one serializer as receiver./ d9 P" V8 B' S0 K
*/
7 E2 l5 }1 ]2 |' n) ?. e1 gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ E ?% O4 |' ]) @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 W1 a& U0 |! [9 B* g) o** Configure the McASP pins
2 f5 v+ k; O0 I5 R** Input - Frame Sync, Clock and Serializer Rx8 m, ^- U$ r3 v' s
** Output - Serializer Tx is connected to the input of the codec
0 [. k$ C/ s. U4 k*/5 t7 n. Y9 O+ U3 A9 O0 j: [; Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* f+ u: y6 r+ G1 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
J* x2 v! r0 P( a! p& YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. \9 n' L! W. l: r1 ?- i
| MCASP_PIN_ACLKX
/ B9 O5 S+ L4 j8 O% ~9 `1 s/ K| MCASP_PIN_AHCLKX
& L; }- E8 A* \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 q7 {9 W) C2 Z* ?1 U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 U9 H d J3 ]. u8 @5 \% {' u
| MCASP_TX_CLKFAIL
' V( V4 W# g! p) t2 i* h) V1 E! G$ K| MCASP_TX_SYNCERROR3 d! `; ~. C8 r/ j, ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ^3 r/ ^2 }- G5 {5 B( f" H7 ?5 b* q
| MCASP_RX_CLKFAIL: k- }2 ]" s+ g: K+ ]0 g
| MCASP_RX_SYNCERROR
. u- M* g& B& A: T" Z8 z| MCASP_RX_OVERRUN);) w h2 b* q3 J6 k7 [
} static void I2SDataTxRxActivate(void)
7 A$ g, N5 j, |9 ~{* i8 X6 Y; b; i2 v& r& }3 U
/* Start the clocks */
2 }7 K$ a, l. I5 i: U+ ]3 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 F0 {) ]* g* r! _6 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 H7 j" w* m5 O) F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. U7 z7 {5 z! C) M' b, c) |; g0 f5 yEDMA3_TRIG_MODE_EVENT);
/ }( L# v) j, ~1 ?6 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" i- ?1 g m4 q* S0 }2 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* w' u; q1 o3 F3 d( _1 k8 d% L& S! lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 D4 b/ Q+ e# O+ O' p5 {' @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 X5 Q8 f, k+ H+ A3 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! h& U( e6 u% {" w1 L4 f/ Z, CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 j6 M f9 w9 ?' kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 l: i$ I( n; ]' {
} : T& M$ X& a6 p; ^* @/ p4 I; i' J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ X( m& F- @! {) C, S% u1 T
|