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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; b1 H% R& e3 V5 r5 c0 P
input mcasp_ahclkx,* @ C# h- X. d( e
input mcasp_aclkx,* ?3 d9 H- w) C) h3 M$ H8 j
input axr0,
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. H# B% U. m( E- Q+ d$ soutput mcasp_afsr,$ |/ w. R/ j) ^& ~: ^9 R$ D
output mcasp_ahclkr,
7 E* }/ X L4 ^/ f- woutput mcasp_aclkr, o- X1 L* r' B" L. K
output axr1,% @& E: i& X4 R6 q
assign mcasp_afsr = mcasp_afsx;+ P2 p2 v0 P, a' ]
assign mcasp_aclkr = mcasp_aclkx;* t# F- M* S6 e( t/ O: N
assign mcasp_ahclkr = mcasp_ahclkx;
' R6 s0 }' x' W8 _assign axr1 = axr0; % W! V$ @1 P8 q7 c& R3 ?9 O1 p' T9 b
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 n& F6 V f0 {2 _% P1 U
static void McASPI2SConfigure(void)
: u/ x# X; i- e, L: J+ \8 v{
" }- ^) |2 f2 e: t4 ^3 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ }) r- M5 i; E) o& @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 D0 S6 E8 ~& O$ o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); V+ t" g; t& a, | N/ @7 I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, p1 w% \' j" q4 A7 l! qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; t& m3 N! {$ ^) f" |+ @" c9 x
MCASP_RX_MODE_DMA);
2 ^* z1 W, S Q4 }, Z4 lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 _2 r8 a; Y6 }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 C1 h' ~' a% MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 B/ b6 C- _' iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ d& h* X. r: V* F. g- bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ p( y2 S! z! s8 L" t$ Z3 P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 u/ h+ F/ B2 w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 M6 E- b4 E: \% fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* ^) `+ T6 l. CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 _+ {* x$ R( [! Z" W" b7 f6 ?4 m0x00, 0xFF); /* configure the clock for transmitter */
$ Q1 W1 h, M& w5 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 \" n( h9 d z5 m1 g( MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 t6 y+ K2 @- |( C. M9 Z/ c1 r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ _1 p- K) F5 [# @9 v0x00, 0xFF);" I. [0 U9 R V7 R
4 P1 H% L& e9 F# L8 l" q" v4 M" k; `
/* Enable synchronization of RX and TX sections */ 0 E b, ~: a, w% I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! L& N, s7 J+ i( J) v# F) d1 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- \8 t1 G3 m% L* T7 k {- T1 i! o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% @5 c" ^" w8 a** Set the serializers, Currently only one serializer is set as; D H9 b, X" l7 A& f( }
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- C( m1 x6 k" O- z, l9 f$ g3 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 j7 M+ _ K& ^ X' v3 j
** Configure the McASP pins
6 u$ M) k2 C' T; Y5 g** Input - Frame Sync, Clock and Serializer Rx1 S3 T; K+ B5 R/ @4 F- x
** Output - Serializer Tx is connected to the input of the codec 4 y& r* h3 \, P
*/
9 X" G" r, ?# i- a) b2 t# HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 D9 p! r2 H* x/ n q8 U8 Q+ _2 \$ }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& O; x, c" w. o% ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX O# J9 e1 ~1 V" m
| MCASP_PIN_ACLKX, S9 ]9 K* j- K5 B( b h0 O3 ?2 V
| MCASP_PIN_AHCLKX
7 [/ o5 J5 p9 M! I: t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# O, ]& g' K* f1 }, pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( e+ A' j- _9 c8 T| MCASP_TX_CLKFAIL
8 T+ j3 C* W' R1 c| MCASP_TX_SYNCERROR6 ?( \0 [% c5 c: ^, n# G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, g1 ?1 Q" v' g# I+ F; |+ I; c| MCASP_RX_CLKFAIL. D+ v. d. n5 ?
| MCASP_RX_SYNCERROR , r& [7 g5 q+ u1 D0 @2 L
| MCASP_RX_OVERRUN);) d- Q& a' u) ~0 `' ]
} static void I2SDataTxRxActivate(void)
: ]; j# B& J# K/ g) U0 z{) X3 A0 |9 M& M' m3 j: g
/* Start the clocks */
& B3 x$ @- A7 xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) z& ^; {! `$ r' KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: i" I% g; q0 ?7 U2 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 {# ^$ R# o2 ^ `2 w7 SEDMA3_TRIG_MODE_EVENT);
2 Y3 d9 c$ Y8 T$ E1 Y$ R) TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 y8 I- Q6 s* C+ q6 t( Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ X4 N3 `0 F( M$ GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. Y. I$ h$ Z" J5 _3 Y) l( a0 y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 E: Q% [/ H0 d& r; D, G" Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ g7 Q4 I: X5 u& C, y) T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% v5 w' f; t& s# X, H1 m8 [0 WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ Y6 x, c b) K2 a3 Z1 [1 T, U}
3 D' A8 R+ h7 e- M8 r3 m/ m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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