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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# f& n2 \) ]+ X0 t2 z+ s, d
input mcasp_ahclkx,& [# r, F& Z5 m! V0 r$ F
input mcasp_aclkx,
+ F, O$ C( E: s' X5 K Jinput axr0,1 r R$ n! u. u. k; v
. r1 b9 m6 i- N( t$ M, p5 s
output mcasp_afsr,4 M9 o( Z/ L1 W- x
output mcasp_ahclkr,& f' y. o) V9 Y5 p) t0 y0 n
output mcasp_aclkr,
Z# D. B# i1 P( \output axr1,
/ I4 N2 ]3 U( f E- u assign mcasp_afsr = mcasp_afsx;
: z3 z0 m- ]5 K& Passign mcasp_aclkr = mcasp_aclkx;. ]/ c* ?9 |# ]& F) z; k- R: ? I" ~/ Q
assign mcasp_ahclkr = mcasp_ahclkx;9 V" r9 a: S' v6 |3 j5 b
assign axr1 = axr0; ( D! d" ^' R6 m- X8 e9 g3 S# c
% V6 t A3 v. Z/ W- v* ^: l4 p7 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 P' z! C* t7 ^# K- }" [static void McASPI2SConfigure(void)
+ Y3 f- Q3 }9 G& J& h8 C5 U{6 R, b$ s x9 O7 M8 e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 I9 T3 A, k5 f# f5 X ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 Z0 u, J* R1 r: E% y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 D: H- ]- a) [& K: I/ R% }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// [+ w9 S0 H, e1 p- i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& L: B5 I! F1 T8 P& R* x w4 GMCASP_RX_MODE_DMA);' r* T& _) L3 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: D u* Z, W! F: G9 ~2 A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# a# [- N9 |' s9 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! L% b9 R# j/ Z* J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 G/ e0 w% J, ^3 y. k, m3 Z( Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 N6 a j. i+ OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. {3 ]' n z! f. r' D. c1 y" xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 U* v; N, h# K2 b. d8 ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ Y4 @3 k7 W' v9 }+ U8 `, b& n/ oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
|. w; h; D/ J1 ?1 v& p) A0x00, 0xFF); /* configure the clock for transmitter */
- {- Z0 O- s. A( |$ G5 m8 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* U ^" R- l: G* v- y6 S" lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 }+ ]8 d. @* V% q4 i; }* ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 _" s" R3 w" X0 ^* L1 y4 b0x00, 0xFF);& H5 Z; x. i7 M+ P0 D1 K: _# u* o
% P8 }8 }# Y8 k8 `7 e' }/ Q
/* Enable synchronization of RX and TX sections */ 2 q+ C; _7 c# ?4 D. j5 {) ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 L& n2 k% t D4 P( V% \ x" zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( ^! b% l$ o4 Z: w& pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! u' F, H) i* x0 l9 a9 q0 c% ]
** Set the serializers, Currently only one serializer is set as
( Q& E8 Y! n4 t5 w** transmitter and one serializer as receiver.
/ |: [4 o* T; {*/, g# {: r' N* A- A+ X2 ?) A9 v; s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: _' i2 n1 K9 S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** T" M3 d$ {: C6 a) Y
** Configure the McASP pins 1 I3 y& @. f3 N N
** Input - Frame Sync, Clock and Serializer Rx
6 P* E2 Q9 A3 r: d** Output - Serializer Tx is connected to the input of the codec
" I& y$ b( {/ k; c*/% k) z; B* e+ w. I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ v! O0 d5 G/ a5 L" k! [+ z) F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; |7 J) W: X ?" X% v8 o! V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ d- l# L8 b% f6 t+ X; w| MCASP_PIN_ACLKX) D7 M! t5 B7 X2 o5 J4 `9 ]9 M
| MCASP_PIN_AHCLKX1 ^" v" G/ s) c. g2 U1 u& p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 I; m% f c! {1 R2 b$ p# [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " N6 ^; w1 A# [% u6 n J: l
| MCASP_TX_CLKFAIL , H2 W! d7 q& x5 l
| MCASP_TX_SYNCERROR! t' |2 X$ K+ n; ?, T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; f2 ? L' @' m% Y& b
| MCASP_RX_CLKFAIL
6 u* C0 N: J. l, a" K+ A" t| MCASP_RX_SYNCERROR
' j5 X3 U# K: |: d| MCASP_RX_OVERRUN);( _0 C' F' s2 H- q
} static void I2SDataTxRxActivate(void)
. ^/ z7 O, F7 S' _- \( G{) [8 z" C f$ `8 n, Z7 {
/* Start the clocks */
7 m( K b U r) _3 m5 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) U/ a+ _0 p0 u; ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ R" h$ p4 e! KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 y$ \) R/ K, I5 w
EDMA3_TRIG_MODE_EVENT);* ^3 j( t" [) I9 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ U6 Q2 q" q$ F1 r ~% K0 z; H' wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 W: s; S2 k6 x! O' w2 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); ~. g# f3 _! i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ e8 ^" f/ X6 l3 I7 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 ^+ H0 H+ @0 C) j- E& }4 I6 NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, P4 j* O: p6 }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: V1 t" J5 U5 W9 m
} 7 c0 w9 S0 t8 Z4 i' _" }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , r" j& X- b$ W9 a! v3 _3 B* q
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