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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( O' ~+ t" U/ ~' U5 W8 p/ C, g
input mcasp_ahclkx,$ a& Y( a! p- B$ s3 B7 D
input mcasp_aclkx,
- w) e6 D9 F2 Z6 r, |7 Winput axr0,
: A7 m% D' b: N; w6 G
/ O8 ~- l$ o4 ^output mcasp_afsr,' s; k7 p9 W# A1 y4 k
output mcasp_ahclkr,! `/ W4 H! {$ d. [/ x) c) x7 j3 E
output mcasp_aclkr,, F% N5 v! [# j' `
output axr1,9 ]* C$ V+ V! Z' ?8 Y
assign mcasp_afsr = mcasp_afsx;. _- o I; u( s
assign mcasp_aclkr = mcasp_aclkx;4 K. c3 l5 h! x7 S; G O
assign mcasp_ahclkr = mcasp_ahclkx;
# r) H# s+ @" H# @, L! f: k- J' Dassign axr1 = axr0;
( i8 R+ j5 T4 T0 T* L* A! U- @# j, f4 {3 h* v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 H0 V4 O' S3 t6 i" p* J( Xstatic void McASPI2SConfigure(void)
: R9 i2 k# y$ M5 c; P; o0 c{
8 {% m7 x8 y% i! x4 Z* ?" F+ g8 e4 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 K3 @, E0 Q: f& \7 Q( cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 q6 [# n& S' v" G# VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 X9 K* O* D' S- k; m" {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// F$ D0 b% N: i$ x+ X% t2 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# J# L/ n/ `0 ]& O9 d% I, _: u
MCASP_RX_MODE_DMA);' E' p/ J$ x: V- [- Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, {9 V" e- | ?6 X- j3 g+ ?$ m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 p5 P5 O' q0 A0 l6 ?- HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% F* R" i- ~. \; e4 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 f1 E: B( e7 E- C1 d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, K5 C4 ?7 S% o# z# _( e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: M- ~5 m+ U L9 M0 V# X2 fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; K2 ^. b! |+ Y6 [( L7 |% T$ ~0 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * d' J0 G% I$ {6 G+ q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! T3 r' e3 c7 @% E" q* @ B0x00, 0xFF); /* configure the clock for transmitter */
$ x# W: Q5 y/ V/ E0 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 n7 S( f; [7 y! Q* k' V2 ~; xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 i7 l1 k! b: }2 o; z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 U- T% l9 w/ J4 v2 M* N- o' _
0x00, 0xFF);- B1 k( Q5 [$ \" k6 m
- ?+ U, k; T# q/* Enable synchronization of RX and TX sections */
9 R+ x2 ]' y1 @1 C. @5 D0 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. X; ^! C7 G( a, O b' DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! [0 P% n/ z6 E0 O" JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# Q) W* T5 N! }0 V3 x
** Set the serializers, Currently only one serializer is set as
8 H0 j9 o v9 t5 t& i** transmitter and one serializer as receiver.9 J+ d! c# x% b
*/1 Q( v; U/ b* ^) c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: l# |/ l$ v) X9 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ S/ k8 Z" [- q# y) _, h& t) [** Configure the McASP pins - d( i- C3 X& {
** Input - Frame Sync, Clock and Serializer Rx- |2 d5 Q6 R7 x: M; k- d/ b
** Output - Serializer Tx is connected to the input of the codec # a2 {5 I) [5 W# T; Q/ e9 W8 U. W
*/& r' j5 z# d6 K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. s$ R4 ?4 [: t f8 v) K/ y! mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- l: R' |1 _4 D) F9 jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( w/ X. k$ i% S) ^. M| MCASP_PIN_ACLKX/ M* F8 p2 `& A( o
| MCASP_PIN_AHCLKX
" { E4 W6 Y+ @8 h) n. H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! d& D# B2 P/ O2 l, c! @# IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, Y+ x9 H( s! [/ q: G& n| MCASP_TX_CLKFAIL
, u# P! x# {# z" y| MCASP_TX_SYNCERROR
5 b' e z9 B/ f3 V7 o5 || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' u; N: g# H; k( U7 R| MCASP_RX_CLKFAIL
' e/ K u9 H$ w. [6 o8 I; g| MCASP_RX_SYNCERROR . p, x, ]/ X$ v# p& B3 d
| MCASP_RX_OVERRUN);
$ b G7 O. F: k' w} static void I2SDataTxRxActivate(void)
" o3 l2 c) z; z4 x9 E/ r{
. |3 w' e) b7 N- h! p6 ~2 o% N/* Start the clocks */3 o7 t2 o; x) W5 R- j' N0 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 }6 [8 Q% L: A4 {1 ~; h& [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// U. J Q+ ^4 [7 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 u$ m3 d$ L" t9 \, @$ IEDMA3_TRIG_MODE_EVENT);# E' w7 b& r2 T7 N' J/ v2 Y! S/ W& _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " r& _. s5 B# U. r; I) D; E: c8 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, P( i4 F7 d* v: Z3 a4 ~3 D- ?; cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) O' ^& ]) f3 k8 \( @4 N7 R! f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& [1 D$ x9 z: F* s* Q8 C( X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 B( L+ V/ A' r' q! F0 N& e7 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) A, o R& J E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. n; c2 G" r9 _2 l7 h6 L
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