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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) y L; S. x/ _8 _9 C4 Hinput mcasp_ahclkx,5 M/ S/ M! }; Q0 i2 ^
input mcasp_aclkx,
, P$ o& @: U" j6 H3 z, iinput axr0,% H+ O& Y3 U! I \% T
9 u! I: I8 k. ]2 H. R3 [
output mcasp_afsr,
/ c+ z) J8 h, P, coutput mcasp_ahclkr,
+ h ]* j& ~, R% r% `+ youtput mcasp_aclkr,
* Y1 E/ C/ H, @. L/ voutput axr1,' J2 p& p" s3 X. q8 a) s/ M
assign mcasp_afsr = mcasp_afsx;' W' E" u5 w, e4 `. G0 I, F
assign mcasp_aclkr = mcasp_aclkx;7 l! [# i! B8 [5 t
assign mcasp_ahclkr = mcasp_ahclkx;/ Z, u( K' ]) \% i6 t6 E! b
assign axr1 = axr0;
3 |- b1 ]4 ]. K! u* V( ?, d
( d4 c [' J: @) I- g% W( T5 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 w1 B, J: D( b- l3 z
static void McASPI2SConfigure(void)8 F }! }( T% E
{
y0 S( ^$ s$ O6 L. sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 Y5 A5 g7 u+ L/ c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 Q5 B* V4 Q6 @8 A& j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 @. {' z" h( ]( k' y8 _$ b: ]4 S$ Q; |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// m0 L* D2 F6 Q4 d5 t: N2 {( R1 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ p+ }" S+ o, i UMCASP_RX_MODE_DMA);
; a: m$ [- D2 w3 [1 KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 i7 M: {6 w4 c1 S0 w$ QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# r+ m3 c" ], L5 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% A* r6 I$ F3 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 H3 S X8 y3 g: T- A l2 T; x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , i) f3 c3 r. T9 X0 b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ r- O9 _( O6 r0 K j7 [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' x8 A3 }& x# m/ d2 b% gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- B6 ]' N. o# K5 E0 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. g! H+ G$ {" w) a; Y o- V/ R
0x00, 0xFF); /* configure the clock for transmitter */' a1 f7 `9 L# n+ X$ }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: {, H* Q9 M$ Y0 VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); d5 Q- f L. Z1 `4 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) H+ {4 Z/ N- S# R
0x00, 0xFF);, I3 O: [, b& v
( r$ o8 P7 l4 C( A7 l9 x
/* Enable synchronization of RX and TX sections */
& k, \1 `8 O* p) `. @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: \9 B, A# n% B1 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 p- d3 [5 `! m( V) \6 PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 y6 t3 _! u5 Z; Y s- o7 \$ S B
** Set the serializers, Currently only one serializer is set as+ G$ F1 V; U$ ~
** transmitter and one serializer as receiver.
9 N x0 Y( ~! q9 g3 U. v) h*/- y1 Y- ^( z3 w P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' r( x0 b* ^2 W: y/ Z3 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# B( p6 K% }0 F2 J9 t4 T- y
** Configure the McASP pins + @! s+ `3 z2 b5 ]0 f) J% Q4 Q, j
** Input - Frame Sync, Clock and Serializer Rx
, m# H( f* i% X( }** Output - Serializer Tx is connected to the input of the codec / p. o0 V& S; l
*/
# u6 \( H% Y. H; K) q" {$ q$ tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ I R5 K N0 G6 O$ k4 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 U. T# F! Q" a$ D' q2 P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# _, _$ b4 c' Q K& W. Z2 w6 c i
| MCASP_PIN_ACLKX0 T# w/ u f. x c* O I+ a. b8 O1 R
| MCASP_PIN_AHCLKX
1 L- u4 U7 o: N9 Y$ n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 C& K7 ]. _. l( Y1 }4 t& ?# o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 C9 f, q( ]2 v6 }7 Q# H| MCASP_TX_CLKFAIL
* K5 o. x+ _ R9 R) P9 M, L| MCASP_TX_SYNCERROR% H3 F) i8 z4 Y; F$ B3 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ C& s0 ? k/ E/ n1 o" T, _6 a| MCASP_RX_CLKFAIL
& z1 }' ?5 B5 ]| MCASP_RX_SYNCERROR / l/ h, r3 y& `$ i
| MCASP_RX_OVERRUN);& ]& |- f$ C2 N$ s. ^0 G/ {
} static void I2SDataTxRxActivate(void)
8 `) }2 C% r+ ^/ U4 A( n/ n{
4 H- B' Q6 W7 e/ b `8 N/* Start the clocks */
3 d; a9 l% L/ V! q8 \! c: ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 w2 ~8 b1 [, ?0 b; [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 h* M; e! A# h" E: J) B* X- b7 y% r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 o+ e$ Z) W1 O# n! s5 K0 |; ]EDMA3_TRIG_MODE_EVENT);
+ ~' Z, n1 C( a+ kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% n' ?- W1 q) O2 x. EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 ~$ v1 X+ ?! FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 a* r8 ? }. F" t& OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 t7 a8 ]# k% v; G% w( O7 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( g1 w# c. {* _ P, E$ a- K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
c! l* s* b+ A! k& s9 gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 C- r$ p& Z: A8 q* M3 |} $ @6 U y U% H( v. Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; ]4 Y5 U, y% ~2 t" t- J
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