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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: b. H5 A$ f6 W: a( Y ginput mcasp_ahclkx,/ n4 b( L) u, ~6 e1 f) N& p( O. D; _
input mcasp_aclkx,8 @- }3 ?# {/ ~8 ^7 D9 X
input axr0,
- M9 {1 `# W' f" E) H* d' W8 }/ ]9 r" h8 z) c' V( J. ^" q& o% J
output mcasp_afsr,' L- {1 K5 P5 e V
output mcasp_ahclkr,
1 A* v, [, t' Koutput mcasp_aclkr,
8 ]4 P _( q+ u: J3 @" m, u9 [output axr1,$ G; O9 c2 b' Z% a. Y Y% ]
assign mcasp_afsr = mcasp_afsx;
+ r1 R0 c2 H. Vassign mcasp_aclkr = mcasp_aclkx;5 G# ]3 l& |, H W! S
assign mcasp_ahclkr = mcasp_ahclkx;
( O4 I/ f# K& c2 v' qassign axr1 = axr0; 5 R' f" V+ A3 D8 N( d% E
1 k5 V: s- w, G" P3 R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; q1 N; i5 t9 E9 O% pstatic void McASPI2SConfigure(void)/ h; R% h5 _: K5 j
{5 K& U: x" b5 k" Z6 Y4 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% l# p& M) ]. I% [, R$ j/ @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: A5 m7 Y& q( p# C+ A3 q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( E8 K! w5 [+ \8 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 H1 }; ~4 }; e0 W8 M: C% P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Y0 `* B( x2 WMCASP_RX_MODE_DMA);
6 ? U, F$ f0 |: H& D- |0 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 E. X2 y7 C2 A% FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& [$ G% p. |8 Q0 d9 MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% b. w7 V; t7 L) ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( _, {" M. K, c0 Q6 n1 Q7 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : z3 S* u0 l* U* u, h3 b% x8 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 o7 W; y- o1 Z* ^" }. K) y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ U3 E% q9 l7 E8 G5 Z9 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 t7 ~# A3 o: f- S' rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 u$ Q( j5 e6 q% i# t3 p
0x00, 0xFF); /* configure the clock for transmitter */
; _- m$ e9 e3 T, E( iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% N8 e& l7 h* |3 b6 S2 F" u, WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ Q' u9 { i8 E# pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ e" ?- S- k+ s0x00, 0xFF);/ e8 w3 q6 E/ w9 ]) U
. A8 u# x2 Q3 b% N: j% r7 C
/* Enable synchronization of RX and TX sections */ , s1 c+ l5 e# b! D. O8 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 y% q% p. z$ k8 w$ [ a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ Y1 v- b! h) z8 s; j" s) mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 G5 `# L' R$ Q5 y: V** Set the serializers, Currently only one serializer is set as
6 W9 w: u' g: b& ?( b- U** transmitter and one serializer as receiver.
+ r1 f" F3 v. X t5 \*/$ g- i9 N: p9 b. q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 k0 e) j3 ]: Y6 Z0 r8 |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% a N4 S2 I' O, B2 Y7 e
** Configure the McASP pins - R( R. B6 X* s7 I
** Input - Frame Sync, Clock and Serializer Rx" Y3 h3 ~* ~( W
** Output - Serializer Tx is connected to the input of the codec
6 T: z: L1 U& ~0 {*/
- B* U7 z% p7 J, l. |' K4 CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 ~: K0 q5 {; tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: W+ r; F% H* i# a- P/ }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 S; c' \) m6 F
| MCASP_PIN_ACLKX
7 w3 b% t/ P0 l7 f# p E| MCASP_PIN_AHCLKX% q( ^9 T6 E( G% Z d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 Q2 o1 L# {/ N; Q) u& V7 k2 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 V; i, ~1 W% Z* ]. B Q( u
| MCASP_TX_CLKFAIL
$ h9 G2 } ]$ d2 e9 D/ O& j| MCASP_TX_SYNCERROR I. x8 D" J& D& R& S9 r- @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 Q+ j: I2 R, q- y1 l% M| MCASP_RX_CLKFAIL p7 |6 U- G/ h6 ]3 J/ X! c
| MCASP_RX_SYNCERROR . N6 E/ p, K6 M8 a, J8 b
| MCASP_RX_OVERRUN);
( X+ h; n$ c7 ^% @, p} static void I2SDataTxRxActivate(void)
& @. b+ O; c1 n7 _7 y1 f7 ^{) o3 u* n' C+ s) d$ E: B/ V8 B# V
/* Start the clocks */
3 s8 f+ j- {0 Y. Y! bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 i' ]) {7 A& K }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' u- m5 ]( Q1 h; E& R5 h" B2 @ N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 g0 h1 ?& e5 ?3 B3 A* k) bEDMA3_TRIG_MODE_EVENT);
/ O! |8 `6 `$ w9 |& O; \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, i" Z1 j9 q: P- H1 Y0 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 i9 E9 i; O: c1 f' q0 k* n& ?- e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 w- R, @. _7 L& hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! O. V" y: n# r2 D' @0 x* H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, l, {# f9 m, O x/ m" zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ N% h" {- ]6 v9 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( h" Q7 s2 b! F5 K7 A4 i, P
} " J$ v i4 k6 R9 V% I' z2 ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) S* Y9 }+ T6 Y& X
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