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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; N4 b: ?$ a- C" ~ Q+ g- ]
input mcasp_ahclkx,
5 v4 `8 Y( T( o) H. ?) |input mcasp_aclkx,# N+ J" ~% k- k: O1 t" u( b$ B, z
input axr0,
0 u: R7 W) `2 A) n8 w; `' W- F: Z% `' O* f# l# a& n8 H% _4 I. y4 ?" f1 E
output mcasp_afsr," e3 \6 r5 D4 C; P
output mcasp_ahclkr,
& j& n5 A6 S+ U8 u4 ~output mcasp_aclkr,
2 p% e; r8 h S4 |, o. z+ |output axr1,. W# h$ F+ p& i5 c0 t f2 f A/ Z
assign mcasp_afsr = mcasp_afsx;
; H0 Z5 V: {; Q2 l/ f" Nassign mcasp_aclkr = mcasp_aclkx;% p8 _ H1 a) ? A, }0 \
assign mcasp_ahclkr = mcasp_ahclkx;
# C* N' _/ v7 wassign axr1 = axr0; $ v1 s- z' B7 \2 Y/ Z+ ]
( z" D7 z: X! ~$ I2 C3 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# o: R6 e9 Y2 U5 Y% C- |, c4 tstatic void McASPI2SConfigure(void)
. Z* `1 \( F0 l4 Q4 Z{. h8 q( v/ D* n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' s ^' d" k' f- M2 T; L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 {1 I0 I2 i' T; B2 B; uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 ]8 J& q4 T* d2 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ I) Y6 k7 G& _* a: ^/ M7 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 s+ I- P2 G: FMCASP_RX_MODE_DMA);% z3 e: r/ I. K z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 w& G' |" J+ ]8 c& {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ D( G& c2 h5 B8 e, m$ t# bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , g0 D3 b( z3 u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' }' m! d/ R% @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 I: N' \7 t+ P" c3 aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* x0 h# M. e5 ?9 a% hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ A0 x! N3 _& ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ ], P; ~8 j7 \; m$ JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& O9 V/ R3 B/ t3 M0x00, 0xFF); /* configure the clock for transmitter */
" f! S, F/ S- s! F, k( b5 oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 L) k! f; y/ [4 ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 n- D ~/ ?4 o! Y2 V! d' w! m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* j: @! m$ `- G5 l
0x00, 0xFF);
$ }' X# F9 x$ R9 \5 S$ P7 n0 [2 e) [ _& ^# \+ P( g
/* Enable synchronization of RX and TX sections */
- ]% C! M, {" d [6 k/ lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, y% b9 n$ O$ r( h# P, K8 \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 x$ O% k h% W) q+ V( a; T6 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ ?( Z/ N/ d7 R. a# x" }** Set the serializers, Currently only one serializer is set as
" n+ i- d: W/ @+ W** transmitter and one serializer as receiver. |, a" g0 o) D( V" ~' R: S) Z
*/; Y* v/ Z' Y/ X5 M" i! b& e @) Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 b- |" r( f% t2 a/ s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 h' e- r+ v( }" E9 w( o3 g
** Configure the McASP pins / n, w8 p0 t/ v3 [( ?
** Input - Frame Sync, Clock and Serializer Rx8 z* A) _, A6 {% d. {2 d
** Output - Serializer Tx is connected to the input of the codec 8 O. {' ]' c0 F( a. s
*/
5 K. ?, T( s f8 _$ C* yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. b. l, E) O, g/ Q) R$ c0 R& f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" z, k% y% b/ t1 N9 d. nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 f9 y' ~! ?9 G! P4 o* q+ u
| MCASP_PIN_ACLKX- o5 z9 W: o$ \* ~6 [8 K2 n
| MCASP_PIN_AHCLKX
& V* ~4 h/ }2 X/ A# L( a d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* m! O9 ?, A4 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 g- d T+ d( q0 A/ _
| MCASP_TX_CLKFAIL
. E6 t8 j. c; P+ G5 I5 E* Z7 ^ C| MCASP_TX_SYNCERROR3 `) Y* S, K8 [: b/ M5 c8 @. o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / f. K, S3 n1 I7 E4 H
| MCASP_RX_CLKFAIL3 X8 ~7 _& c( \0 s
| MCASP_RX_SYNCERROR 8 {6 ?+ H9 M6 \
| MCASP_RX_OVERRUN);9 Z, P) e, _, h6 d: l
} static void I2SDataTxRxActivate(void)
+ m2 f* O) G/ q5 ]{# ]0 q. [! b. U: y
/* Start the clocks */
/ t" ~0 ~: ]1 g+ @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& S4 K {$ w; F6 ~" f R* ^$ C! j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& _9 o6 p& q' j% o& C# P; y0 k- _7 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 ?5 K6 c5 F, ?, UEDMA3_TRIG_MODE_EVENT);
, y7 @% O7 h9 i" `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # N# O" r5 a& H6 \0 p9 p6 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& t E4 c0 g: P3 X; D) g. [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 M5 Y& o2 n0 o* i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# ?) S+ s7 x7 G# e/ J- dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ ^ X* N0 Z8 G8 N/ zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# U) Y9 L3 C; f VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( |' X- e9 M0 T. \6 q# K7 i" H
}
4 x& n# d2 Y' x: A* _/ y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 v# a; P1 h p5 b
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