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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! F C3 b0 s7 y) n4 w; o4 X1 {input mcasp_ahclkx,: f1 P. m! i0 [
input mcasp_aclkx,
* q3 e4 ^+ z* e6 L* E. qinput axr0,
4 A8 o0 V$ n& g
/ P0 z* ~ I: ~output mcasp_afsr,. c' J1 N, E: C# C
output mcasp_ahclkr,: I6 y( I. q2 o6 K
output mcasp_aclkr,
% `* g5 z! N Q7 Eoutput axr1,
/ L) ~$ z$ M3 M3 B; i assign mcasp_afsr = mcasp_afsx;
$ e2 b9 I5 s' j, Rassign mcasp_aclkr = mcasp_aclkx;9 [7 I: q9 D& l& ? h \. A
assign mcasp_ahclkr = mcasp_ahclkx;
8 \( V+ K4 _8 ]: I8 J, Sassign axr1 = axr0;
% P9 H4 o/ g2 l' W2 v5 N/ Q) m6 @1 }6 F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* t" Y$ O+ N- [* I) {/ u0 kstatic void McASPI2SConfigure(void)
# l1 U3 p6 H; H* e{: C, b7 V( ?/ O+ Z* U4 K4 g/ ^% ^: x( k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 ~/ ]& n4 P/ e* XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 ^4 E- w: i" a }7 x+ Y0 v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 L% c- q2 T; B! m, ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 O6 |; {+ @& F# f- C) oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( M9 A* @: U" e* t
MCASP_RX_MODE_DMA);
: O% y" n& [4 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, M6 e4 p; A. [/ u) Y$ f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, K- K6 N3 N' I6 p( V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 q& g# D8 h& v1 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- H$ m- u+ J1 y5 T9 a pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; [' @0 N+ q" r! V1 y1 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 D- s$ r2 A+ {% l2 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. j- k. f0 W2 N; c2 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & j% @6 j7 I" T+ r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- R7 e! Q9 m6 K. {) {, ^- t0 H
0x00, 0xFF); /* configure the clock for transmitter */3 z3 L4 H: j* K% `2 s5 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, i4 P; _# Z. x) f8 @. A$ pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# i( _0 P, |5 G+ C! ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( E, A! O# d' y9 X7 i3 _0 c+ f/ R
0x00, 0xFF);
+ q- ~! C9 e. Z7 z1 [) U8 i/ O ?% n1 B2 A A3 F
/* Enable synchronization of RX and TX sections */
( n7 w+ u- K" S: TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" |: V# L5 [! N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); _, j8 z; k! y$ r! u1 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
M+ K! v. l0 |** Set the serializers, Currently only one serializer is set as
7 H9 s/ V) f; x( y7 \- v** transmitter and one serializer as receiver.
% g1 P' m6 W. a" f*/
8 J9 n. B3 k* j: w. I8 e# D( Q; cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! R( H* E4 r1 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 Y4 M5 D" u2 M& A* ~
** Configure the McASP pins + u7 Y+ b. {+ H
** Input - Frame Sync, Clock and Serializer Rx8 W3 Z& a4 S% ?7 ?8 {: Z$ Y
** Output - Serializer Tx is connected to the input of the codec 3 P2 D, q, U( v$ o* B( {
*/- t) ^( |: N" Z5 `3 v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ ]( g) t# p: P: Z" c% n; M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 ^7 _4 m+ d' l6 l# I3 M- m. H5 O% gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- X9 P$ `" u0 p" _1 e5 H| MCASP_PIN_ACLKX
1 ]! O# W% H% U| MCASP_PIN_AHCLKX
7 Q2 F; @$ `$ q7 q% X3 e. k7 P( p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 ~* C" `) j% S0 k% J9 NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) _+ U3 F' Q9 s; F6 a8 @
| MCASP_TX_CLKFAIL $ n) C5 p3 @. K: l9 b
| MCASP_TX_SYNCERROR5 H6 ~# w2 A) S. z" ^2 |/ r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / p% m8 W3 ?/ l
| MCASP_RX_CLKFAIL
8 Q! C8 ~" r$ O) n W| MCASP_RX_SYNCERROR
% } o D" y; U7 r1 s| MCASP_RX_OVERRUN);2 Q' S' I+ w( v1 D& m: ^& x0 Q/ h
} static void I2SDataTxRxActivate(void)
! _+ G4 O0 `; R o{* k- n+ G8 _4 I7 c6 h
/* Start the clocks */
7 Y# ` @+ m0 d8 A! s' yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 _+ p& L6 G' m' t6 @( K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- }; Z) {( A) g- YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; ` f4 }; ]9 v) o+ l" J( V% n! F; fEDMA3_TRIG_MODE_EVENT);
2 i3 l r$ A2 j6 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 H# |( n4 L9 c: a3 a S4 O6 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) } `7 G! V4 x/ b2 @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) }; R; B0 J1 J, w9 ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. S: f5 r7 e3 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# U- Y% p- C% {* q& J) W: r6 i$ z" FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 o+ y) C0 e) f% ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- y Z& n* P3 D N5 N6 I
} ( Q4 x& D' a7 H/ V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 k0 c; _: R2 B1 G, D: ]$ o% v; P( w
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