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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% L7 \& ?) ?& W* f9 }* {
input mcasp_ahclkx,9 G& ?: ], {1 [" F+ {
input mcasp_aclkx,: ^2 t4 z/ h# \ }* w5 [% H
input axr0,
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3 b% V$ J0 r* j! Youtput mcasp_afsr,1 W; x# ` g5 B3 ~3 Z: @6 ~) |. Z7 F
output mcasp_ahclkr, G( u l! M( q$ J- k. b$ H
output mcasp_aclkr,3 r5 J' L8 O, R& X
output axr1,8 Y" L4 t; @5 d, y% r6 T
assign mcasp_afsr = mcasp_afsx;
+ }) C& x- y9 q/ N/ O0 Yassign mcasp_aclkr = mcasp_aclkx;# a3 c( |" G0 Q% r' x$ J
assign mcasp_ahclkr = mcasp_ahclkx;
( m9 p9 A7 i8 Kassign axr1 = axr0;
/ t9 E" r8 f* V: c* }. r. h
1 V/ B( q7 A. C0 W3 m& W! D$ z/ r" D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 v0 x. N$ t! g2 J! tstatic void McASPI2SConfigure(void)
& F0 W, L! x, ~{9 Z- E& y% d+ {% ]! E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' }! N0 c h3 T! ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( R5 v6 S# }/ x0 Z' Z% _' ~2 V0 H8 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 ?, Q/ M! z' ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' A8 c4 t' v# b. IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. A# z6 U+ `8 z7 xMCASP_RX_MODE_DMA);
' K7 h0 _0 _9 A I) T, FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ y( ^( H2 D, N! ]6 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; G7 o& |, z3 \* G! z- XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 y; L* @. U$ `' c. y, |8 g5 {9 K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% Q, n) J: x6 N% C6 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; |' c* |3 X' j0 P. ~( g$ _" a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 I" x% ?6 p6 ~+ y* k* g; C( a6 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! @' ]: Z/ s* z' S8 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 M: {0 Q9 B. FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," ?- C; H) C& P4 A
0x00, 0xFF); /* configure the clock for transmitter */
7 p4 J, c0 \5 ^, Y7 y0 J! Q, k! \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 e6 j) E" |% {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ j; K4 M* {3 H; @; \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% @/ Y2 B. \& O( d7 l
0x00, 0xFF);: S- ? e) F- D+ i# q9 R. U
% ?" \* v1 h3 U+ p' A( q/ y2 z/* Enable synchronization of RX and TX sections */ / I2 o- k' J, _" I6 G3 f0 ?; z1 d9 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, [0 ^3 |5 n/ H9 H4 W! i/ GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 R& V7 ]+ v. n4 i+ B. dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 C6 y* G5 c9 j/ |- \- D** Set the serializers, Currently only one serializer is set as
/ R8 L k& f& L& s% C$ y4 n8 T" N** transmitter and one serializer as receiver.6 k o( t# i6 g# ^- @" j
*/
$ s' X; R# J; p; Z- |& P; l- JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' i6 ~! t- m, `# {, |5 g6 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: D" C5 J$ b5 t) t' \) y- x9 R** Configure the McASP pins
* \, M4 r5 x- t$ i. J** Input - Frame Sync, Clock and Serializer Rx
0 ^6 w% z& q- T; }# o' j8 x& D! X** Output - Serializer Tx is connected to the input of the codec
/ K6 U: z( X0 N8 ^- z6 q*/
% n8 n( u. h6 n1 k FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ Y( W7 s, _8 [7 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! p/ `6 Y$ \1 X0 O2 V4 yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, E0 U e- X- X1 c+ S8 O9 F
| MCASP_PIN_ACLKX
/ W2 e! u8 |* C* ^0 ^- i| MCASP_PIN_AHCLKX D, n' O' q- [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! Z# g2 E# k& G8 V, v4 {. FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ d' s0 e9 P6 R, ?- G| MCASP_TX_CLKFAIL ) t& m' v* E' c9 N W
| MCASP_TX_SYNCERROR
9 Y# q; e9 y5 ]8 J" H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. `2 F+ y1 w. L2 {7 I1 g| MCASP_RX_CLKFAIL+ p0 a9 w$ _1 o; g6 q, G Q
| MCASP_RX_SYNCERROR , e9 n$ I/ L, F: F
| MCASP_RX_OVERRUN);
% T. k1 v7 Q1 C7 x7 k} static void I2SDataTxRxActivate(void)2 Q" q8 o4 W8 W2 D& Y* Z& e
{; J, K2 z% \! I- r& f% h: |
/* Start the clocks */. P$ D" o2 s3 X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! T) y3 L' W# z( W( {5 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ l3 ^; r0 Z% T% }2 l$ e8 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 [9 y) E; e, W& P1 g3 xEDMA3_TRIG_MODE_EVENT);
: Q- f# M1 Z9 c0 z* k2 y9 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' e( B9 a6 l& O5 _3 H& v, ?2 U( Y9 v+ jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% B! v$ L* y4 Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( e. E6 x1 A4 G- f* R$ k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 l) J8 |8 C% u/ lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; u3 d3 V$ L% |" v4 B. w- Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 g0 t% ]0 V# d8 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 U: q% M+ ?, B! @6 t% H9 A& Z
}
2 T: V4 V0 P/ o" E* C. n* Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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