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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: H4 G( k; |: z2 W: N5 n, o& ?. ?# cinput mcasp_ahclkx,; a7 B4 n/ V" f( R' t5 \- T# K
input mcasp_aclkx,
5 n% j0 B0 P# V0 u; m* O0 }input axr0,
' `5 t4 A; c" o- F! Y3 \+ T, Q4 N6 a! ~+ i6 _9 ^6 g- H9 m# y
output mcasp_afsr,4 `: R, s9 r% A9 z2 [
output mcasp_ahclkr,* x8 B& ~8 r' ?' ^- M
output mcasp_aclkr,
+ C& l, A3 U* Z' E( F @- C3 W" Ioutput axr1,# ]/ s. J! z# n7 u! s, d2 w
assign mcasp_afsr = mcasp_afsx;5 e& w5 S0 |0 }- C6 L' `$ H
assign mcasp_aclkr = mcasp_aclkx;
+ \. c+ O5 p4 p# b6 @. F# Oassign mcasp_ahclkr = mcasp_ahclkx;
0 }3 u/ C, v0 n& l# @assign axr1 = axr0; ; A, j5 Z6 _4 ]! J- E1 z
0 h! F" t* x( F+ b* Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: y( P- O; o: tstatic void McASPI2SConfigure(void)5 j; e- f8 r- S1 A* c
{
7 q- x+ ^6 _) V1 _4 `2 D# _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 \/ P1 L ~2 b0 j1 x) iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 s, v# |3 z1 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; n. X& ^! i$ k5 M! c( C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 X3 R2 M) ` c; z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* u" e' {/ @' B
MCASP_RX_MODE_DMA);' }( u1 h" U. Q8 ?) j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- ]* q+ e4 J! i, E2 `6 A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% T: _. s5 g$ M. E; xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, ]: ]" h; F6 M4 x8 h% i9 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 k* a1 K' r$ d. {. Y4 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 k0 I: P3 g1 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 k, m" x9 O" U& w) M" P% @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) @% B9 n. ~5 D, w7 I! \8 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 s$ N6 A4 e W& w3 q& x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 x9 g7 g0 |9 j |1 h8 V* @$ @: x0x00, 0xFF); /* configure the clock for transmitter */
: x, R/ |2 d( l# @) H$ fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& x o7 D. U+ z% x: D2 ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : P* k4 `+ n; Q' f9 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 J# A' _$ F7 b
0x00, 0xFF);" s6 G% x2 ]) B ~$ J
9 b! ^4 ]6 u9 Y- z6 S) v7 u: z/* Enable synchronization of RX and TX sections */
% _3 I2 _, h/ G, N9 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// |5 s9 U4 R U1 N3 c' {* e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% h, W* r7 ?/ b" T* Y0 |$ M9 u( cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* O# u' |" Y; s g1 A$ h% y** Set the serializers, Currently only one serializer is set as9 M: [+ k+ g2 R
** transmitter and one serializer as receiver.
# D' J w ~2 ^3 V% P*/; ~3 Q6 X6 h1 c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ J7 H! X3 d& i, d- o& |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% G- x( G. L% H. M& w5 a) J
** Configure the McASP pins
- I9 W k1 Z- j0 Z8 A% g** Input - Frame Sync, Clock and Serializer Rx
# O0 v o0 E2 ^** Output - Serializer Tx is connected to the input of the codec 7 n, j! c7 h9 G, C* U! A' @' V
*/
: h6 X- }6 f( P9 @* N* U8 f; o- j( [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; @( `/ L" N7 f$ v% O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* w+ T1 a R9 I2 {( K; _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 C' A5 ~) [) w, v! ]- O
| MCASP_PIN_ACLKX
- `( X* E: R7 v: k" G8 K; ~- V- E5 C| MCASP_PIN_AHCLKX7 I# V1 n$ @6 t h3 D4 a! o' S0 u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; Q/ M' N. ~5 \ J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % E7 U; d( w$ P' S1 E5 b* S5 R. w* W
| MCASP_TX_CLKFAIL
7 c0 S# `2 K" W4 v| MCASP_TX_SYNCERROR: w& h6 Z$ K9 S4 ^# q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 b2 B. `% u* S) w* f5 ?
| MCASP_RX_CLKFAIL
# ?+ T2 K/ Q2 v| MCASP_RX_SYNCERROR ) N/ P' R: X c
| MCASP_RX_OVERRUN);+ U7 b$ a$ Q. F. N5 \6 Q+ n5 x
} static void I2SDataTxRxActivate(void)& T0 z9 M: b9 }" J: u
{
2 O+ |7 P! H3 ]+ r: n$ _* G/* Start the clocks */
5 @& `: P c9 c/ K: QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 n5 `* P/ C8 W) O9 ^( ?6 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- {4 c$ e0 Y& D: C- o% |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; a" h1 V8 v! v
EDMA3_TRIG_MODE_EVENT);, K5 Z2 M/ l# Y( Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- `- \* T7 }7 B2 W! y3 gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 M/ o4 e$ W/ t& V9 W. @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 ~6 j! g l. M7 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 ~& \% D/ l! w5 p9 O- }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" F+ P7 w3 I4 V; g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# B* r! p+ S0 V# G8 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ a' f1 p+ p. o5 ?% v) S
}
], J3 Z4 e z, u, \ z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. p7 H2 m6 x9 m! F1 h% f
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