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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# j9 g0 g- e8 iinput mcasp_ahclkx,
' |2 T- R2 j) t; y. B$ Einput mcasp_aclkx,
6 [' F0 Y3 {8 b Y4 H5 @input axr0,% |3 z3 A( h6 ]$ I, y
; E* m) C3 `3 t. q" s( h
output mcasp_afsr,$ s. O- J$ }# T' T
output mcasp_ahclkr,2 f7 |+ Y+ f# H2 f; E# u" ^8 r1 ~
output mcasp_aclkr,7 ~- e) K' ?* f+ J$ `
output axr1,5 N) r( O9 ?( g, y0 v" ?8 {
assign mcasp_afsr = mcasp_afsx;
7 F4 g( o3 m: d; Z, I7 A3 M( Gassign mcasp_aclkr = mcasp_aclkx;
6 ~7 ^8 N' F* M. w$ b) ]1 ^7 }: f2 I* ?assign mcasp_ahclkr = mcasp_ahclkx;, }2 N3 p' h) N
assign axr1 = axr0; " S6 {% N+ x7 o7 u# a1 S2 K
3 ]0 W( i* _( b$ l+ |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* R( l8 ` k7 J( e2 m' Nstatic void McASPI2SConfigure(void)
( m9 U) }* T/ V/ ?3 {* s. Q{
9 i8 ]6 @, d* L+ v. uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. S1 `6 g9 y, @% d( }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 J8 D+ F$ _$ P+ G* i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 H. b9 l$ h2 u3 N1 u" iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( X- r& M% U' h+ }$ uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ `! _% y0 B. S* j. z& g. D& EMCASP_RX_MODE_DMA);
6 n4 P2 K6 C* u1 y* @ Y% FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 M0 v4 V6 ~4 N4 t* D) ]3 s( OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 |/ h/ @5 |' z9 H5 Y$ m0 \( j$ {# tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 U2 |3 D5 I' Y+ {' j) O9 g+ I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 W% A. I9 F- X- L' z+ P% UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 @+ D& H1 C# Y) V! e1 ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! v$ ^6 I2 ~% |" [7 ?: qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& e7 ^2 z8 s5 `$ K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - a5 r5 q2 P/ \# A3 O- S) `( E& S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' ~: @. g) r; F6 J0x00, 0xFF); /* configure the clock for transmitter */: L1 j: i' [8 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 X6 f, X( S8 A' Y" k5 Z6 p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. q/ z% A- A7 m3 D7 G2 |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% j2 G- |- T( X; B6 M0 H0x00, 0xFF);
& D' s& s9 `" n! P2 J
$ c! L& P. G t2 H* `- ?! l! i/* Enable synchronization of RX and TX sections */
1 E! L7 H8 `, P; V2 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
o4 b2 T' c& {' h# |1 h( A; {9 V* gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); `) i$ e/ U+ \# O# W1 z, v) W+ |6 a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 r/ T# R k$ s* i4 |6 z$ ^! C2 t** Set the serializers, Currently only one serializer is set as+ x! M& n$ @3 f- @% B$ F. J* O
** transmitter and one serializer as receiver./ p$ d$ g9 {1 x! |$ d% k
*/
4 w3 N7 w$ X. Y$ rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 r4 \. @9 u5 G) h8 e$ R" A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- L! L& o' [. `1 K; Q# A5 ?6 u** Configure the McASP pins 8 Z/ N2 a; d( @ \; b" {6 D
** Input - Frame Sync, Clock and Serializer Rx
, O9 b( B$ R1 ^& h7 I" a2 K** Output - Serializer Tx is connected to the input of the codec 7 X* i, P- p. |' o
*/
; N6 J r; L) ?! {4 |, x: P: b& r, ?5 HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ A$ D1 I& r* aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' I7 k: A2 ^, X6 `' `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# ~+ O$ v% z+ V# t- V1 z# m/ A
| MCASP_PIN_ACLKX: W# ]. H' `8 s
| MCASP_PIN_AHCLKX
4 y+ V; ~8 y* P. W% ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# m, Q' m/ T/ x( I! QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' z. Y+ |4 @6 t, }| MCASP_TX_CLKFAIL c3 X7 I0 u2 U1 R, k8 m! h. _ d
| MCASP_TX_SYNCERROR, l" U+ \3 X; m1 E( B, j1 p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' ]+ Q& m; O1 m6 K+ ~7 {5 f1 `
| MCASP_RX_CLKFAIL
, @4 ?9 l3 G8 R3 }$ [# R% C. b; N: y| MCASP_RX_SYNCERROR " L$ X, ?2 X0 L, d/ c5 O
| MCASP_RX_OVERRUN);& {3 H* d/ [* x
} static void I2SDataTxRxActivate(void)) j) K9 }0 t8 @/ S
{ _3 Q6 L* x4 Y, N
/* Start the clocks */
. z1 C8 Y. P7 I1 E: W' ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); h6 R8 {3 b6 e, |3 W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; K+ h! F6 u& h9 I& [8 o1 |4 d5 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# C& C$ z& u3 I0 r% j- z( I, L4 REDMA3_TRIG_MODE_EVENT);
E3 w+ k$ e. u, f3 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # e+ Q' j" y+ V: P: R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 K- q& N2 F4 G* s3 BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( f' D ^4 m! |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 @3 v, a! }# t1 [- G$ G) k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 Y0 Q$ \0 Z$ }1 m+ z; hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 w: ?4 G& q' Y# z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" I4 `+ g3 v" K" ?: r
} 4 ^, W4 h% _0 E' |7 n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : a8 `6 x; j9 q/ i: L
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