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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 l4 u6 D+ N( B+ ~; N
input mcasp_ahclkx,
' C: g% w2 H/ y2 p3 o- Qinput mcasp_aclkx,; q8 y0 P1 A2 n; ^# n" [6 j
input axr0,9 I. S0 b: Z7 R/ O8 ^1 g
9 i. L% c, e4 z, b! |* B
output mcasp_afsr,
8 O3 Y3 L* [0 }output mcasp_ahclkr,% Z) I( M& ]$ |! p, g! Y/ P7 t
output mcasp_aclkr,2 b+ l8 W8 X+ r
output axr1,
1 Z3 g9 w# I" {$ H2 j5 z, Z assign mcasp_afsr = mcasp_afsx;
) C; h8 @2 D4 l9 t& V' `$ Rassign mcasp_aclkr = mcasp_aclkx;3 c$ D& T( d- O' k7 Z
assign mcasp_ahclkr = mcasp_ahclkx;
0 H4 V% }2 g U6 t. J# g/ [assign axr1 = axr0; ' T6 H6 J+ w {% b U' ?7 m
, }' r4 S5 g& b7 W' i0 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 P2 E# Y5 A! A+ L
static void McASPI2SConfigure(void)' @- j0 g! r7 h! U; O+ h; M( k
{
3 b8 T& c+ M! s: KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) e# B: l4 v; S/ b4 l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 ?6 Z9 O" G7 I9 E2 Q2 T2 vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. U- s7 y4 x. ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 f/ c( }, G2 S& F5 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 }; R) M# X8 ~. O& V
MCASP_RX_MODE_DMA);4 Q+ {0 z$ U( R- e" ?* u: H, V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 R$ U. m- @& kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 U; _& ]5 s* N! OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 c0 v4 b8 r& F1 \! s4 c) MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ n0 G9 o3 L9 K+ p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 ~: m$ Z5 M' K3 W( vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 c1 j" p+ Z! L+ ~. [- bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 ~+ J; ^8 O% D& kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- B& i4 e' C1 g' z$ yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, d/ N1 o$ ~% z0x00, 0xFF); /* configure the clock for transmitter *// [& z4 N0 [4 @2 x$ U8 r7 @) p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 ]+ y8 \: P. T2 q% ?: h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 n: e# _. g1 t `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 C% D3 u* L" r: b n, O: d
0x00, 0xFF);
" p# N5 Q1 x( B$ @
; U# v3 G+ L- ~; j/* Enable synchronization of RX and TX sections */
+ W. e3 o8 w, kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 s6 E2 A, ]- L7 A+ }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, A7 F7 l/ ?2 x' J9 R+ dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 |6 L+ ^0 A) |& o** Set the serializers, Currently only one serializer is set as
" ^# s4 Q7 r: c0 s, ~& F** transmitter and one serializer as receiver./ ~+ m( ~9 L+ @0 t/ i: G& u
*/* v0 L- ` ]8 J% C$ F, i7 @$ r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 O. P3 |* ]9 T: A/ FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! I6 L3 a# H9 W** Configure the McASP pins
' [. [1 o! \: x0 R% r5 L** Input - Frame Sync, Clock and Serializer Rx6 t6 u. K0 n% x k
** Output - Serializer Tx is connected to the input of the codec
7 U, ^- G% c6 v6 {: @0 @# |*/
" T( g: |& j+ _7 I7 f7 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. }2 p C/ K! I% t% ?, K8 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 x2 g N R4 Z X/ GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 ~9 g4 t6 y I* N- T" u' t| MCASP_PIN_ACLKX
7 F2 b4 D% y# r| MCASP_PIN_AHCLKX
3 X" U1 O- z# r2 H( x' `% R3 H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ k3 ^7 y; l/ l/ b5 R5 n ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 {$ H: n& C" e- S| MCASP_TX_CLKFAIL
# L. V+ h% `( F4 J6 [| MCASP_TX_SYNCERROR
) ?( ^9 Q! U/ o$ k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 T" w! F. {2 z$ s/ J3 U| MCASP_RX_CLKFAIL
8 L% a- Z' ~$ I# e5 ]' [| MCASP_RX_SYNCERROR 7 r# x3 ^$ e. y, |1 I
| MCASP_RX_OVERRUN);7 V, R! f/ c. p& b; D% Z) Q' B
} static void I2SDataTxRxActivate(void)5 q0 v# w. ~6 b; G1 w+ C* D; b+ \
{* q/ P5 m! R7 f7 t
/* Start the clocks */' S, p8 P$ x2 l8 i: z r' u# @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ c) S G/ R+ O1 ~6 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" r2 [# q* d M$ A0 w VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 E) Q6 Q. X3 m0 `* Q1 WEDMA3_TRIG_MODE_EVENT);. G- n+ X7 C/ S& t( [( G% r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 V7 F [, J! E; t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 W; S0 J8 A6 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ S* ?9 U2 x. ^# ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# E/ p* V/ f7 ?5 v$ A+ x; J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) T" z: Q3 V+ q5 P5 v) H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 Y3 r4 R/ [/ A; R$ \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 n& j- F/ C; z7 w I4 L
} 3 H6 s) w$ Q# b: f- Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 k# Y0 N0 k; Q* v
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