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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- I) Z' i q* E% o( ainput mcasp_ahclkx,
# V3 M( j2 l6 K% }: }( qinput mcasp_aclkx,# u5 _% G6 V& s: \- c
input axr0,: k, n8 k r( O4 `* [- y# D5 P
' y- L' U8 B9 W7 p5 d) m' T
output mcasp_afsr,
P3 T. q* g/ p! U% uoutput mcasp_ahclkr,
5 e1 Q% b6 U0 K+ Z Toutput mcasp_aclkr,
+ u% A7 d9 a1 z `* {' woutput axr1,
$ @# ^8 }" I4 \ assign mcasp_afsr = mcasp_afsx;/ b1 f- l( H* b2 N, l
assign mcasp_aclkr = mcasp_aclkx;* K7 o$ F9 X. o' b
assign mcasp_ahclkr = mcasp_ahclkx;" f% n# G/ f* D9 }3 x" Q# i& e
assign axr1 = axr0; / y/ K4 i9 f% ?8 D8 ] T, r
0 Y2 X) I) I9 g( d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 d. L' F' Z! H) |9 {/ {! Sstatic void McASPI2SConfigure(void) R! x9 h4 Y& g
{
* M# p7 X: g8 {1 XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ T: } K& S9 l* _7 O7 V+ O. j LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 z: v3 B/ `+ ]" ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 X; `$ E) T& t3 i8 MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 y2 @% O% Y2 y6 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" `$ {3 N( C5 N* K& OMCASP_RX_MODE_DMA);0 T* x2 a6 N3 A8 W; h# L1 o! x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 N, [+ m7 l2 ~( JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ T3 z/ @# {6 F; s2 e3 a7 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, V" y8 j5 n9 ?; d% m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. e$ t+ `6 `! w" I) c7 }/ v: R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; g6 E B6 \5 k( B% V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, R$ b& C K% r" J2 v4 J" jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 j K7 _( U* S" z! D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 O( e* U" `$ L8 R8 \# m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 A( a( J8 O2 M3 Y+ K2 n4 v9 y
0x00, 0xFF); /* configure the clock for transmitter */
8 G. ]* I$ F, c. ?, wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 P5 o3 t3 A# D: ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& I8 e2 x3 e) g6 n: C- yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 ?: m; J& P8 h, x- [0x00, 0xFF);
: ?1 Q% {& X4 g0 f. F
" y0 U- R1 f( J4 m/* Enable synchronization of RX and TX sections */ 1 d) V: S; H* U# [6 ]# x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& N d W: r# h+ \9 ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) i/ ^( H9 S1 B. o2 Z: sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ T. H6 g5 V* p% Q** Set the serializers, Currently only one serializer is set as
& p) y" o" m" Z3 n) y** transmitter and one serializer as receiver.7 p7 @8 m+ Q2 G7 a5 B
*/+ _+ j5 C/ [! Q) w+ F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, f8 O% ]: e) V( L" |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ \( Z: `: N- V. C. q2 s! Q
** Configure the McASP pins # P' ?2 L4 n. f$ F& G
** Input - Frame Sync, Clock and Serializer Rx% p6 O. m1 {% I5 w" j8 Q% T
** Output - Serializer Tx is connected to the input of the codec + H- S3 I2 j+ o# ~# j9 f- @ f* C7 _
*/
. {. H2 s# t; M# K( xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" z6 }5 k7 v( P! L! ^0 R* _8 s2 [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& a+ y0 n& E% X7 Z& C7 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 b7 @" T2 b7 M/ Y+ R: s3 `7 `% Y| MCASP_PIN_ACLKX
* F" A% u& r- b7 s! m| MCASP_PIN_AHCLKX8 j0 X: g& W! c4 I$ y, ^1 \: x1 S& e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ B4 F: \6 E+ z% L* p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( ^0 [$ ^' i; O6 S' ?' |5 `) _
| MCASP_TX_CLKFAIL ! b+ e9 J z% G
| MCASP_TX_SYNCERROR0 l" Q; B J+ I: o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 L1 E- q# K$ E4 B5 B; ^| MCASP_RX_CLKFAIL# W, Y8 p1 R J7 _9 b
| MCASP_RX_SYNCERROR + n2 G) V. K+ n3 L% U
| MCASP_RX_OVERRUN);# Z8 f" S1 G6 w7 m3 V$ I# G
} static void I2SDataTxRxActivate(void)
! @) @1 Z5 H' x& H& f! ]{3 j: u* m3 ?4 T8 o' z
/* Start the clocks */+ x0 z) @, `' H9 ?8 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& n, r2 n5 ~; A2 [! ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 I" P4 {% G; HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 K" x! p+ i# ~1 E& `: j5 R
EDMA3_TRIG_MODE_EVENT);# p6 Q) L2 S7 H& i* t( F7 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' E8 k, U' v2 w5 O5 `- @% M: g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, J: S* [5 Y; ]5 O4 H6 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, D6 |- I( j' V4 `$ R4 MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' w3 u; s6 l% b/ Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; @0 C; H6 l( j e% @4 X4 u* Y1 r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, P5 w7 C8 ]5 Y) T4 B/ }# t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 P4 {; T) G& q- M* }8 s, @
}
( m5 J4 _# R9 }. U' v! g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; I, ^$ ^" x- M6 P
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