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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% O& q) i* w3 T* d" r- ]5 p
input mcasp_ahclkx,
8 `& Z) ?5 C, i$ r3 K; finput mcasp_aclkx,2 A# x4 L) F3 b0 K0 l% F
input axr0,! Z" {: y9 ?6 }- W! }" X: |9 J8 A
5 t! G( ]) k! P
output mcasp_afsr,
& q4 I4 _4 F/ Q' g" ^output mcasp_ahclkr,, z g+ e* Y1 Y. V/ p! u
output mcasp_aclkr,# Z1 d: a8 R, d' X) V
output axr1,
8 L# v7 x( f7 y) F( U assign mcasp_afsr = mcasp_afsx;
: F0 {! p! w: V* @# {8 x! R9 Lassign mcasp_aclkr = mcasp_aclkx;
! i4 d7 p {& k! d# v- A, R. Eassign mcasp_ahclkr = mcasp_ahclkx;3 K5 I* q! c" E
assign axr1 = axr0; . d: c8 y% ^* Y) W( D
" W9 }# x# h. }3 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " H1 z. j& `( J! e1 m* g8 }
static void McASPI2SConfigure(void)( ]1 z h/ n( Q% O3 i' _
{
2 `6 \* }, ~% u2 v4 b9 r8 SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 ~" o+ T% b" B0 k8 w5 B% ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# X6 n( }" b9 J9 tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 {1 P/ V! S& }2 J$ yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 F- K- {' j* S( R, K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
`, s2 A c/ H. {2 B) B7 LMCASP_RX_MODE_DMA);
' H. E- w4 w! B, C/ r; j/ gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: O9 w. D3 K6 j4 y6 v8 o# eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// k0 c% a' G# ^. S- L- I3 N& T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * H+ _+ K8 `4 o7 B3 Q* }/ C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 X! ?5 N( T7 Q4 Y) ]3 V2 }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 Z( Y/ b; s: f m" z' r# T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: y3 p" _! W% @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. }* F6 H# z+ J; ` a5 ]3 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * k; Y) `! P3 u+ w; {7 j3 B: I) s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 ^2 }. R# N1 n% L4 [0x00, 0xFF); /* configure the clock for transmitter */
: E s2 d5 n! O5 ^7 h' e& yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. V' |9 {5 K, AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: g4 l% s$ R8 C+ e6 y O: V0 pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. K" y1 `' E7 F, g9 Y5 B4 A; B1 b0x00, 0xFF);' Z% l/ h# f6 U: u4 k/ e6 F
7 ^0 Y: I G6 _1 `/ K/* Enable synchronization of RX and TX sections */
5 y! c, _8 X# p/ fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% N' d0 E& {( b3 [# S: j. r0 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ V3 K3 ^% v; W' j2 U1 eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! D; a& `5 \& b& W% N' Q7 }1 r, b
** Set the serializers, Currently only one serializer is set as$ e. Y6 I# ?/ S$ Y X- A# F
** transmitter and one serializer as receiver.
6 M( p) U, ^8 f" O) U*/
3 n5 U; ~5 y q0 x4 R. m- ^) G: dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* Q5 X1 m2 @! ]8 @' A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% Z0 v3 e0 v5 J
** Configure the McASP pins
5 E. C0 L% f" b: S** Input - Frame Sync, Clock and Serializer Rx: S9 ~) M3 r L% }
** Output - Serializer Tx is connected to the input of the codec
; f% w' [7 X, u+ ?, U, _*/
$ }! n& j G% ?5 |5 F- IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 W6 p! u9 D9 U; Q5 }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 o& Z5 q$ S4 f; S. C2 e5 VMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- }. m- e2 x# v/ k% p2 j2 G
| MCASP_PIN_ACLKX
8 M( m% ]/ d% `6 [1 y7 S P| MCASP_PIN_AHCLKX- i5 ]4 z! q! x5 L: _3 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 p" j# }0 c) |: v2 S) IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& H7 d8 W) g6 d3 [5 I+ U| MCASP_TX_CLKFAIL y% i5 u7 D, d. f3 R
| MCASP_TX_SYNCERROR& u0 R5 t; @& C, R$ D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ n; N) o6 Y6 e$ \- N| MCASP_RX_CLKFAIL
) l4 h. T1 D6 z$ ]| MCASP_RX_SYNCERROR 1 r. a" w* k: u+ x; m) Y
| MCASP_RX_OVERRUN);
( J$ @. D3 G) _4 g+ G( t9 W5 r} static void I2SDataTxRxActivate(void)! k' \0 @- ~8 ~; `' O) o/ E
{8 G- E! ]5 ?% B0 f; H7 ^& m
/* Start the clocks */
1 y; ?4 A6 Z ^! WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
_1 a* [. t1 [) d1 c# C9 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 r: k) O* i0 h0 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 [; @3 c+ V$ ^/ n8 i1 s0 @. s
EDMA3_TRIG_MODE_EVENT);5 T8 |5 M6 P& l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 P" l/ X) g" t/ N: T4 f S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 u+ f0 a- [0 r1 I: E6 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ y$ c( q( e/ ^4 a* P! NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. F2 ~- ^) R" k$ P8 s7 X& z0 W2 M! {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% j+ f u8 o$ eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 g( m, N- H- H4 w3 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& e0 [- ^8 M8 L: H! A3 ]- G
}
1 I( u/ T4 M! z9 E/ ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! o2 }' ~3 e/ z7 h; B% E
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