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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 R5 s1 d; s Yinput mcasp_ahclkx,* Q M9 `9 }6 i1 H! A# u
input mcasp_aclkx,. m1 e' E7 f% i* `$ F
input axr0,
' ^ A( H% @9 n$ f. l6 B9 p2 @; E& x
output mcasp_afsr,
$ |! v+ {; N* Routput mcasp_ahclkr,
7 p2 n" @3 B4 ^% o7 b9 ]9 n# b9 }; Routput mcasp_aclkr,) F) J7 P' ^' q* J( f2 M& o) w
output axr1,5 H7 ]; ~: U- ^4 l) L
assign mcasp_afsr = mcasp_afsx;, k; ~& }. ?+ ^0 H
assign mcasp_aclkr = mcasp_aclkx;& T; P" @4 m" J% |, U g
assign mcasp_ahclkr = mcasp_ahclkx;
( b( W9 k9 r' X" d! _assign axr1 = axr0; : T8 b) [3 L2 N7 ^/ s, g. V
/ ?& R! M Q' i$ p" }6 z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! h7 y* I; F7 U, J! F, o
static void McASPI2SConfigure(void)" s& i/ K# }4 `
{
+ B P6 o6 E% z8 p! y. hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 `; ~: b* J: Q8 ~5 k8 N) i" X8 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 E E% J3 Q0 [. qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& z) x3 ?: S0 F7 p- gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 N% A( w8 K' F5 ~2 D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& n( a' L. G" R& |MCASP_RX_MODE_DMA);2 ?8 ]$ S' f( H+ D6 |5 g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 b. }8 d2 p1 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- g( s b; `* f5 |6 e8 m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 G4 W* S! c! P, q% AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ t4 ?7 j. f5 VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + O; e" O* u( x! J1 K: L5 p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 j2 Y: X; Q2 f1 w" x! I8 s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' Y4 _+ N0 y) o6 d! ^$ |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ ^% `/ e% W* Z) j% g" Q2 kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: q/ @; x* j, W
0x00, 0xFF); /* configure the clock for transmitter */5 Y9 u: D! x; e6 y4 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); X$ {9 O! D* i, d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! n* c w8 d* J9 d( Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 I5 A5 t7 u' a) Q0x00, 0xFF);$ b: |- L. B' G7 b! m
+ l+ \+ F+ ^8 D) b8 N2 [
/* Enable synchronization of RX and TX sections */
9 l5 I3 L3 n* o. q% s& dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* U r4 Y' O3 `3 d- F8 z/ H" E4 Y8 K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 W0 `3 Z- {4 F# ~/ W4 y: gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, Y2 C/ |0 z% Z% M** Set the serializers, Currently only one serializer is set as0 }- i: Y% F X! E1 v
** transmitter and one serializer as receiver.
9 N" @7 a% ]8 T# k*/
5 B* K' h. n" F& L, o, pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; Z4 J" M' L5 T4 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 x H9 x4 |* l F/ q** Configure the McASP pins - f& v- H, G7 _3 b, O
** Input - Frame Sync, Clock and Serializer Rx
- C9 ]2 X# b& I' B; o T4 F9 n+ T** Output - Serializer Tx is connected to the input of the codec ; ~$ U* U3 r0 ~& F
*/8 J( c! R0 |/ U" J7 [' h+ P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& ]/ l' Q" X: h( ]- _: @: fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; y# v; z" k. `+ U; ^& IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ O& p/ }4 I' o9 f) a
| MCASP_PIN_ACLKX
, P# E I; b1 n9 ^' M| MCASP_PIN_AHCLKX, F' F- `: K! F. a) e+ C' v: u4 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 b& w( g% z3 _- a2 ?; ~3 O* E; s( g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ ~0 Z2 f* ?" x' n6 B| MCASP_TX_CLKFAIL
4 v, A8 i7 ]* ^7 r| MCASP_TX_SYNCERROR
7 w- b3 _9 y+ S) L9 `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
|# w; K' \9 @% c+ L8 B5 ^, X6 I+ V| MCASP_RX_CLKFAIL' E. q( w; _' D ?$ a
| MCASP_RX_SYNCERROR 5 E0 K' R1 T" w. d. U1 n
| MCASP_RX_OVERRUN);
0 e) u9 e6 E6 Q- f* y9 M* P} static void I2SDataTxRxActivate(void)9 ]: Z" F/ L) R/ y
{
; B6 b$ }2 [. X8 F/* Start the clocks */
3 U# E! M& m/ ?) t/ mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- o; b. h Q& V. r1 R0 v) aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ a( r- K/ w0 n3 l! z L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) ]4 Y& A1 [) V9 `$ B+ j
EDMA3_TRIG_MODE_EVENT);& u8 K+ }0 z8 u. f! d( g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 E2 p' t8 F% S1 P% T8 T) dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( E# R8 H7 b- \0 @3 H8 C# ~ d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ ]0 I6 |. s1 }2 C! T* WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- \* r( V5 P7 A& U l6 K; F6 f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 k% l2 B3 ^' a" ~" N; sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 h- l- O& U& l; D4 ]# Z1 r# OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 i6 L# G4 s$ j P5 ^
}
, |. J' v" I) d; S% ` o! H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % Y/ ?' }4 Z& h
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