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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 i/ E! @1 Y* \$ h- }1 Pinput mcasp_ahclkx,- |5 V' c+ |4 s) J
input mcasp_aclkx,
9 N8 M, h, X# k' q! }" U% ^8 Oinput axr0,. b, [7 D- g9 b
- f% Y3 V2 r9 p7 Y/ s8 T" Ioutput mcasp_afsr,% G1 K F! `; b4 b
output mcasp_ahclkr,) U* H2 w) a, n% B* Y7 p; D
output mcasp_aclkr,& _7 z! r7 c. J+ ~9 L# M8 K; N. F# I4 U
output axr1,' x4 G3 h# n+ Y+ k1 A0 R4 e% P5 @
assign mcasp_afsr = mcasp_afsx;0 ^) {/ c5 P. H: ^- B# t/ i# A; i
assign mcasp_aclkr = mcasp_aclkx;4 h; o" H9 ]5 Y
assign mcasp_ahclkr = mcasp_ahclkx;
2 p3 A+ A) Z% M( N% o' |assign axr1 = axr0;
8 O4 M4 i% K; o% i7 F; Z0 m( \3 D6 M) F! k4 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * x- S4 v1 a$ e1 E$ U
static void McASPI2SConfigure(void), H4 d; U9 {1 n$ `- ~
{
3 ~$ b% S0 o1 @6 j4 p, gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 @: a, \3 q j. ~6 V e6 i6 @5 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 t2 H6 [! V# {; G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& m% v. E; I6 p3 Q2 f/ gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ d2 o$ K' i2 T$ O1 E) y6 }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 y- o& P+ Z0 J/ Z* YMCASP_RX_MODE_DMA);- ?# @) l9 \3 V# D9 r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; J) B. T' g9 @" `; O+ xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ J7 C7 K: a; g0 L/ Y3 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: N* T1 a5 r) F$ C7 HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 r# L: [, J* FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # O# [3 S8 `4 N1 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ j4 Z' ^6 M/ |4 m' J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 h, L3 c A: X+ Q1 G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, I' l; h* }6 T. L$ t) f8 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' B0 i; G+ f! A4 F* B2 v" }
0x00, 0xFF); /* configure the clock for transmitter */
- f" S7 ?- U, E: p6 U3 CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; L' u+ G8 _7 P' D% x% T1 P! `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 H4 ^: W0 e* W9 J! N* p' \& q- \$ F+ z% `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 N2 l; d# }7 p! j, G9 {3 ]0x00, 0xFF);
3 k7 t/ i: {4 t5 Z1 o% v+ v M/ T# Z2 F! g, t4 D
/* Enable synchronization of RX and TX sections */
# `0 X- i Y' d: {, e/ K& H" [6 PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 V9 t: c' N$ H% H' A4 Y7 b" _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 o9 W4 q# }# t) O9 s# yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% L- g: `$ L R+ Z
** Set the serializers, Currently only one serializer is set as
- e# V6 `% [2 n! d0 p7 O** transmitter and one serializer as receiver.
5 z3 t7 s3 J( o! g1 I$ `*/& v) c& V2 d0 o4 g' h, `2 O; F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 X# `$ a$ S9 S" M+ q7 m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* @( ~3 Q6 u5 P1 Z( [- |** Configure the McASP pins
8 G; A4 b/ j( D+ b2 n# z** Input - Frame Sync, Clock and Serializer Rx
, Y3 H) A) c; x" J7 R2 o** Output - Serializer Tx is connected to the input of the codec 7 x8 s$ w3 C) e# W/ \9 i
*/
& ~2 h! ~& s% n0 _+ YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( S9 S) o8 N. q! G! e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 t' }! N! [1 Y0 |9 m3 c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 W+ u6 a1 c4 [( u$ }5 u| MCASP_PIN_ACLKX
2 {+ ? c1 @% K% K- s l0 D! c0 q| MCASP_PIN_AHCLKX3 ]6 b& I# n2 n( U& Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! g5 g2 h1 w; k( n C9 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ z5 S7 N- X. x; |2 {
| MCASP_TX_CLKFAIL " m; t( M1 B7 S, H* @
| MCASP_TX_SYNCERROR: L! z+ @3 z# L" f8 f+ B; O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * j) Q- A) @ L. T: H/ {
| MCASP_RX_CLKFAIL
' a5 s" m+ r* R" b0 { Y8 m| MCASP_RX_SYNCERROR # `8 b- V% ~3 w0 R" Y* V
| MCASP_RX_OVERRUN);
* `9 r) b; V% K: \7 q} static void I2SDataTxRxActivate(void)
) ^& U& }3 l5 g$ q3 `5 ?{
% k! V7 Z, ^5 ~5 g+ m& r( Z [1 R/* Start the clocks */
# ^ I# J. C, n. @- G: {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 H! y+ j1 w# j2 ~3 ` i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, q) ?7 x4 o1 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 d9 o3 L& S2 d3 |EDMA3_TRIG_MODE_EVENT);
; J8 O; a( f. b, A X4 K$ pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# i3 @& e, O2 ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 A: U+ k! e2 |7 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 \1 w9 }7 `2 z( o5 _5 B! ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 x m& U" h M) S! ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: n- R; F! k3 Z$ G% t+ o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) D# @- G0 x% X7 g! |" d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- c/ C) E/ } S3 I}
% i& v; w' v- N. x7 L0 S, y- U. I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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