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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& i5 {$ V1 G* a. _: w; O
input mcasp_ahclkx,' R& S9 S. M/ j" F* w% P
input mcasp_aclkx,
, d9 N3 V8 u) L9 u Zinput axr0,
/ a V/ v4 A8 V
, @2 \4 P) [4 T: v: loutput mcasp_afsr," u/ b+ a0 ~9 b0 ?
output mcasp_ahclkr,/ G3 b, h1 ^0 l* F6 q3 P: n# L
output mcasp_aclkr,
! B: ^5 A. N: c8 R1 B% {output axr1,
; U! x* A. [$ ?) E, B X assign mcasp_afsr = mcasp_afsx;
7 ^3 K% n5 a( t" R6 Y, ~2 @# Hassign mcasp_aclkr = mcasp_aclkx;4 Y( `5 F; Y3 X: e
assign mcasp_ahclkr = mcasp_ahclkx;- Q4 @* L$ E8 j) C4 {1 Y4 o, T: K2 [
assign axr1 = axr0;
! _7 h2 T: H" R' ^0 M- {5 j y; h' d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- h5 a8 S7 z+ `: Z3 _, Ystatic void McASPI2SConfigure(void)
7 m& z9 l- c) W: n{7 Z5 t5 B9 w$ }. L! W; u' i1 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( r! V8 |8 R9 I: ]3 M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 u2 a; i. L( U( q7 ~( I0 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 [7 \: j# c+ d3 d3 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 o9 u+ ^3 @+ U! FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 F! O" e& y C( `% z3 @. n) j* D5 a
MCASP_RX_MODE_DMA);
" l+ R& Y0 [1 ~1 M. k5 r9 S3 T sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 S" U) M) h1 h1 c" C1 F. A6 H3 z5 C7 p; z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* k- l7 X, u0 H# Q$ w3 k' o. M( z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + }8 t- z. e! o$ K7 d4 S, g! R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- {+ p# a- Y1 w. x- o; M, ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 R5 U1 u/ {8 M2 M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ Q; }1 J5 M$ o" W# }9 BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' R7 l& x2 \7 y0 W3 e0 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 Q0 M& @$ s/ n* J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& L# r5 j4 U; W" G; d$ e% G+ y
0x00, 0xFF); /* configure the clock for transmitter */
5 p* U6 s' z! ?7 g7 o: r" [- ?8 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" r( l% W6 e% G& z9 mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 ~+ |5 c: m/ c" ]% D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% `& \4 \2 `6 D0 {& {2 U0x00, 0xFF);& K+ Y) O' T+ Y" d* d% H, p
2 ]- H, _4 y# g, u* U/* Enable synchronization of RX and TX sections */
) U4 ]' j' S: B% W+ T- I$ kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ o6 V5 q& z4 D' @2 I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ {$ q$ v( @9 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- |% t8 A( |6 _9 W/ k
** Set the serializers, Currently only one serializer is set as
* E: N( Y3 ~* N8 B** transmitter and one serializer as receiver.$ A! F0 z3 _, V( w/ o
*/' L+ b; Y$ y5 Y1 @0 m$ D% `* I4 `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# x5 B5 j: Q& X2 j1 p7 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* `% D% C2 p# g** Configure the McASP pins
* h7 v$ K) {4 B9 Q; b7 h, G7 y** Input - Frame Sync, Clock and Serializer Rx
1 i L/ X; {. a9 N! g** Output - Serializer Tx is connected to the input of the codec : ^/ Q M9 s$ Y3 C
*/
, i! ?( y$ j7 X% Z8 i3 {3 X/ fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 ]- W& F/ v& OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- K+ M3 F/ D. q7 b0 C9 A$ }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, g* ?8 i9 v! [; c1 {. C1 O" D| MCASP_PIN_ACLKX
, ^, Q, q* k5 c% P% _| MCASP_PIN_AHCLKX/ Q Y2 c/ M& n/ F( }+ n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 Z% f. i- O9 KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. p( V: O+ o3 f0 p( z| MCASP_TX_CLKFAIL
; l, Y, D* s7 D' A, ^$ w N% P| MCASP_TX_SYNCERROR! h1 t. t5 ]9 K8 s6 y2 [$ n! r) I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: p# _; ^* a9 v| MCASP_RX_CLKFAIL
( U( b* u" j- |1 G' r7 M| MCASP_RX_SYNCERROR
0 {& L4 {3 C s1 ^( E/ ~1 a% q| MCASP_RX_OVERRUN);
2 m* p! @4 x2 n, q} static void I2SDataTxRxActivate(void)
- u6 z% P( _6 Z t; L6 a* A{' }0 s* p. ?4 R1 ~2 k
/* Start the clocks */3 m( Z8 ^8 I1 i$ T& K# T# @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- f) f0 j2 H0 i e- ^+ uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( }6 R) Z6 ?- } j! Q& e: [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) a- L9 }3 ^0 \# G8 w4 e! d' a9 M5 R% r
EDMA3_TRIG_MODE_EVENT);& D" n4 S5 }3 x6 ?! p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, j6 L7 n7 S( @ j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ B9 t7 j" [- d* E/ h& ^- g. x1 cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 L; G5 V- ~8 N% G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( _0 ]# |# R# [% R; \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# |9 u% ]$ @; v$ x" aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- Q: |- @; Q5 M) n# I0 f, n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, k# s& h. s5 _
} ' Q+ t6 H6 W1 ^: ]: D$ j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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