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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 [1 Q" w7 M, a. X' ^, R7 J q/ Zinput mcasp_ahclkx,+ _/ r: ~. c6 X: s
input mcasp_aclkx,5 R0 V. L9 e" o" @# k- q
input axr0,8 {2 H4 A1 {4 b( k9 F7 L
8 m% a# M6 o4 V% g9 Noutput mcasp_afsr,
) J2 c. s( O4 v( R; N6 h/ aoutput mcasp_ahclkr,0 ^) f5 w, c* F6 J. J9 x
output mcasp_aclkr,
& k7 L' ~$ d2 youtput axr1,, Y/ Q& }# z! v0 ~
assign mcasp_afsr = mcasp_afsx;$ p" n# G' E* B9 G
assign mcasp_aclkr = mcasp_aclkx;
/ ~2 W: G$ n8 V4 ?assign mcasp_ahclkr = mcasp_ahclkx;, j. L3 \3 P1 Z; P. O1 S* N
assign axr1 = axr0;
* Q( `' I! Q# ?! j# I: |# u5 P4 w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: A% f; i& T5 R& F& ~static void McASPI2SConfigure(void), h; _. G2 ~* b- Y6 R6 e& t9 e
{
2 G* P( \" D0 {% v+ d1 ?3 [McASPRxReset(SOC_MCASP_0_CTRL_REGS);* b# Y( O! K; \+ l3 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! q [; k; R2 H# XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' _ |* x9 L) O& l% E5 R/ xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. [& o. j' Z' E! u/ XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 C, `! q6 R/ m( Z
MCASP_RX_MODE_DMA);
, s# ^4 q3 J9 a' O3 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 N+ J$ v9 f7 l7 f$ i* }3 rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ b8 a( C3 t3 KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( c1 F2 }* Q3 ^ [$ g/ k4 v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% Z" w! `- G. ?$ u* R BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % D. f! S' ~( m5 w. b4 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 J6 [0 E2 H, j1 Q/ j* r0 qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' F8 y: s$ {' E5 @; ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) z, d' e# C: y M. \% S+ w( o$ b2 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 }; N9 z8 {& E5 C9 A+ v" M
0x00, 0xFF); /* configure the clock for transmitter */7 \1 W- z6 z. u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- b( U. D' y) b: g8 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - g. Z4 \; p9 a0 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 L" Y1 c9 j. T9 [* x0x00, 0xFF);: L1 p1 P! B$ e6 f# f5 _
9 M9 e* {7 m! L+ ]3 D. z% m1 e
/* Enable synchronization of RX and TX sections */
4 n, R- r8 H! f( o2 P B( |% |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; _: `( F" N9 K- V5 y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 }' j9 |9 |/ g6 |) }1 d% cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* a+ | D* g. w' F! X% g: ]** Set the serializers, Currently only one serializer is set as+ Y1 A6 O3 O7 r$ I7 ?
** transmitter and one serializer as receiver.2 _5 P" M% O7 y& ]3 d
*/
& ~7 t' _4 I( f9 D& s8 fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 e ]4 v7 q6 w$ Y' Y1 q8 h8 U) qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 V* M) c# `- t3 X" j0 L** Configure the McASP pins
1 V( j" t% f1 h4 q** Input - Frame Sync, Clock and Serializer Rx
. A: l. q4 {- W/ c- ~** Output - Serializer Tx is connected to the input of the codec 2 p0 P( ]& J Y8 a8 x* M
*/
, Q" C, T! K5 F: h0 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, y% K0 D% c! z8 \6 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); R% N, r: v* h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! C! a$ z8 x) Z# ~: ~0 u| MCASP_PIN_ACLKX
5 ]+ Y! q3 q* [( x| MCASP_PIN_AHCLKX
4 [; c \/ ^4 V& ^2 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 o& t2 d1 X- y! z1 t9 E/ g& aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) y5 r4 J8 P* f' ~
| MCASP_TX_CLKFAIL ! \9 V7 x: k0 ~% g1 L
| MCASP_TX_SYNCERROR5 q" J& K! L2 U, G6 M$ w6 C P8 {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: Q% x) J; t. l4 A4 M| MCASP_RX_CLKFAIL
W# p5 F% \6 [2 Z4 I| MCASP_RX_SYNCERROR
! c. y: J0 ?2 f# @& ^( g w/ e7 h| MCASP_RX_OVERRUN);& h1 k5 ?6 n% y4 I: f
} static void I2SDataTxRxActivate(void): y, q9 L: s# V( j4 c
{
+ u( K' Z/ J# [8 i/* Start the clocks */
+ o$ k0 W. Q- w4 N `0 M& xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ d% D4 w3 D0 T/ Y. k; _" t- LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ f7 U" p. v8 Q) S" f# ^7 I; G3 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( \- h0 K) A. q% e8 h6 ~
EDMA3_TRIG_MODE_EVENT);
' ]0 _3 W- z" a- \: {5 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 l# }0 j) o9 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 |; T) ?$ r! W! f+ dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- ^- q. x7 F6 F. Q" H ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 e I; r3 o9 a: G) s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; V* |/ e& R; ^3 I: _, V& V4 F! RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. T8 [# c$ d( BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# C% u: q4 V) L( p; ]6 ]}
' I& L5 T( o7 w/ F/ O/ ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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