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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, L$ Y. t# S9 y3 Y( rinput mcasp_ahclkx,
& K) V) U0 [( o$ }$ V8 ?) ~% Yinput mcasp_aclkx,: k. n6 t; m5 _: _2 G$ H7 d
input axr0,
: ^, n4 U9 H- W2 ~: j6 v' @1 } h: g% y1 v
output mcasp_afsr,5 n$ ~+ E: j7 ?8 }) C b2 q
output mcasp_ahclkr,4 O6 e8 }. X9 @
output mcasp_aclkr,) m" p/ a2 V; v) s
output axr1,& `% s3 i w* D( r8 C. n: N/ m
assign mcasp_afsr = mcasp_afsx;
$ ?: z# W- w8 L$ n6 ? N- Yassign mcasp_aclkr = mcasp_aclkx;7 G \3 m2 Z G- @9 p# W) g
assign mcasp_ahclkr = mcasp_ahclkx;
6 I% }) J) ^0 \+ @. A" aassign axr1 = axr0; ! |% ]* [' J* P* ^! p
[3 n$ U& i6 O. G4 U; ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 F3 y9 Y6 C& r9 l0 x; N
static void McASPI2SConfigure(void)4 x9 b9 n8 w+ L Y* m* S
{
& n# L5 O; ]" e) v! C1 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: h; t0 y9 o4 X* e( y5 b, VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, b, n7 v. ?' ~* e$ [' [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) O7 ?0 h6 I+ N; n+ S X5 b1 R4 w- o+ \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 H6 Z* {: i3 I$ ?9 \7 u- u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 w/ e8 V- C I$ R6 }
MCASP_RX_MODE_DMA);
9 v4 |. V% I) ]7 L L, v- J1 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( m$ q# w/ N/ d$ w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' q+ Y7 q( K( lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " }! ^0 q5 T1 V% { v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 w9 Y5 b2 l% Z ~3 V( dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 F2 a; ^: q4 ^1 Z; @; @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) ^) j1 a/ `4 c; D6 s9 s0 S# W6 vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 A" C- i- i$ N$ h ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 l6 W4 J& W" S9 r8 N5 I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 V2 e! \9 _/ V o
0x00, 0xFF); /* configure the clock for transmitter */3 E" [- C4 W* c/ C* I1 v5 G {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& R8 W) ?. e+ b$ c- R7 B% D9 V. v% @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 C: U I% x) J" S1 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 Y7 b$ i% Z/ y, p1 L: Z
0x00, 0xFF);
9 B* \- V2 H) P% l7 X3 X6 z8 p6 x: Y! g
/* Enable synchronization of RX and TX sections */
2 Q6 E7 C/ a" F* R4 F$ J5 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 _" l9 q) o# tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' w; Y* h, ]5 ?2 I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; x* X" v1 F# j; W( k2 {, }** Set the serializers, Currently only one serializer is set as# j7 |2 o+ q3 T/ M+ Y, O/ I" y( I( X
** transmitter and one serializer as receiver.
4 P. s* z) s% B% _*/. T3 y& ~: `- o, s d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ h5 K' E/ R+ I j8 rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 P& d6 G1 q; w- |0 T** Configure the McASP pins
# r D% S, I" |! ]; M3 T1 T** Input - Frame Sync, Clock and Serializer Rx
, o) n) g$ v& K) L** Output - Serializer Tx is connected to the input of the codec 7 q# F% d0 @/ K! m3 Z
*/8 J, _2 S# A/ w' Y) q2 O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" _* U" _2 U3 n4 `+ aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" x+ G& y. o. a9 T6 D/ m9 T( v; }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) j; S7 u# b9 m% Y| MCASP_PIN_ACLKX+ ~, |0 {! s# U) o6 h
| MCASP_PIN_AHCLKX
3 q) p6 Y- T8 C. @8 F0 B9 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! x, [# W9 e$ WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / P2 {4 z0 X% ?
| MCASP_TX_CLKFAIL
( ~& x. I5 }5 \& l) O: g" u8 {| MCASP_TX_SYNCERROR+ c3 Y4 C4 ?" \" E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( ? Y% u' ^. O! g1 ^( \0 M% b. A
| MCASP_RX_CLKFAIL
, M" z" f" `& L| MCASP_RX_SYNCERROR
7 B4 a4 c! E# Q| MCASP_RX_OVERRUN);
0 r3 q- `1 J6 w# v0 b4 e} static void I2SDataTxRxActivate(void)
' b# k2 R0 R% I% k: W/ h{' {1 r2 _- ~7 K6 l/ L/ _9 x" g
/* Start the clocks */
1 G' P; |0 s( }* r7 `1 |& iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
e" y4 B+ S, I5 x+ K0 `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 a7 }6 l0 m! k! N& T3 i. ~- iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( j0 v3 y: o& w/ o4 H c
EDMA3_TRIG_MODE_EVENT);% D- p7 @* i8 _5 _1 {$ _0 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 y- y* _2 C4 ]1 S- |" f' {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ k8 c+ \2 Z0 E$ `! F: F& {9 k/ j; P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ u6 k9 J& E6 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 L5 M1 M( E4 k) g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 r9 ]. a. ]1 T$ y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) X+ N1 n; r5 B. q& [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- m4 L9 n/ Y" M3 f8 l4 Y+ ^/ N$ J; V$ p+ P
}
1 v2 t- p; g7 r" t4 @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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