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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' C8 o+ c5 ^( T" [8 G
input mcasp_ahclkx,
! ?# D2 h4 Q$ H5 G3 jinput mcasp_aclkx,2 O3 t) t; i! i1 L
input axr0,
7 G9 x" Z6 k9 A) r" t2 r
$ S; |5 s+ }4 Z' I8 l: F6 s* coutput mcasp_afsr,
. D( p D2 F! g$ y& x( W& Y1 Youtput mcasp_ahclkr,
9 f2 y4 z4 Z4 ^+ U6 H4 Goutput mcasp_aclkr, I. K: X) t! k' h! b" P: x6 {
output axr1," z" E' y6 H- _7 V- }4 G
assign mcasp_afsr = mcasp_afsx;
5 E! a6 R. { H$ T+ k4 x9 e0 c4 eassign mcasp_aclkr = mcasp_aclkx;: b6 g1 U6 _5 k( ~+ q, @( Y* Q/ L
assign mcasp_ahclkr = mcasp_ahclkx;
1 L; q4 Y) s& U( z& `2 jassign axr1 = axr0; : m5 f* y0 r+ p+ i
+ o' W; S! l7 ^7 A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& i2 z! A/ S# n2 z+ R9 D4 Vstatic void McASPI2SConfigure(void)- ?' i$ q. L, I' E2 r* z# [
{ J. `0 Q* c: J. r/ u. e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 v# N6 L9 U% XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" l) {) n+ t6 ?2 ]/ j) YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- ]0 V, r( e* ^- l, v) `( o j1 u+ gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 h$ ? J6 r( }9 \& P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 z2 `2 x1 f6 N6 {# F& Z
MCASP_RX_MODE_DMA);
! X V! n9 O6 {1 W: ]( e# W- AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; J4 i: g8 G6 U; s8 C7 v; U! _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! @/ K7 o" q7 @. eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 O" H w, q8 c0 b/ E7 \& HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ C5 N# w) C( k& n) m' a) d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' I' g- X7 [8 n _6 @) G( o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 a; Y! K! D8 K+ c; eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 _( v8 E3 c/ k& |5 H3 _7 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & V4 f, O) ~$ {" \& T5 v g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( G: M, B1 W) { A% x% {1 {0x00, 0xFF); /* configure the clock for transmitter */& P, Z2 Z; r# [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; J/ _5 C5 S9 `1 W, ~4 a; KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 ]" P( l+ p x7 o. w6 k1 H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" L/ l+ s( B( {+ r9 l% B0x00, 0xFF);
/ }3 j. |) ?" u
. W1 f# A9 V; d: G/* Enable synchronization of RX and TX sections */
, p: B2 `% r0 D( CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. Q, Y1 u9 \: H( C; n) T# x8 y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 u9 P c; y( G% |2 @: D: k nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 I: u" R$ ~0 t3 e! u" H; j** Set the serializers, Currently only one serializer is set as- L8 {0 {0 i* [; _" K
** transmitter and one serializer as receiver.2 n! n: }! ]9 `$ e
*/1 D( W- @4 o( _. I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* e1 y- m: [7 w9 L5 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. P* m. i6 D$ x
** Configure the McASP pins 2 d7 @/ G+ I" E
** Input - Frame Sync, Clock and Serializer Rx$ B0 h+ ?' ?/ d! q6 I) _
** Output - Serializer Tx is connected to the input of the codec # k1 r, W P$ M2 k8 J7 N/ _
*/( j: [5 a7 h& e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 y' q5 |* a8 n c6 c8 e0 ?5 X$ ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! _) x" F {5 a3 BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 f6 H( m; Y0 V" E( s8 w* c( n
| MCASP_PIN_ACLKX
6 q9 z; P* @) j2 Q4 `1 ]) G$ o| MCASP_PIN_AHCLKX
3 n0 O8 S* t8 n% x" _) Z6 N' l3 _* b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' O/ F' |( o5 n/ S9 j3 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! U8 Q* Q+ s% \9 j| MCASP_TX_CLKFAIL 2 Y5 i @- R) q
| MCASP_TX_SYNCERROR6 _( e c! X9 {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 o# R2 D8 E# h& F( K6 p$ v| MCASP_RX_CLKFAIL# }/ `4 ?: }3 z+ D
| MCASP_RX_SYNCERROR 4 @* G0 m( S" b& `& y Q
| MCASP_RX_OVERRUN);
$ l$ w$ Z% p- ` p; A: P9 c} static void I2SDataTxRxActivate(void)
5 {6 C. v2 [# p- P9 P9 E0 W3 [{
% O9 L/ p2 _) ~# C) Y0 n9 F8 ^/* Start the clocks */ B. t" u) S( z4 }8 w, S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: q8 y" K5 M. J3 Z! \/ KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 D5 k4 V/ j$ i8 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 W% ] a4 P& M( M$ zEDMA3_TRIG_MODE_EVENT);$ k) G/ D" B' T9 o) x1 g4 |2 z2 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 v- ?' G5 Z& R, c' N' b. L! A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* c: B! E8 u7 C2 v& M5 B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ L b4 P! ]6 R) MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; \; m% n+ r, }/ |4 G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( c f, @, U( F/ A; G! c: b9 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 l3 y7 i9 Z8 }; `+ ~: |, aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 t$ H, g* F8 K% G1 U: ^8 i+ w% h}
9 G' ~$ }1 s- ]8 r a" J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 E' l, y1 L; O; K( k$ k
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