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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* `) c6 i0 b, Q: f: `, jinput mcasp_ahclkx,
+ O$ k9 L1 J# Q3 n; iinput mcasp_aclkx,
' `. O) v5 [+ [4 x' ginput axr0,
+ O! ~' T) ~, h0 x3 C( T4 b2 e1 n% I5 u, i- F
output mcasp_afsr,
+ I" M+ C3 Y3 b: b, qoutput mcasp_ahclkr,8 i* t# M3 ?0 d8 P3 f
output mcasp_aclkr,
# t; p/ u" \1 Z) `" P% I a! x/ routput axr1,
- S$ b/ ?/ h! |8 c' t assign mcasp_afsr = mcasp_afsx;8 z4 `' o" ~/ x& w6 }
assign mcasp_aclkr = mcasp_aclkx;) ^3 D" A& D3 j+ r# H7 @
assign mcasp_ahclkr = mcasp_ahclkx;& U+ R3 c0 N; {* c7 w2 r* q. y/ a2 g
assign axr1 = axr0;
" Y5 W' ?0 f8 z" d1 N7 y K9 J1 T- g0 R' L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & \& n4 e+ P$ Y8 C
static void McASPI2SConfigure(void)
" o3 O* B6 Y; t& u{
" m1 @9 A8 u0 m- }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
v- @5 ^# V* w+ LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 s1 d* C5 J/ L& y9 \2 s% F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% q$ v! O, H' B0 c$ d0 B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ {! M9 `: w2 m3 ~2 n( vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 z8 k- s% t0 U0 Z$ y' K# B+ x: hMCASP_RX_MODE_DMA);$ o+ Z* S o) |& ]9 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% u6 X! P' b) JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ l# K* y9 V5 W$ U V- o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
\' p O! }! {7 @/ RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- j3 `" M( o. SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! L( J6 j& ]$ `) T" `6 N, J1 A/ V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. C6 L% _( q. C% J5 f8 M; R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. t! C% }1 ~0 \& z. _- R5 d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 i$ A2 ^. V6 C2 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* L+ n2 b+ ^4 h0 f1 S# D0 F T: H0x00, 0xFF); /* configure the clock for transmitter */
% y" i ^9 M9 lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 i5 F* ?8 Z" ^; n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % L. M/ Y+ e# d" {2 j [1 ~& ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ @) ^+ U, ~, M: D# ^# I
0x00, 0xFF);
9 G) D+ J/ e0 E/ L1 F8 R/ L$ h0 m
/* Enable synchronization of RX and TX sections */ - D, a- b9 d$ u( v' O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ v1 Q Z/ W% D/ G% C9 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! X: a9 H8 J5 W# e) ~7 p2 Q& }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' V6 ]- b- t: J5 }. N' w** Set the serializers, Currently only one serializer is set as
6 u g: ] ?0 S( m4 d( H3 ?** transmitter and one serializer as receiver.
* D9 ^ C6 `" ~) ]1 Z*/
, w2 @4 x8 m* d+ B" a7 `4 oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' c2 X1 b" k4 o: L0 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 z7 n: \) \$ {! `$ g* v** Configure the McASP pins
0 @, N: q: }1 @& C" c** Input - Frame Sync, Clock and Serializer Rx& t: ?! f- u9 i. M/ \
** Output - Serializer Tx is connected to the input of the codec
' v5 X% |: @1 V& J' y$ `% b*// o, i$ t! s% `2 Z5 W4 h; r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); ]% R( k+ s3 k. t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; C) d. r+ g3 L# T2 \6 h9 S z6 d) nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 \$ m' Z) n0 g Z- `( _+ e# Z| MCASP_PIN_ACLKX; B1 M+ @2 _+ U6 g) n8 t
| MCASP_PIN_AHCLKX- @( `( I* @7 H, y9 G, T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% Z7 z, n& Y5 K# M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 C/ K# ^3 L4 u
| MCASP_TX_CLKFAIL
" A- s" N+ [- k% J| MCASP_TX_SYNCERROR. Z8 V7 P | b- g7 Y/ p# }! w0 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 C( B3 n J* R% {| MCASP_RX_CLKFAIL
A; ~' X7 n4 K! {8 p& i) z| MCASP_RX_SYNCERROR
. A: k* V; A8 q& D| MCASP_RX_OVERRUN);
/ }5 w5 Y( @+ F7 t} static void I2SDataTxRxActivate(void)) J6 d& l0 c4 d
{
8 l G/ j* ?/ i" {3 A/ G4 y/* Start the clocks */0 a' u! f' e; d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 O3 m& W9 L1 F3 h% V$ n( WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ S' `4 v0 z, @" O- F9 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. @% a- a2 d8 B4 e. ^7 u" [6 q
EDMA3_TRIG_MODE_EVENT);. {: X% g" E7 M+ r% f8 T- g' ?" a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 U4 |: m4 |* d6 N$ U* A. k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 Y3 Q' \: A+ a% hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 G/ G, j+ w. }, e/ y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 Q. ]0 l0 x$ @1 _* e# W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 I/ ~/ M, m! ?/ D& P/ GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( t& x8 N0 v# ^; w \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' j& }* N( V* E( r} $ v4 N1 X* a4 D/ h P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + L% i+ u; J2 P( I
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