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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 A9 }2 ^( W3 i5 j/ O
input mcasp_ahclkx,2 L" W3 u8 U P, O$ p' T
input mcasp_aclkx,) ^7 C! X$ V( B& u" d
input axr0,
6 v7 @4 p9 ?( D( m4 B
6 K9 s7 o8 \/ M4 qoutput mcasp_afsr,
/ k+ }1 M1 p p9 Uoutput mcasp_ahclkr,
' F3 C" r) ~8 `! Z/ G9 y1 voutput mcasp_aclkr,1 A# O9 Y' ]3 Z: B) }. M
output axr1,
0 X* \9 x" ~; ^5 c0 _ assign mcasp_afsr = mcasp_afsx;9 [, Z& X- W/ @9 K& o/ G
assign mcasp_aclkr = mcasp_aclkx;
1 {+ L ?9 L. Q0 W% |* Q$ Xassign mcasp_ahclkr = mcasp_ahclkx;
! b" i+ o( M$ \assign axr1 = axr0;
1 u% N7 A/ [5 G7 o8 g" {4 L3 y2 P% j; O' A6 i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' y2 ^( {8 l3 W: L5 L
static void McASPI2SConfigure(void)4 x" d6 L0 j. y G* w6 @1 X Z
{
3 C, l# M& U8 rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* @, H( ]( R+ q$ f z1 F; aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 [4 \6 ~* k; P5 | B2 pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 t$ C8 {3 u. Z' Q* D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 T" J; S" S8 _4 b- w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ z5 S) M& l' x+ UMCASP_RX_MODE_DMA);
6 Q. s3 G" X+ B0 q- UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 L1 _6 b6 U' D2 [. N8 w0 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ J, G* ] @! ]3 `, J% S* JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# j! D4 F9 f EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# {; E k- y( _ v$ Z# }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 _" q( z- S9 r& J d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* X) i) Y/ A% C: x- x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. c/ G) {% H# u. N T1 ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( I! e/ Y5 e4 ~: H+ E9 N: bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 k7 l5 ]# \: k9 z' Z0x00, 0xFF); /* configure the clock for transmitter */* H: `* y8 i; b% k$ |+ z$ {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( b1 @8 t" O0 ?4 Y% W& v0 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# V0 G5 O( R, tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, U9 D( @( \2 C) |/ k' a2 ~; G" u; `! D0 @
0x00, 0xFF);
6 x( q, k9 w) `' I2 `$ Z+ c" h, B% h# i7 }8 u% X$ w$ R
/* Enable synchronization of RX and TX sections */
) r! `1 h# v* U$ y! S' HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( A" |. g) g, n9 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 m& @: w; G; o! t" n$ e/ ^% ~- l3 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 B4 n$ O" m5 G# g1 y** Set the serializers, Currently only one serializer is set as
# f( S. E& F( A, Y** transmitter and one serializer as receiver.' M& |# b( E& ]3 @
*/
, [4 r! T/ l2 I: Y- x/ ]! mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& l/ o+ ^! t$ T) A$ z7 G; \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 A3 f. ]" @( y" N7 i** Configure the McASP pins / {0 f( U9 b# e8 @5 _9 F; `, r6 ?
** Input - Frame Sync, Clock and Serializer Rx
O7 p, t7 G! q- m& Z- O# v0 V** Output - Serializer Tx is connected to the input of the codec
! d" V, w; i0 ]$ ~*/1 a% ]0 y6 }" Q$ K! k; Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! Y" B; z; f- G. M2 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 D/ G1 U5 j" f& z ^2 j: Y. OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* Z" F% D2 | `0 _) b: E+ S/ ?, a# C
| MCASP_PIN_ACLKX
9 W1 m( P8 t6 m6 P- H| MCASP_PIN_AHCLKX
' t% C1 j7 z8 v( m- n) M' n4 l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) m2 v( ^8 V* ^( t; l0 ^' U! lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% y7 b" l9 z" J! t| MCASP_TX_CLKFAIL
# m; c$ E* F9 |8 [. G/ C| MCASP_TX_SYNCERROR
# T- U8 j4 w7 r$ J% d# S1 G9 u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # {% X2 {9 j! f% ^- k5 H$ S8 Y& t
| MCASP_RX_CLKFAIL9 U5 p2 H; h9 Q
| MCASP_RX_SYNCERROR ( n0 ^; M! W2 V, z/ @. Q. n* r; h% o- }
| MCASP_RX_OVERRUN);
" L( A5 U& h' b} static void I2SDataTxRxActivate(void)6 G: c8 Q( {( p8 _5 z3 J# I1 Y
{7 Q9 i5 g( M( ~4 W
/* Start the clocks */" b# ^, |* E. m0 v6 ?4 I# @1 [! X" ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 ]5 {# J- H0 K' BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 I6 h7 ?. ^# V6 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 v, j, G0 ~/ n# x! Q$ Z2 k9 H; XEDMA3_TRIG_MODE_EVENT);
, S# a S* V# Q9 o& ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ F) h% h& ~" G7 E8 m4 N5 Y' uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 q4 ]! I, d, z1 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 I- G* C/ T' l) h# FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' D$ e7 ~& ?( |) ~! {$ Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 }9 ^' f, X" V! b( h2 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 a1 v; t. b8 t* c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- k: p' j" {5 A" f
}
T7 D. e$ X& @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , q0 E% Q& e/ [+ t
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