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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* s- b I& a& b5 I4 V
input mcasp_ahclkx,
/ j( r* j, n# G+ W, f) q! ? Oinput mcasp_aclkx,
3 [6 z. M4 N/ Z9 \0 S: Rinput axr0,
" s1 n Y' {* {* c6 B) R6 U: H# C/ e, C) _6 i
output mcasp_afsr,
5 f# j S/ J- @output mcasp_ahclkr,1 ]. k6 ^2 \4 W8 M J; @
output mcasp_aclkr,
: l9 M( S& Z* C Poutput axr1,
+ Y. | R. R6 f$ ?- E8 E assign mcasp_afsr = mcasp_afsx;
5 O* M# Q/ c5 q3 r7 [assign mcasp_aclkr = mcasp_aclkx;0 U, H0 t5 y& F' ]$ o% U4 A
assign mcasp_ahclkr = mcasp_ahclkx;
0 @1 H8 Q" N, Y% \8 n5 C8 k/ K/ Dassign axr1 = axr0; & v5 t$ X6 a# R; `# W7 v% K' a
9 ?7 v+ I' o5 z& T3 m7 \$ p& g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # d4 S7 T, D9 K2 W
static void McASPI2SConfigure(void)% C1 I$ l% i# W' T3 z
{- C8 @0 w \( I4 U7 n& X3 ~- J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ }# [3 r4 ?, Y* p1 B2 {( C, ]1 G4 |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ \- S/ ^8 c' E1 P& TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* H6 l6 w3 o8 o2 a {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 a" i. D V& T+ g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 w8 j7 V5 p( t! R& ^9 OMCASP_RX_MODE_DMA);
" n( A" Q4 @/ eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) C1 O, H: s# X+ e) A% g4 y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# `, y# }0 _' E5 k. N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
V: ?- \: B) g( X$ \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: s- p/ u" ?3 A9 ?" r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 Q# y/ |2 y4 M9 g) p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 N" V9 V) D/ W f, H0 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# K1 r M! F: b0 S4 _( c; b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( X6 I" \4 ?) O G( p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 V6 @9 p0 C" S3 A0 O7 i# L
0x00, 0xFF); /* configure the clock for transmitter */% K7 ^* e% v$ }6 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* Y; Y4 ^' J% B. r# F f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 }4 W' V5 h7 \/ ~! A6 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 `' r( Z- ]# Q. V& j
0x00, 0xFF);1 Y! _& g& C6 V7 S3 H
9 \/ m m* _, M/* Enable synchronization of RX and TX sections */
( q; {( v6 G; |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
d8 M4 }, l' o8 c5 _* X6 rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; v1 }0 u/ C9 S# `3 n! H# D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: s y G* p t** Set the serializers, Currently only one serializer is set as1 N6 ]6 E$ t. d: Q0 C$ s9 z
** transmitter and one serializer as receiver. \+ n9 r, n4 X
*/
# v+ s6 v0 {4 q# L S( Q9 w4 Y4 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 l' f' w+ ^$ I" U2 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ ~# `" U4 _ J5 s! L7 c1 _4 C& @7 X
** Configure the McASP pins ! S2 i( `* s/ p, [- S7 N
** Input - Frame Sync, Clock and Serializer Rx: I: q! E+ Y3 k( P* h& h
** Output - Serializer Tx is connected to the input of the codec ) E6 K. T6 @+ a2 J, D! Z$ h
*/4 C5 Z. b4 l q0 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 Y) m' U2 l3 Q) CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, s" o( V3 \8 `+ L" t" q" R5 k6 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ @: @: W; B; X
| MCASP_PIN_ACLKX
3 r( q- J& H/ E* t+ |9 ?6 t5 a| MCASP_PIN_AHCLKX% B% W7 M$ j1 g6 K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, t. R. ]5 F: D4 a: k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % j; t6 e, ]+ h3 c, D4 ?$ d
| MCASP_TX_CLKFAIL . ^" v% l1 c( _* `3 {" g" A
| MCASP_TX_SYNCERROR# E- R1 e/ x8 r/ c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) M' q) j: F0 D, i( J* w
| MCASP_RX_CLKFAIL$ T/ J. }% m6 d( I: k5 Y" [+ }7 r
| MCASP_RX_SYNCERROR
- L3 x6 p. E, e" F9 H* t| MCASP_RX_OVERRUN);
, e! t; M f+ g3 z+ Q! B} static void I2SDataTxRxActivate(void)9 K G6 i p5 _3 m3 c
{4 R8 K1 z% }2 u% K h( D
/* Start the clocks */' p7 e& O/ A$ N$ n8 ^" u B* O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: g- u+ l" q9 E& z5 R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% H& Y7 d9 u z3 I. \; `% Y% x& vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; ?! J6 [/ T6 e% r+ a( K( A5 M- VEDMA3_TRIG_MODE_EVENT);
% D6 [ A9 V- iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' e: b3 f- j+ Z' c! BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 b& W# N1 h/ ]0 j& S! w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 k2 X5 p+ y, T+ `+ VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- e! l/ [2 q2 z( A- o% `( v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 O D* s5 b4 t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" x1 s1 k4 {" ?$ S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 T# ^4 K% ]: K% c- T* O* u
}
- T# b9 f# t) h2 q1 G5 L4 s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( B4 R r% X/ a) s3 Z: ^+ b# E
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