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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 {( X5 a/ p! f; ginput mcasp_ahclkx,& D3 }$ x& F. F! g0 D
input mcasp_aclkx,& {0 ^! V. H( T; G l3 Y
input axr0,) e9 u' F% ~- q
" }4 @! t: W* _2 I7 w: Routput mcasp_afsr,# ?4 T1 k' |0 Y# l+ {7 B
output mcasp_ahclkr,
3 Q( j, ]) i' d# ]5 P e+ f/ Boutput mcasp_aclkr,
+ h, f, n; h2 G3 [& S. ?output axr1,2 h% I! ^6 K% |' l1 e! x9 L9 J, a
assign mcasp_afsr = mcasp_afsx;; o2 n+ b8 D* f4 c+ C
assign mcasp_aclkr = mcasp_aclkx;
# ?; Y0 f$ q: o) ?# I5 Wassign mcasp_ahclkr = mcasp_ahclkx;$ u% {: H1 k) G8 u$ b2 I
assign axr1 = axr0; / f& U. j& Q% m
+ s+ D4 f% T3 {) g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 U/ P. b1 g3 B- V. U! ^+ H4 s
static void McASPI2SConfigure(void)
$ Q; @$ x, G/ F5 B# g{
% y) }0 L( o9 c0 t8 V8 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
w) y1 ~1 d# kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) ]2 A) q7 S0 r# n# o$ |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! I' r* e& h; l% i/ I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# w" p6 L) H/ T# n1 f9 }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* g" d1 a) N- F) [4 H! cMCASP_RX_MODE_DMA);
* p2 n8 e$ \& gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: N. Z( c* Z- N1 C6 wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' f2 h6 G3 O- E3 i+ Q5 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ h `3 Q: l) b5 l& PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. A2 S' Q6 g+ }& S* D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 E" m- D% V* j: Z* R; E0 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 d0 V* g" I" j" V* O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) [7 @; q! P/ v/ k: l7 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 u" n: X! Q4 Z8 ?: I5 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 A ]3 ~; B) ?( l% e: Q5 R' J0x00, 0xFF); /* configure the clock for transmitter */
7 n7 L$ u8 p IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 L0 D0 U" Q. n+ d4 _/ o8 U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 p, q+ c! ]1 O# s6 V1 I. [4 u$ `: zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' x+ H2 d" m$ p W+ u
0x00, 0xFF);
% }2 h" @0 o1 J* K* ?. u- x4 L9 L: \/ D9 P2 n W' `- [
/* Enable synchronization of RX and TX sections */
6 u* k$ s; f8 b; l0 B$ l7 [, EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ O3 ?* o, q2 nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 m& r* [1 n& n) l. z) S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! S" W" v3 o- e& }0 Q) O! C5 j** Set the serializers, Currently only one serializer is set as$ Y+ j: \" t0 N4 D' s( C+ E4 c* r
** transmitter and one serializer as receiver.
; a8 r% g& b+ ~9 V! ]7 ]- V* }*/& x# z2 v& v6 t& Q. {- ^) m$ I8 R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; V+ C7 B% b+ ]: M% s' z4 y/ s0 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! [5 T6 i4 z! D8 ~** Configure the McASP pins 5 {( y+ h2 Z( ^ E0 c" J7 K
** Input - Frame Sync, Clock and Serializer Rx: A- r R W; A- J% E
** Output - Serializer Tx is connected to the input of the codec 7 L l+ g( z+ r2 H' A- }, G
*/
7 C( u5 d% c, M/ d1 K' E% [2 o( Q# ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 G9 }6 s+ o6 {8 K0 A9 t$ {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 X4 m9 s( x C+ m1 z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& S" Z: g/ H5 _| MCASP_PIN_ACLKX
( {( J, _, i7 W, J$ |# s| MCASP_PIN_AHCLKX
& l; J0 k$ z; L* _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: l2 f# k$ J; e, B1 I( g, c @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ I! I8 b2 J3 h# a6 t6 u1 Q
| MCASP_TX_CLKFAIL
! Q" j7 U6 f( P: Z5 q/ E v| MCASP_TX_SYNCERROR3 b+ I5 B: l( c. [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 T8 m2 L( P* ?8 }2 S
| MCASP_RX_CLKFAIL
3 v* `) ^, ` {3 l0 k| MCASP_RX_SYNCERROR
5 F! e3 M0 l* I3 v# O| MCASP_RX_OVERRUN);. i5 }1 X; e o
} static void I2SDataTxRxActivate(void)
* l! ~* s, _1 ?, S{3 |9 v( C' x: c% t b
/* Start the clocks */ u1 b3 N# O% A/ m" W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* K1 i$ V3 T( _; R, U! A$ r' U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 F- U/ v6 \% j0 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, ]$ G3 a( w) Z' A! I, x' s2 w$ ]
EDMA3_TRIG_MODE_EVENT);/ f `% ^2 w" R7 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ C( k5 k( X3 ?" }7 a+ [1 n4 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; Q9 D% [! p6 ]" S1 h [8 J* y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 J- K& \* T4 d% o1 ?" U( kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- C" o% t: `: R5 u# O4 q+ a: fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& v& M3 U! O1 k2 [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 r! {' m, w' {) ^ P, A3 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 n0 l' i0 l; J o( x/ {
}
4 O& i# j, Z. x" R* p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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