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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 a# ^* h6 l: d! U
input mcasp_ahclkx,
6 g, O0 V( L6 w a2 Z% x: Binput mcasp_aclkx,
2 k+ v8 M- H o: I2 Pinput axr0,* Y* M1 k6 p- y! Y5 ~
- X4 o5 {( b9 _# \1 E9 Loutput mcasp_afsr,6 y- X% T8 X* i: M- W
output mcasp_ahclkr,& s. j8 K) W9 C
output mcasp_aclkr,- K$ ~ N/ _9 p# c
output axr1,
h/ ?' H0 j9 l( C assign mcasp_afsr = mcasp_afsx;
7 I9 Z/ X' R9 t& b5 u5 z( [& massign mcasp_aclkr = mcasp_aclkx;& Q6 R# B6 |% B" @
assign mcasp_ahclkr = mcasp_ahclkx;4 E- T6 i* \. G' u) f2 t
assign axr1 = axr0; # D: A3 A2 X# g0 X# I+ K3 D
( C1 D1 y0 e8 T2 D# p8 W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" j/ u+ P, Q+ s0 f! X+ q9 Q7 f2 [( ]static void McASPI2SConfigure(void)
# i. K* c" W1 x e8 Y$ l{% V4 N4 L, E- s N- J2 ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! z4 O# `4 l2 l) a8 aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 u9 i/ k7 g6 O+ F* ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 i5 I- K4 O; [/ i3 LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 R* m1 {9 U+ G& J0 h6 j9 p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 Y6 u6 H7 k) [3 ~& g6 i4 O. \
MCASP_RX_MODE_DMA);. g6 r5 X" E; ?( i* T1 _" ?2 A9 a$ N& Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 q, n; K3 H) m0 a4 U' J$ J UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 c( i4 a- k8 z2 `; y0 C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 N' ~+ N- V) Y6 B$ v5 K1 rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& t3 w% I2 c e/ Y7 K& Y. ]; N, l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / |. s8 G$ d) g! B$ p% D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ H% f, \% |' G2 F/ h0 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ N9 |$ k. L: Z2 P" L0 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ h h" ~9 L y- q5 I. |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 E" z) R5 ?+ I& V0x00, 0xFF); /* configure the clock for transmitter */
$ Z: X# S, G+ f( [' kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 b2 p0 [+ L& d8 U2 B, JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! O o9 b3 F2 g s; a. S' GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* N3 d$ g# v' w1 t4 S9 v$ L0x00, 0xFF);3 S# g( K& e0 B3 J' l2 t
: ^; V4 O: ~/ Q- @6 q, W* r
/* Enable synchronization of RX and TX sections */
; j0 a9 S; d0 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, \- v$ | r i5 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 i$ j3 T1 }4 D1 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" m" r' s1 c5 c8 r
** Set the serializers, Currently only one serializer is set as
9 ~5 n* G" s4 p9 E H- m** transmitter and one serializer as receiver. u! e. u. K: e) [2 P
*/
" S2 F* u9 \* R" j. m5 \6 K% D. mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: T5 V9 j. L2 [3 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, Y0 p" S1 N+ P2 f** Configure the McASP pins
) h4 f& T$ P) w# V** Input - Frame Sync, Clock and Serializer Rx
- q/ P1 W- c& M A! J** Output - Serializer Tx is connected to the input of the codec
* p0 d( [, d8 x' i*/
) V1 |" ]% C: `8 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 r3 M% A4 ?; P4 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 q5 ^3 T, c' e# A/ n/ j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 g! Y5 c% L, q+ X# i! D( ?& t5 I% W| MCASP_PIN_ACLKX
# K9 t2 p9 |3 C% Z, V5 q$ `| MCASP_PIN_AHCLKX) k3 d6 s% d% g, e$ E0 m6 g6 L9 `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; C, C$ Q) O% ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , W! Z6 V9 V* ~/ Z0 d7 x0 K
| MCASP_TX_CLKFAIL : X9 z( ~- O I; ?8 K9 T
| MCASP_TX_SYNCERROR
% Y+ I% _$ h1 ?/ l* ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 s& J H8 _2 r3 ]+ m
| MCASP_RX_CLKFAIL% A; t9 l- l% W/ _( P
| MCASP_RX_SYNCERROR , k" @% J2 Y' S6 Z1 m- _, _& q+ _7 v
| MCASP_RX_OVERRUN);
: x8 M; ]% u: X( K6 _- s$ S} static void I2SDataTxRxActivate(void)2 k" r1 K; ]6 J" r9 f- v
{
6 j: Z2 x. m/ i/* Start the clocks */9 I8 a+ t! T5 y6 }- `0 G5 U2 q: o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) k5 ]8 v5 W4 G4 z& a+ m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' E0 l4 g9 `3 J( M' L; Q5 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," H! @) H0 b+ B- W* F
EDMA3_TRIG_MODE_EVENT);4 V4 t9 }' P, W9 R& V4 e; t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ ]* U1 ~* a, k3 A4 H( yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& {( | U6 G G/ {! h/ zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ S+ E5 s3 ^2 Z" I o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- |7 ~% T5 ]4 G' rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- ?# @& @+ d* m, k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ g& W; Y1 K' [, F$ j6 e+ _$ L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 [4 j0 W: S) k' n* e! r6 l6 X1 [} ( x# L2 I5 O6 u+ r$ D8 A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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