|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. \/ T. E- |0 i( s" Sinput mcasp_ahclkx,5 ]" U3 |8 P- } x6 K" |
input mcasp_aclkx,
; e$ C/ b5 N" v! D Cinput axr0,: r+ M! i7 C3 X k7 H ]5 E/ }7 @
- Z9 J( H6 \: z
output mcasp_afsr,
' z a; L% Y1 ^; b+ r3 X- zoutput mcasp_ahclkr,
+ x: W2 C* z+ A) Y9 z. G9 I9 coutput mcasp_aclkr,
& S' E& R( @- t1 q+ u# R4 J4 Uoutput axr1,
* a* a$ t: o1 n. ~0 X1 h0 ]0 H4 o% G assign mcasp_afsr = mcasp_afsx;
. c B) f" m% D# I" vassign mcasp_aclkr = mcasp_aclkx;
{6 n$ P0 B9 y& Zassign mcasp_ahclkr = mcasp_ahclkx;
5 ^6 P4 B" e- F& \. ^# E: H, S' X* Bassign axr1 = axr0; ) }& _; }5 L. f' u* V
# t4 X j2 E' v2 I2 C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! {/ T; U& h- S8 V
static void McASPI2SConfigure(void)
# d8 H/ V, z0 g1 [{
2 C* T. K5 Y: q0 N& K- E8 l0 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 h; t* R# t6 U' G& ^/ ~( ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) j0 f: q$ h: J5 r4 {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# e' B% E w' u5 `4 P" \7 m2 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ l) Q3 B' _% C0 f3 L4 R4 e; V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* l. ~4 W! Q% [# y
MCASP_RX_MODE_DMA);4 \: ^ Q, ]" h, J; h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ?. f# }) x3 y. y8 e1 D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, {8 ?- ]! v/ M1 X8 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 w- P# W9 O5 z4 u" _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% @0 X: a+ d; `$ I- lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 F3 p# M0 B8 O. m# z- \* N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, Z+ q6 X# M/ J- R1 i$ `4 kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& D% ~$ ^1 R& C2 I. v. V6 S: Z9 H9 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' l5 E3 a2 e2 @8 n0 A6 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 ]; ~, D+ A1 y) F0x00, 0xFF); /* configure the clock for transmitter */
% q+ C' e3 `+ n) S+ MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 C& c" h8 I* }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 Y4 u% Z2 g" b8 ^+ z) r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, C! h. P" N# r3 h* b" k) o+ z$ n
0x00, 0xFF);$ _* g6 z0 F2 `& J5 Y3 v: v
/ m, v4 F% b6 ^
/* Enable synchronization of RX and TX sections */ : x1 A+ ^; R7 Q. O8 e4 {' u" o4 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, d/ [" J7 ?$ E% P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) R7 F1 ~! Q j1 X& Q8 y/ q9 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' H: ?$ w) u7 f# e) h* G1 D** Set the serializers, Currently only one serializer is set as/ [0 }5 R& \9 U, b9 f+ I" g
** transmitter and one serializer as receiver.
& c. T. o) M, F: }9 V& s*/
0 i4 E5 e" G+ O) ` v( t5 a# pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* r7 F: J' X6 o8 U0 T* O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 ~$ `, x- d/ C) `0 W
** Configure the McASP pins 5 o) K6 {) @# A C7 T
** Input - Frame Sync, Clock and Serializer Rx
s6 ?* ]0 ]0 J6 Z2 r$ t9 g9 W** Output - Serializer Tx is connected to the input of the codec + \2 k' S {6 d8 ]% t+ N& E$ a
*/
9 T Z2 X" h c! R+ U- v0 a9 KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" ^, C |( Y3 F; x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- z3 y9 v; ^& s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% v# i$ o0 l2 p
| MCASP_PIN_ACLKX& k9 @2 i. [, w8 m
| MCASP_PIN_AHCLKX0 {* F, W$ n- N" y2 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- e! j! x, f- r3 g( cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" F Z4 p" N. L& a& }| MCASP_TX_CLKFAIL & K- g) @8 J2 N4 j, b
| MCASP_TX_SYNCERROR
D* o: W: f0 k* D: f( {5 [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . B; E8 |- w" ^0 o( e( |6 e
| MCASP_RX_CLKFAIL
! p$ d& e3 q$ I! R( \! `| MCASP_RX_SYNCERROR , Q) O" B& N7 J; C+ J+ Y
| MCASP_RX_OVERRUN);
8 V4 ^* S2 j" L; u0 a# c0 T, c} static void I2SDataTxRxActivate(void)9 t9 f' [( N6 ]& M2 v
{' l$ R o% W3 A6 h- v
/* Start the clocks */: F: V0 M7 u8 U/ y0 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; `0 Q0 @ N& ^ ]6 u2 Q0 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) y1 u/ T2 d1 Z1 s3 i9 p1 o; W# ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 H5 }7 ]! J4 |; m! _: @3 T$ w
EDMA3_TRIG_MODE_EVENT);% @8 P) I" I+ g E, P' I) T* W; J; W3 ^( S$ z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : N: e9 o& y/ D0 a: Y9 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// L8 z& x; q2 a9 M* g. h$ H% J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ x9 C: `0 s2 m% Z. jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ m, V" |" c( K& ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 C% ]: l N: O( K* G" d: {+ dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: r8 B. [$ B0 i* U+ K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# I! W( q& V! d$ J# R} * ]. Z/ ?1 x$ B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & T4 @' A8 h4 V: P
|