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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 _8 Y( R$ A' ~) D( e. X, U l4 `# H( n
input mcasp_ahclkx,( T1 T) H D2 \
input mcasp_aclkx,
/ j0 X! }$ a; {' E, E( A7 dinput axr0,
+ r9 d, O- \* w' S) {6 A; B
( R s- V! L) Q8 t" loutput mcasp_afsr,
: X( M; R3 l9 Q% |4 moutput mcasp_ahclkr,* W5 Z8 E7 M+ U8 F6 B5 B! R% ~
output mcasp_aclkr,- D$ O' _ h; |: j0 [5 M7 p
output axr1,( L+ \+ n K! ?5 j
assign mcasp_afsr = mcasp_afsx;5 f1 H9 f% e/ W1 e( W/ ]; W
assign mcasp_aclkr = mcasp_aclkx;
4 D9 X' m; t+ o W* Gassign mcasp_ahclkr = mcasp_ahclkx;% i7 t1 R( ]. j! I+ J+ A1 Y
assign axr1 = axr0; 8 J; ^4 G3 }3 ]
% @' u. p5 ~7 A# s! e( [3 Q( B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) T7 F' | A# h2 Q, h8 ^ cstatic void McASPI2SConfigure(void)& I) i, {; n2 r" j
{& _5 s) h3 D* |' L' K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) i! V R! T$ d! \( H m" N. \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ Q1 B' V2 n9 a) ?+ S% fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 h- }3 G8 ?3 {( T" a) wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( D( z) d, y k& g+ X, PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ [6 P5 Q1 _% y% e: [MCASP_RX_MODE_DMA);
; r7 Q% s6 F2 NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& ~5 c6 ]/ {1 ^- h/ Y3 A4 wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- G+ P3 M. v) Q; l& M4 T, a8 A6 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, u+ `- Y! u4 J1 h6 a uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 R( v Z5 F# `) HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * K1 }' |3 u% c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 Y. N, E# I3 v$ A+ t, ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' q3 Y9 b+ Y, S4 j- f2 K8 J' PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# p1 k L5 R) J6 \6 V9 Q( J8 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ l& U8 O5 D9 A/ n
0x00, 0xFF); /* configure the clock for transmitter */
0 M) V x) [8 M+ `$ T; R1 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ k$ I9 u( x4 L' h( `% ~* R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + t( O$ F0 r- i) _$ _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& W3 D8 u0 j$ Z0x00, 0xFF);
9 E$ P$ `5 g7 G6 i* `7 Z) D) E$ b" o9 ?% V. L& n5 N( `% K
/* Enable synchronization of RX and TX sections */
1 e, m$ e1 X' O. [. D& tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 t* [$ L& \$ ~8 Y! N L n, Y }; p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 e/ F& N3 j% @1 R q; lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- }3 H$ ?7 _: M; [** Set the serializers, Currently only one serializer is set as- x! K! e5 b7 i. I+ {& E
** transmitter and one serializer as receiver.7 I& I. Y9 i) G/ S) Z
*/
" s9 j9 W5 Y- [% D( ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 s0 ~; t$ n4 WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
^1 h$ Q) G" r& ?# a9 v9 [/ Y5 k** Configure the McASP pins + W, \" D5 H/ y; X- K. O
** Input - Frame Sync, Clock and Serializer Rx
6 R7 `+ I" F& W** Output - Serializer Tx is connected to the input of the codec 4 w, {0 X/ K' x, u
*/
# E% H- M& ?3 \# f: R# I* OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ g, d- C# H+ j. A3 ^4 Z8 q6 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 D; X/ H+ {6 ^9 a* R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: R/ Q2 R/ [8 _3 `3 Y1 M& M8 k) {
| MCASP_PIN_ACLKX, p1 u; [( Z8 I* N) L
| MCASP_PIN_AHCLKX- n$ |# s# @5 w" J u/ u" s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 ^( g% ^( D& U+ S: aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 F4 L- k" j# Q
| MCASP_TX_CLKFAIL 5 }% D5 ?3 [( j8 N$ @5 R
| MCASP_TX_SYNCERROR/ p0 u6 d' p$ p9 A2 ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) r5 r9 ~& g' [+ m6 k% ^| MCASP_RX_CLKFAIL
, _& ~. r2 A$ {! D! ^4 \8 g8 Y- v| MCASP_RX_SYNCERROR ) m2 H9 v& ^$ h
| MCASP_RX_OVERRUN);' ^: K& W" p; b4 O
} static void I2SDataTxRxActivate(void)/ E; N# y+ e j
{
! X% Q$ @& \1 T( H# b/* Start the clocks */
8 ]1 O$ b4 @4 b; D o4 FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 j9 {2 a% ^) ?1 _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 B e3 d, @ fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& A9 s- {# N* x' t6 n! J
EDMA3_TRIG_MODE_EVENT);* H/ S7 I. ]8 a8 U3 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 b1 b; } s8 ~+ V" T! yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 \: j1 p- U" gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 n$ w, L0 p3 \ r/ J8 R: y+ s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# f/ ]/ {' c" c6 _/ o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 o4 q/ `) `$ [5 V. B# J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ g: ?1 M3 j; g) g1 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, o$ g" V k3 f" ?) ^
}
0 m& B( T3 M. z% i9 T% K$ Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % c1 l [# Y0 s! e1 T; j9 W: A
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