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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 q+ w5 W, l7 I: c
input mcasp_ahclkx,* R# U- x1 |1 u. g
input mcasp_aclkx,
; L$ q: c, X f/ p) B( Kinput axr0,, a9 D/ v9 I& _/ E8 G3 w' ]7 `0 z
w. Y% X5 X2 j# @
output mcasp_afsr,
: ?5 u- v4 |7 n3 h$ l: W# }output mcasp_ahclkr,
( Q' r# K# M1 v6 X3 z- w soutput mcasp_aclkr,2 X r: W- J$ w/ ~
output axr1,9 F3 v# F; K$ G
assign mcasp_afsr = mcasp_afsx;
1 t: s* i) O4 y% o& m q5 Passign mcasp_aclkr = mcasp_aclkx;
* D: _2 K8 |# f- jassign mcasp_ahclkr = mcasp_ahclkx;: y% I# d! U4 y- a
assign axr1 = axr0; 0 B2 U6 i+ M/ [8 ?! k
( z" z% o! A( h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 g$ ?+ O0 H( c, bstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& |- c% p1 U9 a" d" Q) N6 ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 T: X3 r. c# K$ ?' qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; e# D- {6 o1 `( b) O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% H2 O: j' g1 Q7 yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# X$ I4 w+ o4 @( ^4 r
MCASP_RX_MODE_DMA);
% `2 b6 z( U8 i Y: x: {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ q* e6 g. h8 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 @4 c5 E# s- d' ?+ U, C- o, oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 K+ Q; B! B& s0 H/ u0 v0 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ k: _/ J- A2 f$ K. k ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 D7 b1 _3 C& X# C! Z! D4 GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 I: v2 r h9 j% j% _$ z& D, M) W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# L7 C9 y- l6 [4 ^. R4 m5 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; z/ @! s r2 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 U, e6 @( {- f1 U( ?; F0x00, 0xFF); /* configure the clock for transmitter */9 o" T7 Z( b' D- q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 O/ @4 D; R1 sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% ~/ ^* W7 X$ A1 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 }2 {' O" e+ H0x00, 0xFF);
8 W; H/ d, f& T, I; N% J" ~( B$ W {4 p
/* Enable synchronization of RX and TX sections */ 5 X7 v6 R/ Z* L1 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' q" }: @/ q% \; A; U3 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( u4 S3 q1 S1 P( J- cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 ~3 \6 v+ e+ x; S** Set the serializers, Currently only one serializer is set as
4 Q9 Q( ]8 X" f1 [" o' C. ~+ h% |** transmitter and one serializer as receiver.
h0 [7 k2 O# M6 Y7 h8 F*/
- x5 |2 M% M4 C& ~* zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) X0 a6 A7 [8 p; _ `% Y' S1 O3 F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 l! g2 G& l# N( L7 Y2 c** Configure the McASP pins + g- ^0 p( ~1 |' i& K+ v6 b
** Input - Frame Sync, Clock and Serializer Rx
- N; h N0 I$ n1 ~% a( q** Output - Serializer Tx is connected to the input of the codec 1 A# j3 v7 p2 w
*/
3 Y% ?3 n" s; ^& kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 ~6 R- T( ?! G' h4 H( m3 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 r/ K7 N0 U' ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 ?. |0 y. X9 r1 Z) x8 l, S| MCASP_PIN_ACLKX+ Q# K) A! E8 ]
| MCASP_PIN_AHCLKX
2 d# M# l0 V% \) |+ W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
W7 L+ w7 T u) ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 ~6 Z; j" G' Q1 o# o
| MCASP_TX_CLKFAIL ! V% |4 h0 }. M0 ^( K A- |
| MCASP_TX_SYNCERROR* S- _) X8 D5 H$ L+ q$ j6 y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % z5 {! r& r* e: u* e
| MCASP_RX_CLKFAIL3 Y) U6 S R0 E$ G3 ^ O
| MCASP_RX_SYNCERROR 3 ?* y& O2 I0 s; h. {! l* E. T
| MCASP_RX_OVERRUN);* f0 |% I0 ~ m4 D( Y( H
} static void I2SDataTxRxActivate(void)
) y- R: X# [, _* k% M# ^/ t{
( q1 p) k; j7 i' P; J/ R3 q/* Start the clocks */( t8 _4 x# o K& z& ?" f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ L' z) l1 ]# c8 b/ K! oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 h2 P2 H+ x6 W( b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* m7 s/ o& `7 S3 @0 |0 Z- s% `
EDMA3_TRIG_MODE_EVENT);, ^' v8 g* p. k5 A, E3 w( ]; `; c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 c7 N" K; r6 F3 H" _2 b4 h5 F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! ?$ r% c, ^: hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( g" L5 V$ z6 i( F5 b. e$ }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# E0 z$ t2 t$ c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% T# ^! P- ^4 C) v: q$ k. R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" Q2 V7 ~/ {' w' P4 F2 M4 G9 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# K& i" z* ]: |' C}
: l: z" k$ |* K( B- d& F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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