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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
F9 ~1 _$ ^2 F6 P" _# t# M! |) binput mcasp_ahclkx,
2 M* T a- z6 ~# E' pinput mcasp_aclkx,
! o: f# I O/ _( q- n; D4 b8 Dinput axr0,9 ?- Z( Q) c+ a( W) i
6 v3 {6 Z' Z/ W! u+ \! Foutput mcasp_afsr,
' C% u9 O1 r0 Z' _7 ~; ]; i8 youtput mcasp_ahclkr,% e5 L/ A3 J- P, A! f5 W, N
output mcasp_aclkr,
) ]3 i, Y" J0 h* k# ^: Z& z- J& Houtput axr1,; p7 P9 n Z: z
assign mcasp_afsr = mcasp_afsx;1 q6 m3 ? g6 d3 m. `7 P, A
assign mcasp_aclkr = mcasp_aclkx;" E* e1 l5 O# b
assign mcasp_ahclkr = mcasp_ahclkx;% \' t; k: |: q) R
assign axr1 = axr0; 7 c5 k- m8 k; J( {( f* i
. b3 i& r3 \, J2 r2 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ e8 x8 U8 J& D8 L1 f& cstatic void McASPI2SConfigure(void)
6 l( S$ @# S: K{
: c1 i" h0 l j9 d: G9 r0 PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 ^3 j" t1 `6 F- T) f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ P) w4 F0 }- b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% P& m3 G+ e. Q3 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, v3 K4 F; H7 A0 j' eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ k6 K+ b2 |, N% @) L- g' B
MCASP_RX_MODE_DMA);1 v* i; z q( H0 d* p/ @. Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! Y" C8 ^2 m' t0 B0 C/ xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# {2 s% f8 P3 Z6 p. NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! y y) R* I+ y# k. z9 ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% _- |$ b) a; e2 ~& B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* O! S: ?9 n+ DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, p) x$ i7 g q2 a* z9 i; B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 |4 a+ J/ v. N! jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# d" N& h0 d2 j: RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 X8 H7 n. D4 z# S5 e0x00, 0xFF); /* configure the clock for transmitter */* r, V: @( D0 r- G" y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 `: ?+ y! K' p: }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
l/ G3 w. J( }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% }) i5 |. J0 F% I# K0x00, 0xFF);
" _% p6 r O) N" o) H
# W: ^, \" I, H. Q- n9 s/* Enable synchronization of RX and TX sections */ - m& D' Y, C H& T' t- [, i2 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 I0 J8 y! D* j. Y$ t8 M# T% RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 G/ H: T R2 z9 HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- o D* s1 Y7 o% d `( G* q; e** Set the serializers, Currently only one serializer is set as
5 Y# m! C& I7 {2 \/ c' u3 \. L** transmitter and one serializer as receiver.& R1 b4 ?* W3 S- L
*/
+ `+ T9 y) `5 Y& f0 vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" d: D( Y4 E4 L u/ p$ w }5 Y# p2 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! N# B$ u$ G& R4 o( F" O
** Configure the McASP pins . C1 b2 I) h1 M ^, _9 W
** Input - Frame Sync, Clock and Serializer Rx* [* G1 O% o% F% S: F+ I9 a
** Output - Serializer Tx is connected to the input of the codec
6 ]- i, {7 p! m( M( E, t3 Y2 V& G( B*/
3 L: h* Z( C" q) v4 {* A4 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% u: t% e; }; W: x8 D$ H# rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# r2 E. L# @: b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: d! u: f5 G1 E4 {8 @( {| MCASP_PIN_ACLKX3 P* t. v! s4 P
| MCASP_PIN_AHCLKX2 K) F2 z6 w- h1 [3 |( j7 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ j4 ]. _6 ?8 ~7 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 n% o5 u# u8 [+ }1 D! u6 e| MCASP_TX_CLKFAIL
5 f8 P: Y A: x& t; }4 f$ `| MCASP_TX_SYNCERROR" l @% k% }0 p9 L5 r. D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 P) L( n9 {6 A& A# M6 k! b6 |3 \| MCASP_RX_CLKFAIL
0 {/ W: j9 G3 Y1 l1 W# \| MCASP_RX_SYNCERROR
' K3 M& {; j+ m2 A0 G+ d- \1 Q| MCASP_RX_OVERRUN);& } g# t: Z6 f$ _
} static void I2SDataTxRxActivate(void)5 [" ~- u) D, m" i% K1 ^
{: C3 T" w6 E$ M5 o0 B% z3 T" w, o
/* Start the clocks */: a: J! D& ~; c8 R L" x$ ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* z; F9 R/ d. {& ^+ |$ ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) h! ]) _+ B/ X( B D) c4 c$ h% g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! ?: d$ n) {2 M! `% CEDMA3_TRIG_MODE_EVENT);
' O3 Q$ C, Q$ r% s- @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" I) J8 J2 J( ^: ~6 Z3 AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 l. C( x$ D* g% `" E g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 `$ r% ~) V6 ]8 A" H; a$ D8 H, _+ t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' l3 W- k# T! K0 J$ B/ ?: Z1 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 h( S" T3 S" D" G, cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% G: O) b U+ P& Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) h# [' r' l2 ?2 b+ a4 u}
7 ^& w+ ~9 _! x7 f# R6 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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