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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' f) s [+ ~( F4 Z# I# s
input mcasp_ahclkx,7 J: ]( O8 c: D) z3 H) z
input mcasp_aclkx,
% F' w, J# C& S* rinput axr0,) W2 L( ], V: V# Q5 J5 ^
4 T. o: `+ ~% ^9 K5 ?
output mcasp_afsr,' W) _: m% z% t- Z+ I
output mcasp_ahclkr,, r( Q8 e l' d9 O7 J# C: H
output mcasp_aclkr, |, u, l% {4 }0 U3 d* I9 J1 Y/ N% ?
output axr1,
' G5 g. a& v. Y assign mcasp_afsr = mcasp_afsx;
U! u. ]* Q# p O5 E. Fassign mcasp_aclkr = mcasp_aclkx;
! j$ l# c; V- |, _8 K* }0 @assign mcasp_ahclkr = mcasp_ahclkx;
$ h c9 X0 G6 Z9 D: u9 T; J x' N3 Passign axr1 = axr0; " [3 }+ T, C, d- \' S/ T
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 K% X- _9 [; s/ s8 r! O
static void McASPI2SConfigure(void)3 v8 ?, b; C5 ?! ?6 P. r% [
{
, R F. g2 @2 H# XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- I+ x: r" @/ r& H+ U! }$ R2 M9 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ o% W ?4 K' A# [' f0 GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; k. c3 o0 E2 n7 u/ T9 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! p9 E6 a# h( m1 T! F1 B! k% D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ O* q3 u$ a; _8 f2 k
MCASP_RX_MODE_DMA);
3 k J; K5 N# m' ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 a& P& b1 W7 X/ I5 R7 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ v2 }' n7 J* M6 T1 |- n4 ] @' `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: G9 b! W8 z7 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 ]2 M) t. O0 W5 f a) n4 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- A' C* z5 `/ O# |' GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ e' @( Q- e1 F3 }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- k2 [! v. B, x. jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . ?+ F) |' d6 G$ O0 v7 P s$ ^# {! t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) R* P$ j& g3 h/ D1 s/ }0x00, 0xFF); /* configure the clock for transmitter */
/ M0 S# ~2 u, j0 R7 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 b( V4 T$ S5 G+ t- m- W: Q: H# b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * r" k5 H. U: o5 K8 j0 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* Z7 ]. J- k: P( j: w" S1 A0x00, 0xFF);
' G% Z- K- n7 D7 u+ h. f. p# Z. J5 N2 k3 a
/* Enable synchronization of RX and TX sections */
7 v- s* B6 V- i$ o/ ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 Z; r, S5 R+ j1 V/ W k, pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ?+ A& O3 U5 C1 L' G$ y. nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! U( m+ Q' [7 n* M% K% P" m5 @% h
** Set the serializers, Currently only one serializer is set as
8 q& k8 s8 y, R9 E- l6 O** transmitter and one serializer as receiver.
1 p$ ]4 i; e4 _*/' {. |/ Q. t& K p9 [& e# i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 Q# P5 n, t: o. \5 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* D& U. D7 x0 U" v5 Q( n
** Configure the McASP pins
8 V: l0 b: ~9 e: ?** Input - Frame Sync, Clock and Serializer Rx
/ c8 o/ ~ Y1 g7 `/ W$ F7 c** Output - Serializer Tx is connected to the input of the codec 5 N- {* |% ^. p6 h. m$ }' D
*/
* L4 P: {9 ^, _6 N; c2 I3 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 o6 G; |5 R4 }1 OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# b( V G$ R2 ^# K5 A, U4 ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 o2 I s# w j| MCASP_PIN_ACLKX5 G# h' g, ?1 ?" r; \. x9 y" E
| MCASP_PIN_AHCLKX
2 `+ P" t+ o) M+ m; d3 k# W( y4 R" Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) K1 n* m2 v/ n& d/ w' _5 Q: [7 B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 `- R& m h F( J6 I2 T
| MCASP_TX_CLKFAIL
* x7 y1 k# B) O [, I+ I. _| MCASP_TX_SYNCERROR9 q1 D; q! c" s# S$ `8 |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 }$ X* n o! d5 n9 Z| MCASP_RX_CLKFAIL& q" L* F6 V5 C# B2 c' V
| MCASP_RX_SYNCERROR
8 ~" [8 {6 C* M! k3 e| MCASP_RX_OVERRUN);; q' v8 A2 v C3 G x8 N
} static void I2SDataTxRxActivate(void)
& S# O% k9 w" p8 B8 n{: | _$ T' ]& Q% ~
/* Start the clocks */
2 b: }5 M C& v. i9 D. |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 B5 v4 ?5 C- sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" j9 v2 w& j$ k9 S5 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. V; |% c) d ~# ^EDMA3_TRIG_MODE_EVENT);
1 A7 }& A- |6 I; D7 J* pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* o- U( \ x7 A5 [+ w; ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* S# a2 M8 `' E7 g/ L' l7 ?! |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 o: Y- w; Q- m, b% ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ ~9 m: g8 d" x! O1 Z1 F* i! B" k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 z+ E, a3 _8 c P2 K6 {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! d( F0 w- |7 }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 d3 v k% _2 r6 }* K: C# \4 E}
) P% s1 x% C, X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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