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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 k" O2 t6 {- V" rinput mcasp_ahclkx,: }% h4 ?) v' j+ w/ ]) _
input mcasp_aclkx,
8 @( s( A# a( p* f7 ^6 Zinput axr0,
) v! F3 n2 @1 Q8 G. S( y% @3 J# P$ N% d2 F0 w4 I. _/ l; S
output mcasp_afsr,
' `$ B! a* U* ]4 b- i3 m+ g' Koutput mcasp_ahclkr,
- S0 i2 W( ?$ P! y/ C" p; [output mcasp_aclkr,
! o! o! \! q& h: P( ]output axr1,
+ z0 o2 p( U" o& U assign mcasp_afsr = mcasp_afsx;
5 t4 A0 t# C+ c! eassign mcasp_aclkr = mcasp_aclkx;3 L0 @$ N* W, q/ p
assign mcasp_ahclkr = mcasp_ahclkx;
- \ x Q V& D3 j2 Fassign axr1 = axr0;
1 |' }0 v. T5 ~* ?4 i4 d0 L6 U6 l! d$ Q7 H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ d8 t( P8 f+ t- W- x1 b' T/ Istatic void McASPI2SConfigure(void)
% x! k; ~* Q, @- b% W; g, ^{6 ~+ g: G1 q! V# l, R1 n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) ~/ t2 j! c5 L4 P# nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ @. r" v1 Q/ L% N5 i k# k, U3 ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 L- _9 G1 b: z, l$ k! n7 M, aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" M% Y; D. v. f! x) _6 IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 p2 g" o# ?2 u- NMCASP_RX_MODE_DMA);
* |( v4 |) I5 H) ` WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 _1 J# s4 ^ f" J) \' r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, l- O0 O9 q5 V5 l8 A0 n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " k$ w( L# Y3 d& N9 S& w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' p" r u8 I7 v4 X3 r) DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: E9 p4 ^3 |) e; f* FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 Q( H8 t) K6 q: E' ]0 I4 |: x* D8 {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; \$ }$ U3 O6 G2 H: \/ R. @; }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- n. ?5 \9 n3 M$ s6 G3 z2 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' J* C# m- v1 `3 y2 L" p7 y7 t$ O8 r
0x00, 0xFF); /* configure the clock for transmitter */
. A9 m7 Q1 W3 ^* T" S' c# {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* a, _% W. D/ {! @ p/ q. AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" b y9 } H, N# j3 V) _8 v0 t g6 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# }; _! f" S' Z' V9 ^
0x00, 0xFF);
. D! x& p4 E7 L! m$ x6 ~
! z2 _& B' _' _* x9 h/* Enable synchronization of RX and TX sections */ ' I8 n: U. d- y1 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; O& z- s% J" q+ t9 X, zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 D' u* r' K I' w9 A0 `& ^% vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
}) M$ W: b5 F/ K6 n+ {8 I** Set the serializers, Currently only one serializer is set as/ m( `" n) Q0 q4 X3 \. r
** transmitter and one serializer as receiver.
% M+ o% s1 K5 O- K9 F+ h2 h*/
+ W6 Z0 L: a; ]' B+ vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 a( E; I) x9 q8 v% h8 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- \3 ?# R1 C7 c0 S9 d% u** Configure the McASP pins , r+ S8 E/ P: G
** Input - Frame Sync, Clock and Serializer Rx
1 B% o4 q- N% u/ u2 f! B** Output - Serializer Tx is connected to the input of the codec 6 z, ~: _# x* N& \
*/
2 u& i! ?$ Y' _4 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
g* F. n g1 ~ Q" BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ e7 d& g% N' D: U1 m+ P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 J& p0 Q$ p) ~* W! r
| MCASP_PIN_ACLKX1 b; h, H) f. L4 h, ^
| MCASP_PIN_AHCLKX6 M- m6 I9 V+ B4 P+ W$ k1 d- o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 ?: E/ O8 ?* U$ e' {- F8 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! Y4 w% `* ?6 b Z5 {5 D| MCASP_TX_CLKFAIL 7 H6 Q* Z5 @9 d, N! {
| MCASP_TX_SYNCERROR
) B* S3 S/ j! i8 f8 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 m7 _# q/ l6 a) u `| MCASP_RX_CLKFAIL
, v7 r8 l- a) t7 g, k| MCASP_RX_SYNCERROR
: c- o f2 c! `& ?& x, x7 q+ m| MCASP_RX_OVERRUN);7 W2 D' e b; g {8 D
} static void I2SDataTxRxActivate(void)4 R$ D; I- Y$ }, A% N# y; X( A5 X
{
3 } u/ t) o$ ~1 M/* Start the clocks */
8 R. x4 t5 E) O5 e$ H( {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' y8 I* c$ H S9 X/ K9 Q; [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" j4 [6 v8 r$ {! g7 j3 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% n( N* K5 y0 A, d/ J* O4 p
EDMA3_TRIG_MODE_EVENT);- X0 V" n1 U9 _( ~7 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 w6 o+ i# }0 F; J9 `: g1 i& K/ h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 ^7 L# @+ b2 m2 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 X5 U8 [4 Z+ ?7 A R l H/ b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 v4 P) H& o" y1 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 p0 B* ~' S2 p. a. m2 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ o, `8 |" q, O& vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; A$ i8 F/ @0 Q! |
} 2 g) R3 H$ o. o' R3 ^+ i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) p) Z7 [1 p' \" r% g$ t" H% k& f
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