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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# u7 N% O: z: a) c+ ~( i
input mcasp_ahclkx,: [0 I( k+ I6 Y/ u; P* h0 n
input mcasp_aclkx,
3 V0 J7 i* D: [6 vinput axr0,
: O/ t% W' G, U5 x5 D7 M! m
5 ~( a" l2 ~- i7 c: b1 coutput mcasp_afsr,: X1 V9 c# u4 `& h1 B1 P6 }
output mcasp_ahclkr,
: {: _5 |+ z- m5 a1 x2 ]- Soutput mcasp_aclkr,
9 E( H) m( V& houtput axr1,
1 V) C) K8 t# U7 s assign mcasp_afsr = mcasp_afsx;2 t: q4 @8 G( ~/ H# d% p
assign mcasp_aclkr = mcasp_aclkx;
4 Q! @! ?! O) m$ h& M; kassign mcasp_ahclkr = mcasp_ahclkx;
# T6 h9 v! f- m. t/ ?( t) Sassign axr1 = axr0;
Z, P4 Z, ?6 b8 s' x9 F4 N4 \: P/ Y/ n. L4 y( S/ B" h) u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' t7 }# G8 U/ {' P. J
static void McASPI2SConfigure(void)# }% e! H1 F, l" ^) w
{
, M v1 p# F6 z2 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ D; F! o8 e7 F) W6 P' t. E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 w9 j2 b- d! Q9 r& B: A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 |. Q+ z' I2 t0 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 [3 T5 ~6 a; c. W4 _. x0 Z9 g$ gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; R* v8 f7 [+ j8 ?# g$ cMCASP_RX_MODE_DMA);% Z ~6 B2 y) f4 Q9 R# w8 ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& a0 _, s" c' E6 r8 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' x, U6 |, x1 }0 y' YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ b5 W" J0 X$ v* D, r E" P6 D% g3 r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ n& c2 n; u4 c6 ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! D; D* B2 j+ P' b5 K" W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 Z: h7 Y5 c6 W% J$ U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* F/ s$ k0 x4 o( D( H9 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % l) W+ G8 f- Z& R. ]( R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 E S: v& s% D8 `+ u$ v/ o" s0x00, 0xFF); /* configure the clock for transmitter */3 b. z, E2 {3 y7 O3 z! ]0 S& y( M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 z* e6 o' c5 |7 {: c( E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! h6 M# j5 C6 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, N9 U) G* D" V S
0x00, 0xFF);
3 s: b* t; Z" s4 ^, Z+ u- N
# g% |/ h! ?6 J5 ], H+ {8 L/* Enable synchronization of RX and TX sections */
' }+ Z' Y7 @* B! v4 O: ~$ hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* ?5 F) X* C2 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 Z5 B! J* k0 x5 V- GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- G# z8 E$ J. \9 d1 s0 q) k** Set the serializers, Currently only one serializer is set as" I; B% `4 _# v% N8 x5 c' |* P
** transmitter and one serializer as receiver.7 E! R8 |9 H* Q" f- s( \& A2 o/ P
*/- `: k2 g& Q( h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ r/ O# ] L1 Z" c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
{$ T, e( C+ Q** Configure the McASP pins " x$ l- p: L0 r5 j4 ]: }0 M
** Input - Frame Sync, Clock and Serializer Rx; ?) u6 L+ p/ }) x+ a3 _
** Output - Serializer Tx is connected to the input of the codec
+ K+ G% |) K& D& L% X*/9 Q' a( D0 \- I5 I$ U2 O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ @: [! `3 s. B; g' bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 A- q/ J' S8 `, `6 E$ p5 H- q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 q8 q' v% Q. w! u" d| MCASP_PIN_ACLKX
! L) g) c. E8 S. k2 t2 [| MCASP_PIN_AHCLKX8 [: f6 ^2 B& B. V% B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ x0 Q5 a% V% S& w6 Q% k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; y$ g# W/ U9 J! ]
| MCASP_TX_CLKFAIL
& ]/ d! p# I s% l| MCASP_TX_SYNCERROR
! H3 h Y- D1 H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( w0 }7 o% R0 E
| MCASP_RX_CLKFAIL
: K! p8 K R/ H| MCASP_RX_SYNCERROR
3 b& K0 {# Q6 {' ?' S0 ~| MCASP_RX_OVERRUN);
7 r6 c9 z% ? r7 a, D9 ?4 X} static void I2SDataTxRxActivate(void)
6 y3 o2 V" Q, ]& |. p{
1 l9 h- V+ C: r! P/ I. c4 Z/* Start the clocks */
& l8 l2 ^/ g% g2 m O( yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: C2 e" u- j* ~; l7 D3 fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: y1 F: V$ L7 F1 G Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ w9 |0 }2 t1 W
EDMA3_TRIG_MODE_EVENT);% I/ B# w8 d* M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 e7 z) t8 L. e( s+ T6 t! A4 v4 t: \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; k) t( ~+ }- j! U- {9 Y2 U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# W2 C0 T( N0 W5 x4 `5 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 R Z9 G$ e% s+ w/ h$ x- e$ Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 r) G5 t) k9 }2 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 ~2 |. o2 ]( i8 w) D" `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% s3 g/ P& K& B, |7 K
}
! \ y5 @7 }5 S3 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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