|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 G$ Z0 J I3 m4 n0 a `* Minput mcasp_ahclkx,% {0 Q3 q1 u6 x4 n. a
input mcasp_aclkx,
9 @# g. D* B( T; G2 tinput axr0,8 J/ w. i8 C% `! N: e; C
& z e5 R& H. E2 A3 v# Poutput mcasp_afsr,
1 @& @$ {+ ^1 k/ a$ T/ youtput mcasp_ahclkr,
* W' x' K4 p) ]% N) Voutput mcasp_aclkr,
4 u2 w. M7 [7 {; ^$ A- K f# ^# }output axr1,
$ g K- o" f) i assign mcasp_afsr = mcasp_afsx;( L2 U5 M9 X7 B- s9 h
assign mcasp_aclkr = mcasp_aclkx;! f; C$ @5 ~) E$ n1 P' @
assign mcasp_ahclkr = mcasp_ahclkx;) `. y, }: e( _! @" M
assign axr1 = axr0;
) P* ]7 i- N) |( \) k1 R( ^+ H& @$ l* l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, @: c; t2 ?) K6 }$ o# @6 Xstatic void McASPI2SConfigure(void)
9 |- V/ m ]5 _, q9 `: Y7 |{, ^% s6 ]) }5 d# R& {1 _2 [9 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 q& s& I% z; F, t" ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 n+ I* f! V7 j5 k8 p9 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ L& N% u i$ @( \% N C! i8 C0 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; T6 U0 c/ @4 S& @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 h/ R+ E/ Y3 k
MCASP_RX_MODE_DMA);
P7 Y, T4 {2 P7 Z. w/ UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: J: K" b4 O( k. I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 [9 z$ t6 v% t5 W* V. h7 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 `' y2 A# x+ ^- f, q4 D( DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); }/ r3 Z# l- r7 D) u8 Q' C! w2 c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * x2 R/ H( {* Z2 Q1 F o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 `% T2 j( p; [$ bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 K) o) M, }9 v% }: c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + O) `+ X- B4 ?6 ^4 T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( f& f# p) }* l0x00, 0xFF); /* configure the clock for transmitter */' a; M8 E( x, r4 ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: F x2 \9 J: e, EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, F! v9 C# Z; }# h4 I* \- C5 J% r# QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& ^3 X' U, x9 J S; n
0x00, 0xFF);
; t4 C# a* q7 B- w
2 E* ^5 M7 }8 ?/* Enable synchronization of RX and TX sections */
`8 N) N) G2 L0 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ K3 h# Q: ~9 l. BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' o2 w v% G- S6 }5 N2 vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 u+ X* [3 E- M% B
** Set the serializers, Currently only one serializer is set as: d X) I: s9 }* C) {2 `; C' _
** transmitter and one serializer as receiver.
5 Z( @: z. g9 q*/
3 J7 S/ y! \. Z4 _ D; x" ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ }; H+ h- C# r' j1 R/ c, S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ X$ t4 ~) q3 D9 J- W- C i** Configure the McASP pins
; y) Y1 @7 f2 |+ G0 t [1 x** Input - Frame Sync, Clock and Serializer Rx1 M7 Z3 n! D+ p5 ^+ b1 m
** Output - Serializer Tx is connected to the input of the codec
- ]) i2 @) M8 o' m2 n/ t9 Z1 [# [% W*/
' ^3 g; _% F5 }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* l( u" y6 |7 V( ^& T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- k1 @7 x* @9 ^( p& |" N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; Y1 ]9 C% v4 s6 J/ _1 W| MCASP_PIN_ACLKX$ M6 l X% }* ]" x: ?+ T
| MCASP_PIN_AHCLKX
; B6 V3 K$ i0 V, S% ]; i' n! [- f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# g2 y+ o# e$ i9 h' m0 N: J, v% f7 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ n+ M- g& u' P c1 c* a! {
| MCASP_TX_CLKFAIL ( w1 Z: C# v3 X5 w, V* S5 D
| MCASP_TX_SYNCERROR
0 g" Q' U9 `' I4 S: m# i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: F- @0 g5 g4 y( C. r| MCASP_RX_CLKFAIL& c* H# |( r. _* u' Y8 \/ X
| MCASP_RX_SYNCERROR ) }* k( h- l! s4 `! m1 w
| MCASP_RX_OVERRUN);5 H" n+ j8 k# L$ |' ?
} static void I2SDataTxRxActivate(void)) m4 q# T% ]+ `. l+ i/ a8 w
{# V* `+ Z- l- N5 Q7 q+ F; ~
/* Start the clocks */
4 }; N5 i+ F: `: P( Q4 i4 EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" s1 B& d# n+ ~ M& M) gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 a) C5 X$ f& PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 I6 d" v6 N: H A' Z& uEDMA3_TRIG_MODE_EVENT);0 M; }, @( _4 |# Q. T" E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 M3 ~+ F0 F0 |# DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- U0 N2 K+ ^4 E3 L/ h6 u/ |7 z" ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! k9 T% e% {# j1 b* S) ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 g$ o: b# o& j( T' c$ |0 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: G7 W- e _; @2 E" Y& nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! L. \1 z5 \+ v' G) S4 \. cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) O" j% ?( D/ y$ F8 X
}
! D" B* D; m: a l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- Y/ Z) `7 u1 v- s! m |