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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, C, O3 N3 f( T7 }, e% ~- finput mcasp_ahclkx,
$ t, g/ y' Q% v0 vinput mcasp_aclkx,
9 Q: Y6 a# B$ c9 Y0 q( Dinput axr0," z& |* {7 A; z4 o7 }
- Z9 k0 d. L6 Z( Coutput mcasp_afsr, m) \) I. U' _. D$ y# B
output mcasp_ahclkr,
! ^. Y# H* [; \+ S# I C+ o1 qoutput mcasp_aclkr,: E# d( i) x/ p. J9 `/ L# R! c
output axr1,
; B$ c/ X: z# h- e) z assign mcasp_afsr = mcasp_afsx;$ t8 n% J( y+ }% R3 c7 j0 a) h
assign mcasp_aclkr = mcasp_aclkx;! Y) u- D( I$ a$ d# E- e f
assign mcasp_ahclkr = mcasp_ahclkx;
3 C" S" ]9 d( _2 Cassign axr1 = axr0;
4 a, T; j; b/ f5 L4 _8 j/ D6 a! b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( A, w+ x x) y# l& ?, _1 m! Wstatic void McASPI2SConfigure(void)
0 X5 e$ s A, O G: w% W4 e( @{" R+ T+ C4 B% S, p" t4 I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 q; K. _+ f0 f' p8 U2 b5 ]% jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; B5 N! _& ]* U/ p/ a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 c9 {+ f0 {% s) F9 |$ K. ~1 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 Q: q- u7 }( x, ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 O) F' k4 A: _- J9 v+ _8 w+ oMCASP_RX_MODE_DMA);: P1 W D/ [) C$ U& ?; z }" L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ L3 N9 |/ p# U2 @5 G( \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, E+ n; W- k" b# { `* @- tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ g4 s3 \: x$ y! e4 [7 {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 M) R5 x) L7 H; jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 s/ o9 t0 d0 _( a8 M" w" H' ?+ Q6 d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 j) F& H# s' r! k1 a& W% ?2 n( j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- v; K+ S P; B0 {& B! P) ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# o2 \2 ]$ I* Q& _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 ]% V0 E4 n `0x00, 0xFF); /* configure the clock for transmitter */
{/ T4 {( o: s& p0 uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ X% |8 m. W% I& ^5 \9 Y h! l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 r# O: |/ t1 M! A c' }6 j, [) M$ FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ C4 d" r/ Z& ^- |& Z6 o; p
0x00, 0xFF);
2 U( J0 ^2 F4 j c, Y: ]; u
- T! h; r4 Z% K# N7 v* G/* Enable synchronization of RX and TX sections */ # J( @! b% c( g( ?4 M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; I# @! {+ `* }: ?" T$ Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 ~% [4 s$ [1 M& j# ?/ @( S. JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- i: \ Q8 v3 \** Set the serializers, Currently only one serializer is set as
c$ p$ Y+ B q5 Z2 g) o** transmitter and one serializer as receiver.9 U( ~9 A/ r. x8 j, ~, W
*/' ~" D4 i; R! J2 a4 o. E% c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" p' X6 S/ L4 y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 u7 t" I6 v8 e8 @** Configure the McASP pins
1 g/ @& V! Z, N6 s** Input - Frame Sync, Clock and Serializer Rx
- B3 S0 ^8 C5 h% j& J& [** Output - Serializer Tx is connected to the input of the codec
L0 @1 H8 x3 f2 z8 j6 E: H*/
' u& q* \# R- m0 W9 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 |, v) F' m! U/ c* u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) N) s8 @: y' R, Y- T# B5 ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% z# L( U2 G8 H [
| MCASP_PIN_ACLKX
9 ~ C! U( C% {7 q+ e| MCASP_PIN_AHCLKX. c! Z$ W6 _ y+ l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' G# N; H& J% M; E% B1 t vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 c i$ W$ o" ~| MCASP_TX_CLKFAIL
0 b6 {! t4 U& o| MCASP_TX_SYNCERROR
8 F0 s7 Y: @4 Q+ M1 @" P3 l! d- }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ P+ a3 T1 N9 |8 ?: G) R
| MCASP_RX_CLKFAIL& B, d8 k; X9 w7 e1 m4 A
| MCASP_RX_SYNCERROR 1 J( g4 w7 a6 H
| MCASP_RX_OVERRUN);
" e* ]" L1 N( T/ J} static void I2SDataTxRxActivate(void), z7 b" M; T2 R/ ~
{
6 F( @9 ~* e9 m, c3 ~/* Start the clocks */
% U6 h9 ?4 |% k( B/ jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* W' a/ G. Y& o+ l5 T2 M$ H5 XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 `3 i! x" v" u2 C' _! v9 A* wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 n# c. H* U5 e! GEDMA3_TRIG_MODE_EVENT);
- a% p" F2 j# `1 [9 r) ^ NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * r3 o% H/ W0 k$ h5 F! y( n+ a% z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 n; I& ~7 b$ \% H' b. YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( B; |1 i! S) k5 O# F# [+ xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 s1 b0 f% L; {; m/ m8 G- ^, X3 z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% j+ [# {: A8 g! l$ |, t: `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: ~/ I' x# Z! Z& L3 u# wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; f4 u/ o4 D' ]% |0 Q
} 6 k, p/ _0 C8 f( e# a* w& h. I8 [& c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 X. N% W; k. w
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