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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" A( }, m1 F$ ~( ^input mcasp_ahclkx,
# m7 o1 v& w5 yinput mcasp_aclkx,
3 h0 W& h8 l2 a8 R qinput axr0,, y2 P& H( x1 j2 q" |& v
: m6 D7 ?+ w L2 {! S
output mcasp_afsr,0 F( I3 k8 H) ^! X7 ?! i* K9 f
output mcasp_ahclkr,: e" ~5 f7 k! G, \# Q6 F4 O
output mcasp_aclkr,8 E0 t+ d# n' o0 ^. U9 ] f) b
output axr1,
5 L5 L4 Y: s1 B- z8 Q assign mcasp_afsr = mcasp_afsx;
" [9 J2 c6 E( y* @" g, L! oassign mcasp_aclkr = mcasp_aclkx;
/ d3 z$ e5 x8 I4 W0 Vassign mcasp_ahclkr = mcasp_ahclkx;; z8 o+ K6 P e- H& [
assign axr1 = axr0; ) r7 A/ v) Y R5 V2 Q9 e5 T7 t3 W
0 i& {6 U2 b8 d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # t7 J; x3 L7 L/ D/ R
static void McASPI2SConfigure(void)6 p7 u* j2 Z* S# H: \5 r
{
" P. U# t* a, k D+ |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 Z7 g% L5 O& eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 C4 ?( @+ E4 A; @0 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. {; t! E0 K$ J+ N/ H8 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 [, w4 O" K. [* pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ f- X* x, @8 `& I$ c4 K/ FMCASP_RX_MODE_DMA); s* O0 M+ h$ M, ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 N2 S. C1 o+ A: h4 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 u$ K7 X( r4 v7 o* d. o9 n4 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 M: `% C) c, J! U1 M" g3 ?" L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 ]- `4 L& x5 s3 u+ E0 y7 S/ Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: M8 O; Y0 e7 s3 d6 U" zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 S- n' v8 n' V6 e3 }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ ~8 I1 g3 W; n, c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 \/ b: a4 K2 |% V7 y1 A% O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% h& J- a- |0 H6 x
0x00, 0xFF); /* configure the clock for transmitter */' Y! }$ g5 D* C1 z' Y" D- n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 D' j7 a8 \ O( gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ w8 _7 ?- S4 ^0 R# q' f7 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, q0 M, j0 l- r6 i# r0 d
0x00, 0xFF);
% k& f* L, A7 B: v6 @8 M3 d0 J# L4 D$ Q' i" ~3 e+ |
/* Enable synchronization of RX and TX sections */
' g$ }. y; Y# Q! @4 v9 g0 w% T2 mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% d* F' e. O# `8 x8 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 D" v' C4 L. t$ W/ K0 l4 v, p. M- DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 O: ^" R. ?6 G( l7 b$ V
** Set the serializers, Currently only one serializer is set as# [8 B/ C8 l/ x) I$ ~
** transmitter and one serializer as receiver.
; t6 V# H1 {- n! c*/, A* g5 @9 o( V4 `! H! B4 c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% ^& s' e$ J4 ~+ ^' C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* b$ C6 o/ |( _6 Z
** Configure the McASP pins
* n% f- B" w9 @: u$ ?** Input - Frame Sync, Clock and Serializer Rx, u! Y+ X( b. W7 f9 Y- O0 M1 p
** Output - Serializer Tx is connected to the input of the codec
- o( Z' G5 u6 s+ A+ |( h# V*/ ?# H7 K& G+ u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 ~- H! f" H0 d! v7 G8 D, bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% k5 i: S) N; v% N- @; g# u% h. d/ `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* W( s* J) e2 s% }- ]| MCASP_PIN_ACLKX; H0 d* g0 W3 X7 s8 v; V
| MCASP_PIN_AHCLKX
& h( i8 U: B' T6 m/ A' e, E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 }% R% ^- a* B3 K4 q( |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' w p0 w5 a( j* L( N2 Z
| MCASP_TX_CLKFAIL
9 i2 C6 u. ?" F| MCASP_TX_SYNCERROR
# h' g0 N' [" a3 ]$ p6 J; {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ M% a! F3 j9 D: Y' T
| MCASP_RX_CLKFAIL' K4 d: p+ i/ x
| MCASP_RX_SYNCERROR 2 l( h0 [1 s' b" F7 q
| MCASP_RX_OVERRUN);
4 v9 W# \1 U* B' y+ O+ x$ U} static void I2SDataTxRxActivate(void)% s! Z7 Y4 y- V! C; { s5 l
{# k' m8 U' o9 r6 W0 W) D# r2 m
/* Start the clocks */( t i0 m1 Q0 f; k* C' F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 k% t; O! J$ d: R' B6 r: w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' T! a- I5 Y) `. e) F" wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; k' e/ Q" p" x. b9 Q
EDMA3_TRIG_MODE_EVENT);) k8 e5 b: _! q% Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 y' k8 d: C7 C+ SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) ^! ~1 x- s5 E; z- s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) c: `. f$ G& E% c/ x. PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, k0 d& q9 x. _# [8 @' v; Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" [& b7 J, z5 Q& q9 u2 q; k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 {' S% `8 F# ]' G Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; h% @6 h4 H3 B* ^) G} 8 P6 D" z$ l9 E1 Q% Q! x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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