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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 @8 q9 l& }( S. ?& r/ L
input mcasp_ahclkx,1 s6 z5 K$ J5 ^: t% c8 D2 `
input mcasp_aclkx,
9 X& P, e! m% T7 _6 vinput axr0,
6 _/ q+ R& Y' r$ g! V; M' y+ F# a4 L
output mcasp_afsr,
& O3 N( }+ x& zoutput mcasp_ahclkr,
+ F' P' H7 D, b% h& `8 G$ Voutput mcasp_aclkr,# r4 _2 p7 L4 Z
output axr1,
/ T& A7 l) Q- |0 e' O assign mcasp_afsr = mcasp_afsx;/ w i, M' u$ S* x4 u6 D0 p$ D5 f
assign mcasp_aclkr = mcasp_aclkx;9 ?# t+ _ G$ W4 E, Z
assign mcasp_ahclkr = mcasp_ahclkx;2 V8 L" l+ z/ i+ A2 c) I# `, d
assign axr1 = axr0; . k) d& Y' t& |8 R2 m
% H" s+ i+ p& G0 `# K1 U3 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 n& {6 i; x' l2 @) E
static void McASPI2SConfigure(void)8 T! f% i" G, t0 z% F8 F1 }+ B, R
{
1 A& K& g& O4 u! r2 m8 c$ y/ y, zMcASPRxReset(SOC_MCASP_0_CTRL_REGS); a, G& ?4 S9 J% w9 H% M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) E( h* D2 L- m E; r6 h6 P6 c3 ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: u2 t" T* A8 ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, ^2 G) W) D9 @% G' \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' z: O5 _5 \0 p8 G+ DMCASP_RX_MODE_DMA);& x' E6 \/ M- ]' x; l4 i9 |3 r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 ^' C9 q: [2 N4 }# n8 ?# o/ lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 w0 h- E$ ^2 P$ Q2 n9 t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 g6 M: E' F) v3 e6 i. r; H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 T; u0 ?- w1 d7 _& r$ W7 O! [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 ^ Q% Z: S* {( R3 R4 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- _+ p4 u- B; w7 {" `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# h1 v1 E6 Z# j1 |, o) u% J$ BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& j. _; f! N2 `3 X8 Y# U0 r2 U$ rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; ^# _" \# Z% R& ]" D* G0x00, 0xFF); /* configure the clock for transmitter */2 u4 d) b. ~! Q b2 A* y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 ]- d$ R# a) \1 Q7 D6 R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( x9 T/ ]" O# y4 C% w: U* ]" d! UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 j8 i: X6 C, W# q
0x00, 0xFF);9 G# {0 x6 l3 H5 A& f9 H
& o% \9 @0 L1 [+ w0 B
/* Enable synchronization of RX and TX sections */ 9 l5 w7 X- _0 R1 w/ P4 w( R+ D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) l5 r) Q: s2 U$ k( E$ E) g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' T% ~- G2 H- v& L9 `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ `; g* x% a: p$ A g** Set the serializers, Currently only one serializer is set as
U; ?+ h0 B, m0 r2 m! f2 N** transmitter and one serializer as receiver.9 i0 q0 }6 z# V+ N) e" I
*/
2 t9 l1 N6 r5 e7 a0 LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# E+ |* y3 k8 Z) GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, z I" P8 Y; I4 {** Configure the McASP pins
) q& i8 V) d( g1 F: x/ o** Input - Frame Sync, Clock and Serializer Rx
# v/ i% f; h4 N** Output - Serializer Tx is connected to the input of the codec - J: R( f" e* h+ O. a
*/
/ F# j' w* u1 G+ u/ vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( c: F0 H7 D' y% q! U; t. l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" b$ ]% K( F7 o" r! H& L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 k/ L7 ?7 ^& [
| MCASP_PIN_ACLKX
( R" \+ u" T5 q4 l| MCASP_PIN_AHCLKX8 v0 I0 e0 z z& V) X% a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 d: Q+ F4 `8 g/ H* L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! I4 A: R$ E2 w: W| MCASP_TX_CLKFAIL ; r8 V7 }5 @ C
| MCASP_TX_SYNCERROR5 P6 R O; p& S0 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! F K3 _8 M1 Y" _
| MCASP_RX_CLKFAIL
9 T0 O1 K' J; X4 y( C5 c| MCASP_RX_SYNCERROR
1 v+ S8 z; ]& m| MCASP_RX_OVERRUN);! w+ G8 @% e( o, c
} static void I2SDataTxRxActivate(void)2 S7 \ ]0 ?3 G
{
2 z. g4 g' E4 l/* Start the clocks */
& A: z9 n( a. K" pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 {) o" E4 Q, T* T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- r4 O5 y0 Z9 s& N* `7 r" iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- E/ i4 R, D) {' REDMA3_TRIG_MODE_EVENT);* U h8 ?# V- S* o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 ~3 M1 x* }" ?" YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' v( Q( c3 h: ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 Z( g V+ k3 p3 G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# ~6 W3 m" |5 m5 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 d7 Q+ I3 ~. m3 G! A% RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# h- y" H# v5 U( J' `! A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% i' H5 j$ [% M; N9 I1 R! u( I} 2 W' l2 s+ [1 m. V. a6 i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; A7 g1 {! s: L* b2 \; c7 y
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