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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ z- S: w' d' g, ]* L
input mcasp_ahclkx,
; \; o) ?; `7 Q* w% _. l+ z# |) \input mcasp_aclkx,
/ s( }2 Y3 B$ ?6 h8 D. oinput axr0,
- I8 p9 @7 R/ C/ W4 |4 h5 Z# l3 s% r
( G0 ]: H+ |6 ~' u% @output mcasp_afsr,
+ o1 C8 s7 B( x7 M6 D' o$ R) m) Qoutput mcasp_ahclkr,
1 ]/ p/ A* ?8 I! b: f4 y: A4 Y/ Ioutput mcasp_aclkr,) D9 k% C3 J0 z- ~$ @- S
output axr1,
) _2 m9 T, [* O8 o& c assign mcasp_afsr = mcasp_afsx;
1 U; F& |8 `- D3 b) M {assign mcasp_aclkr = mcasp_aclkx;
& o" d1 \' N0 r1 gassign mcasp_ahclkr = mcasp_ahclkx;! j( B( _" Q6 H1 t& k
assign axr1 = axr0; ' @" ]7 M% h2 G" Y! f
4 p4 X( ~+ ^2 q+ K1 a3 J% C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 {; N0 [. t- ?
static void McASPI2SConfigure(void)
3 g4 J- x% Q3 c. h{
$ i. c/ j' R5 g" y+ E% }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 [+ Y P4 v- `8 YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 j& h4 k* U6 ~+ i, r( s/ q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; j, p7 P4 r- Z0 D; aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) p" F6 U, b$ k) a- x5 i' c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% g3 ` F6 A s* x
MCASP_RX_MODE_DMA);9 M( J# z* r' Z8 R8 _! I T8 h/ B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" p1 d3 a* N# \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 t& d0 C; [: m( t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 J4 }' k2 V. o/ }) {2 a# v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ e" S6 I0 B+ MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 y" ]0 u7 d. W/ ~, {: d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" N/ n8 v" A" F# N$ N' i( cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ J' A/ E6 g; z( i' l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # }$ j) p v2 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 ~4 B/ ~: `) g" d
0x00, 0xFF); /* configure the clock for transmitter */
/ S4 P8 R. R4 O3 ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* K5 `2 }, a( X8 B+ w9 E+ H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& j8 }6 `( L1 R, I' sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! q" |: R5 H6 w( E" Q3 m: \0x00, 0xFF);
- B8 ~* h+ \. h+ j
7 f m9 i$ A5 P% J b% i4 p" J- S/* Enable synchronization of RX and TX sections */ % F4 @8 Y8 T- r8 ~2 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 }) g: G# Y S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. e L, Z6 T( y7 a) g9 j) a! |( Z. c6 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 Y6 v) r+ Y$ ]# x0 x. T# J
** Set the serializers, Currently only one serializer is set as7 b, }7 ^% F' m. Q7 \% |4 ~
** transmitter and one serializer as receiver.
9 B& I1 | c' A# X*/
& z1 ^# W1 o$ M1 gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" P2 F- k; S: N3 S, fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
r" T X3 l* ?, z3 h. j4 F** Configure the McASP pins
" _4 `+ ]) Y3 B( m% X+ {1 l- V** Input - Frame Sync, Clock and Serializer Rx
* l" H; p4 n$ P% y2 y** Output - Serializer Tx is connected to the input of the codec . \" z1 D' i2 J. n) [: V+ ^, b
*/8 D; `& N7 V5 F- T( G: z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 U m, ^7 I4 h3 b S: dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. ^2 a9 f) ?# s; y7 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) v6 l: J2 r, D) H& t
| MCASP_PIN_ACLKX' M0 P8 R# c7 g8 L$ d5 a
| MCASP_PIN_AHCLKX
. N% M7 C2 p# b3 O& H% t; f) M& j0 M2 \8 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! M V# c* H, K5 B! D& u" V' r% JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: L q+ B$ J/ }9 n8 W0 I8 [| MCASP_TX_CLKFAIL ! F- ^& ]: L& H( x7 u9 p
| MCASP_TX_SYNCERROR; \ L6 x. Y$ u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 B! J, Z$ v1 C* e: _% A# W
| MCASP_RX_CLKFAIL
; R* d6 T3 M. |- L9 k5 ?. [& `| MCASP_RX_SYNCERROR
" S$ ]! h* ~0 e| MCASP_RX_OVERRUN);. O6 o" m; C9 t# e
} static void I2SDataTxRxActivate(void)+ |7 w! ~" l+ \0 J \8 ]
{# }- Z1 z! F" Q4 I
/* Start the clocks */
4 |* a) {+ u) IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# y( N: H& h; s* k6 M9 ]1 j8 WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. ^! y) I' Z6 M0 u( V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 E# E) V6 v: L4 c; ^& L
EDMA3_TRIG_MODE_EVENT);) V' B4 _' O; H; k$ ?9 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 }' O: w: Y7 N# L: s4 h4 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ b, u9 k2 d* E1 [( L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! [' ^; X7 l5 w. E3 O) W% g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- | A U' P+ k' G5 l1 c/ [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 L. W* z; Z, V ^" \9 gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' e1 _4 ?* N, R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 j! N. s8 ?+ w* M* o} ) F, p d7 X x0 Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! f! s+ _5 f ~$ h# |" M1 G- m
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