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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ C" [' b g* ~- r, {' k& g rinput mcasp_ahclkx,
O' u3 l' U5 A6 M x% Binput mcasp_aclkx,& o5 W7 c, K6 U: D4 ]( P% N
input axr0,0 v) K1 S# x0 C5 a8 Y- E
. @$ `& }4 u% G* ^& K
output mcasp_afsr,! @; m' S: ~" R- {
output mcasp_ahclkr,% x( L: g0 G3 Y
output mcasp_aclkr,/ E9 W/ @, f0 a3 \. @: v
output axr1,; _6 ~* S( S: U% D9 I) k; Y) s
assign mcasp_afsr = mcasp_afsx;
4 L# z& N2 a2 |3 r5 y8 dassign mcasp_aclkr = mcasp_aclkx;/ p( h! {% G9 o
assign mcasp_ahclkr = mcasp_ahclkx;
! V, y3 A3 W6 P7 s, Eassign axr1 = axr0;
0 B( {7 I) y! ^% Z6 D0 Z* Q
) V! L; z' X. o8 M% s! t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 w I0 J- ^# s, Lstatic void McASPI2SConfigure(void)1 S' m9 [# p. H$ r: U+ ]9 ?+ V
{$ Q- ~# c M3 s% F% t* q9 n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 r) q6 g: Y0 P' Y @- LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) H2 s$ C2 f1 I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; A5 a9 w/ I8 T" B2 Y7 @- C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 P- O0 D. i( n8 d8 |. g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 v1 ^. p$ o: p7 D
MCASP_RX_MODE_DMA);
0 d; L; S* ]1 x2 EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 e& i8 K5 \; D, L4 d& E4 |7 b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 H6 \4 L% w! l" `6 D# g( e' [( zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; M) w% Z( ]8 H1 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' P1 O1 i& |' J) \8 L$ L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 `; j8 F. h/ Z( C4 ~7 R+ x# l1 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 I3 b; w+ |; R* Q8 x8 h/ O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& O1 T2 H2 m( K% H6 s1 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
C0 C& ^% _4 l' cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ O7 O2 K0 q0 m. v8 b
0x00, 0xFF); /* configure the clock for transmitter */
: D2 d: q. K/ AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 H9 f( H# k. ?- n" d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) s8 T) P$ ^! J" Q- ~2 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' S* E" ?% t# ~3 w9 |4 V" @
0x00, 0xFF);2 ~0 w# z, H; \7 x# S
9 v4 o- b1 t6 J; O8 t
/* Enable synchronization of RX and TX sections */
" n7 M7 }" d j* r7 xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* V W) \: V4 Q! R2 a# jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ M" n4 V( T& ]& B7 F& b. D6 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. ?7 h3 b1 Y/ q
** Set the serializers, Currently only one serializer is set as
5 p& v; E) z! v3 E3 U7 h** transmitter and one serializer as receiver.. N/ U% j( L- h5 Y3 `+ I
*/" y8 l w9 \# z; Y5 p: w; }8 `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% N; b! Z2 Z# t r6 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& G; A1 a2 G* I8 x6 n, L H** Configure the McASP pins ' Z, l/ o* b @7 A
** Input - Frame Sync, Clock and Serializer Rx# K4 ?6 u6 K: O
** Output - Serializer Tx is connected to the input of the codec , I) q/ h# Q0 c' W) A+ }- [) T
*/2 O+ ^( q" y; p/ J% \$ C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 x& N2 o0 n9 d5 V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' }9 {. L* l9 ~+ L9 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ T- b/ P% Z, W) [ s! Y
| MCASP_PIN_ACLKX" j3 K" V1 B2 @ x, U7 t4 |2 e
| MCASP_PIN_AHCLKX
0 H R7 }$ f2 C( u9 i" w0 A: _: {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- q& V% N9 c0 s) d0 e( T1 r2 A9 Y4 K, Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
E; }6 ~9 S* [1 V/ W% `0 t( _3 X| MCASP_TX_CLKFAIL
, Q/ h3 l, i. q9 c# S5 j( ?| MCASP_TX_SYNCERROR
7 D3 m+ c$ A# p. | X t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 V, J5 j: e5 J2 n
| MCASP_RX_CLKFAIL2 l6 C S% t5 p: }. @5 m
| MCASP_RX_SYNCERROR
) w" c" O" Q# J1 ]+ V: a4 B| MCASP_RX_OVERRUN);
0 ?- a. \6 |+ V, M) \5 j' \} static void I2SDataTxRxActivate(void)" Y0 R* ^; {4 Y
{+ G3 c9 r: a; ~
/* Start the clocks */
" h; J, E2 l2 [2 J) m) cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 o- J/ ~+ ~3 l, N3 |/ @9 Y# j* C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, v2 A- v( X' E% i5 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: o$ J2 V+ S) L& D. W
EDMA3_TRIG_MODE_EVENT);( q0 v* X n0 r9 x8 X. @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " N' D4 M' z' z! i9 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% M0 M' i3 D& P8 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* _8 m; p: F. @8 G( q, D' AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# O# \9 g* y6 p5 B |: c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" i2 K$ v* Z, h2 E, D% vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% |9 t+ A: H6 ^, B+ q4 z) p JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ K; L9 e* @# Z4 l
} 6 Z6 ^6 H- I7 Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , O2 ^& v2 |, J$ C
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