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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! K4 } c. V& M2 R0 y: L5 `& m
input mcasp_ahclkx,+ n& f6 w6 O k9 t" D; s0 z
input mcasp_aclkx,
# n& L6 X2 l4 X' c% Uinput axr0,
5 f* q0 a9 H- U' Q: H. y8 X
2 j1 S* ?8 u4 M: Joutput mcasp_afsr,
! D+ t4 M) K, \2 Joutput mcasp_ahclkr,/ F, Q9 {& R3 {. `0 R
output mcasp_aclkr,
1 G9 S1 X. m1 v0 q7 R4 poutput axr1,. t; V/ F1 J3 n- q' v& C' V: o
assign mcasp_afsr = mcasp_afsx;
) [4 `9 F, s/ D6 u0 kassign mcasp_aclkr = mcasp_aclkx;( F" R5 L( }5 O9 B9 R/ T1 @
assign mcasp_ahclkr = mcasp_ahclkx;
* P) w9 h. R; Z8 a) Jassign axr1 = axr0; 1 u7 O5 W9 |/ R7 O/ v
( \/ {5 |+ v8 T0 t% {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - d+ G; K% z2 g# `
static void McASPI2SConfigure(void)9 Q( f) P) E" f
{
( ^( i- V* B& \6 c$ YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ T7 t1 Y6 t, f6 F! I3 Q, nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! o8 E$ T) R& y$ D7 e" @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; {4 t5 t# V6 S4 w2 H6 IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- K }& c. ? z, M6 ~# E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ f5 s7 l/ `! h' ?2 q9 gMCASP_RX_MODE_DMA);
7 K( {% c; {7 Q+ Y4 c9 A& Q4 t+ ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ Z1 Q: u0 B1 x9 l$ X- j0 N# _" o: r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ {3 |% u8 I( I4 b K, a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' H( y5 j, U1 Q0 u7 g1 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
o8 e9 m4 @1 \9 Y$ x d/ q% {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / I) j8 m: u" v) ?+ T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 e6 v4 Z, q- O- d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- n2 _+ u1 a$ [1 i; V# w+ o. lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / l* ?. G4 Q" k1 A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! [: k) E3 L8 X+ d# o' \0x00, 0xFF); /* configure the clock for transmitter */( Y* c2 ]. E9 Z3 t6 z; K9 C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 E, D3 V- q5 x) A$ q% s# _ AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 e' s+ C# |( d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" I, H& b7 Q! C, H; }* _8 z0x00, 0xFF);( L% T$ ?5 @4 R! G. y9 @+ @, w! a2 X
7 C# T- _. p8 r: A
/* Enable synchronization of RX and TX sections */
$ l- S0 `6 M& X: j8 V- K4 {/ ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 K: m+ L9 @# H0 m. N' `2 \) J0 r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 U6 T' H4 [ [0 B3 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& {0 z9 U7 ^6 Q/ b
** Set the serializers, Currently only one serializer is set as, i0 {5 z2 G* `# D3 t8 \$ Y
** transmitter and one serializer as receiver.0 c$ p8 i, `" v+ O- ?; W' |
*/5 Z2 @6 i/ k. C5 B% x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. P" W9 a: c3 \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 Y7 w: @4 p" R Y
** Configure the McASP pins , X1 O4 i' F& h" G7 y6 j% _* `
** Input - Frame Sync, Clock and Serializer Rx
7 P, G0 [4 e! f6 N/ f** Output - Serializer Tx is connected to the input of the codec
) D' ~/ v5 {& O; h C, ?*/
9 f5 \+ ^ r- j+ K/ AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 D# H2 d0 N9 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 u0 b ]6 k, s7 ]1 b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* ~6 @9 E# g, v. t5 W4 N! D
| MCASP_PIN_ACLKX7 G4 t2 ~% a; p t- x3 g
| MCASP_PIN_AHCLKX+ e z0 M/ j: V* `5 L- `% b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ ^2 @" W: q$ E! _1 O$ mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / x3 n/ s; ?' Z: L% l7 I
| MCASP_TX_CLKFAIL
8 M1 _$ |7 K* w- d; _3 p; s" || MCASP_TX_SYNCERROR, K$ }5 {, J" ^! U% x H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : y; [4 P# p# c
| MCASP_RX_CLKFAIL: @2 F* q9 d- A
| MCASP_RX_SYNCERROR
8 i6 K5 ~( ~5 v# m$ V$ `| MCASP_RX_OVERRUN);
Q9 [7 \3 g' d1 j9 v} static void I2SDataTxRxActivate(void)' Q6 @3 x. V; Q! r. A# ^1 [' x
{; N; s! A; D/ \ s! I
/* Start the clocks */
) J" [" t0 s) k8 iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( F: N# l2 s2 E7 b3 N9 p/ D+ o% \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, g9 x' ^2 s) U$ Y6 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, i6 J. j; N: J% f4 C
EDMA3_TRIG_MODE_EVENT);
. E+ y6 ?' `9 _- s% Z* EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( l. ^9 b6 J% w, U1 ?2 XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ p- L( e: e- G+ F+ D& w/ mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: l9 W5 l- O& \8 F) {" v% `' B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 P8 c3 V$ g/ v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 k- E; d+ N N3 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 k. s$ ~$ c* ^# S0 LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* e& h: L# s5 P9 [% M3 \} & J' j) r- S6 w$ O' P. R- Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) W5 \/ Q) {' n' k. |% z& d: Z4 P
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