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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 j2 O+ l9 n G6 Jinput mcasp_ahclkx,4 o: K/ l2 x) @( J
input mcasp_aclkx,
! K" O- T; e& }6 v+ Iinput axr0,/ t- X A' W$ {: O/ ^
- s4 Q! d! G) X3 M8 Noutput mcasp_afsr, G; g7 H* i: E& G m
output mcasp_ahclkr,
) E1 N; D, {/ { r/ ^output mcasp_aclkr,# |; y g% E9 u) R1 S/ E
output axr1,6 N L' H4 f+ ]
assign mcasp_afsr = mcasp_afsx;
4 k: D, c: w* y3 lassign mcasp_aclkr = mcasp_aclkx;! b' k' Q- a/ A z& w9 Z- \0 i
assign mcasp_ahclkr = mcasp_ahclkx;
O- o: [" g& D. zassign axr1 = axr0;
. G4 M! q' \8 d( x+ c- l' ?2 q! w% H% F: Y% x- R$ o! V% t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 S8 X5 U1 L" s7 _+ T7 I
static void McASPI2SConfigure(void)
7 `9 ~0 a9 _/ W+ [( k) Z+ b3 d{
; R/ C' \8 s) ]3 ]0 D/ FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& R: a% C6 I: u w2 `2 \; n% y, z$ E/ Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- F! e, {: X1 `4 W4 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 m" Z: t6 B! a8 E; [( ]; p( `, g- n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. c% f p/ Z1 x/ zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* i8 l% g6 ?& ]5 o7 n( W
MCASP_RX_MODE_DMA);. w q/ v& X/ c% a2 V% h z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, [7 J' S: f- U% t* q8 E8 e5 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ x0 Y0 D+ t* N4 c( D; zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# ~: O) `4 i3 Q! m9 OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- A4 j5 @$ J+ V, p1 \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 R9 J" C. E$ s, Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ l; B0 V' A' l! W) dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. L2 Q- Z- q0 X! nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. H0 f P6 C) }# F# bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 x) a b+ m: M, L* p) C0x00, 0xFF); /* configure the clock for transmitter */, a: Q3 G+ m0 b. _ Z, [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& M" U5 P, N7 M9 o6 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. s9 ~# o0 }9 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! R* ^* B( N) G0 u
0x00, 0xFF);
; I# }# C7 ~6 V9 F% Y, a7 F6 q7 G, _+ N% B# Y% {
/* Enable synchronization of RX and TX sections */
( ]$ d- o) R" X. k, G8 v1 L2 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- y/ ^; E7 d3 Z# I% x9 H, ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ F2 {; \# M5 H9 w/ D% N) X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ l% N+ L0 I7 Y* d: s** Set the serializers, Currently only one serializer is set as
& } [- s7 E; ?) a7 X+ Y** transmitter and one serializer as receiver.) I( \6 ]$ e: h0 ]
*/
5 r9 P! T6 T& O: P$ LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 w" d" i: S7 z4 r2 `1 C9 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' \( \' K6 u. |
** Configure the McASP pins
) L+ h& x- V/ O* ?% t( a** Input - Frame Sync, Clock and Serializer Rx
7 }2 `. d3 I1 S2 z$ c** Output - Serializer Tx is connected to the input of the codec 1 ~/ w, I4 J0 S! |# h) g. O' W
*/8 l: y' _* v5 e2 Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; e2 T: S. O) y9 q, h& U6 T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 C! T% A* m C, b+ @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- g, g3 Z. q1 a) e. l" v. x
| MCASP_PIN_ACLKX
$ X9 E# K+ Z' c| MCASP_PIN_AHCLKX
0 |" |) L, V5 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- x2 p: S9 V. w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
o: I/ ]" L3 m/ O| MCASP_TX_CLKFAIL
1 o1 d# a6 {6 S! |' T) `| MCASP_TX_SYNCERROR
, O! K: N" |) {' U2 A j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( k* Q5 ?8 f$ u4 }$ g$ S| MCASP_RX_CLKFAIL
: r. L3 w* H* |5 T" p9 w+ g| MCASP_RX_SYNCERROR
2 w q; m$ A- @) c1 V% e& U| MCASP_RX_OVERRUN);# X8 _/ V" k6 s/ |& H4 W: @
} static void I2SDataTxRxActivate(void)
' {' \9 u8 y" P( ]3 z$ i{
' D3 s9 L ^9 E V8 p* `/* Start the clocks */% K- J5 J/ |: T% s' e1 u. g$ E2 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ n% [1 k0 @ H% g2 I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 Y8 s: k* c4 P) b$ oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% z$ {, E" Q$ T \/ Y' KEDMA3_TRIG_MODE_EVENT);
K$ N, U/ _+ y, F( w4 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# \: a7 f! k, mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# p5 A' L! y4 K7 m0 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# y5 q2 ~+ U' g9 w* r* ] t7 z: wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. i2 z% y, X# s. |) x! R" a: E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% a3 Y/ m* ]9 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ s. n4 {: W0 I @& }1 X! I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' t, l( `5 G- t
}
! k; K h) @7 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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