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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 Q5 g+ @. a; [6 a1 F' n
input mcasp_ahclkx,7 u# e6 p, d' O
input mcasp_aclkx,
}; k' S: m4 v* R, K9 v2 H/ Minput axr0,
& @6 n3 h3 m- J. e# i* P; `! U3 A1 X5 P" c, u* C' S: f
output mcasp_afsr,
; G, M9 o% w9 o9 @3 s: Loutput mcasp_ahclkr,/ N) A0 Y L: V" j7 ]
output mcasp_aclkr,/ x( l, @# f6 F' }; J8 q
output axr1,
" ~" P# w$ T; \5 O assign mcasp_afsr = mcasp_afsx;
1 T* k7 V/ O% Q4 R8 F; y7 _% Zassign mcasp_aclkr = mcasp_aclkx;9 Z0 V" }) \# p& m: M2 N
assign mcasp_ahclkr = mcasp_ahclkx;- X5 ] {% X' o1 {3 V
assign axr1 = axr0; - x( i% {9 ?$ M
# H! D- p: r8 |' ]) }0 G. l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : l2 ?2 }1 w7 J8 S. |7 K; S
static void McASPI2SConfigure(void)
& `8 w0 b% y7 q+ V{: H) |* O3 H8 j) ?% ]& X; `
McASPRxReset(SOC_MCASP_0_CTRL_REGS); w" v: @6 V5 `4 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 y1 A: o8 C; M: ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( [+ H7 K6 u# f3 c6 V: ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- _7 H& w* F2 X4 H- f# A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; R4 q1 K' j0 U/ A+ A6 D4 U. Q
MCASP_RX_MODE_DMA);
$ C5 G) r3 n1 w" u+ ]3 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 a, O8 R4 f# \- H8 U2 V' A1 }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 K9 f, W: B3 D* ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, l3 q+ D8 M. w1 ?! F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 W0 T% n& Q% u# {8 s D# g* Q: oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! c" p) l+ G+ ]) p, L7 u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ M+ B8 U$ d* o$ Z! Z& m9 V! W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ t4 `3 W9 N }! {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " g* W% x' n- D U. S0 D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 N0 t9 {9 l7 Q9 I9 C" k3 w" l5 r0x00, 0xFF); /* configure the clock for transmitter */" [& D% s7 e. x6 T) F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; s$ |# t) P! ] Q8 G" tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); f+ u& Y6 V6 K; V7 Q3 V- K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," T7 q; a# V: W6 N
0x00, 0xFF);
: |- R& n3 w4 c* T6 i/ Q, `8 [1 q# I
/* Enable synchronization of RX and TX sections */ ! L; Q+ m5 q2 O. \" q z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
Y% f: Q( b! v+ F. ]7 N2 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# A: [/ H+ b2 m6 g2 o) { [9 S+ dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; Y) Y T) ?5 q" S+ v! I** Set the serializers, Currently only one serializer is set as
0 z: c2 O' L% {. o" j) a** transmitter and one serializer as receiver.. d6 T7 l- c& K K' x, ^% V# T
*/
. ?% x9 W X% x4 n. {0 L% p: yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# u3 I% \+ r* E6 e+ H* |7 A; Z6 j0 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 d b: T: F6 A& h- C** Configure the McASP pins
& |( c( y/ x- j** Input - Frame Sync, Clock and Serializer Rx, n$ @' ^) v% J! N a& w
** Output - Serializer Tx is connected to the input of the codec
- }5 o+ }3 S0 J7 _! o) U& ]8 U9 c*/" B# `8 M9 _2 ]4 g) M8 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 i9 y0 b* C8 ]. \$ IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); b$ `9 `8 i" o; o! s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; T& I) t* s# L' m. v| MCASP_PIN_ACLKX
9 V! M0 i& @7 h# _4 \* S- b3 G| MCASP_PIN_AHCLKX2 b3 I. H- |0 i- _. Y! `" l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ @% b Y) x% o0 N, H/ sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / C* \, p& K1 y( a5 h
| MCASP_TX_CLKFAIL
; r: R( i, d$ W+ w| MCASP_TX_SYNCERROR1 W4 {1 r# J: Y3 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& U6 u( d! O; D/ e| MCASP_RX_CLKFAIL9 c G; D ~3 H' D
| MCASP_RX_SYNCERROR ) w% G+ g; R. r- k4 c- x: ^
| MCASP_RX_OVERRUN);
) d" r9 T* G. t9 b) n8 _8 I} static void I2SDataTxRxActivate(void)! c+ d2 Q* A* S7 u
{ y. N, Q7 C" G J
/* Start the clocks */: M5 ]! N6 I/ f9 G" j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 }4 |9 [1 u1 C' k- c8 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
X9 O# F* v9 d) a% C7 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; _" n0 L; R! v1 r1 D4 _
EDMA3_TRIG_MODE_EVENT);
% R& ]8 m" {9 @2 [3 \, q% P( b) GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
e! f7 B6 b" l7 r- ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 T( I$ ?' u7 T6 M+ B& D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 Y, Z8 X- K* H6 [$ g/ j; q) e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. X! q: X. n( U2 _! `( n W1 w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 l* @8 F- q9 V2 F& |- ?7 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ b) t/ e) k2 u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% O; F0 T- M5 F& i% o, h: S w/ Y2 f
} ) s1 t5 h! w8 b9 v) j" g9 ?: w7 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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