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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: y; g- l$ n2 {4 K% P+ v( ?- T, m% binput mcasp_ahclkx,0 u4 t% j# z u7 T8 U2 W
input mcasp_aclkx,
( B! w1 x1 c; R8 Uinput axr0,
( o; |3 I: ^" T9 h) ]$ c# z+ o+ u) i- h( H1 |: E8 v+ S( p
output mcasp_afsr,
9 a4 ^, A$ Q+ G. F$ Z0 Coutput mcasp_ahclkr,
4 u- p# g1 n; W5 `' F( F routput mcasp_aclkr,
' w5 y; D( s+ Z9 C& V8 boutput axr1,
5 J, v( r3 H& V% `9 r+ }% c* M5 M assign mcasp_afsr = mcasp_afsx;
0 K: d( u( |2 ]0 P7 G/ ?9 G* wassign mcasp_aclkr = mcasp_aclkx;
3 E% a i8 S8 m6 q9 t; }- yassign mcasp_ahclkr = mcasp_ahclkx;( G7 ~. \+ _* M- N) ?# N- A
assign axr1 = axr0; ( S5 H: w; W& j: x' K; t0 b4 o _
" ^, d: l2 r, F$ f7 B) L$ V! |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! [" c' [5 A: w, d* t: z8 m/ Lstatic void McASPI2SConfigure(void)/ ~; Y* t& v, A) b; p" Y
{
* Z- n& Z3 @; p9 R( U l W7 A2 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 l+ |$ Z: [# D, p' qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' a( x2 s' P7 B1 n; K3 G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' Y9 a! \: g4 b# ~2 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) @- a" J; {& ^; A! [' QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# j9 u, r6 |1 Q" G. Q; j
MCASP_RX_MODE_DMA);
w0 ?' C+ O1 P# b. P3 cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, k6 \) o" t7 N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 E: K6 | q! V6 X' O: RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , ]- I& c9 A, [( v3 \5 Q' u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 f8 O) X! u P' m6 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. l& D7 ~$ s- s, e3 t z e8 pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 @0 D* a: Y4 {3 L# bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, v" n- p8 V4 g8 \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, I" J& P$ e- \; K* b* H' zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 |7 D5 F s& q' ~
0x00, 0xFF); /* configure the clock for transmitter */
% N( [7 m' c: {3 _- B$ J% EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ ~- \4 d1 b: tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ ~, W% D5 {* I" k! vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' T1 \; b4 \4 [& `8 C0x00, 0xFF);: [; a0 W: \* Z% I' R+ w
( e, F) R6 Y+ [" J
/* Enable synchronization of RX and TX sections */
1 W7 b) z/ L7 [; G9 ]4 ^# S1 YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 N" n3 d7 Y" x% tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 r6 _" x# u# r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 F O* t' q9 _+ `. d" W
** Set the serializers, Currently only one serializer is set as: O% I! Y! a) G0 I7 C
** transmitter and one serializer as receiver.4 F/ o. g9 x$ f: F3 t! g4 Y; @
*/# B8 w7 s2 Z: U% w; D: T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 J" _* u+ f* S( ]; M, `* w( F2 \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' f: X! t8 P5 v C0 A: E$ H** Configure the McASP pins - }+ G2 t8 z$ C& {
** Input - Frame Sync, Clock and Serializer Rx4 e" [, s; e$ n+ C$ m2 s! r
** Output - Serializer Tx is connected to the input of the codec
: L$ M' q, a5 n8 y4 C*/
; z0 U) e ^1 E/ c% {8 _6 V- b% fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ D7 l$ {. Y' f. c6 UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) W; n) [2 B2 h# A9 e( y4 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& D- T" n, `# i7 Q" i0 W' S" O| MCASP_PIN_ACLKX
; H+ N4 U( ^/ t& n" O/ p6 X| MCASP_PIN_AHCLKX7 P; T3 J# l9 m% f {2 Z2 v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 w O- y8 |+ t- V+ iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 }) R" r) t( o! N7 K. B
| MCASP_TX_CLKFAIL
* _6 D6 o& u7 R0 V& }% v| MCASP_TX_SYNCERROR
6 j7 P! u _, }* d2 n( a7 M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - a7 X, k$ X1 W0 P, g# |% Q
| MCASP_RX_CLKFAIL2 z. `' k% P. L) q5 G; c
| MCASP_RX_SYNCERROR
5 N) j5 G. G+ x* }" z+ ^| MCASP_RX_OVERRUN);* U' K8 n, ]' D$ u( J# Z7 t
} static void I2SDataTxRxActivate(void)5 w) d! C; ]/ y% r
{. ~3 [3 d1 e) e# g4 p. v
/* Start the clocks */# C& G0 U- j( \4 O4 K: B( F7 h- g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! x: }( I3 U$ }1 Q5 }+ X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& C$ Z& U$ c% q. r# U" a; G- UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: \& ?% z5 X/ F6 S' y3 ?) o
EDMA3_TRIG_MODE_EVENT);
5 f$ {- K, A: FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* J8 h: Q8 H4 N/ W; g$ F) iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& z0 [! |1 _; S( m: v- y `. oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 R) o+ F6 A. R! i9 pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' f: P/ x' m% t3 L5 E+ W+ Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& {9 F$ s+ C5 r. [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 v, n5 j' E+ R2 F4 fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 x( g0 A; W0 O0 D9 f/ ]9 Z- y6 ^- Z
} ) G- W, I. C6 I4 w& ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 z1 @8 k( \3 S
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