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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 n2 `$ E6 k( I& a/ A* }
input mcasp_ahclkx, w4 Q) ]4 Z+ h0 X# j
input mcasp_aclkx,0 x7 q: x \& j7 o6 l" n k% @
input axr0,3 v* s: `# f8 `7 @4 u" t; h, b
* S( m, d+ g' S# C% R+ c4 [* K5 ^
output mcasp_afsr,
' k4 @5 L( V; |7 h; S4 ioutput mcasp_ahclkr,
4 k" r! m1 b* `/ i# a2 k! ^. v+ _output mcasp_aclkr,
# A0 h+ C& L/ ]+ Q [output axr1,) d9 f" p& q4 Q) s
assign mcasp_afsr = mcasp_afsx;/ b% S* [. B8 d! D
assign mcasp_aclkr = mcasp_aclkx;
$ D) `0 m* I8 p, O0 t! j& m2 Iassign mcasp_ahclkr = mcasp_ahclkx;- r4 N1 U2 x1 \& _
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ X; Z' B6 E) |; X; ]' |, } C
static void McASPI2SConfigure(void)
# J/ f3 X# h- n# I{
) {. |6 t: l% n; i' eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 i! y- D% n- _9 i7 |+ h7 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ E3 C: `2 j! Q& gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 ], k% l( E# B+ [9 m% T7 X+ HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ K8 h" f; x* Y K: i. c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 g8 p4 |2 ], ?) ~% a
MCASP_RX_MODE_DMA);$ i' }' H' D; L' R' b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( O; E0 d J; i. j/ P8 y9 JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ A- r. ]/ V/ ]6 V5 d. v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " z; z) U% J. x6 t" C4 T, \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 _% a0 } E+ CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 H6 b" U b. P, a. N, K3 u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ T8 H3 I6 c2 f1 ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. k4 A! x% Q+ }9 S; `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. V+ ~+ x, T: B/ G3 }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( g8 i8 r3 B5 t5 ?- [
0x00, 0xFF); /* configure the clock for transmitter */. n' ^7 ?0 ]- s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# g; g d6 Y' C) W C" X6 q" sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, I1 E/ v% H: n6 ^" o: ]8 jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 s/ q! B" [6 A! e- d3 T
0x00, 0xFF);3 U; F0 z8 k6 d( @
8 F; q+ u8 g* M; h* c+ n/* Enable synchronization of RX and TX sections */ " @( U3 V0 O0 G4 p2 z5 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 s- V( I0 J" Q! J" _$ GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: m% W$ h0 _9 P% l; z1 N+ E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 J+ \( G* d' k8 s4 g6 Y** Set the serializers, Currently only one serializer is set as
7 w) z. S( ?; f5 J9 {** transmitter and one serializer as receiver.
* {6 \/ K4 ], s- p4 h" u: ~2 f*/+ s3 \( O8 d8 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% L9 W: h6 h$ m0 K& W: Y) o! wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 L! l$ u9 V9 W4 Z0 }% _6 o9 g
** Configure the McASP pins " t# D( K" k. H( Q
** Input - Frame Sync, Clock and Serializer Rx8 Q( }5 @, N% r7 P* O; X- o S
** Output - Serializer Tx is connected to the input of the codec 3 l0 L: n5 L$ G9 U
*/+ U3 f& t! z8 {7 x& S; H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" X) x$ F$ L/ k s; Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ _0 c& U/ C1 o9 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! l7 K) R3 w- p9 N. P" V4 t; [: O
| MCASP_PIN_ACLKX$ S' v: m( q' P+ _
| MCASP_PIN_AHCLKX
' n @* j* B: T, B/ t4 f! J5 _) A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 J# N2 _& k* p4 o( G! W" k2 h9 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 R3 l! C T/ h; @# t0 z| MCASP_TX_CLKFAIL " `4 |2 `7 I6 w/ [+ I% d
| MCASP_TX_SYNCERROR
; v; H1 |, E( D) o/ i5 D. w* S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% s6 A& q# V7 J* y& t& j* K| MCASP_RX_CLKFAIL! I) p. Y2 N: a) [- _
| MCASP_RX_SYNCERROR $ ^8 o9 m8 R1 s6 [' f
| MCASP_RX_OVERRUN);2 y- S; R8 T* M" c+ B% a- B3 f$ q. x
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */% @# w6 S7 S" P$ w2 Z' T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 P* j7 i2 D5 m. e+ o4 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% U3 d) E! _9 Q- i/ `* e* s, R6 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 @/ G7 k/ e8 S/ _( y8 JEDMA3_TRIG_MODE_EVENT);" f6 B: a2 ~) \% M2 Q* P! V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' l6 b& }/ d9 I; j6 Y. X6 j* A; Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ [. S8 ^1 I4 c% ^" Y3 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 @ ~+ b' B9 d9 n- p- n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 m. d: G9 n, v" |1 M2 S4 dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 I' |) [$ L) w! S L2 \9 z! J! L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 n8 R. \4 [4 y0 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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) m$ y+ e: n) N/ n7 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 Q2 J' [) B' z b$ I
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