MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
0 c) N, R4 _  E8 R5 o% Pinput mcasp_aclkx,
1 J# S, t: g  k. w* k, j/ K3 rinput axr0,

6 t8 Y  `; P( K/ Z: ^5 loutput mcasp_afsr,
output mcasp_ahclkr,
' [9 ^) a6 |0 V% @& Ioutput mcasp_aclkr,
  a' |/ U/ `+ @! z) ioutput axr1,

assign mcasp_afsr = mcasp_afsx;
& M! D+ r' J0 g( Z' h; h( {4 ~- v1 r% Qassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

' T) y# W0 ^% o6 g  a: z
3 U/ E6 w  n5 L

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
6 x  l' @! L! I( B  a{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
3 x% c* w( z7 J0 p1 N0 i5 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% J8 E$ k/ x2 J' uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 X1 L4 A, e! ^! U. }4 C- eMCASP_RX_MODE_DMA);
/ Q4 B( Q5 \9 |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 u; `1 f& b8 d. Y7 a( mMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 R/ w# n% b+ Q8 ]$ R- V! }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
3 s, D/ k0 [& y/ {6 k% y( S1 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
0 c2 T/ E# t8 V$ p$ H; _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ E7 i" b/ X, O" w* w$ c6 C$ aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& C( n8 _6 ]9 c3 ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) [( c& N1 |# ?4 h0x00, 0xFF);
0 c/ o: g* v( x! b/ }7 ]
. M4 G4 H; R) _8 b7 I$ a6 s) k, `/ p/* Enable synchronization of RX and TX sections */
" X: [* B5 F' F$ H6 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 A7 W  p: T9 U) cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 Z- U: B; \  [3 M5 M& D/ \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
9 \9 p5 ~- Z, l  }6 P1 F** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
9 S" S1 z- A# V/ X- x** Input - Frame Sync, Clock and Serializer Rx
7 j, _9 J3 S  \1 K! H** Output - Serializer Tx is connected to the input of the codec
8 I- D" _! Z5 F5 P8 G: _+ Z*/
  n8 D0 l$ y0 t5 l2 u! y' gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; K2 m6 w2 N" F% n; [| MCASP_PIN_ACLKX
. R: ~' ~: B) L9 I% Q$ n| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
' o0 n" ?# k2 D" i+ g3 w& {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
. d" m, ^& a" w! ^" O" ?0 L9 p9 r| MCASP_TX_SYNCERROR
4 ^0 M* N: I* r| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ x* U1 U+ b7 {$ L( F6 X| MCASP_RX_CLKFAIL
( T8 \' x; ^! I2 Q, q( U; _6 l1 n| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
$ T' w4 e: ^" T}

static void I2SDataTxRxActivate(void)
  F2 {; @( w" F! _. J' n{
6 _# P! X/ a" y  h9 |8 Q0 }, s! g/* Start the clocks */
) u* x9 ?3 `# _  S# zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
: w9 q0 J/ g9 P* U7 A: Q! ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 J2 b6 B4 S) ?3 TEDMA3_TRIG_MODE_EVENT);
: ~" P) B8 L- S/ w; {) IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" M; r( i0 }$ [) P) g: J1 Q5 h1 m  aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
1 L# O; I! Q' ]" RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& N3 n3 b4 V. c+ U" c4 n% cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
' x& y" ]+ m! C  g3 Y+ J8 jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

6 ?' u& P% R4 Z; y+ R3 V' V

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

/ K: X9 u# `: t" E/ J/ V" q