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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, _8 s0 X7 ^- k9 C
input mcasp_ahclkx,+ W( b) K: ^8 t+ i/ V8 m( I/ d- Y
input mcasp_aclkx,
+ o6 g# W2 w; G' L: Uinput axr0,
* q1 ?4 ~& I- Z0 F# Y, R: k$ J0 ~$ m1 H
2 x( l$ E) {$ ~% uoutput mcasp_afsr,$ Q* Q3 }* q: J( m% j! o
output mcasp_ahclkr,4 k/ m- a M; p( ]' d. [6 F
output mcasp_aclkr,, x( R) b+ l7 [
output axr1,9 B; N3 d! f" I
assign mcasp_afsr = mcasp_afsx;
" h; T8 o, t' J- \' {# }assign mcasp_aclkr = mcasp_aclkx;
9 T1 N# t5 S/ n% i1 t2 h! H/ p6 D6 jassign mcasp_ahclkr = mcasp_ahclkx;" R7 L) H6 E/ A& C: D* ?; Q8 M
assign axr1 = axr0; # j2 S% A) A" p2 L( S& |
/ }# p& t4 |. f4 d$ F3 _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ k% b! i) E0 p( r$ K" Ostatic void McASPI2SConfigure(void)
+ k3 W, T" |, W9 h5 x{
9 _" w8 }; ^( N% A* ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- o# [! i- @6 O/ x" ]+ u' f9 X1 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* J- ]- e* t8 w& f5 \ y( p6 VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 r) Z$ r5 E/ ~; xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 A- G. N' a5 ?% h- h2 t$ W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# n5 y$ z" t- _, ]; m# m+ W! N
MCASP_RX_MODE_DMA);
5 J' Y; W$ R* q0 i. ~9 mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 q. Q/ k9 T3 t6 V# U0 \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 l1 A! a4 t6 `1 {. R" }' wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ q- \; q( J' L8 N. k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 u2 Z+ y4 c$ g) B2 v$ R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 P3 c! W7 w0 p& `! Q3 x. H: N2 xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( X3 U, {" r0 H& @8 G" @0 p% q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# N# e7 Y! t! c' y, n- Q0 Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - m) J% u$ k4 a5 I# s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% `4 _; F( a) O0 w. i2 l5 M0x00, 0xFF); /* configure the clock for transmitter */
! f8 ~4 E( o% R8 rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 Z) Z( W% d! O. h7 b( K# ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 n7 l/ w" w; x) f1 WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: ]& R9 ~# I& t. Q6 M
0x00, 0xFF);
. \( R( j* h3 U1 M, ?
$ K; u* I+ t9 k( Q& F/* Enable synchronization of RX and TX sections */ ' q. }& h0 X/ T" f n8 o' O6 q8 t2 R4 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, i m5 T. n6 P0 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- x# g$ n2 w' S: l# j' Y8 }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 L+ p# R: c7 A# S** Set the serializers, Currently only one serializer is set as) K6 Y' E) j& r* d7 V
** transmitter and one serializer as receiver., q, z# L* C* k" A" \8 |- u
*/- P% _$ r4 e6 R9 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- x& w1 M4 D' h, F$ LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 I0 V+ @# f0 {7 @
** Configure the McASP pins ?4 ^% l+ M3 X- E
** Input - Frame Sync, Clock and Serializer Rx3 {* k, {7 C' f& {% Q+ m( E
** Output - Serializer Tx is connected to the input of the codec
* @; q! V. A6 z- ~$ S*/
/ B5 v" z: b, H& I; X( u h% j5 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ B$ V7 c* O) P' w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% C# Q: K0 P {( R# _: CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- l- I* \& ~( V2 h' Y. l1 ^) c4 w| MCASP_PIN_ACLKX& G P0 b8 v1 p Z! s! Y' p
| MCASP_PIN_AHCLKX
! i0 o, D) g; o( |) F+ I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) R: u) x3 [: H: M# H8 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 w5 |. F3 @& I5 I' F$ ~| MCASP_TX_CLKFAIL 8 k8 V* |; q# }2 K, C- t
| MCASP_TX_SYNCERROR' W9 j! V: T$ o0 \8 t+ d' |2 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 [# Y4 b+ o) \! ]$ r1 S$ T6 ~
| MCASP_RX_CLKFAIL9 c5 V/ |! S$ D! i1 c8 B
| MCASP_RX_SYNCERROR 0 p1 G% l8 ?; d
| MCASP_RX_OVERRUN);
$ M! t: o+ q1 B- y} static void I2SDataTxRxActivate(void)
3 z: d: G9 @' a{
' k& x1 c ~% R. [( S/* Start the clocks */% G4 B7 D* t+ I3 x0 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: ~- C' B, f' \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 g& s# j* F E- S ]7 C0 C) rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 S8 b5 _6 ?; q1 {: S6 U O }) @
EDMA3_TRIG_MODE_EVENT);
, ]( w8 K7 C' c5 Y/ _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 r2 E1 i" M7 V# xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- N ~3 K4 A; x3 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( f+ v k/ _" U" b" r6 D$ B! d" q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& @4 n3 W P: A1 z) T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ `* `* B3 @( {0 v: ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' Z* i9 z& }7 i+ CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 F4 T8 x* Z% }+ _9 y- ~+ y}
( }3 s2 S- O/ Q( E. ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% ~* O- n8 A, v: O: r' E; L' { |