|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 s! l1 g- D4 E; j0 o) vinput mcasp_ahclkx,! ^8 V! Y. g+ u! R% R0 Q! ] K1 D
input mcasp_aclkx,' @4 ^% H r5 N$ {* \
input axr0,6 ~; J# Q* n+ j, J9 W/ F
, b8 h: K9 B z6 d# H
output mcasp_afsr,
! I' r8 m* E8 q9 W; Loutput mcasp_ahclkr,
$ Q6 v; n! E+ M# g$ J7 foutput mcasp_aclkr,9 \$ Z* Q/ a% O. o( l ~
output axr1,
r- s1 u+ _ a9 O) A assign mcasp_afsr = mcasp_afsx;" C( e o1 n' B4 S, ?
assign mcasp_aclkr = mcasp_aclkx;
/ K- O% h5 D, r! l0 p4 `assign mcasp_ahclkr = mcasp_ahclkx; |( |5 t, j2 e3 F t% w7 X/ w
assign axr1 = axr0; + s4 x+ S* d5 i
* `+ q u7 F" q; N) ^# b7 {5 O2 L" z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , m5 T# L1 [' ]
static void McASPI2SConfigure(void)6 y" l" x) t$ R, o( i/ w3 z; h9 Q
{# Q; Z7 X V: l/ Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 n( b& P7 n9 _' @5 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 [7 u+ G0 L$ b! s: Q4 B( w `4 OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ s& ?0 |, [& U: A! S) R* oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 D5 N4 [8 ?5 g: Y `+ H6 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 Q4 o4 q( U9 i! L, M- P. j
MCASP_RX_MODE_DMA);1 C8 ~. \- P$ }, n! V" y" D* N! v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- @, u& O" _/ u8 V" J7 Z1 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 z9 y0 x8 ?& o, [! T3 x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 N. g2 z# t& c' C, }2 a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 P+ |% `2 w( z4 B: J) S- Y6 mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 c! K: l% D8 \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ d3 r! H9 h1 z7 S6 w5 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; f {* `% Y% a. r: x! i* Q% B- xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 c8 g% p; | V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," S% s) l$ Z$ ]# i6 x
0x00, 0xFF); /* configure the clock for transmitter */
h* h: m! W/ B, xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! y4 b) z! L1 k) h& O+ E3 X" SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " `$ i4 m6 @+ T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# [" e4 r+ r/ S$ t, @( ]" M: g7 H
0x00, 0xFF);: j9 z3 ]3 I& B% k" Z+ c
0 `2 e1 K' {" O6 [' l; W" E
/* Enable synchronization of RX and TX sections */ & |4 E9 N# p+ m. h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% h+ |0 N/ v: }3 S/ xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& |; m# \3 Q6 A, S$ T2 C& j7 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** f7 a5 [" E4 z, r# A* v% d# D
** Set the serializers, Currently only one serializer is set as
# o' R* o" y! V7 O( Q# u** transmitter and one serializer as receiver.
( n* M# M+ @7 ^+ A! `) ~*/
8 G* I; n1 S' u7 `4 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ z& @; C& D1 m- ]: u; V9 o" h* B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 _, E/ F+ p3 L
** Configure the McASP pins 8 L- x7 }- S5 g" Y K6 S3 Y
** Input - Frame Sync, Clock and Serializer Rx
" w& {# e7 m: K- n) |7 _** Output - Serializer Tx is connected to the input of the codec ) m3 e f( @! t
*/
* r% c. f, G' R' a) iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, S1 }1 c4 n1 M" m* f4 [( o+ |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' E1 X# t, N" ?) M: q" E" ^3 PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 W8 b1 |( |- g: y; @2 b5 ^+ F
| MCASP_PIN_ACLKX( j I: b1 s/ H
| MCASP_PIN_AHCLKX
1 i) ~' z0 a# R' W' g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 O }- F1 u, c; \- U1 s4 n: z( BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # C; P/ m+ \7 R2 z
| MCASP_TX_CLKFAIL
3 S" y' |/ {: j. ]6 s| MCASP_TX_SYNCERROR
- z8 G' N9 w5 U& s. z. b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 H* x; K. j# Q: y% @| MCASP_RX_CLKFAIL
6 m" [9 P; {6 m7 M; V6 D| MCASP_RX_SYNCERROR : F8 w; {3 o2 Z5 W0 X. B
| MCASP_RX_OVERRUN);4 G+ `5 _8 ?4 [
} static void I2SDataTxRxActivate(void)6 v X$ n( @0 B9 g8 u# @( |$ Z4 j% P
{
8 [8 k5 J1 w3 e( r, l, d7 j* `/* Start the clocks */
5 t; ?) @, Z) v( `5 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 E. {7 |/ M0 m5 r- dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 k- u1 e# }1 z; J C% bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# i1 g- ^% E# sEDMA3_TRIG_MODE_EVENT);4 q% ?- L/ o1 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 V, _' ?" V; P* r; P- E1 F( K. hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ b C* S) V8 e. ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 { A( `% d9 z' _6 J+ vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: Y" b. ?* ?7 k: |/ f9 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, L( \* @4 D& V! j# J9 m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: ~; D) P" F8 [$ A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 `- @/ r: d) M+ |$ B
} 9 Z. ^* _% R3 g8 p8 y' l# l H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / L) v3 H5 R- H4 x+ ~8 x- X! K
|