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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( P5 @: u Q* Y
input mcasp_ahclkx,
! v' i0 }: z5 ^$ D3 _; z% \. ginput mcasp_aclkx,8 x! f* w- ^ B" u+ ]3 O
input axr0,
$ q# ]6 ]/ {; \
6 t* Q; c4 x: D% F3 ~5 G6 z' Boutput mcasp_afsr,
* o- Z0 Q- M" F* |! w3 X4 R3 J0 w% Ioutput mcasp_ahclkr, Z2 X" p4 S: |! v! i. @
output mcasp_aclkr,+ {% c9 K9 R+ S0 R
output axr1,$ O. y8 L" T+ K V9 T9 M
assign mcasp_afsr = mcasp_afsx;
9 v/ w8 k2 T J+ K& Sassign mcasp_aclkr = mcasp_aclkx;! G/ O0 y% U* r' _2 [
assign mcasp_ahclkr = mcasp_ahclkx;
' [- l5 Y P# s- |0 passign axr1 = axr0; 5 }! |- s5 T2 ^: l
/ F# V/ ^! e) f6 ]" I7 M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 s Q/ |; w, q
static void McASPI2SConfigure(void)
7 I4 z+ Z( e# i; k; x{, R! b& E6 n6 L3 p5 R; |( `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( A0 {) A8 U8 ]) [% h* `; T pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% O5 V# @# T. [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 }; e0 G* n) A! fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* G0 }- ~1 }; B ]0 q. k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ i6 s* x) O- W' u4 c6 gMCASP_RX_MODE_DMA);
8 n- G& o- ^9 F6 h2 p' `6 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" I, ^5 E0 g. ~5 @4 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 d4 S o& O: W1 r4 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 F3 l% u. {7 i9 [/ M) pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- ^) T& B! U7 w3 F% T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & A0 \: f' S4 a2 H' S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& M: g8 i8 R) i6 ?6 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); Z X' Z6 _& H& r, L4 |. _" u2 G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / F% i1 t, G; M: _; r' {1 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. O$ [) A8 R& N, c3 E! f9 k0x00, 0xFF); /* configure the clock for transmitter */9 @; d7 U& D* P" T( e3 z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
|9 x ]( n& Y3 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / f6 q. I2 S, v+ i9 n$ f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. C( t: C0 `2 X0x00, 0xFF);
* s& N' ^' t$ K/ C7 \) H8 [, H2 E0 f
/* Enable synchronization of RX and TX sections */
% K; j" I" I" `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: T) y6 L1 r. a: JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) f" T4 U1 J- {0 w, l8 Z/ @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 _, d7 t2 ?% N3 A) P. t7 O" B% H
** Set the serializers, Currently only one serializer is set as
/ T0 W9 ?% `! |* `8 b** transmitter and one serializer as receiver.4 {! I- \% o9 M1 m' J0 ~% }
*/
5 \" w/ K! Q/ U8 w9 C3 U/ qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 `$ U+ C3 c& {# N: [* P! s jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 }0 p* ?+ Q$ n% @! _: {: X7 P
** Configure the McASP pins & W' I. E6 L8 L( v8 |- m5 N
** Input - Frame Sync, Clock and Serializer Rx/ ?2 V1 h. m% y6 [* e; ?' B
** Output - Serializer Tx is connected to the input of the codec
, ~/ r/ P3 L1 j) ?# J*/
7 _3 u6 G, ^, b: {; T7 I7 @: @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 h8 k3 G+ o0 C2 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 L& _, v/ b, z; p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. @" N3 s& Q+ @9 B8 w' O% \
| MCASP_PIN_ACLKX
" p9 T3 [# B5 [9 E, z0 u' F3 f* \| MCASP_PIN_AHCLKX
0 P% D+ z; Z7 s; n" l5 W1 t# y: I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 ?' I4 H! L, D) v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. B$ p8 D7 i. X9 I| MCASP_TX_CLKFAIL
9 x/ M* Q$ x0 S| MCASP_TX_SYNCERROR
" ~0 X$ w0 X- ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + I. v- X3 b$ Z
| MCASP_RX_CLKFAIL
; H9 d# i' j @* Z8 w" Z4 M% Q| MCASP_RX_SYNCERROR + w i/ ]. [9 v% _- A V3 |4 G
| MCASP_RX_OVERRUN);5 |/ W& E/ I$ L% |0 O) j# O, e: V
} static void I2SDataTxRxActivate(void)9 C' y% z5 @* s0 O
{7 X6 U+ X" U' B4 C$ ]% a
/* Start the clocks */" d( ?" {" g' e1 T/ K, e) `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 M/ ?7 ^* p$ i" J5 _, O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 ]# F8 l: f- U0 i* d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- ?- b/ }5 ^8 G
EDMA3_TRIG_MODE_EVENT);5 b( X; M; v( u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " K5 i. e1 s: R( {+ E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) f4 m0 l1 ?/ ~5 |% h* uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 ^2 g$ r3 O% x4 ?1 I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& C6 H+ C0 P: q9 J2 h+ C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! w1 z7 k) e& P ~: k1 O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; g! F6 ~5 T" j; ?" M* V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 d9 g( z, K) n6 R}
3 G3 I* q3 k" G& X" _- \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : I, v& j$ k0 }% Y- I! x
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