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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 P- I% V3 _. O$ K4 C& r0 K- ^input mcasp_ahclkx,' ?0 d" _+ z% U2 \2 H
input mcasp_aclkx,
) q* t+ a# I: N3 a! ~8 [7 c: Cinput axr0,
* M6 J/ \' X) g$ H! d0 K) s
8 B8 K9 i- G# a# E \) C8 poutput mcasp_afsr,
* g# A9 _) X9 N! ooutput mcasp_ahclkr,
8 w' w% W6 w# qoutput mcasp_aclkr,
" f" D$ R& ?$ O; ]/ c) p9 Q( xoutput axr1,# j/ S: Q9 d1 d3 s6 u% h/ w
assign mcasp_afsr = mcasp_afsx;
, Y- w3 C7 f7 g6 l0 a6 K0 |assign mcasp_aclkr = mcasp_aclkx;
7 a, h% F+ j+ \assign mcasp_ahclkr = mcasp_ahclkx;
: S! J6 o9 m" v# |9 G* x5 e iassign axr1 = axr0;
8 S4 I, |& F8 r" z8 |0 v8 r. Z1 T: C9 [9 a# r4 I9 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 V) }! @ C9 p" p; q9 |: h% S
static void McASPI2SConfigure(void)2 F1 f; b. S4 q; h5 ^
{4 U6 I( v- D3 i2 l% Z& S7 Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 A6 V% A0 G5 N( D2 \& f/ fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ ~: C* M Q. B" w* LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 z) R% [. Q1 e9 x+ E; LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! D7 `4 X6 E7 p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 e2 p/ Z, Q1 p/ n
MCASP_RX_MODE_DMA);# Y+ H2 ^: ~$ a4 k' |' K5 O9 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: F- Z h% p, r3 a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 H; h0 A0 @6 l! N( r6 D. OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 B8 ~" s1 x. v* F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) R: {1 {! Q2 [( u3 e# Y* O5 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( G+ q( h5 ]. Y0 [( A5 {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: r% a% u' Y3 J9 b2 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: d! T1 f: _# A' ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 G4 m7 j# G$ p' DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 r# i* P. s" p/ g
0x00, 0xFF); /* configure the clock for transmitter */
" H' c/ k; F0 l, ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; y; F$ g, V; L1 T2 i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); F5 r* X [3 f) }/ x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ P5 o) S/ a. k+ e) X$ g8 i
0x00, 0xFF);
3 i! a. A4 ]$ h) V5 r; Z7 s' H# n I) A/ }( m/ Z6 Z
/* Enable synchronization of RX and TX sections */
6 o" ?% ]# v: OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' G+ u3 V, g4 `! X3 w. z! O$ KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) F$ y6 e) }: uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 {6 M4 \& q, _3 o# l** Set the serializers, Currently only one serializer is set as
8 y9 q* ~8 K+ F** transmitter and one serializer as receiver.+ [1 z& W, q8 S
*/
- ?; [+ E- {# @$ y6 b1 U: jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 w- g$ ^. P7 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ ]- W- d, j, D6 j" i& w
** Configure the McASP pins
" z5 P1 {: \, h+ s( k+ [' D0 `: i** Input - Frame Sync, Clock and Serializer Rx
, Z; Z, Y2 Z& R% P$ I0 `** Output - Serializer Tx is connected to the input of the codec
; M$ c* A$ _9 ]; S0 M4 w*/, ^; G4 `0 v0 k9 A3 N/ s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ o/ {( u& F0 G0 \* H2 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 K& u1 G4 V$ H1 ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ y+ [4 t L( j8 j: l& Z| MCASP_PIN_ACLKX
! N5 O$ R2 i' C# Y| MCASP_PIN_AHCLKX+ D* Z# Q1 S6 C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! Y. _! b C8 @0 t1 A4 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 I% l0 C; h* B2 ~2 T5 c| MCASP_TX_CLKFAIL & b4 S, I+ _' i9 z: i0 V
| MCASP_TX_SYNCERROR
: A- R6 T! j$ q$ U- t" d( Q9 M7 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; o& _$ K: m t
| MCASP_RX_CLKFAIL0 o$ p( U1 ^% U# s# L, o
| MCASP_RX_SYNCERROR $ Q5 U% i# c* Z8 C
| MCASP_RX_OVERRUN);) Z4 Z, |/ r" J& Q& [
} static void I2SDataTxRxActivate(void)
" {3 n$ i* v: _# w6 E" I, S{+ @9 G! _& p- B8 K5 ], H- ^* T
/* Start the clocks */2 @' M5 R- V- b! T8 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! z6 O6 n, `+ B- N2 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 z8 X* o' p. E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 o! I' ?8 V1 v1 z+ V
EDMA3_TRIG_MODE_EVENT);3 k" J8 e& d: z5 w* N! h9 W% J: r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: K4 a; \# O& ~! Q' h* `3 @- QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 i( e8 w$ m2 R% i- R& a' X& F% O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 E% V( k8 ~) P2 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# B( K) p' K+ x) N9 G" f {4 y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* r4 \1 g/ n4 X6 i3 P7 d* X) W$ eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" S ~5 k) }; k0 I% L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 ^7 C& F5 i- G}
: @% [6 Q) _) u2 E [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 ?8 m0 H7 O, j7 q' ]7 l
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