|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- R* h$ W" L! m$ Z
input mcasp_ahclkx,
6 d+ a, t3 C" J, M" Y# Sinput mcasp_aclkx,
0 L! |* n; z, A& Sinput axr0,7 I. \) ?* M0 ^7 \' q
6 i" I, g" t Aoutput mcasp_afsr,7 h- O7 D4 h8 E/ k! ]% I
output mcasp_ahclkr,, F/ {" {& J: f; t
output mcasp_aclkr,
3 o' P* v0 c+ O! k! I6 z; aoutput axr1,
- v, ^" N$ M2 e4 }- U9 P assign mcasp_afsr = mcasp_afsx;
; c6 Q: p$ h W4 A) Tassign mcasp_aclkr = mcasp_aclkx;. x! Q) A* E; ?3 }
assign mcasp_ahclkr = mcasp_ahclkx;: p2 j7 P7 Z6 Q
assign axr1 = axr0;
6 n/ x3 y U9 M; X: |$ X# B+ k+ x, G6 b1 `; r# q1 }$ ^' r. n7 T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # a8 U$ x- `: ^; m+ K
static void McASPI2SConfigure(void)
# ?$ F" b0 G2 E# C% w{
2 {: t) f/ l) b5 X6 c k$ x1 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 j9 Q6 |0 }4 V' w5 I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: y" Q2 o1 h+ m! R/ |% H( b4 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! D% E3 v& |2 `/ t, j4 _: ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 p4 P2 A4 _0 \) P8 q: W# z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 h2 N; q' |3 K8 f2 R0 O
MCASP_RX_MODE_DMA);2 T# |/ z+ P6 u) a: ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ U9 n5 f) A4 m0 z) m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, ?! ~7 h6 t1 v) z# e# sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; I0 V5 o6 b5 J$ b& `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; m$ ]" n0 y6 E! R* @) i+ pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# Q& c2 N$ N/ @- L8 ]6 b& NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- X& }3 B! U: L3 T% @: k, ?' ]- B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, a. u0 E! _1 F" KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 M9 \ Q7 A9 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ W& k! R" k) D, d& F: k; l0x00, 0xFF); /* configure the clock for transmitter */
" v" t0 g. W7 R- E5 F' FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 t! g4 S6 [7 z3 b. H- l0 v; Q( XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 R* U- k$ e& `$ qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ I' O& L# y0 S. {0x00, 0xFF);
9 ^( Y, x. i+ b7 v( a M1 N0 f' Q; B% O" d3 h: i
/* Enable synchronization of RX and TX sections */
6 r! p0 P* k* [' }6 ^: X4 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% {6 A: W- U' k# M$ B. v5 q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ I4 @: Y- ?9 K% ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ S K. T* {0 d. _+ \( ?# o( ^$ u** Set the serializers, Currently only one serializer is set as# q0 {6 F+ w8 V$ l9 I
** transmitter and one serializer as receiver." @& A- A! M( f! b
*/' w+ s/ h W0 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* q' b/ |+ [( K8 v: a1 RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 R8 L; ]/ O/ v: b1 Z7 w
** Configure the McASP pins + ]0 p, p" J0 V& o" R
** Input - Frame Sync, Clock and Serializer Rx
9 W) z/ [3 z) ^** Output - Serializer Tx is connected to the input of the codec , X& r6 m, s% m4 D7 b2 r
*/2 g2 f6 f% z) I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 C4 h w7 N, u" u* B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ \9 N$ h" Q3 K; aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ g7 S8 `' s' C9 U ]0 V( f6 d
| MCASP_PIN_ACLKX
7 Z& T) _8 q- G# k! ^/ c| MCASP_PIN_AHCLKX
/ z, e9 @# O1 e6 a4 M0 P4 U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 n6 s2 \/ l1 g" T+ C& {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / C; J1 }# I6 I6 o
| MCASP_TX_CLKFAIL ) G H" e7 K, T4 i; Q7 W- q% }
| MCASP_TX_SYNCERROR
- N, [5 Y# \' g4 A5 v, J. [* Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
X. L" X) Z# O# B' {* x, p| MCASP_RX_CLKFAIL
, C3 n* H: b- z) }1 B| MCASP_RX_SYNCERROR ' ]; c' {1 c% u2 C! x& j0 K e
| MCASP_RX_OVERRUN);# ?1 z! F; e O; U* E, f, O9 d
} static void I2SDataTxRxActivate(void)
1 [9 `. d( I s{/ l3 {9 j; U: E, m" ^
/* Start the clocks */' B+ r7 ^8 s4 B8 [/ t9 ^ z2 ~5 ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
R% \' X4 H2 y3 ^8 R6 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! N' D# l- V7 m: b2 a4 [! kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( S) q8 R- G) M7 S1 nEDMA3_TRIG_MODE_EVENT);
7 U$ j$ S& }7 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 l; R! o J! w; q/ ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 j& ?$ |+ G+ A/ w3 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 L7 Y1 F9 C% J1 oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
t% ] ^5 | Q. x0 X, Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 l' c$ `9 L. H: V1 B( z( I# k& sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 w0 x7 G. \0 g: k5 h. ~4 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ h! {( Z: H. D. q/ ~0 K/ [9 {! l, @} 9 s$ R1 T$ z, S/ y* R! l; F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. H4 r/ E3 e/ O |