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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& U! C& \$ m; F3 S5 U& winput mcasp_ahclkx,* o7 B: ^! R+ t* S
input mcasp_aclkx,
! a& a+ b/ K8 K! q& `input axr0,9 C! v. l# y) G; f/ o2 V
3 g i; p5 s7 H( ]7 L" z) uoutput mcasp_afsr,0 @7 w- }! D' n8 L0 @6 e$ `& {
output mcasp_ahclkr,
5 G. _& {! p7 n, zoutput mcasp_aclkr,9 Y! |: [0 p4 T# X
output axr1,# {& K4 ~+ A, }' v% j; a0 _
assign mcasp_afsr = mcasp_afsx;
5 z6 @0 o; s* q4 G; V4 b/ V" Tassign mcasp_aclkr = mcasp_aclkx;4 b& b8 A* T& c7 ^+ o6 w: g
assign mcasp_ahclkr = mcasp_ahclkx;9 D0 g: K6 s8 Y9 Y
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 H9 Y5 k* F3 S' N8 Z9 Fstatic void McASPI2SConfigure(void)
- k* `7 u# P* U0 @{! b: K) D5 e/ Z9 v5 O) R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 Q' i, c, j% ]$ ]6 C7 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( m9 ~+ a) y* b6 Z/ `5 p2 }/ r6 c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ i6 v& |9 U. s" _' l3 `# A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! U9 O: r8 V) t( i- r* x0 X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, ^* o4 j4 J' t+ ~2 w' J
MCASP_RX_MODE_DMA);
4 i+ Z5 n' A" B% K+ LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 O i% D' T/ W4 h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( a' V# p$ S6 X- M# [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 s, O! t( {+ @' q9 k5 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* E, e5 [3 |+ g0 ~0 \1 D' m+ qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " k. n1 R% Z; l6 v! _0 T3 g- w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) i$ _4 O& z+ J7 `/ M# f4 A) g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
C' Y. r+ o* f: h2 q) sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- u- p) F$ ]& t3 G3 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- M' r& S7 b8 y& ], X( j# u
0x00, 0xFF); /* configure the clock for transmitter */
) f `4 X5 R- g# tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' r( J7 ]& g2 X2 sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 k# ?5 n6 t: c6 l4 OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# E' ]1 b2 c; t2 p+ u
0x00, 0xFF);& ]" c: T6 H7 m& w7 H+ N
/ v! p/ P+ G& r9 Y% N6 N/* Enable synchronization of RX and TX sections */
/ z6 Q9 r' U+ h1 bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" V3 y+ `; A3 p/ Q4 K" cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' R6 B' [0 L+ F, x- f8 C! E. {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- c9 V' |/ ^' J& r$ l
** Set the serializers, Currently only one serializer is set as4 e2 m; |3 o4 f; S+ d% q* a
** transmitter and one serializer as receiver.4 U7 l" v3 U; f% M& n
*/
; d9 d4 i! ?) U+ F- r' GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 k" u9 L3 V7 v" R2 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ {, D9 z0 A1 P
** Configure the McASP pins
Z: J7 X/ n+ {: k* a4 W- j** Input - Frame Sync, Clock and Serializer Rx' `5 G/ g% E! A
** Output - Serializer Tx is connected to the input of the codec
1 H9 h4 ~+ D" o" Q$ M6 C) J*/( P$ m* Q, z+ A9 k; r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% Y1 e+ q, C% \, R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( @- D* {) v$ e5 {+ ^. qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 u$ J5 G% @( I& F: h| MCASP_PIN_ACLKX, J- S0 @. ]8 F4 `7 ?! X
| MCASP_PIN_AHCLKX% P: z7 n6 t" U! d: ~7 b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& G5 _. u4 o" u, ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + k; x4 H7 y4 v+ c. Q& O) ]
| MCASP_TX_CLKFAIL
" c: H! [; j! E| MCASP_TX_SYNCERROR
* j& P7 b- z1 D5 k( v. p- y! b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! n: O. Q* J6 W& g* x
| MCASP_RX_CLKFAIL
* X; v" o/ C" c/ h% M| MCASP_RX_SYNCERROR 1 ]& ?" c, L, x- G4 Q
| MCASP_RX_OVERRUN);
) M$ Q7 b3 n* Z$ ]& r: H} static void I2SDataTxRxActivate(void)
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/* Start the clocks */+ z l& `0 w+ X- t, I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% } K2 L% {8 @: H) wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 V, j) E# o* P$ {0 M* C, h% \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, g; @' w: C" M' m' n
EDMA3_TRIG_MODE_EVENT);: _7 }! U3 W7 Q' }+ X- a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& f3 g& R0 O9 ^, d* a- wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" O" Q ^9 f( D$ z6 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 I: p7 D% D& ]" q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 {" W; p, m* t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 |* \ J3 }3 m7 E1 z# gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. [- g& N6 W I5 x9 K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); ?: z3 U" |1 C7 C3 `
}
( Z( m% s- F( r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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