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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ E Q/ v! Q/ T; uinput mcasp_ahclkx,1 t4 S7 J1 N2 k; G
input mcasp_aclkx,
6 j- n4 w) s W: G) Hinput axr0,+ w: r' U9 H& E3 r) U
) H) D, |: {" T. H+ _$ ~
output mcasp_afsr,- U% t$ z: F/ C
output mcasp_ahclkr, b: h7 Q9 R% X8 b
output mcasp_aclkr,
6 `( y4 {+ [; N# A& Y$ `, a1 u$ P1 ?output axr1,5 w3 G2 a8 e) y$ Y
assign mcasp_afsr = mcasp_afsx;: `* l+ f: K% U1 x" O
assign mcasp_aclkr = mcasp_aclkx;' m2 k4 C) n( k# _: H2 O% t
assign mcasp_ahclkr = mcasp_ahclkx;/ Y6 J: T) {1 q2 H6 d4 @
assign axr1 = axr0; 9 T o' G" A* B/ t* }
: C8 A$ ^ Z% z& @1 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 {* B$ c- ]0 v+ ~static void McASPI2SConfigure(void)$ C n% ]$ {: C8 O# M. M0 m
{
6 \9 x0 S6 d% l/ OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( M( @6 G4 [: m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 r0 B' `+ U/ Q4 N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); i% x7 s8 d0 i& K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 ?% B6 J; k; @- \2 Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* X" m8 U7 j) p5 ^- I6 z! e
MCASP_RX_MODE_DMA);9 q3 S0 E; `4 A s$ j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 L/ V' C0 r( W# U2 ^; Z! R0 `6 T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 Z; H; \ w- k8 _2 q2 w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 _- G' [. Q6 Y R* D: pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 w; f7 g( W* x8 L6 N6 B" g) u1 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 V: ^8 q) _& M; V+ K% M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 R O: ^( D3 q* Z/ i6 l6 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. i) T& Z- ^$ l) j3 x R" uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 B& G9 q0 P8 J" K( w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 L4 o/ w2 X- H' B- v0x00, 0xFF); /* configure the clock for transmitter */7 P) W) |) F9 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 Z' P# f* H6 ?6 I/ c% g' S0 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " r3 S' ]3 G+ S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 q2 j, {* w$ U# a5 R: B9 k
0x00, 0xFF);* ^# h$ g) P- l6 e
- h- ^0 Q+ d6 ?1 l: E0 c/* Enable synchronization of RX and TX sections */ & h2 z, C. W% {5 N8 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ E8 ?6 w0 Y; }' @! a1 H6 [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 p( E( w" e- o o5 D" T5 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; P3 h" R. E/ W) j- ~9 y1 q- f** Set the serializers, Currently only one serializer is set as! [+ I" N5 v2 o0 o7 h5 l
** transmitter and one serializer as receiver.
, `6 Y, T' r' }, |' U*/
& w, u2 q# {' c! M. j9 G: t5 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" y1 h! X! L# g9 b; _6 Y0 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ p: \6 X2 c, y/ i: E** Configure the McASP pins
! M% R; P L; G* C W** Input - Frame Sync, Clock and Serializer Rx& u: B0 M+ c/ W* g0 O
** Output - Serializer Tx is connected to the input of the codec
2 m& r& S: z0 p: q1 {( r; J5 J1 F*/
4 H# }" U8 m+ NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) ^# ~% u' w5 ~! @" C2 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 |; F) M( ]) W2 r$ k n) ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 u: L5 R0 x$ t, D" u
| MCASP_PIN_ACLKX2 I# M3 g2 {, N! d+ F
| MCASP_PIN_AHCLKX* h) l0 Q( q8 H( m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( C; s( W% M# Z- L e5 iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: I# K6 \" Q6 U' Z| MCASP_TX_CLKFAIL
+ N$ X# Y1 d* t| MCASP_TX_SYNCERROR
5 O2 B4 Q- `& P! S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& I: M5 R. f% o| MCASP_RX_CLKFAIL
z" U+ O' K' c' _, U/ x/ A( ]| MCASP_RX_SYNCERROR
( m4 k) [7 t, G- q| MCASP_RX_OVERRUN);
$ w k" M5 E5 Y. t# ^} static void I2SDataTxRxActivate(void)
, R( g( @4 O$ i3 m{* s A3 T+ q$ w9 c$ s) n
/* Start the clocks */, Y7 J2 w: K2 l; W2 _& w% f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( I0 [: \$ N/ X& P2 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ `+ e" C. w* g0 D8 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 b( N( a0 Z6 K
EDMA3_TRIG_MODE_EVENT);4 S; D5 z* Q6 Q, m4 a' v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" z; }$ }. [1 T0 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 |3 o+ l2 H, uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' p; u. Z, h* t$ x+ }% h9 \$ @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ E6 I- X8 f: ?. x7 C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) ^6 _) d: A' ^" R* u/ [/ EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 \& L* S- D7 Q9 |* h0 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) K9 ?5 D" P- \1 f) S" W} 3 a6 p9 c+ a7 C) e7 M2 \. T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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