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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 M: d# X7 L) \' J a
input mcasp_ahclkx,+ y" U2 q8 ?- C& r) w1 Y4 \( d
input mcasp_aclkx,( A' _. A A6 z4 D1 V5 z1 @
input axr0,
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5 i) s Q8 X3 ~+ W3 m$ i9 U! [output mcasp_afsr,
+ L, c# P# P' S& x7 qoutput mcasp_ahclkr,
1 K% o4 g: `) f# d6 J" Foutput mcasp_aclkr,$ i# H! j% l, M
output axr1,
# ~9 g# v& b5 A8 i# B! i assign mcasp_afsr = mcasp_afsx;
3 S% v+ ^9 B/ Y3 `5 E$ v2 wassign mcasp_aclkr = mcasp_aclkx;+ C0 k5 R" h3 g' ~' _9 A
assign mcasp_ahclkr = mcasp_ahclkx;
% r# y: z9 }! r9 L- z9 F* d9 xassign axr1 = axr0; # l4 u' j/ j6 V# r2 ]5 N4 ]" |
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - |/ X" e; I7 }( {8 J6 q* E* q' A
static void McASPI2SConfigure(void). v6 t0 X* w3 G- m7 {
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);- O3 O+ p% `1 K8 o# _. r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ z: z6 L# o) O2 x, F) IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 \" Y4 j) f: D6 F) y; Y7 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 M2 _% x- |* g- yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 k6 a- F$ o. y$ A; C% q* N+ f2 W% c
MCASP_RX_MODE_DMA);" L5 g- ~" j1 ]# O% |% O: S5 [/ X) L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( O {9 C. W; K+ [. @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. W: {* [' \$ H8 G1 uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' T Z) M9 {! m1 c& |5 y% ?& F% d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, D( @( |/ Z# h/ J! A0 p' z3 OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, z% y. x7 B& B; k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 ]; D; n8 w/ i" _; KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 g8 R Y$ {) t* K" e$ ?+ T+ U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 y3 \7 m, P' C$ Q2 }" N. z* ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: A; L8 y1 D; `0x00, 0xFF); /* configure the clock for transmitter */
! _ L4 T" p7 c9 ?5 Q" `: RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ @9 o) f1 W* m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 h0 c# v0 E# A) M$ W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& y" X7 Y4 Z# t) R D
0x00, 0xFF);- _, I$ v4 g: Y$ a5 X
' s5 l# r' ^% D0 `# N/* Enable synchronization of RX and TX sections */ 9 o0 C# {' G8 ~, y0 G/ c/ U9 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; _0 I) Q& v3 J6 C- _5 p6 z3 e; YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 U9 N. q) N/ X" o+ q) H) V2 G$ e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ h% @2 T6 H" i8 L, I2 z: g
** Set the serializers, Currently only one serializer is set as
& c+ W' K; c; R& g* y- \, b' B** transmitter and one serializer as receiver.
4 J* y/ ]5 [( S*/
`+ u. y f' L. \- bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ p+ p H. h( k. t, ]! KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( i, m$ t; q$ y
** Configure the McASP pins " F$ I7 c3 o! z6 E* W* c0 U
** Input - Frame Sync, Clock and Serializer Rx8 T0 A3 c$ k# r0 S
** Output - Serializer Tx is connected to the input of the codec
" Z; B7 o2 ^( {& n6 G*/
9 q2 B: A+ o5 Y& q3 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 x7 w5 o6 q: t" m; u, L9 e0 h, i8 _' N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 m1 m9 |# a; ]; U! L# eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: T- Z$ j' {# Q% [8 J| MCASP_PIN_ACLKX/ N. q0 i$ G) A: ^
| MCASP_PIN_AHCLKX
1 @2 X. o* h) l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- O) L6 J+ q7 Z, @9 pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # _! Z/ k% Y: i: L; v/ K1 N
| MCASP_TX_CLKFAIL $ J+ |9 f6 ~* P4 R) Y0 _$ V
| MCASP_TX_SYNCERROR1 j, Q) M) d3 v* O9 Y8 {3 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! p A% L/ F: x, O$ Z3 r# c| MCASP_RX_CLKFAIL
" E0 D1 q- I7 k# d. Z# @& d| MCASP_RX_SYNCERROR 6 r& p1 x2 g- s) ]' i
| MCASP_RX_OVERRUN);# A1 {8 P6 [/ c0 \. G% o+ F! g7 Z# @
} static void I2SDataTxRxActivate(void)
: L! y7 a" n8 Y) N. q" v{
; R# I( g: \$ |& Y+ ~, r/* Start the clocks */
2 S0 {' X$ I% \' ]6 m3 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); X$ i7 n" I! e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ a. g* \, k- P- I8 F6 h* ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# q0 D( W# [' w+ w- \EDMA3_TRIG_MODE_EVENT);8 c3 R& t8 }( V5 e2 \; {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 b+ c& _4 P9 i0 O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( _! q. f+ _; H0 G6 d6 WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% m7 E! P X6 B/ u' A2 c: ^. B1 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 W) s4 C% \' D/ p% m# U' wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! Y2 y& ?8 V0 s# o8 r4 ~% fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 M/ O6 z- ]. c% F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! _4 T7 R5 _1 o6 V
} * T" A3 F- g+ T/ A' L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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