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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# z, W' Z( ? S* h0 f* binput mcasp_ahclkx,
$ H; H4 U6 B. z {8 Qinput mcasp_aclkx,
, f: b' K3 \! O" T- p( ]& yinput axr0,9 }2 {2 [* g- b( _$ T* Q m, M g
7 B X* a$ T( l
output mcasp_afsr,2 v F# w+ e" |% k2 h6 `5 [
output mcasp_ahclkr,
1 y6 V& b0 R. h& ~6 a6 Toutput mcasp_aclkr,
: v9 l" L T) C2 h* Joutput axr1,
3 R' e2 Z) ^& [$ [: V) O j. _ assign mcasp_afsr = mcasp_afsx;9 @6 j- W, J, _9 Q. K
assign mcasp_aclkr = mcasp_aclkx;. \/ u* c7 r0 o" k1 U# Z
assign mcasp_ahclkr = mcasp_ahclkx;
$ y! E- m8 Q7 T* |1 q" ~assign axr1 = axr0; , G# d# m$ y0 @+ w: ?' Y! C
2 R3 ~# S1 @) O/ p4 w; ~6 s( G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + C2 h5 n/ w* f
static void McASPI2SConfigure(void)- f) M2 s; J$ _
{
1 n1 b- o+ M- ?* rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( n- | B5 G2 P5 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 x( w4 _5 v, i+ w0 [0 v% wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, }7 U; G5 F5 E* I/ [6 v8 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ x& | V9 {/ N/ T( z! a: C/ }; ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," t0 W2 j. y% M6 [/ v; I
MCASP_RX_MODE_DMA);) o- T, O3 B' s( b5 r8 x# q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- d5 C, v3 \% R$ A, l0 e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ v& V" W+ n6 PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, R3 j+ Z+ W$ L- r4 T7 W0 o. YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# x# J% ]. P2 P% y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 T6 s4 L# ~0 }$ O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 v v# M2 M- S; M b7 u" o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' i: j2 j" L% o; @9 D# VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 ~5 D( [' |1 s& y( n: m' hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 b p+ x7 V* p8 J& F0 U! M/ e0x00, 0xFF); /* configure the clock for transmitter */0 s+ W2 u) ]+ l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& y d) K4 `2 v' e, G/ I# y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( \2 e* n; t* m# L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& [, F7 N0 {0 I) a/ W2 j
0x00, 0xFF);$ m7 Z* v' V- ~8 a- \" e
/ v1 a* J8 f! S7 U/* Enable synchronization of RX and TX sections */
; N6 s! C- p5 } Z4 QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ H6 Y7 W& C q9 E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. Y0 k% J& x* `% t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" h8 E: \+ L% Z% I' }1 X4 L2 I
** Set the serializers, Currently only one serializer is set as! a# T8 s( }( N: j9 m f) S
** transmitter and one serializer as receiver.
7 @9 ^* z( ^! |*/
0 r4 q, e, t% A& sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. f; y/ O& N+ u) Y9 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 l3 j4 X5 Q, g) m, b2 [, K' u' ]1 \
** Configure the McASP pins 8 O2 m* Q4 \5 j5 S2 N5 d* ?
** Input - Frame Sync, Clock and Serializer Rx
' \, L0 L! C/ F' ]/ n** Output - Serializer Tx is connected to the input of the codec
( e/ e! p4 C& y2 t% T' u2 }" ] x, C*/" E9 w8 [$ o8 T0 R8 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 T; v& |- J6 q4 K3 YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 U5 [5 a) X3 W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 l/ j, S6 [: \7 l) K
| MCASP_PIN_ACLKX) c% E0 k7 v9 ?% m
| MCASP_PIN_AHCLKX
9 Y) @) J" j- t8 J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 {3 w N. @% a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 P1 y% Z: C( I1 j) c0 P% p| MCASP_TX_CLKFAIL 8 s3 \* T9 K6 {8 F, f0 p
| MCASP_TX_SYNCERROR3 U" Y6 O/ h" s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; `7 l8 T; c; _* Z| MCASP_RX_CLKFAIL
: L) v; e& t2 Y* ]7 H| MCASP_RX_SYNCERROR 5 k" |: K6 \ o( N4 L* G, Q' K3 M
| MCASP_RX_OVERRUN);
7 G t3 f8 _ r9 ^1 K8 @; L% E; I} static void I2SDataTxRxActivate(void)
7 ]5 b! r3 w5 q9 S" c9 \& w# {{
( Y9 p: A- {+ w8 s' t/* Start the clocks */: ]. g$ s; D( r0 ^/ \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) n5 g0 Z# e5 p/ l/ ]( I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" H3 I6 C# ]: t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 w" [7 j) G3 ?8 W
EDMA3_TRIG_MODE_EVENT);! I9 ?( ^# y ]) |! ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " H8 |6 I l; T: [. o2 I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# f4 l. U3 ?9 R! b) u8 N( ~/ MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 {# ]& f7 Y& B, [, m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 h5 L- k3 E; D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( g( D& r- ] m& K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# Y/ Y- y% `/ X2 E0 B5 O: j$ L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 N& `5 T; a: ~9 }/ U: ]" g} l i: d% Q# f6 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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