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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ h- Q @9 r6 E2 e2 T" s, P
input mcasp_ahclkx,! a) J+ ? N1 c6 H/ a, B. j
input mcasp_aclkx,( q7 I: O$ S8 r5 a( f& K' l
input axr0,
0 @$ |% p$ W% q
5 c2 e) n& \; j3 [output mcasp_afsr,' c7 r- I1 H8 F j) h6 P0 W
output mcasp_ahclkr,& g. F$ m' ] { l. Z. \9 o
output mcasp_aclkr,$ n1 ^- M+ x: x- M: S" l
output axr1,
- m% I9 }7 x3 |+ j! O assign mcasp_afsr = mcasp_afsx;0 x5 @% u& O" Q. G* I+ ^
assign mcasp_aclkr = mcasp_aclkx;
+ O) I" e+ T! p& _assign mcasp_ahclkr = mcasp_ahclkx;
1 b% Y( F3 U/ H' V$ E+ Oassign axr1 = axr0;
* {, ~8 x# S6 T
, }- n/ l' t% O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + ~+ a8 z' a) ^) a; |( y8 y: C3 u
static void McASPI2SConfigure(void)& ^7 P `5 A! n; I" f( L
{
# e5 {# N* n6 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) F9 I" u9 p6 p3 ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 Q. ? o0 P9 ` H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% ~* r, N7 t# RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, _) {4 Q( T. v+ g0 }* e1 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, r8 t* q" M r. W, Z1 z
MCASP_RX_MODE_DMA);9 w" S$ Z3 A) `- M% n8 e0 m/ @/ a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, M3 V# G" {6 b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! u4 M# I. t. H* H+ w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 C8 u4 W/ r: F( I6 {# wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 [3 Z& B7 C: j" y1 Z8 |) \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " q9 @2 \! W* x$ X' q4 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) k5 G6 L% E! f) ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 c# j9 G* ?8 @( M1 O0 d: K7 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 S Q7 K( g1 R1 W$ z: T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 Q$ `7 ~$ k" X! f7 T& D1 r( _0x00, 0xFF); /* configure the clock for transmitter */
$ v' i9 m0 g3 P% ] |3 eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' U' A& M. f1 } p6 M/ ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# C! P% X) U4 m/ rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& M0 |4 u) t# p' U; S) h, U
0x00, 0xFF);
7 u- m: X# C& @! {6 C! c4 n
. d$ D" G% \" s" ^; J/* Enable synchronization of RX and TX sections */
0 d+ C* p% j, c& ]1 W ]' y# `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 V) [" e5 A1 n% V, w7 f$ o6 C0 rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, p0 c$ t& m% c& b2 g6 u) g! NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** Q0 Q& q- Q" y, K( K# U4 Q( ~: H* u) p7 j
** Set the serializers, Currently only one serializer is set as8 h' N% K7 M- v+ X' `* ?
** transmitter and one serializer as receiver.
" o0 v7 @1 I9 {" x) Q1 u9 [9 t*/2 R5 \7 b# m& c+ f; V! ]7 r6 X6 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* P U. Q$ Q$ tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ ?* \) S2 G# V: _/ i
** Configure the McASP pins
6 e" i, J2 A0 y8 \+ n** Input - Frame Sync, Clock and Serializer Rx2 V% H- O( p* h
** Output - Serializer Tx is connected to the input of the codec
Q8 o% n: M. M* A2 V/ C*/
1 ]! F6 W) J, V0 r0 z9 D6 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 G( g0 y" R, g+ b/ g% ?: e& xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 k- } ~% \" ~4 }( F9 |% Y! j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
?' o( U' Q* y% I: e| MCASP_PIN_ACLKX
6 f' j. S( D4 G2 [/ R| MCASP_PIN_AHCLKX; B& F3 [3 p* H5 V/ ~2 C( b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' M. d3 i' T4 O3 `8 {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 A% d; k- S, [+ y U ?| MCASP_TX_CLKFAIL
7 e% _! K4 ~/ h: G| MCASP_TX_SYNCERROR
, h9 r4 o& F9 \" N/ q n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % ^2 E) V2 _" K! {
| MCASP_RX_CLKFAIL
" d' ]1 B0 l; t1 |* D% c| MCASP_RX_SYNCERROR
$ D! z) ]% G- p. y0 t| MCASP_RX_OVERRUN);# L/ f4 g; b! A' ]
} static void I2SDataTxRxActivate(void)
) F* g* ^0 D: q b{8 ?% I9 g: ^- ?. Y+ b" j, D
/* Start the clocks */
2 Q: [' r; Q4 M: Y$ cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( X- r7 f5 y& _4 H: w$ FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" f# z: W; x2 K0 Y: F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 ?. F# l3 k" u C
EDMA3_TRIG_MODE_EVENT);
% ^& ^+ r1 _0 i8 p* zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 t" \: M% T8 _) b; nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! s% v9 K* `3 D/ ]/ l/ mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- Y8 T+ K5 O) I% f) u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* W# \8 {- w$ Y. c& \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 C: ^' P3 s! ]* o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! H- y+ c0 Y7 c/ V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 p$ d1 J; z9 H1 w/ t$ c, W. e
} ; [' p* m# e+ G9 Y1 Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 \+ Q2 f9 J% ^6 ^: D! R3 P
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