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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 K. N' V# f. ~6 ?2 }input mcasp_ahclkx,; S" ^2 ~) F( @* d, t
input mcasp_aclkx,
, ~% L+ i! g; D6 Y& ^5 o5 tinput axr0,
" b1 U" U7 C% G" e' c' l, |$ x( l- X$ Z; t* K+ Y7 }4 I2 L
output mcasp_afsr,- B5 i: K4 ?) I0 w& |$ C
output mcasp_ahclkr,0 r; x* i1 r' _7 C# e: u
output mcasp_aclkr,
! m ]) Q( y$ _* }output axr1,
3 L- i Y V6 Q assign mcasp_afsr = mcasp_afsx;
" X6 m: o6 Z2 U/ L) j5 Yassign mcasp_aclkr = mcasp_aclkx;
3 T% D ~! _4 s2 q+ E2 Q+ Fassign mcasp_ahclkr = mcasp_ahclkx;2 ?7 F1 Q0 W7 d2 C" k
assign axr1 = axr0;
% \) y0 {% n$ [) q+ {; T0 V, V
8 w! \4 J9 n9 W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + `# d( Y) {3 W. h6 [; h5 [
static void McASPI2SConfigure(void)
+ n' x& M H. j) I x! A{/ F3 T* r$ V6 k% K' r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 } [8 e" f6 S# O; F; LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; k! N4 G; W! s' l' L( D% ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. r" ?$ H% V0 g* @2 QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 s( l6 I3 f( a6 j/ zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' b7 u8 P6 j% I2 J9 l8 y( Z" m
MCASP_RX_MODE_DMA);
w4 v4 n2 l9 o8 }$ s' h) MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: O8 W6 p4 S, V' j9 j6 M6 y8 J* iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 u1 Z+ g. N) T. `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . p/ m) q0 t$ Q, q# i$ {* y; R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ V3 v* A7 T# n1 R1 B0 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" _% z z9 P' {* dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' K9 ]. V; M9 W+ g- `$ x' CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! r, `! x) |, zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ Y; L9 q7 j/ d: C: @: W' vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 y; M* N! Y# r, f8 M% B
0x00, 0xFF); /* configure the clock for transmitter */. \8 _3 H( f& b+ u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( _9 m, x8 p e; Y! k7 p( ~( o0 {; _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / z+ [; t: U) M2 ?6 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ L( T8 G0 s) ~
0x00, 0xFF);4 Q+ Y! I- c# Z) }) l, D @
9 g; r0 r* f6 T' z% s
/* Enable synchronization of RX and TX sections */ 4 k3 ~+ W$ w( N' T9 M8 c, z7 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; i" ^( N/ ^1 [$ K l4 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* `7 }0 N3 F- x/ i8 |& b, a% k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 ~' J- V% I' S
** Set the serializers, Currently only one serializer is set as- B" U0 Q6 S1 m7 s# A
** transmitter and one serializer as receiver.
2 ]0 S" K+ Z0 P*/4 u4 x2 x" [* B& L, j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 R# K3 s/ M0 K" I' T0 y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ O+ a8 }2 Q& `1 U
** Configure the McASP pins
3 n# _9 W; p% X7 t1 i }) f" w** Input - Frame Sync, Clock and Serializer Rx
& T3 q/ F* y. k' l" W4 c** Output - Serializer Tx is connected to the input of the codec
. V2 h+ O7 r9 a# T, E& L*/
( x: x. Q d+ [0 z- vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. O \/ C' f. U+ N, I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 S5 i( w) R0 b- t" [! ~) MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# h, ~! F ?; P5 Y) \
| MCASP_PIN_ACLKX
' Z) Z ?+ t5 u a5 U| MCASP_PIN_AHCLKX K, ?2 J8 x s+ h; Y G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ |7 W3 _- ?1 c! }2 BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR p7 f- {* x( a. p
| MCASP_TX_CLKFAIL
I3 n/ i0 c) n| MCASP_TX_SYNCERROR3 ~' K U' e) H) n+ r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % k( F# m; D/ J# I. b' Z3 s
| MCASP_RX_CLKFAIL
% ~/ [* _7 q* M! l2 \| MCASP_RX_SYNCERROR
, H, X. j: G2 h0 y0 q8 E| MCASP_RX_OVERRUN);9 f e0 [; ^) a3 }) ~( Q% i
} static void I2SDataTxRxActivate(void)/ j0 c9 p9 k/ V: U' B9 O
{
: ^) E4 b) ~9 K3 U2 v8 K+ \$ n( n/* Start the clocks */
, n; g* V6 U7 b2 ?4 R# l* q6 z8 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* G9 [1 e% c. RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; I1 m, E* F" k- _7 z/ a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ d+ A( n ]9 u9 i' Y s- j& g
EDMA3_TRIG_MODE_EVENT);7 h1 Z, f8 g3 n2 B1 }' w( ?. n/ L5 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % I6 H7 o1 u- v9 n0 `& h/ A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- M# ]. i3 V2 a& c$ s+ ]3 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 B# p* Q) q. \6 v- \$ W7 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 E. o! C8 v/ E7 ~3 \+ d# V$ `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 X3 g r9 v4 \+ G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( ?) i# ]" A& c# X1 }; |- e; j0 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 g. t8 g; G& l} ; x( s4 b9 S7 Q$ x2 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # ^" N/ O% d* d
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