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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 A% R. q; g+ F: uinput mcasp_ahclkx,
' y2 K4 t# ?0 w# A' _5 @8 }/ Hinput mcasp_aclkx,
% A6 o) n' S' X5 R. k% Einput axr0,% [$ _% f1 ^( L' O! U5 T1 D* c
: f* p4 U4 m/ U6 D. V3 u5 p, [( doutput mcasp_afsr,
/ g9 F! L2 C" e+ H0 Foutput mcasp_ahclkr,8 q8 q, @6 Q+ d! b
output mcasp_aclkr,
, w' N0 Y0 G; ]output axr1,
- @, ~8 i4 @+ ] assign mcasp_afsr = mcasp_afsx;
- h3 \3 J0 f- @# Z- @+ B. iassign mcasp_aclkr = mcasp_aclkx;3 A8 `. d( q, A) H3 G' R
assign mcasp_ahclkr = mcasp_ahclkx;
- \3 ]8 W/ M. [4 ~/ H: S9 `; F* jassign axr1 = axr0; * Q0 l7 c) \' s+ {4 B
# K2 C3 o# ?4 w, D/ G D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
n6 s0 M' m% {: g1 d+ Pstatic void McASPI2SConfigure(void)0 T8 b$ K# |( Y- t1 y
{
) ^0 s( X/ w t9 ]& q) BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 ~9 a8 F q9 g B( O2 h9 VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ U: n* i/ a! A6 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& [% _4 ~9 c. S7 p% HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 C) e; b5 _1 {8 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 `1 s! {$ [$ G- I" cMCASP_RX_MODE_DMA);; }8 ?0 y( i# a1 x: X3 S, M* [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 y. @6 m8 _8 p+ [/ {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% ^% w" P, j- XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. D- e/ K+ Y5 w8 |) AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 w' U. Z( p ?1 H- kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, N# T; m2 ]" a0 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. a7 s3 R: H' V8 {% o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 i- V, d4 L% ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 i- R3 {+ ^1 |2 r7 ]8 F+ KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. Y7 M) I+ K7 c% e0x00, 0xFF); /* configure the clock for transmitter */9 G8 {$ v9 O" @5 B) s; {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" P0 T3 W: I- a9 v: n+ q0 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ T7 V# ^7 e, ]+ C$ I9 B! |8 v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 R/ b# K+ V7 J3 T
0x00, 0xFF);
' }0 b$ Y- T9 F1 @: p' q: N( B: h8 E
; K# ~8 M5 w6 X Y2 V; P# \/* Enable synchronization of RX and TX sections */
0 ]; X' B9 @& i) B* c1 sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ h t* X( C# R* Q2 a5 c) CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ i7 |) Q N$ V. x) n' aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ ^& U2 C6 T( {
** Set the serializers, Currently only one serializer is set as
$ b0 k0 c. l! a& `** transmitter and one serializer as receiver.
& U% h) N% a4 ~4 ?' {* H% U*/
- f, m1 o8 g; k' J, s8 G3 lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' Z8 h% \9 e1 ` t5 U# N9 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! u/ V- b: g! V ~7 e& N1 Z
** Configure the McASP pins 4 K. c. a+ g: ?4 d
** Input - Frame Sync, Clock and Serializer Rx+ c& Q5 n) j- a9 {: n" d/ Z9 M& p
** Output - Serializer Tx is connected to the input of the codec 0 K7 C3 q5 m' W. g: {: f
*/1 |9 F+ o3 k- ~! A" a. I6 \' U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: e; A2 U) N5 w6 k2 G& y0 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& }% C# T& y s: d; t/ T6 q3 [, rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, B" f$ s. n. B. m5 s3 \| MCASP_PIN_ACLKX, F: g, u3 J5 ]" D' [' @4 S: f9 a+ Y) j
| MCASP_PIN_AHCLKX# O. j; j5 e' X8 G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 H# F# {' R/ F- c0 M# m$ Q4 v$ h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 U8 y# j/ }, ^4 c+ J| MCASP_TX_CLKFAIL 6 `: O$ ^% h7 t6 ]) H+ n
| MCASP_TX_SYNCERROR
6 _9 U( ^3 h+ V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ u3 y3 H; k; N1 l| MCASP_RX_CLKFAIL
* f F& W# v. A; D| MCASP_RX_SYNCERROR 3 u9 T; [( a: L; B) b
| MCASP_RX_OVERRUN);0 k1 @2 [2 O: I9 }; ?7 z0 E
} static void I2SDataTxRxActivate(void)
: i" I# ?+ d: h+ e! k& g/ x{8 j2 [' Q3 q; l) N. ~
/* Start the clocks */0 L Y Y! ~5 o1 z$ |: |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 c$ ~! q) m. D; c9 e1 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 M/ s/ }1 h# V0 S9 L7 q; IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 w9 b. A8 e+ _
EDMA3_TRIG_MODE_EVENT);; U+ D5 S" I3 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 K7 c* c5 I% t7 s, a7 K; L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* ]* g# o0 E2 N- t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! W( V0 S1 p* ]/ Y/ `& E# u1 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 t" Z& A" I* Y" Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 G9 k/ s9 N5 X4 |$ JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 m9 z) R7 h9 A0 m* p, s+ V" f8 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- ^, `! a' v4 a- c4 Y1 P
}
8 P2 \1 ^' n6 ^& T p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - S$ k7 l; x& F3 {5 N3 D1 Q3 N
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