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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) R2 |6 }( q: |3 |1 v
input mcasp_ahclkx,0 k5 L j/ J$ s3 k: v5 N
input mcasp_aclkx,
8 f7 x# C& [* f+ hinput axr0,7 q# P& g5 v" F$ Z# d
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output mcasp_afsr," ]# j% ^: V1 |- J( F; h
output mcasp_ahclkr,
+ c# q8 q# A1 doutput mcasp_aclkr,
+ B4 ~4 D: t1 }( J: \output axr1,% y+ U: c* E! g: J. H
assign mcasp_afsr = mcasp_afsx;
* y0 E# B& T) Lassign mcasp_aclkr = mcasp_aclkx;! Z- S: N3 Z1 h" g, R
assign mcasp_ahclkr = mcasp_ahclkx;
2 z9 ]7 {) s; r* v8 sassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 p2 F- G: p8 y e/ n
static void McASPI2SConfigure(void)- B; Z k4 Y D2 M% I# i8 A
{
6 Q T! Y* \. Z1 k3 D! F6 UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! ?0 }( r0 B, ?9 X: U+ o4 |( uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 v' S" H5 k5 u2 x! K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 g, L ^/ P# w; W9 x _8 H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; s) e2 W2 o k7 ?% R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% M) @: _$ O; J2 p
MCASP_RX_MODE_DMA);! } F. @7 X7 _# p. W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 Q" G$ Y. c0 a- RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* U% v& D+ a! E E y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" x, L7 s1 _. E0 o5 Y# i# LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% ~ _+ x5 C! I! ?0 k0 _7 m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 S( H0 n) h6 E6 J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
Q0 X, M! Z5 U+ B' K MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
c( b; q5 {) L9 q! e! CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) f$ v& t0 m z3 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% r; k c3 M4 G( s" V
0x00, 0xFF); /* configure the clock for transmitter */
! c% C5 C+ P j# b1 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 W8 Z; q. y* ^% `$ @1 h! U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 N- |) ?) |+ V0 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 s4 H1 f& @& Y& f
0x00, 0xFF);* X& {! I g$ M2 A/ T
9 T7 A7 N, [, o7 d h% p0 B: m/* Enable synchronization of RX and TX sections */ ' {( A% ^9 S% c/ S1 r' e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 i8 H9 i( _) ] XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- @+ J( w* E4 _; j# _6 u! K) yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ a+ q! c: k: ^3 I, N G% @& K% l** Set the serializers, Currently only one serializer is set as7 Z; c4 Z) H: i; }& g; _
** transmitter and one serializer as receiver.
6 C8 G4 k/ Z; g ^ N+ z" m1 Y. J*/
! `' i+ ~. z- h4 h( y$ ~7 { rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ _ g. I, B" ]8 k) J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 w2 T# n$ a6 t6 E, i2 s% p" U** Configure the McASP pins , g2 G: ]4 E( u5 V( F% }+ p! |
** Input - Frame Sync, Clock and Serializer Rx/ h6 x1 {5 ]! C; W1 Z. A: b
** Output - Serializer Tx is connected to the input of the codec . ?2 @3 Y; a0 ], W4 b: {7 ?& w+ P
*/5 y. Q" d; Y6 w( l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; \3 }2 t g gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 g$ s$ R, Z& X6 N. N- O* T# q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& g: j% |+ H) a| MCASP_PIN_ACLKX
+ P+ w- G( k- y3 i2 ?8 \0 V| MCASP_PIN_AHCLKX0 j3 k5 Q4 r5 R6 R6 E7 a/ @; \' y8 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 o8 ^: b! U& e' y% a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - I+ q* x4 e+ B$ a" E4 Q
| MCASP_TX_CLKFAIL
+ `5 t" r6 k6 ~( _5 u( H0 d| MCASP_TX_SYNCERROR
: P/ L0 }& v2 v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ b1 g& Z3 e6 W
| MCASP_RX_CLKFAIL) o+ z$ `4 Z% Z# `2 ^0 R1 c' C
| MCASP_RX_SYNCERROR 4 }9 Q" o3 s1 \ m
| MCASP_RX_OVERRUN);' {+ D+ \; U0 z, i4 m' F4 W9 o
} static void I2SDataTxRxActivate(void)
& ]3 ^. p8 R3 X3 i{
4 E6 x5 K: Q6 M/* Start the clocks */& |% @2 g: l* Q4 B3 C" E3 I1 f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! g" S5 Y9 I$ o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) K5 X8 n/ {' JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& ^9 v& W4 N6 w" r9 q, z
EDMA3_TRIG_MODE_EVENT);
( f( Q) a4 l4 P7 V( eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & G5 [, J5 u+ B! F+ }$ i6 H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ {/ y3 u/ _: k9 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( X% T, w) c5 r- I" n; Y$ B# u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 `: p8 w. z' {. [1 S$ |, e4 Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ w; C7 N D0 M" {7 [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' n5 d8 f" q3 X7 K& v4 ?! q5 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 [0 Z5 z. c1 t, H3 ]
}
' v0 j. {# Q# J1 O" V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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