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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% [9 F% F% e- k4 b0 n
input mcasp_ahclkx,
1 D3 g5 I' Y- }1 U9 x4 ^input mcasp_aclkx,
7 Y; ~( j0 A# N* Qinput axr0,- j0 n0 U \" ~/ w2 b! _
+ ] K% H; Z& o
output mcasp_afsr,# Y9 Q" r: z/ g* C! Q) b
output mcasp_ahclkr,
+ s& x) D# C3 X& Voutput mcasp_aclkr,: J5 j& Q5 `5 e% D8 p6 J
output axr1,6 w& v z: t8 S- ~7 {
assign mcasp_afsr = mcasp_afsx;
. j: n) E+ w0 ]% ?% zassign mcasp_aclkr = mcasp_aclkx;
0 p% G* e' y$ c3 k) z9 Q& Dassign mcasp_ahclkr = mcasp_ahclkx;3 ~, Y) @; ?/ D- m8 x6 G
assign axr1 = axr0;
+ \2 @0 y9 L+ `/ l! Q5 V
2 D( }( O p- b7 V/ P) K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% Y" t( |( ]& z3 k- P3 P m& @static void McASPI2SConfigure(void)
0 Y! `" L7 P, O9 D& r* U @% j{$ Z- B9 c$ [% u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 ^- G9 P3 S. X: NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! v! q! S* ~' E# ^. k5 i6 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 t* ] v3 O7 A8 c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 m1 i; W; z1 I0 G U9 K7 k. d; tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! O% E' e9 O, G0 Z u. W+ ZMCASP_RX_MODE_DMA);0 ~6 v: T$ q9 c' D8 _& P# K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 T7 k. M+ w2 [! ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 k; H W `# _9 I+ p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' O8 a- U. e1 X9 T$ U+ gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 E' Y: T! C# [6 ^, ~! h: I: QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ H# j T: U) e' Q3 {+ M/ IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 i( p: p" X- `3 R# h. nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 F/ R* _3 g+ A; Z7 Q* ?1 ~$ r/ pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, D* w% V# \+ @2 L7 p9 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' G$ O" ^) _( u% E8 k0x00, 0xFF); /* configure the clock for transmitter */
n+ I& l5 y7 k8 G d$ yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* o3 ~/ S5 D( ]7 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ ]. ]; d2 W `5 i1 d; [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* J' A! [& v7 J7 I6 C6 I6 M+ f
0x00, 0xFF);% ]6 i4 Q4 w! u! v7 p% Z
6 G, G n3 h! h" M* t
/* Enable synchronization of RX and TX sections */
: w! J d6 Y5 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ s0 Z$ q7 U% q; z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; M; }# ?0 X+ k2 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ R. e; w, ]4 [9 s: A
** Set the serializers, Currently only one serializer is set as$ X3 }' T$ n1 S( M* X
** transmitter and one serializer as receiver.5 l* ]/ f$ k8 Q3 U' V
*/# k7 F7 v R9 ?# z4 S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- i# L+ x1 A* ^6 i+ |% xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 M2 Y7 X- i5 C Y** Configure the McASP pins 0 e" |1 G# i( i7 Z/ W" U
** Input - Frame Sync, Clock and Serializer Rx
7 X! k7 J* y" ]** Output - Serializer Tx is connected to the input of the codec
% ]5 \, \/ h, V# q, H! I*/& N& p7 D$ }& F- }2 t3 ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 z( A, f, X. |9 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* p0 s7 e9 H6 l( m8 H: Q G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# {' v& E5 w: m
| MCASP_PIN_ACLKX
& Z% _5 W6 b$ C| MCASP_PIN_AHCLKX* l! |2 h7 L4 ?* T2 T5 B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 i8 i% f) z" ]4 p+ y1 z' w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 Q3 T8 w+ z; y* c7 C) }2 a| MCASP_TX_CLKFAIL * e. c6 T8 I" E, }/ U9 V( D
| MCASP_TX_SYNCERROR
2 B; s, R# j3 \" ]' H) ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 P$ c k( A) n: V| MCASP_RX_CLKFAIL3 U8 |3 V$ k- n$ L& ?( X
| MCASP_RX_SYNCERROR 5 X% e" I4 @+ n. D6 O
| MCASP_RX_OVERRUN);
! Z& N7 G* V2 D} static void I2SDataTxRxActivate(void)6 i. Y! v+ l8 U6 E% }
{! m2 T$ b: X# ?! |# s( s
/* Start the clocks */7 Q: ]! d9 T/ k8 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 z0 a/ ~ U9 g9 P3 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 X( s* U+ [& a6 B4 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) k2 h1 z; l- F- T! k
EDMA3_TRIG_MODE_EVENT);
; Y5 L- I- v1 U- v) j' b6 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: p/ o9 q& o5 D8 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 Y* j- N5 j" O: j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 w8 G. ?5 K3 f i2 A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' P" a% M9 ^$ H9 W% Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 z$ z6 U7 m' L/ n$ i' cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# t3 j! D2 s0 T5 p \/ \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) Q. D+ ~1 v% k6 H& ~! V5 o}
/ D: h2 b' l5 ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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