|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, U' u7 b1 K8 S* t, o
input mcasp_ahclkx,- L) n. k) `( u
input mcasp_aclkx,, ~; I% t" j; D, o9 B' b) ^
input axr0,) p" W( R0 |; V! R& T$ O" v3 f
# }" W# c$ K/ D, v7 m, y' L8 Eoutput mcasp_afsr,
/ L$ j* L; N$ T5 q. joutput mcasp_ahclkr,
0 h. y; i7 h- P2 T7 e" h1 [output mcasp_aclkr,
; \$ ^9 d0 t( ^( doutput axr1,
/ X0 e: G2 h( E0 }+ r6 q9 C assign mcasp_afsr = mcasp_afsx;. ^& D' p, J+ h* C
assign mcasp_aclkr = mcasp_aclkx;' c' v4 s1 z2 B8 |0 q. {! `% w: u
assign mcasp_ahclkr = mcasp_ahclkx;% v0 [2 s& g) D7 ?* j9 s( s' Y
assign axr1 = axr0;
% G/ T& d& \5 T1 M7 ]5 @; [
T' I7 U, `1 s6 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 A' f4 B6 X0 _2 |" n
static void McASPI2SConfigure(void)4 X2 [- X& X# [* M# P! H
{
. d/ T4 s3 |1 v- D. ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 s% G5 F$ E) t3 m& {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ G2 \% a* _- j. s: {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, y) _3 U7 Q# a/ C- ]! pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 _, Q" r6 M" hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: t% H5 ~+ n) F* k2 j1 P
MCASP_RX_MODE_DMA);
# J6 L+ W- E3 A0 L+ eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 X* i! G0 ~) ~# w. P! j; p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, T6 J3 @! ], G' A; }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; Y# N! K- e" I' [" wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 ~4 v' N: k; [6 }' r6 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 E, Q1 S( p8 K. D' x/ B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- ~' B2 D) M/ r, ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; @/ m% y, J: ~: q/ S- FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( T; Y9 }: n5 b0 v) V1 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ h9 V2 s5 _ y* b0x00, 0xFF); /* configure the clock for transmitter */
! s e. j% ?5 f# Q4 ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' O6 c% A/ B6 x- s1 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % {5 p1 l# `+ |/ s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' t. {( A6 J+ q+ O
0x00, 0xFF);
# n( p t+ t$ q, P8 F* l6 w" G5 ~% }3 q/ f" _* \( {* O
/* Enable synchronization of RX and TX sections */
; T3 x$ d# P- s" D# ^/ H5 m+ O4 ]. dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 y3 [1 ?4 d& O) k9 E! jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 f$ b+ [& u+ V1 Y- \% i$ [" y& q% s3 _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 W; @9 `$ B' d% ~& l5 Z** Set the serializers, Currently only one serializer is set as7 q- ?7 L6 ^) a
** transmitter and one serializer as receiver.
, J+ X8 P5 x5 r8 j, p( e*/
8 d5 |: d* {2 K1 f' ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; P; w" R5 T: O+ ?# I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( U; j# w3 B7 S1 p' r
** Configure the McASP pins
5 o0 j4 j8 {8 g3 E7 P! r5 c** Input - Frame Sync, Clock and Serializer Rx0 M2 R# f2 ~+ O' o r% G
** Output - Serializer Tx is connected to the input of the codec
: l/ e# r" [, y6 L: _*/
Z# K# P, T6 }/ ^' }, }) [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* n2 U2 L* p- S! g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: L2 U7 Y! q2 R* J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 y6 n& e! `; J| MCASP_PIN_ACLKX0 F; x7 }3 ~1 f. N
| MCASP_PIN_AHCLKX
( Z3 g9 a7 z6 }9 w% [8 r; Y P5 `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 p6 ?5 ^3 o. p' y7 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 E; e5 V2 ?' D3 u5 e| MCASP_TX_CLKFAIL
" T% \' G ~8 p* u- e+ I| MCASP_TX_SYNCERROR, | `7 h L. D; h( @% i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: w4 P! _; S, n" P| MCASP_RX_CLKFAIL
; p! d/ z" z( [! L| MCASP_RX_SYNCERROR
, [6 u# y# \6 i| MCASP_RX_OVERRUN);/ N% ^" _& g1 G0 n
} static void I2SDataTxRxActivate(void)
) \% s* }# Y" S, w) Y" X{
# n3 f( N& e5 F/* Start the clocks */
2 x+ n" e: b2 N) ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 T4 t, C# {! @6 Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 M8 L5 [( R1 ?, E I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% l5 J# i: M0 s# J) o' TEDMA3_TRIG_MODE_EVENT);
0 [& z4 k- Y. zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 K X6 g, m$ EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* @# R" o0 ^% h* D+ {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; |1 N L% S: K' U/ I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 |) z# i1 r z; N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ B0 d+ Y! F1 t+ T3 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 |+ @% X d' q5 w/ eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 a/ g. u. U v/ q
} - d1 y! H. p. K: k2 ~2 `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 g# K/ q4 c# d% s9 h) h2 S/ d
|