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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 A7 F; A3 ?1 I6 y5 D5 {input mcasp_ahclkx,
( Y% K+ A; f! H: minput mcasp_aclkx,$ K& [7 ?" m% g0 i4 ]3 j1 j
input axr0,
& t' R) W1 j% m* @" ]; B3 U0 A
1 W# L! e8 a9 k- n5 j8 aoutput mcasp_afsr,
+ ?/ e- g9 M/ F% X5 F) A5 coutput mcasp_ahclkr,
8 W* h% l7 }9 S# _ J' b% @output mcasp_aclkr,& s. ~+ u( k z: d1 c
output axr1,
& [( E" |3 t2 o2 [# U assign mcasp_afsr = mcasp_afsx;
6 O, a! E5 {( R% K- q8 W" cassign mcasp_aclkr = mcasp_aclkx;
1 m; i5 w" O9 x7 s y, Q$ Lassign mcasp_ahclkr = mcasp_ahclkx;- H0 J' f5 F+ m/ o, y9 d' j3 s) d
assign axr1 = axr0;
n& H: R1 X( O5 I6 I/ D1 M T! ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * u5 W- G9 f& ]4 f8 X% J j9 t
static void McASPI2SConfigure(void)
) b5 ^ C8 j+ l5 e" @{
& p9 b' r; Q* b- D P, _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; }! f. \$ ^: i G: GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* l `( o3 [0 V( ~+ H/ }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. Z1 @) ]4 f* N0 H7 b( `" _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 B$ C" H' |' ~# QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 F" l2 w3 [5 i F: @ SMCASP_RX_MODE_DMA);# S$ b. H/ d* Y2 Y- K+ o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 y3 {* C* Z& W. T8 u# BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 W; G; z: |# U9 B) T$ rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 u# y0 }8 ?2 ?& NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* e$ I/ H U6 B$ i) s; nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 b2 Q# v- Z2 b" d& c$ bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 O3 H% @, B" \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* O2 D( N- W3 }! n+ E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( i, i; d3 Q( N0 ~$ k' V) H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. p" R" K4 O. _2 m
0x00, 0xFF); /* configure the clock for transmitter */' E- R# P" H7 T8 Y! V! E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- U) y6 D( q5 QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, w0 B& G! L' iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! j9 ~' @# o; R3 x {, k: q0 Q0x00, 0xFF);
2 j; ^: t3 j/ X' [. |% J! M I2 z+ L3 J
/* Enable synchronization of RX and TX sections */ - i# Q9 Z- b1 }; W. A2 {/ u) Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( `' x* n' y! I9 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' K& s( {; a8 V! b; a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 D4 B7 G- R, R* M. W& R4 M0 |** Set the serializers, Currently only one serializer is set as
3 p6 }4 i5 q$ h** transmitter and one serializer as receiver.
! M+ ^' F3 e% u% P$ w* D2 y*/" Y3 J& t# u* ~: [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 q4 w$ }, E( G: R1 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) r" l7 J. o1 T0 d
** Configure the McASP pins ) G. N" J2 p" ~) W5 Z9 z+ t
** Input - Frame Sync, Clock and Serializer Rx& b+ U8 o' h% C/ I1 m
** Output - Serializer Tx is connected to the input of the codec
y8 @) n# f' j9 V*/* I8 a" E/ ~ q* F( R( t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& |0 I+ Y% J) n' ~; hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
]7 l6 _4 D0 j1 ^5 \$ r8 f7 ^9 w# EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 B. g5 X. l$ A
| MCASP_PIN_ACLKX
- R3 G( b$ L/ O; o# u4 O1 _| MCASP_PIN_AHCLKX
' E; E6 M! h: f5 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ p6 B, _% f8 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 F8 D6 f' F5 m; p; Z| MCASP_TX_CLKFAIL
8 ?3 F; p6 g: Q( y; _| MCASP_TX_SYNCERROR
0 T' j: a4 j1 ]) j: {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 p3 C! |0 w% g( U& [5 \
| MCASP_RX_CLKFAIL; f" M0 d: ~& |5 w% w1 E; }' }
| MCASP_RX_SYNCERROR
9 D, L/ {$ E4 A! q/ c7 x| MCASP_RX_OVERRUN);
, S) Q: o7 ?3 \- ]} static void I2SDataTxRxActivate(void)
. U. i& t9 b. Y; _& O{
2 i% |1 ]6 f/ P5 v3 D/ G/* Start the clocks */
3 H% X( W! E- x; Q/ fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! J% z9 I/ t( G& H& }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, p' u" l9 S; `* SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! y3 k/ A- {; C. ?/ s
EDMA3_TRIG_MODE_EVENT);/ t. g' o- n3 _- D- e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 V9 y) w% B* w& ^% S' N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% P7 \' h% o1 R$ z+ _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# D! N6 _& P4 q/ ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: G9 j, T6 [5 u# b2 }" M; ^( O2 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 B) p2 V7 `5 Y3 N2 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% K9 e) B* j, O0 @- I% @6 |4 v: xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. V" i3 Q* c3 k: o# @& f& [}
; a7 U4 [& w: O# `7 g! O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : ^4 ~6 T; P) J; @4 g3 j
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