MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
9 P; f+ f5 v7 y* C
output mcasp_afsr,
0 ~+ Z- I; P) m8 h! @3 K4 f3 x6 @output mcasp_ahclkr,
output mcasp_aclkr,
$ s' F% \$ c2 c, V- v4 }output axr1,

assign mcasp_afsr = mcasp_afsx;
& Y' u; @! _$ o" f! _assign mcasp_aclkr = mcasp_aclkx;
- {; c4 v* V3 }& U0 Rassign mcasp_ahclkr = mcasp_ahclkx;
0 C5 _+ y: ^2 ^) M; o, P8 V6 jassign axr1 = axr0;

& h+ H8 C/ f' B; x8 d: @( h5 k

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

' _/ v% q1 r7 p/ @* T# Z

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
  v- O* F; X1 N3 gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 t9 R! [  X4 W( q, {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 u  W" A% G: ^% w5 r1 k3 w: eMCASP_RX_MODE_DMA);
6 `3 K, R" U5 d; d% f7 u. J! fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 a- c/ F/ F& e" k* i8 BMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ ^8 t+ T% l1 m+ Z- v3 X8 jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 ~8 |' ]# B7 b6 ~$ n8 @' x$ MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
2 s4 G1 P; F1 E" q3 B- {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, w" }$ s" P) R8 {0 z% x- @% R; {0x00, 0xFF);
/ X$ z2 g2 {( [9 {0 e
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 R/ i$ ^! l' tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
9 a$ a$ _* `; R0 Z+ w*/
7 L; \. R+ a  `0 oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 N, U0 K+ j* j$ `9 }- lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
* T! [4 F( W3 X# }** Configure the McASP pins
9 R. G; q# @0 X5 A/ D% y/ \** Input - Frame Sync, Clock and Serializer Rx
  P; o5 a0 [/ ]** Output - Serializer Tx is connected to the input of the codec
6 `* P) }6 k- e*/
1 H* ?+ _& _8 P0 x6 {- QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 @' c8 z3 y7 g5 V  ~& H- cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
6 H- N+ f4 @, u/ H4 {8 I8 i6 j| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
# f% k1 L; m. q7 _. z# c# T2 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 Y( `+ P& ]" p: W| MCASP_TX_CLKFAIL
/ m, `) ]2 ^1 f- e5 p/ W| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ P) h# r7 ]2 \  v| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
5 R6 f! U% M$ C1 o( ]9 H0 z$ E# D- G$ A| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
8 U; e# U% S2 q- g# w7 |: TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& v' B2 N/ ?+ i4 \3 }( \$ l6 mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
& A! e2 R0 \% Q' I; x2 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 \  _4 H1 m7 ]! v- REDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) M8 D' D0 H' b- `( S- C$ cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% {+ r1 m3 Y9 W$ U+ O" \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ ^0 Q- t* ~1 w# e}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.