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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 q, z. d) m3 n- c( Dinput mcasp_ahclkx,
) G. V# U9 [4 finput mcasp_aclkx," O$ J1 _. P5 N: \ g1 _* ]9 a
input axr0,
/ Z: x- j! F9 E3 I5 E4 Q0 [$ c$ r8 x. S1 u" E; B) ]
output mcasp_afsr,
- Y }) k R e1 g7 ^# `output mcasp_ahclkr,% g9 T7 c' c2 z) O% F
output mcasp_aclkr,$ C( ]1 B1 b6 q A' j" w5 G
output axr1,! B7 b1 Z: L) p% }5 J
assign mcasp_afsr = mcasp_afsx;2 E* f9 N9 M9 ]6 v2 Y) F
assign mcasp_aclkr = mcasp_aclkx;7 H* O/ ]! k" R% a
assign mcasp_ahclkr = mcasp_ahclkx;
1 d% {( O& s8 ?" Z. e' h& eassign axr1 = axr0;
; u, V9 p) I4 v# m+ l& J! `3 V# \6 H: o7 f1 t0 y- o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : ]+ G5 i4 i; r1 l" f
static void McASPI2SConfigure(void)
4 j7 ^7 W% f& `4 r a" w{
8 k1 I5 w( u- n' T2 P( SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! Z: @/ S p- f+ G( M' b& i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 M# A2 f1 b6 y. e! H1 y- a9 y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" M9 Z, \8 l$ ~. A- _! a, EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* [& j- T l" r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 r6 |9 j8 k7 P5 Y: v* S% {
MCASP_RX_MODE_DMA);
+ T, `+ J( b" J% a! Q% Y" WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 F! r% i5 ?4 F6 y6 L5 zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, T+ b. C0 X( N- M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ F! i7 ]" |' KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: \! C2 ~) r6 Z$ o8 H/ CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 h# E' N3 k; IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) y3 _ Q( K, OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 c4 v0 g. y/ A8 ^& c: f, Q" {. ?0 R2 `; |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) V! Q4 m( U. O0 x* U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 V" h1 A0 x3 c) S0x00, 0xFF); /* configure the clock for transmitter */3 V8 s+ H/ \$ d3 J! v) \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 ]+ H, T) S2 X5 y3 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) H( y# r5 ?& V/ t& j4 Z3 ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; u0 I+ B5 A1 F
0x00, 0xFF);
9 _7 ?" m0 ^+ E7 H: J# U/ X; `) d( o: \7 x
/* Enable synchronization of RX and TX sections */
. `* _1 L, D) G/ i2 Q, qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 z4 w$ V' P; R, i G% MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: K7 I7 [7 v' A1 {5 }1 s3 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; R* e) B7 F+ F% w u3 I** Set the serializers, Currently only one serializer is set as
' D* k. C: V* o! k. j$ z! [; Z m** transmitter and one serializer as receiver.
: j) ^+ _; E- V P3 ^& H*/8 n! {" r( A- }( _2 z& ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 L" g" _: \% uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ ]: x0 [* O0 {8 R" Q* u" O
** Configure the McASP pins
9 u8 _0 t+ K+ h** Input - Frame Sync, Clock and Serializer Rx
1 j: v9 O; ? f/ j! P. S** Output - Serializer Tx is connected to the input of the codec
% ~0 r: m: ~9 W- A# C' l*// n. N( Q9 m3 p- V8 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 G3 K) W) x! l5 f1 A7 B4 S# l O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" f2 Z$ p& ?1 v& E+ b9 zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. h3 d' q) \" B% f8 Z5 o| MCASP_PIN_ACLKX2 {/ D" s6 v2 @ L: i# |3 g$ W
| MCASP_PIN_AHCLKX
$ ~7 O3 ~% M- [" Z& L, n9 Z1 l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 D( D$ S9 R0 m, ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 _, D( d' o* n& V7 t
| MCASP_TX_CLKFAIL
( M7 v# Y1 l9 y3 `$ O3 G- O| MCASP_TX_SYNCERROR/ d' ]( h/ `7 B% `! n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# i8 Z3 Y3 F% ~| MCASP_RX_CLKFAIL2 V3 ~0 ^3 Y6 K' L
| MCASP_RX_SYNCERROR
: T- b( W1 s: R| MCASP_RX_OVERRUN);! e" _5 R9 {. M2 a! j) ~( s
} static void I2SDataTxRxActivate(void)1 h, i. {& O2 e) f/ ^' X- \
{
' Q7 I: Q8 ~: v/ Q0 J/ C) M/* Start the clocks */
, u- R$ f% y0 Z( n4 I8 ~. `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 ] w' T" v" L, H' B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 y" s' ]: ?( H0 T8 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. T o2 ?6 A% E4 r3 ` @
EDMA3_TRIG_MODE_EVENT);! f& a) `; j6 U$ e4 l, M& Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ K' [7 ~+ n. I8 zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( Q7 G5 e' R: C$ D6 N& _: n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% D! B- \+ @$ ^8 ]& v9 H5 ^$ e% Y2 a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 @" [1 b. h$ t' `7 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ N. B# s6 b% [1 Y" s8 U6 mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 P/ U* |: f2 a- `0 s; n9 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
_3 ]" H, G6 Z9 Y+ M} . d4 [' v/ P) ]/ v* O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # [/ w7 @. ~6 K# M& G
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