|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ W _1 A, R; H+ g9 q+ t% B ]
input mcasp_ahclkx,
) {4 H9 ]0 G# ` dinput mcasp_aclkx,
# o( }' O; o, T E, D7 xinput axr0,5 w9 s1 K3 j. v0 M3 E
7 E+ ?9 j2 g8 J8 l: E% ?
output mcasp_afsr,
9 |; M* h) b( v4 ~; e9 moutput mcasp_ahclkr,
% O% ?* A b4 h. B8 [" [3 Routput mcasp_aclkr,
: ]/ m1 B* j6 w$ ? U# x M) ?8 joutput axr1,8 r; r7 ]6 w7 C6 Z/ g1 n0 A
assign mcasp_afsr = mcasp_afsx;5 I+ c+ `! \7 E
assign mcasp_aclkr = mcasp_aclkx;
" h! C4 {- N5 x) S8 x' H" nassign mcasp_ahclkr = mcasp_ahclkx;
" [: j+ L( o- Rassign axr1 = axr0; . ?( [4 {! v, E `, u( Y
* W {$ e0 Y) A8 f- S e5 E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( y* Y' a* D8 \. R9 v, H. mstatic void McASPI2SConfigure(void): T W+ g2 w& ~8 F8 S
{5 `/ o: S* C3 _8 n7 h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 a! O6 U- O$ x; h7 Z b; g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( j5 [" p6 C& D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) B; A; J' B7 Q% q! Q+ z4 d. Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) D8 T6 O' }% t3 `+ z- mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, q" g- \% \' _+ F' r) W- I+ k. p
MCASP_RX_MODE_DMA);
$ \- y' P) } W* _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! D; O% q! x$ X0 h D/ Y- v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" {7 Y* P0 B7 N$ c, V" t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" Y9 u" y9 O$ b0 f3 o. wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ {6 X/ I; r) V4 n8 V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 e# p/ M/ N7 a' G4 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# h- I0 _+ M# Z; r8 [: p6 W* G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! I: V6 ?- r' Z \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 y# O5 D, ]5 i# ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* h* l9 v, K! N( y8 L# c
0x00, 0xFF); /* configure the clock for transmitter */2 A+ G, g0 w4 Y- i" V/ h$ ]3 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. G0 {) a7 i. m9 d: C4 Z/ UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ t; T# O; i4 {5 ]$ |" OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ N6 P2 B- M) ^3 a0x00, 0xFF);. E. @# D% X, z {. J
( b% u& E, ^ e, \
/* Enable synchronization of RX and TX sections */
% x. P: J. X! `$ F8 }7 J; ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 e4 u: ?1 i/ y4 A- d' b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. ]5 Z7 S& t$ w9 l( HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& ?/ D: s; t; D" U) l
** Set the serializers, Currently only one serializer is set as. D% H+ ~: y! ]+ _2 E: d
** transmitter and one serializer as receiver.
& m: Y8 m" a4 @ } f7 h*/) k+ H4 h8 G' G# w* x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); T2 O0 b4 w# E" `5 z5 ^4 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
]8 {0 p5 g7 C( ^7 f* |** Configure the McASP pins
7 Z' y3 j, t( p( T. R/ A d** Input - Frame Sync, Clock and Serializer Rx: Q+ @) T L0 T% X- x' R
** Output - Serializer Tx is connected to the input of the codec
& E S1 |3 u6 g" z+ q8 e( e) s*/: o6 C& U9 X8 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. Z l g7 `1 o7 d! x1 k8 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ u/ F5 e8 s4 f$ n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 K% d- M7 a6 v- I
| MCASP_PIN_ACLKX9 K% z% l9 x3 B7 d6 P7 x
| MCASP_PIN_AHCLKX
$ x- d# C3 k5 t# s1 r( H6 _, Y1 t6 V4 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ }( ~3 p4 `3 Q7 [( ^' M/ t# K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 v1 I% R+ }) ], G( L/ Q1 u
| MCASP_TX_CLKFAIL
5 \0 \# m3 Q" O0 P' U& P$ m| MCASP_TX_SYNCERROR
, G- ?4 P; u( ?/ W: S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 }: A$ t4 t$ H) @, G* O
| MCASP_RX_CLKFAIL
: }1 A# Q/ I |8 O+ q2 `| MCASP_RX_SYNCERROR
$ Y5 C( [# [& R2 T. s& J6 F2 p# r& S| MCASP_RX_OVERRUN);
" }( f' S4 V$ b7 L, H3 h} static void I2SDataTxRxActivate(void)
7 P) d" s8 p/ ^. @! F4 O2 D5 q{/ {4 K( N. E7 z9 H- N
/* Start the clocks */' A5 U' u4 x, w# `% N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* \" s; U8 B9 U$ c! J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* I, b' c9 N2 e- S0 t7 ^" {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 {! q( r. r* N- }EDMA3_TRIG_MODE_EVENT);
6 p1 X* r1 t! X& o8 ~/ u, P' m7 Q' fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # x0 J4 Y, |7 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 H/ \6 l" N7 |& |+ A ]7 ^% [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 K7 s; p) Z* @" W4 _& E8 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* m" C$ D# F/ q+ m8 v" |' F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. ~" H' l! G5 n" \( kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' J* @6 y7 L2 W- WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 V! @8 O! r+ P, s
}
4 E+ l+ `7 F$ |! ?. _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) y9 _8 z( X* n1 K$ U |