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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ k4 p! M" s5 h0 b7 O3 [: [$ T2 E( }; K
input mcasp_ahclkx,' i- H1 a, A. h5 {
input mcasp_aclkx,
: Z; a) q9 N9 z9 zinput axr0,
9 _" L9 z Z9 I
2 Q1 \- g0 {. Q2 K; @- \8 Eoutput mcasp_afsr,7 q9 Q. Y @- q; M" s# N6 B
output mcasp_ahclkr,
. v4 s2 f- r& g# u0 youtput mcasp_aclkr,
, l$ `. X% q3 Z4 R2 Aoutput axr1,! O2 T' q' ~3 r# s0 @5 ?
assign mcasp_afsr = mcasp_afsx;
( _4 m! D* L' \! Hassign mcasp_aclkr = mcasp_aclkx;# i( d$ s I4 r1 Q
assign mcasp_ahclkr = mcasp_ahclkx;
" ]' Q' s+ H ]4 u$ g" i! Dassign axr1 = axr0; T: C% q$ a5 A7 T, F( Z+ S; _
' L5 g' B/ m8 G, y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # E4 [7 u- f6 A- y" @ H
static void McASPI2SConfigure(void)
9 D) A7 J( [ E' y{0 K/ |7 T! a5 N# \$ C. f! K" l7 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' S! t5 t7 `- S/ f$ g0 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: f) }. y) S" S+ z3 A9 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, g0 b# e: l* v2 s5 c3 h: P# u. [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( ^$ E/ t9 z* X* j: H) Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& }/ L# l7 l, ^2 H/ G! J
MCASP_RX_MODE_DMA);
# Y, o, U& K" n( y' F; uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 j( t6 s( E* n1 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: K1 W# d0 t+ f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* z& @3 g' a* e" J8 D( O2 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 B: ?: S+ ]2 G+ g0 A6 V# E* @4 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 [/ z$ v+ i/ |$ q) E' xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! I$ t9 P% M9 ]: c/ j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! }$ |2 o: C1 Q# V, L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ A: ^( x5 h' Z* hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," m9 k1 }5 A+ s& d; c
0x00, 0xFF); /* configure the clock for transmitter */- @9 y0 n/ g1 Z" d; L* C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( n9 r5 ]% F1 [8 u5 H0 q9 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 `7 }5 j" R. j' J/ F! @; UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! H6 t# z0 }9 Z0x00, 0xFF);. _% L: Z7 V# |0 ~+ v
" m" | o; l x1 X0 d. ^% l, j# d
/* Enable synchronization of RX and TX sections */
8 J2 X/ a6 o3 T4 N9 E, xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 y; T: r1 ~8 E0 Z3 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 L$ T8 K5 X' t7 d' ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* R0 C2 d% k" s. n% q8 _2 E** Set the serializers, Currently only one serializer is set as
, p [& O+ x- ^9 V* u$ }** transmitter and one serializer as receiver.
! F( \2 Y+ m+ I) ?, m*/) R$ m; i q j4 }! F- L% Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' f! n9 B; I. x6 Y' l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 h: p4 ]0 _9 S* y1 w: J) E/ p
** Configure the McASP pins
0 F$ J) u3 t, `* e) g) n$ b** Input - Frame Sync, Clock and Serializer Rx
7 i, L) @( ^* ~) }5 y! D/ ^** Output - Serializer Tx is connected to the input of the codec " h& c- M' r# i/ |4 y+ ]: t% ~
*/
7 j3 h* H6 J) d0 xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, r( c, M& R4 }* r4 F! ~' y$ HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& h; y: J7 Z3 X* l3 r X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" J) Q; X) n1 _% {, A( S" A% ~
| MCASP_PIN_ACLKX7 G E. E$ Z( M9 W- e( y
| MCASP_PIN_AHCLKX
7 e& F8 R1 Q0 r7 k8 E# ~7 n: K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( W% m# ~, x, i# w' A. ^' f* p" G) e8 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 Q/ [: ]1 h( B2 d6 [| MCASP_TX_CLKFAIL " }0 Z8 E' L- ~- z8 V
| MCASP_TX_SYNCERROR8 q9 g5 d& r, z. \. @# x9 x" n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 Y9 d2 K! ^- L) Y% m| MCASP_RX_CLKFAIL# g8 @# T* c! T
| MCASP_RX_SYNCERROR 7 S- D) K3 _$ \
| MCASP_RX_OVERRUN);
0 n5 w0 Y3 u' t. H' B& D} static void I2SDataTxRxActivate(void)1 A& G% O e* \' J3 L, N" Z0 k( \
{5 S. T2 d' P2 R0 Q- O, R
/* Start the clocks */
2 h% S% R" g+ s, q: rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% e0 Z- T# I m7 t J y1 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' @* ]9 q' H( O+ r& k9 B: r4 S( y/ jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( l- B( B( ~; Q, r* G, n" Q$ @ P
EDMA3_TRIG_MODE_EVENT);
( b- p6 U; S, oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & Z% I" P; L# o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- z) G9 n) B& L; F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ Z( K P9 s) R' p O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 E1 ?1 E9 o( w1 }' a4 F% @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% u! S3 U- a0 [3 o1 E* R3 W+ jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' _- P- @7 g8 Z% h1 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! V+ `* C. E; ^/ ?! I9 ?}
% Z. ?' O" L) G+ Y8 H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 V2 G& }2 K4 j. q1 C, l; ^( M
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