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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ @( q) }3 N: A; Q4 tinput mcasp_ahclkx,
, \, a# m2 G* m- Einput mcasp_aclkx,
/ K6 y ?- X- @; Vinput axr0,
% {3 V* d) Z; G# m; C
1 v8 r3 n6 v2 R. x+ |$ Voutput mcasp_afsr,
5 E( L/ q. a( Foutput mcasp_ahclkr,/ f# e4 _# o4 P* Z
output mcasp_aclkr,5 `+ U$ X7 k x. l( `
output axr1,
6 {* q# d& N1 O: x6 Q# i6 K assign mcasp_afsr = mcasp_afsx;
9 ]/ X ^3 v1 ~8 g! Zassign mcasp_aclkr = mcasp_aclkx;
+ L& q. `* e: l% `6 O1 `1 ^assign mcasp_ahclkr = mcasp_ahclkx;5 z, f4 j3 m5 d
assign axr1 = axr0;
6 p. F- }; r/ u! z5 e2 }9 D; D
( N) C8 O6 z' P( a0 N) p# w8 J, e& f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) p# X1 p% l( L/ E7 P, E/ i; t0 n
static void McASPI2SConfigure(void)
2 O. L& {" Q, m+ c7 \{
% F y* ^+ m. e3 U# }McASPRxReset(SOC_MCASP_0_CTRL_REGS);: {" r! t. Y" R# ~9 h5 w7 H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
b5 Y' Y. V4 ~! m% F/ i K' j' L/ uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 ^0 i1 Q F7 B8 z$ c4 h% G3 B! y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 ^+ E+ Y! O, P/ F3 E" tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 I" l+ M3 J9 \+ h! S9 qMCASP_RX_MODE_DMA);9 t+ F$ g$ d* T5 f2 K5 Q/ T" X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ c8 `9 G) Z3 o) c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 A6 K* q( Y+ @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " x N8 d. [+ r/ r: b" Q2 }0 l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% K h0 J `/ O+ R7 S+ e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! L5 ]0 u: G/ c7 C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, I$ V2 d7 ?& \9 ^/ n( c$ K% d& |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 H+ ~; T+ O0 ~) v% C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( M: u' G( m3 D3 A& s+ uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ |5 O" V7 c# _ O1 H$ {
0x00, 0xFF); /* configure the clock for transmitter */
2 }8 \& w! K6 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 R* ]$ j& G9 D6 f, A+ fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' u5 p; Y1 ]! k" O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) [6 S) g- U0 n( o0x00, 0xFF);
" `" U3 y5 U n' ~$ \4 `/ w5 B* I; I" ]" S9 n) u% N
/* Enable synchronization of RX and TX sections */ / Z( x) A y6 m. z+ [; C* S3 z) q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, M; Z B5 _7 w" bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 D* v- R6 ]) S) x- h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& D8 ]: c d7 M# Y# u$ V3 S! t s; q
** Set the serializers, Currently only one serializer is set as
- g; Z6 ]: j% W1 ~0 g# _3 ~** transmitter and one serializer as receiver.2 M) ?9 t( }3 t) J8 r/ p1 h
*/8 ~: J) K# _# H% J5 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; p3 v$ J9 u9 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! v0 {% U& F8 T- u; v* z$ o** Configure the McASP pins
' ~7 M4 L6 ]0 [** Input - Frame Sync, Clock and Serializer Rx
/ c Q9 w) s0 r( E1 p** Output - Serializer Tx is connected to the input of the codec
: q; \+ K6 r( C" P" Q- t* @*/
& g. }9 | [' |: }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% U' x! C) B: E& m$ I UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ v# d) M* F" g6 u1 b3 c! }; e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 ?2 i4 c3 A' q
| MCASP_PIN_ACLKX+ h# R( G$ l& e5 j+ C7 Y
| MCASP_PIN_AHCLKX/ M4 k7 G; i9 S3 G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 U' g, ]; z; Q+ d3 U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 m, Z, u0 P- D8 a$ t2 x+ Y
| MCASP_TX_CLKFAIL
2 F$ K7 f: y- v4 Q8 q| MCASP_TX_SYNCERROR( J; {4 s2 P7 u" f9 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 J: i2 S; M8 P3 _& c; i- Y6 d0 @
| MCASP_RX_CLKFAIL+ S6 _- ?0 D7 v0 q v) f1 S
| MCASP_RX_SYNCERROR 4 ]: N* O- }5 L0 ?
| MCASP_RX_OVERRUN);$ @" v' N/ K2 h! k( j
} static void I2SDataTxRxActivate(void)/ b9 J% T/ ]; W! U' P
{( I8 d1 u7 j& l% }% M: I0 c
/* Start the clocks */! f7 V; Y3 w: }! I* U5 O/ g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ U7 s8 A( U1 J8 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ F6 z7 @+ P' ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* ~4 u% p; e( \3 Y5 h
EDMA3_TRIG_MODE_EVENT);
2 Z7 q; o, o bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ S$ `+ d; o2 B6 r- cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 A% e g& m2 ^' j) t7 Z2 i* j/ F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 u* g4 x: a7 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 p3 u, _/ v$ D9 z& A% S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) n7 ?+ @1 h! u2 p0 t. MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 g5 k m& Y r# q& pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& {5 R9 t3 v4 x1 q/ }2 n% m
}
- ?* f( |/ E! `3 J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 G9 y% M6 ~+ `5 T+ F' S
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