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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 S, Z4 K% J4 g* E
input mcasp_ahclkx,9 a. ]5 T1 Y* `+ W+ h. ^& x
input mcasp_aclkx,
k Y8 u& [( q" Q7 s6 ^input axr0,
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output mcasp_afsr,
5 v C0 Y4 A# D- Y1 Koutput mcasp_ahclkr," Q% |6 t9 U# N8 f
output mcasp_aclkr,
9 r5 R& M& J8 Q4 n( G$ _0 ~# aoutput axr1,. z( b9 h- s' A# R2 D3 [& [
assign mcasp_afsr = mcasp_afsx;
& U- n5 T4 i* X/ c0 P4 }assign mcasp_aclkr = mcasp_aclkx;% t0 q; `0 d9 P% `1 ~6 v
assign mcasp_ahclkr = mcasp_ahclkx; ` r6 P- }6 n
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 A( v! I6 g) ~& ^" `) G
static void McASPI2SConfigure(void)
% y9 t8 ]% A) h5 A& H7 ~{
0 s& ]# R. p, d" fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: D/ F L* i- n) Z; N2 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ c! Q6 N% `7 J. z& J# yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 C$ J9 f6 H0 v$ A+ r" X6 F2 GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& L, j: t$ v* f0 T) u& F: X* x( OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- Y2 H% ~ Q" p' UMCASP_RX_MODE_DMA);
% U( o+ {9 h9 l, k2 X9 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 \) O+ A3 X7 E- e+ f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ b+ Y" i0 Q6 ^- `% B) \" R. f/ S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 S1 W2 J( K: G! i2 t/ gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ n5 L( W# g. ]9 J* V4 _$ @2 ]8 wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- S8 r0 b( E1 F, R5 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ m8 T8 l- M1 w! k5 ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ \' }& M' Y+ G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' a: R8 u- l2 `' i' ?, Q& r2 p( AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& E# S) _6 z9 c9 U' D; U$ N
0x00, 0xFF); /* configure the clock for transmitter */2 c+ Q; {; C& s% k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 V/ @( F# }) ^" MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; h" H) w1 A4 v( [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) Y* z4 {7 p7 }4 ?6 O9 U7 g. C0x00, 0xFF);) {8 N8 [/ o& M$ B
2 g( i) S5 u: w {$ v/* Enable synchronization of RX and TX sections */
- |/ a3 S1 [0 |5 DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 _0 u5 T6 j* I: \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& b( C( m' W- o. _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' U5 `; M2 H \* w** Set the serializers, Currently only one serializer is set as6 J! T$ j' O! v2 ^. I! d! o! ~. z
** transmitter and one serializer as receiver." J$ d$ |, q Q
*/& e1 f/ `$ t: ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ c1 U# c, z2 |+ x) t3 i. s+ \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" @( O9 \* |5 j* J$ J** Configure the McASP pins
( d3 z) \7 z" H** Input - Frame Sync, Clock and Serializer Rx! l0 r% u& ?4 I8 b2 L1 `
** Output - Serializer Tx is connected to the input of the codec
* [- R3 w6 [$ u. p: I0 y& N*/4 r: b5 L+ U) `5 B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* u9 U* m- ~# k1 C5 e4 D0 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. n& P4 ^- `4 E) l8 T, Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 |" E/ _; z7 N% S) o( u
| MCASP_PIN_ACLKX2 ^% H, E& @; S3 z% c9 N
| MCASP_PIN_AHCLKX
; C9 b( t8 ?, A7 P( [1 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- b+ q. G0 p; g8 b$ t$ w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR H4 H2 Q K# L0 h- e5 @ O" f
| MCASP_TX_CLKFAIL 9 I& A& }8 ^! r: [3 S
| MCASP_TX_SYNCERROR
5 |% N4 x2 u4 u/ }4 q, L6 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 G2 [1 p6 v% k+ ?3 w% r7 S$ Q3 M( D$ ^* C
| MCASP_RX_CLKFAIL9 l/ ?# N$ H+ Y
| MCASP_RX_SYNCERROR
% l& R& w# F& }, v| MCASP_RX_OVERRUN);5 f6 Y; e: @6 M `
} static void I2SDataTxRxActivate(void)) F- ?( @ h: ^( [/ d
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/* Start the clocks */7 w- l- D' h" _: x% R3 i Y( P# u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! T4 e: n( W8 z% k7 e' O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ L7 l( h/ K4 N4 d! a- }8 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- o* Y* k( h5 X6 X, MEDMA3_TRIG_MODE_EVENT);
, y' a3 A. I7 [; z" l' ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; }: g" ?/ ]8 T! ~1 T5 i. v6 P/ }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 R& ?/ n/ z2 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 |( w5 }; g( f; q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: D$ Z4 X2 U% v e* q. gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* N* x* j8 l) @ I" Q6 ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; j, o9 l: Y8 V; S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ [( j8 G" }- w4 l& c
}
/ b6 Z! e; [+ R% v7 p- Q3 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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