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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# F3 w0 D& Y" Dinput mcasp_ahclkx,
+ _% T j9 L! a0 o0 [4 vinput mcasp_aclkx,
+ Q$ H3 o, {0 }9 s3 b2 Rinput axr0,
, H- f1 m" L2 w$ O% L5 C3 C3 a$ C1 y6 a. I" ~
output mcasp_afsr,
6 i8 y$ Q4 m5 B1 ]- d8 P/ p* zoutput mcasp_ahclkr,8 O* s( j& |% ~' a
output mcasp_aclkr,! k4 Z; c2 O& y1 q4 {+ i9 V
output axr1,
! ~) n$ h9 O/ D9 ? assign mcasp_afsr = mcasp_afsx;
' C; N- I7 |/ H: passign mcasp_aclkr = mcasp_aclkx;3 k/ F5 R5 Z/ p: Z# W g
assign mcasp_ahclkr = mcasp_ahclkx;$ P; [$ p3 i9 ?! P
assign axr1 = axr0; 5 K: @8 l+ @: m, Q* ]9 I' J
) v2 x& R- u6 o6 }" ~" P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 J/ K; t% m; x# \7 j# _- K
static void McASPI2SConfigure(void)
" N! Q% W' q0 o: B: L3 ~9 `{! J# |4 b1 n" D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 ~2 F4 L( S/ t) k! a8 a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 g4 ~" f! X% {$ L7 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 b! Z. g! U2 ]/ U- F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 {7 [8 e$ \3 {2 x! UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ @' Z$ t( w$ IMCASP_RX_MODE_DMA);
$ _1 }! h/ K; T, j# WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 R. q+ D- j- i! B+ c2 q' v* GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, J1 m$ O# M4 a5 t4 BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " M# Q5 q8 |4 n% ^/ c& F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! w6 x/ \9 E( l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , L( I, L+ W0 M6 c* ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; N5 d! l7 s5 A1 Y/ _- x$ W7 ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: c6 t) ^9 M% c7 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / [, ~9 h. a) F6 D1 ?7 ~. {2 h$ Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, G7 {9 \/ r) R5 n. T* ^+ Z
0x00, 0xFF); /* configure the clock for transmitter */
k: L: u" c0 c6 uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 t, c7 }/ r1 W8 d; h* U. f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; Z# t, A3 M8 ?5 z; L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- O% X. j+ K" e0x00, 0xFF);2 e6 f' a4 T' o L% q; V, i5 Z
) [; N+ G/ v7 j/ x& i/* Enable synchronization of RX and TX sections */ ' ]( E, q2 i. X1 j% d) k! A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 {5 B' d6 S/ \5 ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ G$ `! g: ~ b# |: v* l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ v. n$ c/ A* a) `# D" C
** Set the serializers, Currently only one serializer is set as
/ S& y _0 B, r** transmitter and one serializer as receiver.
4 f$ T. j) T- a d*/; j* P0 N5 F, [2 K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& V; r/ j E" b3 g+ C5 H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 L& k; t9 P, N3 W: n2 N
** Configure the McASP pins 2 m/ B; A$ N, K; b
** Input - Frame Sync, Clock and Serializer Rx
9 ?/ c: I, b" ^7 `# `. [ f$ r2 S** Output - Serializer Tx is connected to the input of the codec : J% }0 E' H0 a5 B6 I/ }/ O( I
*/+ @4 R1 k2 F m3 p% ~+ C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 H9 O9 b- M' v {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ {+ a0 I1 D1 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) C4 x. U+ d- T# D| MCASP_PIN_ACLKX0 E: ~, |; @2 [. l6 n& b# R* m$ e
| MCASP_PIN_AHCLKX8 M: {0 N! e C2 r4 y2 q4 H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 }8 A/ w* t3 w, [9 M; Q& P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 r% b! d! y& U( ?# v" h| MCASP_TX_CLKFAIL + j! x2 R# u* [* t) r
| MCASP_TX_SYNCERROR; j M6 x* q" X; I/ S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ h% D" `5 Z# V; \4 E/ x/ W1 V| MCASP_RX_CLKFAIL* D" O* J1 v( a, f# N
| MCASP_RX_SYNCERROR
4 c S- @7 R/ m; i& y/ x6 j8 Z| MCASP_RX_OVERRUN);
8 K7 |1 L. I/ h* a f% N4 k; n} static void I2SDataTxRxActivate(void)
6 E+ X- N6 x- f7 }" r{
3 j* x5 z( @% {5 y2 e, p# K: L& f/* Start the clocks */
1 M0 B1 ?& e; ]. RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 p. k) \" U+ H$ fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, M. H( f& f& }# ]9 b" f) e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- T7 N F4 m$ T" ^( ~ Z/ oEDMA3_TRIG_MODE_EVENT);5 B0 i5 `& f$ H5 c# D. W: O- r. `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" l# a' {% E$ q( J6 q! y; P( k8 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, [# I8 h' F( A+ c4 D% ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! b0 s! I: ~1 TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 g8 U6 j$ C: p: n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 Q! l v. _) K. I0 LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# ^) w& \+ U7 A Y: g: l3 E1 wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 D+ B; Q8 A9 ?
} 7 q2 O% `1 n+ H' b) e+ R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ K- M/ {: O* r& j. Y% t8 B, K
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