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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, a# f; N# \' r0 \input mcasp_ahclkx,
, N( R9 c0 g) W6 F; ~input mcasp_aclkx,
6 a+ R( d8 ?- r% }" r" X* T% Vinput axr0,
8 k' @! [4 o8 `
' B" @. r1 \& z6 ~0 ]* G! l% Boutput mcasp_afsr,9 h, K) Z9 C9 S8 D) F5 J
output mcasp_ahclkr," t+ t& a6 ]9 L
output mcasp_aclkr,
) }& w* F( D) Q j$ z9 G* loutput axr1,- v" O( J, O# t7 s P
assign mcasp_afsr = mcasp_afsx;* z+ h3 U9 M) j5 P
assign mcasp_aclkr = mcasp_aclkx;8 `6 R. l% A' B1 E, m
assign mcasp_ahclkr = mcasp_ahclkx;: C* [+ h. h' _9 X
assign axr1 = axr0; 3 y7 Z- s' a2 P* O- c- q
7 k: h" Z- Y2 o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & i) h" k: G6 Y% f( K% a+ v
static void McASPI2SConfigure(void)
4 M: t9 U( }' [6 Y{
5 I% r$ @) v' }3 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ i& z0 H7 }; Q4 j( _' }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 w& v' g8 T/ V. M- m; \% M3 R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ w7 V& Q! k# E. \# F. e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 E4 y2 l" n$ U6 X3 a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ~; t, ?, n' P- @MCASP_RX_MODE_DMA);1 f, D- o0 j4 s" R. O, k2 m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," o* V, q: o. T; I$ p( t6 Q' X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, ~# I& r2 Y& Y' I+ A' sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 U2 P+ G. R6 e: b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& N3 W: `: M# ]6 m- ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + c) z- W) `+ @2 ?1 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 r: h$ e# Y( \$ X CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: U) U" H3 \ hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 S P0 R7 a& a1 ]$ Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& x2 Q1 v, r. J" F; i
0x00, 0xFF); /* configure the clock for transmitter */
6 J( q5 W" k6 `6 ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 W& c' L9 K# j! O+ F9 m) SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% g; v. J7 L2 _ y0 x& cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! D8 [ n0 s5 q+ \0x00, 0xFF);+ P! i5 j) P! U" _& F
# o6 |+ D4 I& l/* Enable synchronization of RX and TX sections */
9 X- Z7 X4 o, o$ ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) K1 q C9 \% Q: aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& U! {3 j+ C( v3 N" fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# |* B7 _9 T, O/ y+ v. m** Set the serializers, Currently only one serializer is set as% Y; n9 @) _5 `* ^2 }
** transmitter and one serializer as receiver.
( z/ E; `2 b- K2 \- S8 y( J7 n* x*/. s d' c' `- ?* T2 i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) U( I/ w3 ] S; Z: e) F8 u! }' g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 _0 r! @8 `6 j/ i1 ~! U** Configure the McASP pins
; ]+ i+ o8 p& l** Input - Frame Sync, Clock and Serializer Rx4 v6 D, V; Q- V: J
** Output - Serializer Tx is connected to the input of the codec & p2 K- Q0 M, j8 x; b. _0 T
*/
5 n' z+ w* t' r/ \& mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, P2 ^2 q8 a0 D1 X) H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. Q( L: B3 p; M! n7 t, R! k* YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 x2 H0 u2 J6 n( N x| MCASP_PIN_ACLKX; {. |" G( ~" u# G( {0 t
| MCASP_PIN_AHCLKX3 f$ q- F7 J2 p9 V# @6 P. B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. m3 _9 R! i9 E$ ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! T7 B/ y/ O+ p! H% H| MCASP_TX_CLKFAIL # a1 Z% N: O9 F7 V: M% Y
| MCASP_TX_SYNCERROR: ]- f; v7 y7 p4 X7 N- R- ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 F+ _- v1 u4 q, S& V X| MCASP_RX_CLKFAIL
. N; a, ~3 J( J| MCASP_RX_SYNCERROR
& ~( Z7 i. U0 |$ t- c, e| MCASP_RX_OVERRUN);
# s; k$ M2 i5 G" `! C3 O+ j0 S} static void I2SDataTxRxActivate(void)
; n4 Q+ y* T6 Y6 _" W{7 \4 e @ @8 p6 }. b t
/* Start the clocks */
3 G6 q* B; r& M3 K7 n7 x% ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 `3 [& ~0 w* x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* E' Y0 R* Z% A! a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 [0 N8 Y& d3 Q# a# s% c4 g, f
EDMA3_TRIG_MODE_EVENT);6 e/ |( f L0 ?( J$ v) s1 y. C, F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( c, r! \3 `. A# sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 j }+ E* p* W2 p# A, ?, h) @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 U- z6 L! l6 a3 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* w+ N" s. j( n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 K' q2 g" h- uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" @( E, t: l- _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ v- u3 j6 G$ u2 H}
: `% t6 W# N: I6 a8 q0 A$ [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / o- h8 `/ Y8 {* ?
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