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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; S' Y% z2 c- j; R- g! ?1 S s$ L
input mcasp_ahclkx,
" Y. b M. w+ V& s2 R6 \7 Oinput mcasp_aclkx,7 s) `2 o9 O. n+ T4 X/ k% _
input axr0,
- \5 ^" \( c$ h3 K) r1 X+ z% ^4 F3 ?8 A* u
output mcasp_afsr,4 x( k8 }* K5 p
output mcasp_ahclkr,& ]7 B+ L5 s' Z4 n3 A9 G
output mcasp_aclkr,
- v! W' N$ o" O; Koutput axr1,
5 g3 f; e3 t5 z9 X. r) ]+ c assign mcasp_afsr = mcasp_afsx; N. b* s0 i- l! K
assign mcasp_aclkr = mcasp_aclkx;
8 h* y3 V2 S9 @- G; }* `assign mcasp_ahclkr = mcasp_ahclkx;5 T1 F: k) `8 l/ k
assign axr1 = axr0; & ^! P9 H) m8 f# _2 S( p% [
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) f, C; X; f; C7 Z/ ]% N( h
static void McASPI2SConfigure(void)1 w+ e3 f0 E9 N* I/ y v
{
. c0 R2 o. }4 N$ G/ n- o; xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ W/ h- V7 X! d3 f$ QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% P1 i: b8 u2 G* h- I8 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, Z) g5 s- [0 L0 E+ S; p# GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ I; L; t% P; ]1 k" HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! W: U" _# X9 z* s/ C* U2 A9 b( |, z
MCASP_RX_MODE_DMA);
: \2 U, h1 f6 K7 Z0 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ C: S! L; X5 p: p3 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) X: ~; t" D: N8 t& _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . d) P9 ^' F2 \2 @. e' c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; l4 o9 A; O/ i9 y* Y$ l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# L& @# D7 ^ uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ o7 M* v" Z, R# g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. U9 O' B5 C3 T$ r# k" K; K$ YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 T( P% ~; R- T1 ~ K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% t9 [3 Y Q7 G
0x00, 0xFF); /* configure the clock for transmitter */
, ^7 F: Z) ~% x5 \' E7 ` a8 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 w- B/ n. y( {8 ?5 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 Z7 T F) w/ r0 P% V2 y0 a# F: B# cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 h4 c8 c# B% f( k6 n0x00, 0xFF);
0 z: I8 Y- H: P- N: ?
' M; D- t3 c6 m; f, P( J# P B1 V" k( L/* Enable synchronization of RX and TX sections */
3 j6 C2 z) w8 b' m/ p% @! o! Q, GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 o" B: c7 h, A% e. kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) h3 ~# ` ]6 @* H5 }3 @0 ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 r& F$ F- Q% v+ {
** Set the serializers, Currently only one serializer is set as. l: _# e( _. a, `, `
** transmitter and one serializer as receiver.
# D" ~! o- H* D4 }7 K*/
( I( g4 `0 W0 G; y0 l6 oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 }; O* {1 P, KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** }. H& n4 w5 P3 j4 U
** Configure the McASP pins 3 n' }* A/ `% ?% E# ] k/ B
** Input - Frame Sync, Clock and Serializer Rx
9 X. Z3 j; L" h( ]. g* H** Output - Serializer Tx is connected to the input of the codec % W$ H8 Y$ F7 ], [5 X1 D* L
*/
2 ^" f- z @# e" Y% O: oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 o6 _: q8 m# W4 @1 t: k1 j& V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ O% O; S9 {' E( s0 Z: s v0 `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( A$ @; h6 {2 G0 W| MCASP_PIN_ACLKX, [9 [- t+ O0 E3 [, T$ _
| MCASP_PIN_AHCLKX0 [6 _: f- {- e e# h# o. c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ ?3 K( ?8 F) r7 b8 z) U1 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR l* B! g( r) C- a+ b3 J: s
| MCASP_TX_CLKFAIL
' t, n- ^: S* e0 T; o2 z1 }- V- K| MCASP_TX_SYNCERROR
9 q$ B1 `7 g+ e" H9 D$ J8 H* Q( ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ }& R9 V4 k9 e _| MCASP_RX_CLKFAIL) t$ r! \4 b' R) S. y- ^
| MCASP_RX_SYNCERROR
* [( }$ R8 p3 u| MCASP_RX_OVERRUN);; x3 x M, Z8 t
} static void I2SDataTxRxActivate(void)
" S) ^* Q) }9 f6 D{
/ |" n: D7 Y1 ] {! R/* Start the clocks */
6 x5 f9 e" _: |6 m! CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% B$ c8 Q" A* @! g0 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ T( ^4 H1 W: r) {. z+ lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ l, {# F1 P! }% c9 `
EDMA3_TRIG_MODE_EVENT);3 E; x. N: [% ]! x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 p: F4 @$ s; z/ }1 _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* T) `* i5 u2 Q# S/ O1 V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! s H" c9 g3 S1 a7 U2 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 i1 R, |8 P% K6 v8 L! O1 a8 {! Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 ?, _- q; A8 r$ B a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 `! O% h; J$ e) o) NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ K. @6 i" i* D% i7 E5 [
}
' f6 U3 X2 _: ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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