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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 p+ X1 a) w* R9 Y# Z' T) ainput mcasp_ahclkx,
* {. K* Y& A& j3 P0 ~input mcasp_aclkx,9 y/ ~* k* l8 j( r8 S
input axr0,, O# c2 j, J2 o; e
* M' B/ U( R# S' j Voutput mcasp_afsr,
- e: {+ l& V$ B1 ? p! coutput mcasp_ahclkr,
1 H7 @9 _3 |- Q uoutput mcasp_aclkr,, j( Y7 c. X( E" b
output axr1,& ?) l# w7 r# O# W
assign mcasp_afsr = mcasp_afsx;+ h# _' B0 Y. s7 |) \2 x5 d; j
assign mcasp_aclkr = mcasp_aclkx;" J$ ~% N, E$ ?. K: m& f2 e5 _8 D1 a
assign mcasp_ahclkr = mcasp_ahclkx;
5 s, J& ~7 C) T2 {9 }+ _. Dassign axr1 = axr0; 6 h8 Z/ s, f9 ^& h
9 H+ J% R- O8 J/ T$ e8 \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 i G- Z: `5 g8 H5 s( j ~$ Ustatic void McASPI2SConfigure(void)8 N1 G5 r+ D$ f" y0 f% `
{
5 H: C' Y3 `4 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 u! {. f! m* S2 T4 W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 P# W5 m2 [. z' k' Z! ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 \1 @5 M0 i# {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. ]# ]& Q3 {/ }2 |0 Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 [/ \: P; X8 O8 o" ?
MCASP_RX_MODE_DMA);
2 t9 B& a/ P7 T9 M, j) }7 g* WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. V0 d& N% n* i6 v( Q2 x: I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! Y: t" Z$ x% F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : O H8 k7 |/ u3 o8 x: u& r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& \4 [: _+ q! mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 ?. h, ^" I! v1 d, |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* o ]7 L+ H+ j' i0 o' X4 BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 `6 w& d6 _* O, sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 N' m; K1 }/ a, ?( S% ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
X: C: w8 @0 K) I/ Q0 M0x00, 0xFF); /* configure the clock for transmitter */
( G% i/ X* @7 E4 @( V( t% c$ ?- HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 G& b- i& v8 |- O2 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( a# A4 G( c5 R6 I+ m6 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: W t" G5 |6 C2 n" r0x00, 0xFF); B* v( ~1 o8 k1 p$ h, r
0 ?$ q4 n4 u. H) s4 n* r
/* Enable synchronization of RX and TX sections */ / Z: b0 d2 {6 v# @. {: p2 a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: g1 [# H c& Z. rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ G2 s j7 }- Z4 c% r9 u% C: T6 I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) d8 f2 _) ?# [ _: ?& x6 w. V) v
** Set the serializers, Currently only one serializer is set as2 J, c4 x! ^5 B" c1 e
** transmitter and one serializer as receiver.
& D4 ~/ n! L* n3 u8 H*/
! a1 c! w: g' Z' }8 y: U/ h, i/ O2 aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ h5 V# }" i- \1 w: K1 P: F/ A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& [1 o: P" B R8 P$ u: {' ?" i9 y
** Configure the McASP pins : `9 x7 H& u# r$ D0 F) [/ o
** Input - Frame Sync, Clock and Serializer Rx
. X+ M {) q8 {9 D** Output - Serializer Tx is connected to the input of the codec
3 B$ m4 B1 ]5 ?( H- b1 M' M4 N+ G: `9 R*/+ m6 Q8 t. ~2 N/ `4 \' U5 T( u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' m" V! n/ F- j0 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 @7 V- x1 Q+ k3 _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 ^/ ]0 Z1 m) ^8 h& }* J" i e
| MCASP_PIN_ACLKX
! r. E# A3 |' q: s5 ^- |% I( {| MCASP_PIN_AHCLKX
b. Y1 b7 w7 {$ @/ R4 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 B% X! |8 Z- U8 K0 V2 T- OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 T$ c4 m* |% H7 b4 Z| MCASP_TX_CLKFAIL
5 ~% g3 m* i% X* ^| MCASP_TX_SYNCERROR
: `: |/ q' w" A5 w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 `4 X" I# E9 H, z4 [( o9 i
| MCASP_RX_CLKFAIL
5 i7 ]; M( e" H3 ?| MCASP_RX_SYNCERROR
8 K' l- u! ^% u$ R| MCASP_RX_OVERRUN);
7 @, U( ^6 U# |" Y} static void I2SDataTxRxActivate(void)4 O& r x/ D; J# Y' z
{- d5 r+ g: l! e3 O
/* Start the clocks */0 _+ u& j" d. N+ W! ]( @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# ~, i6 q2 S9 n+ Z! Z2 a6 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ f2 O7 D9 D6 p! v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) l$ b6 _+ v+ i1 ^' DEDMA3_TRIG_MODE_EVENT);- t# x) _! h5 J' |! b: U& Z. y. {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! ~" W& e& K8 W4 w9 I' q f3 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 _9 ^8 {0 V' U3 _* o/ D# ?+ E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 _5 @& i; d, O4 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! b4 U. B% b1 x8 r3 N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, s Y: P( [% D8 e; g3 M: L" @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 k- x3 ]$ J5 @9 k: C9 R( J6 S" J5 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ v6 k$ n4 L) |. T( p# S( A9 G} / g7 H. m; @/ o) m" k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 ^; n3 `. N, S% N1 P, e
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