|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" ]/ v. Z, }, X# s8 a2 linput mcasp_ahclkx,9 ^" \, |4 B+ P* N% h
input mcasp_aclkx,7 I: d; I, J+ p
input axr0,
, A% A5 y! ?4 u# d" U ?6 n4 D" |$ Q. [2 U) N" _$ \
output mcasp_afsr,
; H3 e' v& |$ _( ]+ Y3 Voutput mcasp_ahclkr,
2 _, _% X k, w0 N5 ?output mcasp_aclkr,
* E; j3 ?% f9 i2 }9 w4 voutput axr1, z9 O- b. Q; ]' s0 L7 L
assign mcasp_afsr = mcasp_afsx;. A) z; n6 h0 g7 l
assign mcasp_aclkr = mcasp_aclkx;
* Q7 Y0 u4 z+ _( }) ]assign mcasp_ahclkr = mcasp_ahclkx;
5 W' d; [, a& ]% Cassign axr1 = axr0; . R! C7 a" P3 h+ k; T$ i; p1 ]
, x0 \, i- ]0 ?: P' D/ h2 r; o! ? [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 W9 u0 b3 E9 k6 T/ _0 y7 t
static void McASPI2SConfigure(void)8 D/ a! V: Q/ c
{
8 E" c2 S+ j$ |2 |' xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" ?7 T) `8 n% iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 R6 L3 x/ _" |/ @! J0 _8 g' ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 j0 G7 k) ]2 x( K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' ^1 B* L. E7 w4 H; U( W- s+ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 t4 o* w% p. u. F0 O5 T; @8 J
MCASP_RX_MODE_DMA);6 q' {( B: O# E4 M2 v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ r# X! X) g' H- l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 x3 O* K1 y# f1 C3 }0 `) ?2 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! `$ ~6 o: r" X( H" L( r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 X9 r4 n# V8 D5 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% D" S' k4 X' i0 n3 vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; s- y* n6 u! V& I7 ]7 |4 TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 P3 M I' g8 M6 a# L7 A# O6 ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ i, A- ^; ^$ K { ?! H5 z8 eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# ?7 c6 u% T; V7 f) ?& Q( O O0x00, 0xFF); /* configure the clock for transmitter */
" P0 Z8 Y7 k2 z. O$ O1 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 [( u2 y, M' S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ i! i3 f) ^2 K' v+ D* R* Z5 E3 ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- i$ j! G) h, j' r" H0x00, 0xFF);
) c4 K6 Y# D& l( u) }; w& e8 Y2 C# U3 F ]
/* Enable synchronization of RX and TX sections */ - H" z z" N9 B7 m& j8 n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 @ R8 n; J, i: H# Z8 f7 PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; n, e9 P" h% K1 Z2 N3 G! R7 z/ U0 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. r9 J4 E9 p! l5 U" F** Set the serializers, Currently only one serializer is set as
2 ^+ F9 f; |% k7 F** transmitter and one serializer as receiver.
. T: N9 o9 ?/ H+ K# X" g/ O*/
9 Z& {5 L% V( o7 L( ^3 \) BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* h- G5 D- D' u) F6 k u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 a4 P) [* n$ k$ U5 V* d** Configure the McASP pins
8 d0 @8 P; x* ?5 A** Input - Frame Sync, Clock and Serializer Rx% F8 o, t- o$ I+ W1 C+ a u
** Output - Serializer Tx is connected to the input of the codec
0 k( l; a7 x P*/ ~- }* v; x1 h6 v$ ~1 m v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# m5 v% y7 A" E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! n* z; c& q( \. S; jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# a- {% p* Q+ c) l- e J9 t| MCASP_PIN_ACLKX
v8 m% p: _* A; u, x| MCASP_PIN_AHCLKX5 {. z9 p2 ?! ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. O1 n+ V2 O& K$ ?/ e8 \4 Z+ w% tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 @1 ^8 ~0 I+ K1 X. u$ o| MCASP_TX_CLKFAIL
* y* V2 h2 \" V( I4 { a' A| MCASP_TX_SYNCERROR
, E, [4 G6 U6 @5 ]) U3 U; r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - L8 i' p9 B0 A( N+ w
| MCASP_RX_CLKFAIL& h8 P$ q# G# G
| MCASP_RX_SYNCERROR " }8 b! L$ H7 z! S: }
| MCASP_RX_OVERRUN);
4 p, t% a8 r+ o( v} static void I2SDataTxRxActivate(void)
$ s' z C. d- D6 h& D8 B8 O/ P% Z' C{
; ]$ m+ x) E1 U. [/* Start the clocks */0 }/ V5 A5 \7 a1 L6 D$ Q0 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- [2 w* k) C9 J8 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 m5 f/ j. E* I1 L7 e ~5 w4 s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. F; K/ z2 l. M5 g. K) {
EDMA3_TRIG_MODE_EVENT);) U5 Y1 H1 m: I% h* R3 ^3 c6 G7 L# S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. Q- q: q+ l qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" t" w: T5 u# O6 JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# P* y o) J6 g7 l% n( w" {% OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: j0 T" z* P2 m7 i/ `+ `/ w$ p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" c/ P; L' B) C9 L4 h J5 ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 [% C3 x6 K& B \8 m* k2 zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 i5 W" t( K2 u4 r
}
! J) [, i Z: Y8 h+ |( |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) @8 D. ` i: Z4 j9 x0 D |