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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% l" |- [$ S% Z' f( Q' s- q9 Zinput mcasp_ahclkx,
: @ z/ M4 H& L6 y" `1 e, dinput mcasp_aclkx,: A! ^5 {) C6 I
input axr0,
$ @: e+ X2 z1 Y9 r4 W1 y$ i+ d3 b3 Y6 w9 L. O) m _, l
output mcasp_afsr,
' }, W4 p5 q3 K T2 \7 x! woutput mcasp_ahclkr,
# ]% [7 h6 }3 I8 g7 ooutput mcasp_aclkr,
1 B; Q3 H& L" o1 {0 Y# }output axr1,
" c; b/ D: x6 l& |$ N assign mcasp_afsr = mcasp_afsx;8 L% C* C$ k( T+ N0 h7 _, D
assign mcasp_aclkr = mcasp_aclkx;" p3 f# u" s- N
assign mcasp_ahclkr = mcasp_ahclkx;" k5 p: a# ^5 G* m" F
assign axr1 = axr0;
* z& N( q5 ^2 d% n# E; z, `' x8 `
9 T7 X3 Z0 l4 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! z( ]4 G7 t* K8 k# Y! Y/ M2 i8 cstatic void McASPI2SConfigure(void)# r3 E- x1 G% }3 b" \) O) @' f2 O
{' Z: G( o) U, w6 H- c' z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! T: f: R4 O, q8 ]4 b9 ~& k& ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- d# n$ L0 s. D- {8 B3 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* @: e8 i$ ^; L. a1 m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 J6 V8 p/ r( FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& W% _0 U% N. G! P" t5 l/ X
MCASP_RX_MODE_DMA);( M! u+ {4 a& c' q' S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 s, i! k( x% }. G# v H2 p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ k, ?2 R I- N1 j5 @* k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: i* c* N( g$ a+ [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ l: u4 U+ R3 m4 u4 ?, T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 R# B* S7 b2 x% X+ b2 B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 Y4 \0 {$ c. g; x, j& w, {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 D; S6 D! ^8 ]* }, ]6 p0 A+ v/ }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - ^. M5 `- K& w9 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 C2 n3 Y0 {6 k6 C% {
0x00, 0xFF); /* configure the clock for transmitter */
K& P A5 Y0 f# [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 K# T6 K! O5 K$ L) F. l; z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); v9 e/ r( H- {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 `: q% ~& }6 ]; p
0x00, 0xFF);$ |& K. u: G5 S
2 |7 T9 O# o' X' U P4 u
/* Enable synchronization of RX and TX sections */ % y* t F. ^6 h4 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) T+ d! l' o# l% K1 z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! T3 U/ N' v9 n4 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- [0 M9 v$ \/ B1 W6 p** Set the serializers, Currently only one serializer is set as
: f J2 A0 ?' ~6 |, D** transmitter and one serializer as receiver.
" E$ J( u. n8 ]3 [1 D*/
( i% x+ C, h9 |0 s$ U6 ~7 P0 c+ CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( D* h4 S$ b8 f. R( h) _2 l; I' A- M+ }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: t' K! t5 D0 i4 H& W) [: _# G6 F8 u** Configure the McASP pins
4 w( v2 A+ w$ I3 b3 F1 C** Input - Frame Sync, Clock and Serializer Rx) K7 s |/ }, h
** Output - Serializer Tx is connected to the input of the codec
8 m7 S3 T) r2 S4 p1 i4 F*/4 c4 C" y: m6 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
|2 ^5 H- \/ b% k" M$ K9 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 a& \ x1 [/ i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
L% L# o- P. E| MCASP_PIN_ACLKX3 q& f }2 f9 y( ^
| MCASP_PIN_AHCLKX
; C- ?4 @5 A z2 I" u8 H( J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 v+ `& \5 U1 i0 `* m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ U+ a" Y+ e- Z- H% K( F| MCASP_TX_CLKFAIL ! k3 A5 D* O1 Y- _/ @
| MCASP_TX_SYNCERROR5 d# A- |: X6 W- X6 l: [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 \. k% H( N0 y8 e9 q9 ~
| MCASP_RX_CLKFAIL
" ]& D6 p1 B$ ?5 Q| MCASP_RX_SYNCERROR , i% A [; e$ c8 U5 g) ^! L8 }
| MCASP_RX_OVERRUN);3 \! K( \6 N0 ^& r: C/ A
} static void I2SDataTxRxActivate(void)
I% Z1 Q2 X- N8 P. Q, `& {{
& B: H% x4 ~# @; w; A6 @$ F/* Start the clocks */
& e+ M0 V( P8 A1 C/ vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 Y/ _, n) p# m# b/ k9 [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# r: ~" _, `; |9 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ B( V. Y w& t6 l
EDMA3_TRIG_MODE_EVENT);! {, g/ C: D! Z% r+ ^# ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # U4 c4 O6 y$ S- C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, T' {. q, y7 x7 d7 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. ~! d4 F i. g. p. V# z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, \0 \* Q0 k4 a1 l C9 c0 `6 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 w! ~5 c+ j6 D. `; P& W& z+ jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 I. @; W& P; X' z* B5 R) F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 A; Y, P" W7 Q: K8 u- A. r' L9 v} , T {% _' l9 q* X2 p2 j. S# I! a3 Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; s7 D7 i4 \" s
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