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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ R6 ~) ]( W9 h; I% A0 S; E! }& yinput mcasp_ahclkx,
+ I% i3 a7 W0 U6 j* ~input mcasp_aclkx,1 m) P) y7 X6 `$ Y
input axr0,
, v: L1 ^9 f) G' s1 U
# Y, h" O7 ]3 ~/ Youtput mcasp_afsr,' H* d/ s8 u" ^% Z$ n1 u. k
output mcasp_ahclkr,* N5 ~7 T0 O% \2 M, z
output mcasp_aclkr,, G8 a, C0 `: Q0 g b$ y
output axr1,
. k" a" `/ l, L! J assign mcasp_afsr = mcasp_afsx;
6 D8 ?: i+ @. L- Y G7 K2 Eassign mcasp_aclkr = mcasp_aclkx;+ n3 s7 e2 R+ N# m( Z$ r
assign mcasp_ahclkr = mcasp_ahclkx;
$ P9 H" y9 E9 X$ zassign axr1 = axr0;
3 X2 j: _9 [7 j
3 x# S) s q9 b/ `/ u/ ]& a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% A( S& z p7 n+ t: C' Q cstatic void McASPI2SConfigure(void)* G2 @' g1 r, f$ P6 k9 h1 I
{
4 B! p" T1 w S5 J5 [, ]( xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# N# @8 `# ~9 C- c* b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 J' n- r5 ^! U! @. {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; t! |+ r, ^ O5 T" i; Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) S& V8 ^- a% q$ ]( S [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. g$ t, \ d! J, b6 h* E, CMCASP_RX_MODE_DMA);
0 n* f9 Y1 G1 G' BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ \: y, K0 H, I. U) Q- f9 }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* q0 Y' a+ d& }- X% a/ l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% Y/ X3 E4 n+ R) [1 b& Y9 A3 iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 p% H. J; Q4 a; N2 _( x8 K( r: k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 w/ L* ]9 r- H: C) \" u9 r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( t: j: R! d, [! ~" O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 h" A- Y$ l; g; b0 s* L4 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, _0 z3 N& m5 O sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- ]8 K4 R: A9 A! b1 ~5 m: u: `0x00, 0xFF); /* configure the clock for transmitter */
- [: p- d0 h, _ ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 f3 E( _) q/ Z7 c( [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 k7 Q, c8 L2 j; Z& K" R, Q) oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 s8 `/ R! B/ N, f) m: k# [0x00, 0xFF);
% h. K) J! X+ f- g9 \4 h/ C" A
% v# N! e1 c% _/ ~, P/* Enable synchronization of RX and TX sections */ % K4 S5 M; s, ]/ X+ M/ j5 a, s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 c! L7 Q- u; sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ z* P4 H5 r- V6 ~7 A6 ^" @9 n& HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& e/ r+ i" V* K/ s& a8 i. ?& x** Set the serializers, Currently only one serializer is set as$ g' Z8 s& {! y* a( P5 v
** transmitter and one serializer as receiver.! |% E) _$ |7 @2 a1 c; o
*/1 S/ U1 O7 s. X: y: i1 c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ j! [) ]7 t1 a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# c8 t6 O% z/ W3 j7 i0 X** Configure the McASP pins 7 @, m, M) N1 ?% _1 i% k
** Input - Frame Sync, Clock and Serializer Rx
/ J7 v) u7 W% p" F** Output - Serializer Tx is connected to the input of the codec
! r) U7 U& {( b8 f8 ^/ ?9 k0 e*/2 O( T, _0 j- ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 C. J3 W2 H' @: W7 ~) @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& }3 @6 M, h0 T/ G$ j0 m$ f5 R5 v* n* {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; ~) t3 q; e& u! e4 T| MCASP_PIN_ACLKX4 M- {- Q* w% w. |7 l
| MCASP_PIN_AHCLKX- E' N- V& @7 f7 G: B2 ~1 H6 ?8 Q, `9 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- M* ?: m; b7 o HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / O* w* i) @! g8 D# V* j
| MCASP_TX_CLKFAIL 5 ?% W1 g( J0 h% b0 S
| MCASP_TX_SYNCERROR
; I, F0 Q; o' a4 U q" @+ F4 l$ r: e, j' ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 r$ s, U! A. e" T% J
| MCASP_RX_CLKFAIL* A% x& ?/ ?+ a" f9 T! j
| MCASP_RX_SYNCERROR : N2 v( v! i3 ]
| MCASP_RX_OVERRUN);( L+ R$ ^ s C
} static void I2SDataTxRxActivate(void): b+ T/ f( i3 S" ~- A( ~( T/ n; d
{
+ Q5 B5 I/ y% @9 y1 C9 q9 u/* Start the clocks */# [8 H1 @& D; K# b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" f# C3 B( ?0 P$ l* g6 N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- | w! j5 q/ C6 p, U/ JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- J% s8 x8 ~; x# KEDMA3_TRIG_MODE_EVENT);, \1 B E8 |( g9 M, m: o) d' a# N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : [0 T# U; @3 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 |' R0 {5 `% t, G# d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( g6 u4 q" u$ |% t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 w2 B- g* s. v& N. t9 N0 n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' }0 v2 K* c# x, |8 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 E( s d5 d9 t" c9 U2 W, C# U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ S0 p- t7 G# a2 [# E7 |& J} ; J0 ?% D4 a q% S$ G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 w# H& T4 S/ L) }$ `, y3 r
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