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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 A7 N$ C# Z" U4 C$ w# finput mcasp_ahclkx,
! S) s9 Z$ X* E; _" q& Yinput mcasp_aclkx,1 z; u0 B8 E% ?' z
input axr0,
. h8 Z, A5 U2 p% V' B# G0 J6 w- G- ^( z3 X
output mcasp_afsr,
# O% B% w2 q2 H/ Z9 G$ f3 Routput mcasp_ahclkr,
8 @& E4 p9 H0 r' t: \" ^output mcasp_aclkr,
' ~2 u+ \' ~' b; v3 t. Voutput axr1,, _. h0 J5 k% k; C5 D0 c1 j+ D
assign mcasp_afsr = mcasp_afsx;& w' M( L! m8 o; z/ k
assign mcasp_aclkr = mcasp_aclkx;/ E5 @( z$ O, X7 i
assign mcasp_ahclkr = mcasp_ahclkx;6 ~' H* f* S0 a+ B% j$ c0 F
assign axr1 = axr0;
`# W5 q' _) R, f
( }3 e( j" `' _: I' k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 M0 b/ J8 S( N( {' m' lstatic void McASPI2SConfigure(void)
) n. o4 P1 @( J0 t1 k{
]. ^# F/ Y& f1 M, nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) b3 {3 E/ m5 b2 [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 `6 c* Z3 r# f: `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# o! {. Y9 m$ T& a( g9 ^2 iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' d4 t; O2 k/ S2 ]" l. n. i" v7 R6 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ^8 |7 r" ~7 Y; hMCASP_RX_MODE_DMA);2 z9 s9 B; Q% k* n o6 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 W# w0 Q0 N: O; H0 n. eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ p9 ?: X$ _; y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ ]# l3 x* J& e, N. Y# |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 v/ ]4 _% ~% F! T0 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 T: E( Y+ A9 h; C9 J6 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 r3 t8 E8 v | I: R* mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! ]2 L& M' M/ u& ~5 L/ F4 D/ DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 ~2 Q* \0 U9 L1 e0 v4 j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 w" |9 U" J4 C, V
0x00, 0xFF); /* configure the clock for transmitter */; Z+ `2 R; S% w1 L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# g9 U0 g* |- Q# }' pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 z3 s2 ^8 K8 G' m/ OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" l8 b) U9 {' S6 M; N) z0x00, 0xFF);; b. l, H+ I$ {2 _5 m5 |
% {& C6 m7 _0 X' R; n/* Enable synchronization of RX and TX sections */
% s! r0 f) {9 U& S* Q5 EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ l/ o% n. W2 p! P) F# `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ s/ c( w) Y# x9 ~3 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' m9 g& D6 ~" S4 l( q S
** Set the serializers, Currently only one serializer is set as2 K; R1 j1 R0 z
** transmitter and one serializer as receiver.6 X" h) L2 T" o% E0 i$ \
*/4 h3 P* c+ X' _& y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* V9 g9 V" v+ t1 u; X& V: D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 S) ?( g9 B0 m& B** Configure the McASP pins 8 M1 G3 v# q3 |1 s: A0 h# _1 E& k
** Input - Frame Sync, Clock and Serializer Rx1 w7 z) e# @3 b8 ~4 W( v
** Output - Serializer Tx is connected to the input of the codec
* R; F% m. C3 B8 i" i+ K+ n' F*/* d0 G$ }; P+ K" p' a1 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% m9 ~& _. n8 }% `0 ?. M6 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, q2 `7 d! E1 p& A8 \, N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 D+ N& B0 j- e! F A| MCASP_PIN_ACLKX
+ {5 H Z" ]# c* X| MCASP_PIN_AHCLKX
5 R$ L4 z0 Q4 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 t3 Y! E$ D8 S6 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) w0 u7 k( ^2 u% p1 o
| MCASP_TX_CLKFAIL
0 v7 @, i# a4 d* }0 D( {| MCASP_TX_SYNCERROR# f" c7 v$ k" P, F! J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - W- _/ X& f3 S
| MCASP_RX_CLKFAIL
6 d( L8 L/ I( E2 d' m' R$ x| MCASP_RX_SYNCERROR $ {+ F# j6 h! Q! {6 i3 H# C$ ~- ]
| MCASP_RX_OVERRUN);7 e' y0 D4 k# l! ~/ b# M& F
} static void I2SDataTxRxActivate(void)# [/ I+ J, {- q @8 \! X* x! e
{+ |% R5 M: G% s2 G& U
/* Start the clocks */- P+ x6 ~7 X$ h* z8 O. c5 V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( C( L2 k: Y+ s( k3 H- u* A2 j/ }5 \. RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; t# z- q V( b( h3 {: r$ D+ y; d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ ~$ c4 `% l: ?0 {$ \, ^4 mEDMA3_TRIG_MODE_EVENT);
# v! Q4 V- c% \3 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! C, x: T; U! H3 Q; uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% t. F: C# O% r6 x# O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: Y4 m2 n1 M: XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ s) f$ B j$ @* I, m" t- n( h8 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 A. d5 ]2 \+ h( q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- Y3 o ]- B+ H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 K# }2 N8 c$ `2 \# s
} / u4 e" V/ _2 P0 z, I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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