MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
) l5 V3 \2 o( B# K3 j8 ~1 _- M0 binput mcasp_ahclkx,
input mcasp_aclkx,
0 ?0 K: X. O) C# V1 sinput axr0,
1 M% p: d5 Y" n: I$ {$ m/ e  _
output mcasp_afsr,
output mcasp_ahclkr,
5 D7 h! U' ?* H  t, Y/ V4 R) Eoutput mcasp_aclkr,
/ G, v% d& w9 H" u6 R! zoutput axr1,

assign mcasp_afsr = mcasp_afsx;
! I& V6 K( R: u* p  o3 i9 yassign mcasp_aclkr = mcasp_aclkx;
- p1 r7 t2 z2 Z4 [assign mcasp_ahclkr = mcasp_ahclkx;
2 T0 E2 ?2 U; Passign axr1 = axr0;

6 [+ P# o( ]7 d- H: T+ e" z
3 ~5 E/ \( }/ [( c7 C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- A' ], h3 ?9 r3 M! I7 |- b1 e+ uMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
, S$ C0 \1 h2 J8 M. T( x- b& _( JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
) ~8 E. U& P7 D0 b( ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# {; ^" W+ q# C6 s3 kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 O9 ?4 o) q8 C# X, c8 g; QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ B" Z4 U1 ?% d: {* l" {/ j' zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
4 y# E7 i2 e6 U7 C( QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) q' q4 w4 w! x9 W- kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 {) i& }( y2 I* iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! g' \! w, B/ N% c8 A  ~# k* ?* l0x00, 0xFF);

/* configure the clock for transmitter */
2 q; w8 R7 o* OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ i1 _6 d) V% c0x00, 0xFF);

( P1 y+ c  Y  U7 e% O/* Enable synchronization of RX and TX sections */
) r- Y' k) s0 @8 W% }; ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 y: J; [: U6 i/ W$ j  _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
  e# I0 e% K1 r# N7 F% F9 Y" u/ O** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
. Y, m, d; d, e7 S8 t; QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
# I6 B0 l( t: R& B2 |- s9 c0 MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 E% T' I0 B+ oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ ~- `8 P- k+ Q$ y| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
- o* n! p1 H: G$ o. ~+ _' S; ?6 h| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 q% a2 ]  p5 f| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
; Z& x% K8 V( h| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
  o( o! Z2 j. e{
/* Start the clocks */
1 b1 l8 h) U, ]1 _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 ^; C7 @( n7 P; H8 U% |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
3 M# s  b! H9 c3 ^& I/ j/ k: YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- a0 l' b6 \) {* IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' L3 F3 }/ [& G4 b2 TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
0 w! B% p' p6 V5 t* k$ u; v0 t0 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 S1 ^8 Z: q4 K1 N5 t7 D. yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* p0 d& G4 a1 s1 |' f9 U$ b}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.