我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 ^* ^* L+ T2 U7 n
input mcasp_ahclkx,
+ ~$ t4 h8 S3 s5 J( Oinput mcasp_aclkx,
4 j# _4 j# ?+ }7 v7 O4 O) V/ jinput axr0,9 y, o) A% @! V, K
4 m) C% W! k) V9 I- k9 B: ^2 D3 `output mcasp_afsr,
0 v% ~6 ?0 s# p4 x; b+ Z! ioutput mcasp_ahclkr,
b1 e ^4 S0 B, V+ d% |# H6 R" |output mcasp_aclkr,0 U: _9 v7 \, a$ {' T& G' e' a
output axr1,# _1 j; a2 ]7 _+ e3 N
assign mcasp_afsr = mcasp_afsx;
8 y! B0 J Y/ qassign mcasp_aclkr = mcasp_aclkx;( `# b* O- j% b. d; _- C3 D' }
assign mcasp_ahclkr = mcasp_ahclkx;* U v; S. X, v
assign axr1 = axr0; % L* a: _5 ?5 ~
0 M& J; G6 \5 U; A+ P" \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ n' [1 [/ w! ?static void McASPI2SConfigure(void)' A9 [" k* C6 _
{
6 ?# V( ]( r1 X3 p+ U' y. BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) h+ [" k1 W4 n0 j% H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, s0 X. r( b6 f, J" @& J# l9 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& [" f3 P! t# q/ r% F" k" z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ }" d3 k$ H: \% x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# q2 H% R4 X- V8 \; Q
MCASP_RX_MODE_DMA);
/ Y# D9 T7 Y& c3 e( yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; q" F! A. u+ o- Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# X' A. p( ~1 F- J" P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) X8 M3 A: ^: A$ \4 n' D% }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 S+ k4 u* c5 i, h( F. I) [$ c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : Z+ r9 S* B' _2 T) v: f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) [2 H4 f( g3 Q/ A& c$ r- hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 Y, n0 ?3 c. b+ sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 Z8 t/ ?: j/ E) {, f Z! m: g) t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 f" ^( W8 s/ Z; }2 E+ q, b0x00, 0xFF); /* configure the clock for transmitter */
- L7 `# i( @( l% b0 k/ h/ A9 I# rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" V9 Q" ]. C5 O2 ^; {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / n! \5 m# t. _6 Q& z. J/ _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% j6 {/ _* d2 l$ ]7 |) M! v0x00, 0xFF);) w# j7 j7 S. Y+ X
) l: J O) F. e# i. A a
/* Enable synchronization of RX and TX sections */
# @8 e% [* {0 e( r ?; DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; u2 r2 Z0 Y; ?4 u9 i% H0 ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; i7 B9 ?6 p# k, A6 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 g$ e7 u( k1 x0 i. L** Set the serializers, Currently only one serializer is set as
" Z* A2 E" O7 N8 T' ^6 b* O** transmitter and one serializer as receiver.5 u$ R; s+ K6 d5 \" P4 J, ^
*/& i6 Y0 V1 b0 g& z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& j+ k( ?3 r9 f. N T" p& x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ Y- e* c! D, b1 }** Configure the McASP pins
7 Q, {( k. v! B, u** Input - Frame Sync, Clock and Serializer Rx
6 c4 c: N0 i( T** Output - Serializer Tx is connected to the input of the codec # O% D# [' k2 _! b8 ]2 t
*/. n: L" G: T! o, B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ o3 h# r" V' d+ R# x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" f2 e/ x( F, |# |" E9 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, {+ P' U0 Y. g- l0 L) U
| MCASP_PIN_ACLKX) E/ [7 P2 L" H6 u0 V- ^' g
| MCASP_PIN_AHCLKX7 W: `8 n- v" C. R6 ~- M, S) o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; S' F6 \. x( C6 @4 o: D4 f( r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # V- C8 [& C+ i6 e+ e
| MCASP_TX_CLKFAIL - j7 l) S/ k2 m1 E4 ?/ m" p2 u; M
| MCASP_TX_SYNCERROR% I/ E3 Y3 U" j( k8 r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ y1 E9 j0 k8 w: }4 f2 p$ N| MCASP_RX_CLKFAIL- {/ Z+ O& T* n$ Z* k0 x
| MCASP_RX_SYNCERROR 4 I( ~& I; Z3 U
| MCASP_RX_OVERRUN);
8 m0 x$ o/ C q! ], a} static void I2SDataTxRxActivate(void)2 S3 I) J; c" d: x D% p; X5 w7 Z7 J6 p
{
* J4 ^$ } J) ?- e/* Start the clocks */$ t" M3 f6 `; C/ ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) i& o( C8 ^# c2 O, g; ?: S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; W* I9 L9 G: `' b$ X/ F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: f4 G7 G+ g2 J) e) cEDMA3_TRIG_MODE_EVENT);& s1 j0 k1 h- o. C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; E/ Z" f: L, v& M! U& Y8 t* JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 I% z6 y* |- g4 a m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; [ W( g9 ^+ Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: \, l8 W, Q; B' _8 `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ d+ @0 N) J8 ]3 D- a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* [& j" {6 y. q- q. z- M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 ~- g' ?7 ^- P: r& q! ~% K}
5 d" v* c1 S) a; S1 O. \' X% V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 \1 D$ H9 t# X' C/ i! ], y. z" e ]/ r
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