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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, u* ~1 N. {- c2 z/ u, u& Linput mcasp_ahclkx,
9 j* H9 B, E4 @. T* ?input mcasp_aclkx,
0 p2 L9 r" N* [4 Iinput axr0,- g3 ?7 V# {; G4 ^$ ^$ S* X! Q
4 D6 z1 j7 E& c1 {' o: e7 Eoutput mcasp_afsr,( ~* b+ o, ?" Z; ^$ ~3 `
output mcasp_ahclkr,, ~$ q Q+ e8 }+ V% T' ^9 A. M
output mcasp_aclkr,+ |$ E. v( M4 D
output axr1,
`6 c, d! @! k( F! }3 }, d assign mcasp_afsr = mcasp_afsx;
; {4 f% }; X( y! A4 O' R- Gassign mcasp_aclkr = mcasp_aclkx;
' `1 ?9 D4 f/ ]( Jassign mcasp_ahclkr = mcasp_ahclkx;
/ e- H- z4 ?* D- w, W% fassign axr1 = axr0; 6 c' W6 S- A2 P: d3 k7 \
. G k, Y" P. @2 q4 g/ z, P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) p8 a) o0 j) O2 ?7 B2 jstatic void McASPI2SConfigure(void)
- O }( n1 ]8 Z" f g. K3 A{
8 a- }6 S5 E7 x y* m5 Z" s1 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 W5 a. ]! H0 v9 l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& F. ?! X2 W+ o& F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 s& J6 T, ^; T5 G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! s0 E" @# f; s. \) X! VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 v: E! d$ v" l
MCASP_RX_MODE_DMA);* z$ q& X% v6 {7 Q3 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, P. T. P" x% t. B2 {# L0 d" M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& e# @: |+ }/ D6 Y3 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( U! A3 W4 Q0 Q# d# ~$ c0 c6 ^! [# O5 _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 R. B! ^0 B/ I) N$ u0 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" ~+ q! K/ @! C. h# b7 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) o; G0 @* |, j( W8 E/ h. J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% Q; V, i% H3 G7 w1 `2 _; u( ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 T4 i% }/ Y) }* o* `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 y& F: h9 Y* J* B' r. z3 O9 i
0x00, 0xFF); /* configure the clock for transmitter */
; z) l2 H2 N2 ]8 ]! fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" ~5 V( r& W, I: L, ?3 V- kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) Q: f: `4 H, B4 d, p$ RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 j6 Y$ m1 R; Z2 L" [0x00, 0xFF);
8 E% \% Y! H! l# Q9 p* J6 Z* t+ t% V6 E; H0 M' n3 x' K
/* Enable synchronization of RX and TX sections */ 6 a9 `' l8 l) M, N" W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 W6 T0 f& Z' O9 V* b, z, u6 f& N# M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( u6 G% g7 ]: w2 z* g4 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ }, h% K0 R/ E- }9 ?: b9 X* V
** Set the serializers, Currently only one serializer is set as; X$ S2 h/ r$ }9 e3 M6 ]' ?( j
** transmitter and one serializer as receiver.
# h6 h6 c6 R! w# T*/% O% b V0 y0 Y* x# k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 _0 ^! P [ Z4 R+ ^, c0 n9 Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# w U6 K1 e( ^ h; r7 w' \** Configure the McASP pins
, ?2 J& n$ ]2 H6 U( R O** Input - Frame Sync, Clock and Serializer Rx- |9 g w' N3 X5 }& @( q
** Output - Serializer Tx is connected to the input of the codec ) @, y0 |/ n3 u6 }. b& P. w
*/
9 x% o+ q3 j0 t# X# WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 {* u6 M% t9 Y. T! K+ W" q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! F' t, d; O6 @1 Q7 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
R& B* y! w6 T9 s| MCASP_PIN_ACLKX
0 l9 q# i% C9 ]2 j| MCASP_PIN_AHCLKX/ x; T; N; r, `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. }' L; e7 O$ w7 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: a$ @' B5 Y2 @( s- ^ A| MCASP_TX_CLKFAIL
5 a3 f4 j" [- W E7 `| MCASP_TX_SYNCERROR
- |- o+ H$ Y) n+ i8 ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 Y9 l% U% O; C& U+ z* A8 N) N
| MCASP_RX_CLKFAIL: X. E) `$ j* A8 v/ X
| MCASP_RX_SYNCERROR
2 K' z* @ c7 P: {: m8 L R- T3 M| MCASP_RX_OVERRUN);% o# i. b, w4 {3 S& \- [7 u
} static void I2SDataTxRxActivate(void)4 y7 G& U. _ J2 o
{
2 g5 T! f$ U9 g* l$ Y5 I5 U/* Start the clocks */: S3 Q- }) S7 w/ L; ~0 D+ N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" I8 u2 i! o B" f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 s3 r) |7 Q, f; p2 g+ MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" m R4 o5 O9 W5 W2 Q5 R+ v" QEDMA3_TRIG_MODE_EVENT);; j l* S' V) b& \& \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 H1 J9 @. |+ Z4 |! ^4 R9 ~, BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; b% a# |4 b! F) `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, E% \) C7 f8 h, C' ~, u+ `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ [ V3 N9 S2 F# B9 X4 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 \# z3 g; M* |5 C3 W4 |" rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 r6 t6 g0 C) Q# |. f$ ?& gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, e5 @# P& p! ^, Y7 [: E
} 2 G/ c1 U1 z3 z/ h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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