MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
% l& v4 O8 r( n+ B" c8 U* H; Hinput mcasp_ahclkx,
9 D; S( O. n# {: J# _% @input mcasp_aclkx,
input axr0,

output mcasp_afsr,
5 X0 X9 B/ m) x* K: b1 |output mcasp_ahclkr,
3 x" O) \. R& ~$ N! M% X0 _2 |output mcasp_aclkr,
output axr1,
. r9 p+ J3 ^( a0 n& H. \  a, t

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
& K, q; p! [7 dassign axr1 = axr0;

! Z1 X! T, n6 c: Q3 V( T

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
# C' z$ b2 Q+ @* p& }{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 f0 N: z2 r. @. f8 E8 d/ ?McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
) h, B+ \/ [) H+ u- S/ c, ~/ UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( J) y9 P0 W& D# M# KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
4 R' T8 I* \5 X) ?2 C/ OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 R, A" Z, @! qMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 N. t7 ?% o6 \# w, j* X+ x% aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# F" J( F8 X7 L0 ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 s2 A6 v- z. v. m4 V' ~- N8 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
1 Q8 D( h# l; d% N! C' IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 g; R& P1 j: W% c6 K; D% C+ x+ CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ m0 ~8 H# G* K" d; x* a# ]0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 |7 E2 ?. N/ Z" V( lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
" L2 ~9 M, A" E3 P) }1 |4 B4 t** Configure the McASP pins
6 H' ?2 j/ }! Y* \# v** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
2 r3 A3 k4 N& R*/
4 s! |6 O, b) l. v9 [& LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
% x* A2 A6 j$ e7 N- g: h% Z  d| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- O- ^% m3 v( f) R; U5 s! W| MCASP_TX_CLKFAIL
" t- l5 w' U9 A/ x9 b/ Q| MCASP_TX_SYNCERROR
: ?  @  M) Y% P- v6 z7 A% l, E| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
4 Q! B( C% L' ~2 f  U| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
( r/ J( Y8 r1 s/ s{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 q1 w. V  Z. i  N. [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
- L3 H2 ^8 a) Y5 Z9 W6 g/ s1 x) P/ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 S5 C- d2 |2 H' ^) C% H9 QEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
0 g: ]: Q( C7 j) nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
- ^5 ~; B6 d+ M- I; J% Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
% u: e+ s1 f0 o/ g  c7 C* \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! p' e+ \" Z: h- Q+ L. `( J/ PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 F0 m. K5 ^0 h  v0 G0 b6 y$ k}

7 b6 m4 i7 K1 `9 `# w& d6 O

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.