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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ f4 o" s; g. f# X8 E5 H3 @+ q- h
input mcasp_ahclkx,
`1 H! W' m0 l% C0 R! Uinput mcasp_aclkx,, F @1 w' Q0 w' T6 y( {3 s# z
input axr0,
1 {* }5 f. r/ b+ G+ a4 |9 k" H4 ~- |) K# V$ v9 N
output mcasp_afsr,
( f( ~ \+ {5 H: koutput mcasp_ahclkr,% n0 H9 {$ @* H0 t3 h! i
output mcasp_aclkr,2 j' z3 n' F+ P) p' h8 J2 |2 j. b
output axr1,
% i) T" L' u) c! [$ z$ b7 l assign mcasp_afsr = mcasp_afsx;
; a/ p' L+ {% S) Z; z+ [assign mcasp_aclkr = mcasp_aclkx;' I! b: R; _ L& |0 C
assign mcasp_ahclkr = mcasp_ahclkx;
/ r5 X/ O" a0 X1 Tassign axr1 = axr0; 8 {7 f5 s1 A0 V) ?% u) i
9 B( I) Z8 H. l2 N$ j' v6 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; K& l7 t" y A' A: R* C+ Mstatic void McASPI2SConfigure(void)3 L" v8 S6 s8 i9 b% L8 f" U
{! R# r2 S# p! f1 m+ c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 k- ?( i1 n3 Z" K/ a( Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ Y( v( M# c5 [& OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- L/ V) x4 f6 Z* q9 l6 m7 y* yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* ^- H' J: Q% F. Y' s+ s3 `3 R. IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 P- ]$ @: g/ x' S6 k# O0 DMCASP_RX_MODE_DMA);% g- }$ W% b5 e3 p) _% w7 x& B' }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 Y. E. q0 G) V2 Z& Z) aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 l% T% Q# ^" h; J! lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " J' h8 `$ C @' o* a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, d" Z, d0 O' k' E ~4 d3 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, k4 B0 s& H) t9 dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// |- Z5 n5 L6 P& n9 P. N: [! j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% X7 |0 a" O2 p. T8 a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 q5 ~1 ?: W; c. R& y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, M5 m* {1 V& H) P/ d6 H1 y5 `$ y, e
0x00, 0xFF); /* configure the clock for transmitter */) p5 |* ?4 r0 D; d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* Q# h6 {" d; ]2 B, `5 W) hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 X' P; \0 {/ ^+ j! L" K" jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; l5 y7 C7 x Q7 q0x00, 0xFF);& \! `/ N Z# g" k9 a0 g7 w7 M$ ]! ?
: U( Q# y! o B, f# w3 d, Z/* Enable synchronization of RX and TX sections */ & P5 K4 R0 T/ l, E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 W9 ?0 b9 G5 O+ nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& v! G3 d. W2 n# H: C& t! q, o- E! B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 e* t: V# y$ [+ c; G** Set the serializers, Currently only one serializer is set as$ q# _8 b9 m6 n& b' n: `
** transmitter and one serializer as receiver.) v4 L3 x E1 x' u. B3 C* j3 h
*/* V1 V& ^( t; M \/ ]; C# f9 J3 f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. X7 [0 |3 b2 i& M+ mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 ]5 {. t7 n$ q8 W& X O** Configure the McASP pins ( N# i, k9 M8 x4 N, y# w' k& J
** Input - Frame Sync, Clock and Serializer Rx
8 d9 R! y6 B3 m$ h** Output - Serializer Tx is connected to the input of the codec . W- D/ @5 B% G8 a. I
*/5 ~( p. P2 o) I) d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ G4 U) l# `- g8 A8 ]9 o1 @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- k& E, a' t: ?2 ^$ N X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 r" G- [/ Z9 \
| MCASP_PIN_ACLKX6 `. y! F8 }8 `
| MCASP_PIN_AHCLKX* n& j9 a: _( u5 V, G W W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 t7 U. {* }+ }6 w2 [1 L# l- b5 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 W* \+ n) a2 C) }8 M2 \| MCASP_TX_CLKFAIL
8 l2 p: b2 g8 k$ `" R| MCASP_TX_SYNCERROR3 [0 s+ h# B2 ]' H$ d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* f+ w! L7 U" \0 V| MCASP_RX_CLKFAIL
P4 B/ E2 M v( n| MCASP_RX_SYNCERROR 8 S1 z" a1 U, j* P* J5 G
| MCASP_RX_OVERRUN);$ O1 T8 [6 D/ c+ T8 g
} static void I2SDataTxRxActivate(void)
! I2 c+ V l% e5 ^0 K{/ C" e7 @" ^, s3 E$ K$ d5 b
/* Start the clocks */
! T" i7 D- A* z8 i' q! \$ pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% W) t2 P+ d2 ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% H$ W+ x3 f2 @* j, U$ D% h6 a* l/ cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 G$ |' w( t7 D3 z8 M& [# W& d( SEDMA3_TRIG_MODE_EVENT);2 _" T( [1 b& j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% t* _/ x+ A5 t( c4 |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 s1 Y( O y: o; ~8 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 a! e \& b; L: K; J3 v( g0 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. `" P* U( l9 n! p' n5 v: q1 U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. w' \& y( N8 U3 ?) ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, C, l8 t0 u( O8 HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' n u1 d0 D" z6 H1 b* c
}
9 Q4 x+ o( P; [; s" [' R0 y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 `" _8 V, L' j6 W! I3 K! E+ R
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