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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) H8 R1 `; q3 Dinput mcasp_ahclkx,# I7 J7 `( D( @8 U, j: `9 ^
input mcasp_aclkx,
0 C4 v! F5 ^* y6 Z; Binput axr0,
6 c3 H" p. T% M; ^ } r1 J8 ~2 ]7 `3 }2 e) ]
output mcasp_afsr,/ c3 B9 R. P7 e" x+ }5 U% y
output mcasp_ahclkr,
! L+ F" {. o2 \2 S" ]7 v; x9 H1 Zoutput mcasp_aclkr,
9 \$ p' W/ [: D- ]3 joutput axr1,
9 ^3 e: _- r' `2 ~1 E% } @ assign mcasp_afsr = mcasp_afsx;" Y4 _& x. Q! F% B- n
assign mcasp_aclkr = mcasp_aclkx;
@% W1 H* T5 O# |3 J6 V8 m! eassign mcasp_ahclkr = mcasp_ahclkx;% E4 f# S# K% U- U
assign axr1 = axr0;
! o9 w2 v% ~ O; _8 E% e& U4 ]
2 u7 k( v0 M0 U- }. v/ D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 ~ {6 U! ~& h8 Z; }6 k2 h3 }, I
static void McASPI2SConfigure(void)
" K7 E( M* ?! v& u8 D( f, U/ D# O* p{
" L8 c `) d8 y" MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ _. C1 k4 R6 T }' PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! {* [" m7 i- H9 ]8 |, L; V( j) h5 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* G# b/ n+ e( P' P8 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- v$ J7 e* Z* ?1 P+ \% ~5 U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& `' a/ c& Z$ i
MCASP_RX_MODE_DMA);
" t% _; r+ w: ~# ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 @2 m y2 I6 [3 V/ cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 F: }0 Z: E8 s, Y0 Z4 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( p4 z; t+ k$ \! R' UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 C9 A$ B3 }; D( H# ~3 h, j. K: u. j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' V. U4 t5 ~; AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; g7 t0 f( d, Y' h9 m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
W% I& L y f; w" c3 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 N) | s+ x& U, H2 D$ |" Q6 X# mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' x9 ~" {' s0 h! p: _- I, O, P0x00, 0xFF); /* configure the clock for transmitter */& Z+ D' ?" q' n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 w6 h3 s: O. z' ^" y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # I% s. B$ |5 w: \2 u$ p( ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% l; d" s2 ~) C
0x00, 0xFF);
6 g% _: h3 r) G. e9 K4 W# J2 U4 v9 ]5 f3 Z+ r
/* Enable synchronization of RX and TX sections */
3 i$ O1 @2 Q1 Y" x: {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 F8 X; O, |2 K& W7 w- {& T) h) ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 \& V+ I8 v' m( `8 i, P; ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 [$ e) r; t+ }
** Set the serializers, Currently only one serializer is set as
* n$ ]& t3 I( N+ E** transmitter and one serializer as receiver.
: a& J8 ^5 Z! v( f* Q*/
$ O3 r$ r q' i4 U& K1 D. mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 B" c8 q$ E6 v) |; QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" O8 t/ k1 U' X% o& s! O0 V) e
** Configure the McASP pins 9 A+ e7 @) M6 M }" [! z4 h
** Input - Frame Sync, Clock and Serializer Rx
$ W7 a" }, I! M9 `6 a9 F** Output - Serializer Tx is connected to the input of the codec
$ k( F- J Y" Y7 l, ^9 c e# ?2 X7 ^5 o*/3 K# l& W; K1 c. ?! \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 h3 r0 a( u9 Q z) b. YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: ~3 n$ @4 V0 t/ h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ l; f9 Z4 H! ~| MCASP_PIN_ACLKX
; j5 D% e6 Y0 F( i- ~4 f| MCASP_PIN_AHCLKX
9 t e# ^+ i$ C0 `, S6 j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: U: F$ k5 ~' U1 I6 b7 k2 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' a' b8 i6 n! H: S| MCASP_TX_CLKFAIL ' S" {9 F: i/ T% a0 D f
| MCASP_TX_SYNCERROR
( q3 B( K# f/ k( ^) a; H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 H+ ]3 }' X5 n- y6 G& r
| MCASP_RX_CLKFAIL
7 ?( O$ V) \" R( P* w: s2 Q: u| MCASP_RX_SYNCERROR ) h5 K2 Z8 B( [1 G$ T" k4 [
| MCASP_RX_OVERRUN);. V5 O. i& n9 ^
} static void I2SDataTxRxActivate(void)
) j5 _0 V) M7 _4 F3 g0 w7 \8 V6 _{' g4 @9 S/ I9 }4 r3 l3 }* v$ x, i' \6 P
/* Start the clocks */
, Q, a1 @) l( Z i3 \4 G. I6 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: x2 n# S3 O* Y: I# P4 u0 p/ dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 Z1 I, y3 [) @% P+ X3 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 v% l, q2 T# R+ _
EDMA3_TRIG_MODE_EVENT);" o) N# y9 H4 Y. S+ b' O" w) |( }+ z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 Z* ~ E# g: n3 G: m2 S- _) @% a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) f R" B; C( _: \# R7 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 B) `( @0 A9 b, A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 G, W g2 {1 }3 b+ i0 y) R. i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 z; a5 e. _* N+ ~7 `1 qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' V% T2 s+ K) a# H2 eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# d2 R; k7 q" S/ a* t5 i: |
} 3 h. B/ j' [+ _% I. d( M8 G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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