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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, X u) e2 w0 |1 b7 l, S) P; _' Finput mcasp_ahclkx,8 d) B- T+ s0 D
input mcasp_aclkx,+ `# u* [* H% B: g
input axr0,0 ^. C' g$ u/ @% }; x+ i
# A8 J# ~: p$ V; i% T& d7 E
output mcasp_afsr,
% ]% q8 S# t& q) v/ m0 r* z* c1 M0 houtput mcasp_ahclkr,+ f8 C: N* k0 F2 a" }" j0 R( Y
output mcasp_aclkr,
0 ^7 o/ \- S0 x5 Y* j( joutput axr1,
- y# B5 b; l! E, a2 ]; z- N assign mcasp_afsr = mcasp_afsx;
) {; J, o: c; H9 G# @1 Dassign mcasp_aclkr = mcasp_aclkx;% C& E3 k9 w. x% d, P. k6 \
assign mcasp_ahclkr = mcasp_ahclkx;
7 E; X+ z* _" f2 w. \2 jassign axr1 = axr0; ( c/ y7 E; }! f& v( N5 b2 G$ t, z
8 M: H5 K C( w. G! U9 ~& V: m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , e' t. W& Z9 B( r# Y. q
static void McASPI2SConfigure(void)
" B3 u- \" y6 G4 ^{
# L$ v0 e0 p# i' m, aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! U1 t- K) x$ P4 R6 i# \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 ?, G( M% p) q/ G6 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) g6 T% P( h+ w8 v9 c9 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ Z9 {1 P+ {' O7 b' IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; W% e$ m. O2 ]7 ]7 v/ A
MCASP_RX_MODE_DMA);0 [, q; [" A @ \) H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ x; @" u R# v; U7 M5 \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. h' Y" {0 m4 B- vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ @' ?0 |/ x6 l8 D+ T- M# P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" ?9 R& g4 Z! ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - F2 t/ a; y W4 m6 l9 p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% r6 L$ w8 I# P; t8 W: `+ MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. W( t- P2 U" X, k0 ]9 m+ C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, Y$ P0 m8 Y0 a2 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! |3 h- K5 F' t+ L2 K( g$ j" @0x00, 0xFF); /* configure the clock for transmitter */
1 j! W: ]3 t2 @" x1 P/ K" m! C) @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 j" O5 p; _; t! O+ aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 S4 m9 g3 f+ a( ] f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 n7 j& T6 b3 U/ p' o4 l0x00, 0xFF);
; g$ V% q) ~7 N
; N, H6 \$ {- K/ A* i- z! _0 \! O/* Enable synchronization of RX and TX sections */
, ^) n- ^# `3 P8 x. _, ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// K1 U8 ~% {, j ]& _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. r- B8 A& }# z: ?9 ^7 ?2 HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( h7 @ f0 c. C. o/ X1 o: w** Set the serializers, Currently only one serializer is set as+ S7 G p, a1 F6 T
** transmitter and one serializer as receiver.
" |, L, {0 y) o! y! S$ t* x+ e4 q*/
: I( O( i" g/ VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% B4 q, q* o# Y; O, B! _ ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 ?# D! N6 f" V4 c
** Configure the McASP pins " ` p; D( S; r' D! L
** Input - Frame Sync, Clock and Serializer Rx1 o5 t& p2 m8 \/ J4 z6 \- f
** Output - Serializer Tx is connected to the input of the codec ' N5 q1 J _ h2 p" @& l' _
*/6 Q% J+ |, N$ `& W7 @# h( m* J8 q) L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! r1 M7 H6 D* s! d6 H6 lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; y) T# p+ S( {7 d/ b$ ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' J4 @9 P+ x+ ?3 F) G; |7 N
| MCASP_PIN_ACLKX2 r6 z6 O7 G$ `
| MCASP_PIN_AHCLKX
: M( N7 b, f- S7 O& B0 @7 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 c' p5 S. k1 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 O; |* R/ r4 {/ h# c2 I& `( \% I| MCASP_TX_CLKFAIL " b! i V* R% p; t' S: N
| MCASP_TX_SYNCERROR
( ?8 f" \: ~' A2 _: A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- y4 n7 n; x+ J9 J- i1 C: `2 P) b| MCASP_RX_CLKFAIL4 A% E2 W' e3 D
| MCASP_RX_SYNCERROR ; |9 S( ]; N( ~% f" g$ y C* D
| MCASP_RX_OVERRUN);9 F$ D/ g; Y3 B& ^. m
} static void I2SDataTxRxActivate(void)# A& I9 j t/ y& K* X/ H! _
{" a9 ?. `7 g* t$ J9 N6 Z: h: Y
/* Start the clocks */' h% ?: `5 `' a; j m8 s( x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* V: J5 t' r! P1 j9 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
P" Q! H5 G- |& i/ S' Y) b" ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ s/ P0 ~0 ]0 n# T' Y- e
EDMA3_TRIG_MODE_EVENT);
5 i. c/ U; I8 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% k. ^7 D% V% W8 F. x- m; TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! _$ `+ o3 o0 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 P: \6 W# E+ U$ B! H8 D$ [ UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" |) n" d2 G5 h5 v/ A1 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 g/ r, B4 t/ y9 g! x- m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# D' G6 b. S9 B% A2 c+ O; Z: ]2 @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 Z% `* l5 r1 f
} 9 G$ x" q) }, |& }* L) u- l" R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ l* {1 A5 A! t4 {3 O1 K |