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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ v3 ~9 l" k) b8 t; Q9 A
input mcasp_ahclkx,$ G4 |/ V+ ]; R+ Z
input mcasp_aclkx, |- c, G2 U* S% y4 G# {4 z/ C
input axr0,
* y# G) O% B, U W6 m# J
9 R) _! j+ F. X# a# {6 k8 d6 {* Aoutput mcasp_afsr,
7 @! H4 Y% ] Z4 ^3 f( Eoutput mcasp_ahclkr,
3 L0 m* ^3 i& Foutput mcasp_aclkr,8 B% q5 B p, }2 s$ c4 h3 x7 I( U
output axr1,
3 d8 V/ }3 [9 E {: \ assign mcasp_afsr = mcasp_afsx;
5 @4 S1 B3 n& P' y3 l. W* \assign mcasp_aclkr = mcasp_aclkx;
8 Z4 ^+ P3 l8 `; I0 B2 rassign mcasp_ahclkr = mcasp_ahclkx;
2 D1 Q- X! S( R) xassign axr1 = axr0;
( @# Y+ O! F6 i% D: k. t+ Z
+ ~8 W- s' ~( E. `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* ~8 d9 m3 I7 Y5 {& z1 ostatic void McASPI2SConfigure(void)
, N9 C/ ?- q" h5 J" u{
% w& j) d% g+ q2 }+ xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- s# e- R! N* V5 {4 L+ r7 L- gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, U. b7 K2 Q9 z) |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# c8 K/ w& Q1 t. NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ L6 P8 F W6 f! ^, ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. Z/ l$ k# f& |" ^4 ]MCASP_RX_MODE_DMA);
]6 T! o( l7 KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 H7 O2 ~$ e3 V8 O3 j V2 s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' X. t' _+ i$ z; g. ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 E5 z' @- V& v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' @. ~( \! C0 ~1 _0 h8 n5 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 E8 Z- U2 \7 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 E# S ]/ c. s/ @3 b: r' g8 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 n( ^$ m7 {& I& sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & N; O$ ?6 T; b; Z6 n: c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 E: o8 o1 w3 k( ` c5 r0x00, 0xFF); /* configure the clock for transmitter */
/ l6 n& k0 Y9 \4 B- j- v+ xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 e3 R4 y1 D4 N% q# U6 `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 g1 z$ [# y* `- g! |- fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," E' A) [6 Y- V/ f, V% f
0x00, 0xFF);' E' D% e( z0 l, q' G1 k
5 j% [# z ^3 _0 E/* Enable synchronization of RX and TX sections */
3 |2 i V e( E" |& u; GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 D: b+ z3 q3 ?. N/ R9 g0 s3 @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: R8 \ ]/ P/ C! U% R% T6 S% A4 ?, QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 b# _3 A& M+ ? d1 j3 X# q7 c8 M
** Set the serializers, Currently only one serializer is set as9 c& m1 m3 \" J6 y1 O% O
** transmitter and one serializer as receiver.* h! q, M. E1 j4 e8 g7 L
*/1 n/ k: j! C) I9 D0 C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 h, ?8 f% F7 i* q$ F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 F1 H7 [# m* t4 _
** Configure the McASP pins
0 P( ~' W* h" y& e, a** Input - Frame Sync, Clock and Serializer Rx
( q* B2 o4 v) g# X* K** Output - Serializer Tx is connected to the input of the codec & v& @5 T0 N1 \) ?7 R
*/) j. S/ B7 T- R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* K7 v/ a: o A4 M3 J( U0 {# G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& y- E/ ~8 G) {- D |7 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 }) q$ s/ j2 H4 b2 M$ n0 E| MCASP_PIN_ACLKX
! W+ _( Z) [! K3 E3 T, k; ^| MCASP_PIN_AHCLKX: p2 T2 \8 J( @6 H+ V/ j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" Q. B$ H$ z, t/ p' w7 S b' ? k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : S" G' ]1 p% f4 V- {2 U, }- R
| MCASP_TX_CLKFAIL ; [9 e5 }. o2 U' H3 p# j
| MCASP_TX_SYNCERROR
8 D1 W5 D1 r$ f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. x4 K8 i( Z7 e. h% `2 q& i. R| MCASP_RX_CLKFAIL: [6 j& z3 l9 v6 N5 A
| MCASP_RX_SYNCERROR ) x" v/ e7 M- Q6 K4 {* M/ L
| MCASP_RX_OVERRUN);
: W( P k6 T/ V+ o} static void I2SDataTxRxActivate(void)
! F3 K4 a8 N+ I+ d3 b2 u2 M+ }: I" g{
8 X5 A7 {5 j! L/* Start the clocks */4 T* I. E4 k' H9 L" u* _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- N' K% [4 Q% _$ j3 u& F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, c, q: ?1 c8 h& G6 D l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 w7 T! p4 A7 A$ f1 F" M' W0 N! P# Z
EDMA3_TRIG_MODE_EVENT);* i: J- P; d9 r* T: Z/ \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 G! _" `+ N( NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 N- S0 A/ E4 X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* _) U$ z3 w8 |: ]6 l& YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. u n9 T8 e+ `9 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ |5 A9 a N- NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 h1 ]( [1 b+ ?7 @% c1 Z6 o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 N6 l0 W( A. l9 L: Q
}
+ r4 L& I5 Z7 q* T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * k7 }. _ k8 n% }& _; j
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