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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 H: a e( N( q2 u J; minput mcasp_ahclkx,
6 m9 l6 w+ }' c) Y( l9 ]1 linput mcasp_aclkx,
( l' ~1 X5 p# Y: O4 Winput axr0,
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output mcasp_afsr,
+ T: O }7 k1 }/ Poutput mcasp_ahclkr,0 z+ K3 \( W3 d
output mcasp_aclkr,
5 x+ A& X8 | A2 O& Poutput axr1,; V- t. F( u% |( d/ T
assign mcasp_afsr = mcasp_afsx;6 F0 g ]* w9 @7 f
assign mcasp_aclkr = mcasp_aclkx;
3 f1 b6 s' D' y Y9 K2 n. h! f3 A& eassign mcasp_ahclkr = mcasp_ahclkx;
, e2 D: a7 S3 V& w8 Gassign axr1 = axr0;
/ W+ [5 v% H' ~% p' Z5 i' a
4 k& a) K( E# }8 q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & H0 z& F4 t2 U2 ?4 K
static void McASPI2SConfigure(void)1 K* X6 f* o. K4 o! @
{
- f: Z+ y& |! r8 ^4 ~1 m0 k- {6 DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 \. L( O; ]# `0 D8 U3 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# C- i. Y3 s7 ~( Q- f7 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 @1 ?5 T6 e6 x4 vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: X: X s: G' D7 I8 @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ S. A5 F/ M) G8 g- c
MCASP_RX_MODE_DMA);$ Z7 X! @0 S" a( A) Q' J. \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 `2 S8 f% _4 u7 o# ^" Q0 MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# p: C! j& }# E# n9 K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & v! K, t- Y% e0 X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ _: _1 ^8 {, m! E) U7 u* h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * V0 K; W: v) l& O# u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 Q M* k. y) C3 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. Q# Q9 {* q' p/ u; J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ w% f; T5 W5 w" h# U4 y5 X; ?+ lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, F9 W6 p! E+ i! j" K' v0x00, 0xFF); /* configure the clock for transmitter */9 F' g, ^$ N0 p0 b4 j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. C( `; h- T: H% [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 w Z8 R% N' [# T |' @( kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; z l& @4 X' `; B0 ~( D8 |/ G
0x00, 0xFF);
2 S4 G) a/ P/ F* O* ]" u$ \" n
- z* A. e2 B" p% l5 i/ g/* Enable synchronization of RX and TX sections */
) ~; k1 I( b& t6 Q! Q7 q; ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* S4 G2 ?# e2 ?7 t3 Q; V: V( IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 g& _" E, f' B7 h% |% cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& l) F& G& F& k4 p2 O7 A1 n** Set the serializers, Currently only one serializer is set as
O' S! U) T! H6 y( I** transmitter and one serializer as receiver.
* H; A8 u, v6 H( w6 y*/' W3 \( K4 A( |0 \: W1 z" L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 V" D) t9 b2 I& |1 G1 Y* tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, R- u. ?# r2 |! D- r C4 a5 _& f. E** Configure the McASP pins
# s* x g2 ^# U+ H# k T1 M** Input - Frame Sync, Clock and Serializer Rx
/ s* H# r% o- \8 e9 [** Output - Serializer Tx is connected to the input of the codec
/ ~5 E! X7 ]2 x*/
5 C# H* d$ b( G, D0 l6 XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); y+ }, h6 C9 u0 m! A0 V1 D+ ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- ^5 @% Z- q0 o0 l. I8 [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 m: U e, k( _; R, J* V# i6 u
| MCASP_PIN_ACLKX
/ F) j$ _) e3 n/ Q2 M7 h& t7 p- j6 M| MCASP_PIN_AHCLKX% F/ _3 }+ R6 V# n P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
T- P, C( `9 T; u. zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' R) ]8 W7 n6 C$ s* ]9 k
| MCASP_TX_CLKFAIL
7 S6 _: t- X6 K6 H; O* x| MCASP_TX_SYNCERROR5 T: U3 F3 T w7 u) z( r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; F& ~3 _( b) V( x
| MCASP_RX_CLKFAIL
3 t7 ~' q" {+ J$ \6 s1 X| MCASP_RX_SYNCERROR
, t! _$ I# q: i* x( ~7 ~7 ~" l% B4 g| MCASP_RX_OVERRUN);+ y A( S- f4 L1 ?, m5 F* p
} static void I2SDataTxRxActivate(void)
$ G& U' Z: O/ M( ]- X2 s& Y{
. H% ]7 g) ]% f' ?' J! l/* Start the clocks */% t( v2 W' e, B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: Q) @+ k4 J: \& S2 l9 b" `* c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- ^4 g. v, |, G' J+ @- {, }( tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 U X+ r3 v' U4 f/ u/ x0 L
EDMA3_TRIG_MODE_EVENT);
# h4 }8 b) C" o7 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 U* s y2 B! r2 o: `5 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 J# k1 E& Q; V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! h7 K# w2 A5 Y. G% {* |0 ` ]/ _2 `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 {3 Z% u. [. Q4 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# w3 H. {% W8 ^ |: `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( z% Z$ [, t# [0 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 K0 \* c1 V3 C5 \' @2 g}
) }+ f+ B% f/ H) @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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