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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 B+ r6 @% t9 V
input mcasp_ahclkx,
6 E% S0 y/ B2 n( finput mcasp_aclkx, p9 r+ ^8 z) G1 L: Y, A8 m
input axr0,# C: m* g4 `+ N. F' a. Z' V
1 D. L% c( N3 y8 Z5 Xoutput mcasp_afsr,3 n8 \- V' _6 G c7 W9 G6 G( n: o
output mcasp_ahclkr,7 O, N9 B9 x# F& X# P. @) T3 T
output mcasp_aclkr,
' w' y6 W; z- T" D5 l6 h, H& ^+ j$ ]output axr1,
3 `9 u$ d: w: B9 `; {, ^; F assign mcasp_afsr = mcasp_afsx;. ~6 W9 ]( x W% H$ h$ w) X
assign mcasp_aclkr = mcasp_aclkx;/ O: ~ I5 U0 b4 ^- E/ c t& B
assign mcasp_ahclkr = mcasp_ahclkx;
. O1 H, G6 u; z k- T9 |; c2 B: sassign axr1 = axr0;
+ q' B2 D: `5 g1 o ?
5 }2 \) f- h4 g/ R2 k0 c* N) c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ {; h) d3 l8 T! Qstatic void McASPI2SConfigure(void)) C4 Q& o. Z* g8 |% r9 n
{
3 L6 _- o/ w, J- s { j: EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' l) N* i+ `, R% j S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 h z9 k- J$ G- C" s8 y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ E2 x3 `; M3 d. p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( \6 O, ^5 V2 ~, l2 \ f. _! U& F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, W' u5 i; G8 L
MCASP_RX_MODE_DMA);
" ~/ B0 n2 V8 H xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 a* k8 w9 q! G' v0 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 E/ K7 ~( v# K! J7 P$ pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * W: g& A" T) R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
@/ v9 `( P. p( _3 w: {8 _0 } OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 i7 u; p, \* x: m6 H- |) a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- ]; ^3 l T, z+ t! S, O) k! n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* E# V3 _6 ?5 p- x0 I" wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" |3 P1 f2 e. W* c5 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- ^% F: P! b9 Q: @5 V! S+ a% X
0x00, 0xFF); /* configure the clock for transmitter *// u! F. s4 I! B5 b. Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 X' {4 M9 m g1 G# m1 P- }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 }' U/ ^8 J3 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 G$ x f+ g# E5 J, B
0x00, 0xFF);7 ~& _8 M3 x1 L2 F w
1 t/ K* _7 n) R) }/* Enable synchronization of RX and TX sections */ 0 @: A9 h/ T6 }, W, n1 u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ a) q7 b5 F- X. f$ M. ~) h' ^7 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ t+ U0 N1 D% ~7 [ y9 {: Y/ uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% T) u6 W* k! p m** Set the serializers, Currently only one serializer is set as0 j3 S, v& g0 M0 d4 g5 W5 S; N
** transmitter and one serializer as receiver.: s0 r2 C; D+ M* D" Z- m
*/
, B2 u+ \+ |( g2 S: O/ DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* B' ~4 O$ C% }. GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 ]8 O7 |6 L: e4 Q! K
** Configure the McASP pins + T+ N. b$ f0 `$ I; E
** Input - Frame Sync, Clock and Serializer Rx
% B% n! f; n' j! D7 L" B- R** Output - Serializer Tx is connected to the input of the codec
- ^' S4 C( Q( V* B- g% b; l*/
, `) e; D6 \. ?( gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 U( X; {; L' C+ f, m4 T6 O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 B8 x0 E1 f; f, ?( xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; E# v' V' M/ |+ ~# `! | ?8 y6 o| MCASP_PIN_ACLKX
, v, p0 @0 r) Z| MCASP_PIN_AHCLKX
1 N8 e" ]1 c. L% G( f! z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 x( U. m6 w& \+ ~3 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 a/ r, O. J1 Y: c
| MCASP_TX_CLKFAIL 2 e& o* F3 @* S: w
| MCASP_TX_SYNCERROR( P8 S6 O4 b7 W4 U" U& i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 C' ]7 k q* T- e$ C| MCASP_RX_CLKFAIL
0 d( Z6 z/ @5 \7 U+ [| MCASP_RX_SYNCERROR
* w, ]+ s8 o, m, P! ~9 E8 n/ F| MCASP_RX_OVERRUN);
5 j8 L% B; d2 F; c} static void I2SDataTxRxActivate(void)
2 d# |( ^+ K9 @{
( W! l# K$ f4 ]' n: x! n$ c/* Start the clocks */
`5 C' D, U' V1 t) O3 u7 fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& J* J( a. R) [* \2 L6 B) J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& N3 ?; t* r% R4 ]' r6 O) EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* ^, L' ^7 }, C+ ?$ S# SEDMA3_TRIG_MODE_EVENT);# p- I; s4 t+ I6 e0 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; L8 l4 C( g! F& KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) C0 Z8 B$ l8 U% z1 \2 sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ K& @ d# S4 R; hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 Y+ x F* \5 M- m# q1 k% Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ G0 @3 {: o6 @+ |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 Q1 x9 B9 Q9 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) r- U8 K3 ?7 d2 }: c
}
* Q$ k$ x _4 ^- @5 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 ], k% O, H3 u% k
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