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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 m1 b6 {4 t9 q1 hinput mcasp_ahclkx,; Q2 b3 G( z& D0 c. K3 Q' N
input mcasp_aclkx,: S( A4 Q3 G/ [( H
input axr0,7 p# p* Q0 t# H
- h+ y: Z: h' j* g
output mcasp_afsr,3 E* b" [) W" {, T( d' n
output mcasp_ahclkr,: n7 k* b1 @- _$ M
output mcasp_aclkr,
; w* {( m1 z' o" o9 F- Koutput axr1,8 G9 }' ]- ^& ?
assign mcasp_afsr = mcasp_afsx;, Y4 J7 Z! ]- r9 ?: U1 T
assign mcasp_aclkr = mcasp_aclkx;8 x& Z8 r1 ^, k: B8 R. l+ y6 P6 o
assign mcasp_ahclkr = mcasp_ahclkx;, T8 _' B3 a4 s4 S
assign axr1 = axr0; . b6 e6 ~7 ^1 X5 b; T
0 y. ~ U3 Y; d* O5 B6 H# X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 A: g4 S- e) R+ U, j6 I) k/ lstatic void McASPI2SConfigure(void)9 M0 n" ]7 ~# ~& r
{9 u9 H, _, L4 P& Z8 |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! ]& X) m m, h$ q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 A% R0 a, L* C! O' eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. z- J* g Y( HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" u0 l+ S% ^+ ~9 o3 `; p0 @ {# R' \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ B0 B5 }' o c* D: ^& P
MCASP_RX_MODE_DMA);
3 q% h- g3 X% @8 B% |4 hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* t- a5 ]0 O' N! K2 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 d( b' Y& A( z) H: ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) z4 M1 c6 W: u p d/ e. rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: B4 l3 ]0 f9 O2 t" d( G( uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& }1 t$ L1 R( B$ C lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- J% w) V7 I0 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: i5 V# d, D8 J+ c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. p3 L$ \/ b" M! |1 k' _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 n4 {1 k6 u' a2 l3 T5 T
0x00, 0xFF); /* configure the clock for transmitter */
) _. \5 E3 Q/ }$ y1 {7 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& j1 R2 M: H( `! q0 T6 s: m8 L5 `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 E6 z7 E7 ]8 ]( xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% X8 A; d' s5 v0x00, 0xFF);6 g) `) T. [. w
) {6 n- }2 K- {! d0 Y+ B
/* Enable synchronization of RX and TX sections */ ! k( V) R6 k' O8 S6 ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 o# t- g. t& S. D7 x9 _7 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 [; }6 G4 k. W5 |; j5 ] r* XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' z1 S0 w. H* m; ^5 M** Set the serializers, Currently only one serializer is set as1 L% e+ S& c. d( S$ J+ x9 v1 ?
** transmitter and one serializer as receiver.+ {2 }* Z' u' ?2 P
*/
4 {4 y( I5 c) e; E! s1 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# G6 r3 P7 Z2 t& E: N$ j7 G/ V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 H5 D" G+ p8 x+ k** Configure the McASP pins
7 Y; Q6 U" H6 U# x0 y' M. |6 \; I** Input - Frame Sync, Clock and Serializer Rx- {2 ^$ e1 o0 P/ w) F
** Output - Serializer Tx is connected to the input of the codec ( V: r2 x+ i8 `7 G$ x
*/" D( t4 [* A8 J6 A1 G5 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; N3 m( }- y* \, f+ ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" R9 q5 w, b2 h( }; Y2 m. j/ K3 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 {- A" W1 q9 T5 k| MCASP_PIN_ACLKX
8 h; X3 S* d- T+ R| MCASP_PIN_AHCLKX
, r- t7 f. n6 K4 i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 }" P' \1 E& t6 s$ Q. h. i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : k4 Z* Q$ n+ x" b3 G& X, {
| MCASP_TX_CLKFAIL
: N9 A2 ^4 g4 [/ ]( n+ F| MCASP_TX_SYNCERROR
H$ R9 ?. U% k/ F9 P, m w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % U, X7 ?" t" ?6 J- T
| MCASP_RX_CLKFAIL
2 r" C u: j% s. H- l| MCASP_RX_SYNCERROR
- N* K Z; h# r+ l8 v; {( P' b| MCASP_RX_OVERRUN);5 w5 b8 `$ v+ {7 N# P
} static void I2SDataTxRxActivate(void)3 f) Z" B. q) p
{! z# C# O2 ^! N& n: [
/* Start the clocks *// S1 E6 P" A ?4 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) ]) t6 p5 S |8 ?& v% k* pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* R( s; Q: {0 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 q) m! s% w! u* @# D: n! DEDMA3_TRIG_MODE_EVENT);
7 C$ S3 G7 l. ]- }0 q$ W9 o$ IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ D- X# P& r& y% ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( r' Z! j2 f. ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' r! X; S/ O, Z5 T" i' j nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ v, f @% I( p1 Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 `: u8 B0 R$ L7 D {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 d; l6 j5 ~7 K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ M, T. G* ^9 m
}
+ O) |9 k& g& }( E7 ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " C! f# b4 k; w$ r- u
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