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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& C; Y; R! l' F4 x: |input mcasp_ahclkx,5 p s7 Y( l/ P
input mcasp_aclkx,. j( X, [2 b- b0 {5 b; A) D" K6 e
input axr0,4 E/ Q. \' C; Y" M, n
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output mcasp_afsr,+ m' ` y& C0 S. V
output mcasp_ahclkr,
: P) m4 ]0 s' @5 \) Goutput mcasp_aclkr,
8 ^2 M! M8 |, [+ ?) g3 ?( @ R+ @output axr1,
7 R V8 t8 S' C5 n' _2 g assign mcasp_afsr = mcasp_afsx;" T6 _8 Z9 \: C6 g$ Q0 N4 H, N
assign mcasp_aclkr = mcasp_aclkx;& i% G3 M w6 r: b
assign mcasp_ahclkr = mcasp_ahclkx;' q' P! V# Z. e3 t( \
assign axr1 = axr0; / c$ i" i' M M2 ]+ F
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 f. D6 G6 I9 n! `! h: M5 C4 F
static void McASPI2SConfigure(void)
- s7 E9 c9 P5 `& v{
7 N4 @' l# L# s; U# j8 P+ tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ N) j( g. W8 G! x8 b' t$ QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. q2 j- |6 @" m8 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 C+ p% K0 i$ Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* d) M) I O/ tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ K! U: G* Q' a& ^MCASP_RX_MODE_DMA);4 \1 A/ W/ u- ]4 _4 O6 b& o% [& M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 W( o' m( H# i8 w: g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% P! t. J- o2 ^+ @: J( sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 ?$ q( h0 c4 l. t+ S3 ^4 L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# o8 D7 e: H+ ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - i# m+ ~, j1 `. K! g& \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& A+ d2 R f* R1 j' l1 W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# U5 B, I# m# l8 V) ~. s3 T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" K! u+ J0 ]7 V( X5 u% UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 n/ g: n; q7 l! W+ v- Y
0x00, 0xFF); /* configure the clock for transmitter */7 g8 l5 _7 j! x: M* L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 o* N9 u6 l7 _& |, K0 V! ~5 f1 {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 C* r$ ^& k3 c0 |( Z RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& K8 L: U* U: P5 I9 ?0 \9 h
0x00, 0xFF);
6 K4 u( q# F( h3 j
- u5 r& Q2 D u6 C/ ^/* Enable synchronization of RX and TX sections */ 3 ]6 D3 n# N e; A5 c( z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) A" d1 B6 [% _! x7 \6 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" V; w9 x) q$ p! AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: c1 ^" T6 Q; T# A** Set the serializers, Currently only one serializer is set as' h6 N6 K9 w& g- u' i# C: x* o
** transmitter and one serializer as receiver.! X: r; L8 q% K! J; x" F. }# m
*/
' q" O+ {' D$ t2 P% V* v5 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ J3 d {6 Q( o! U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 ?9 d$ ]9 u; w
** Configure the McASP pins
0 r3 e- w. C! S6 R** Input - Frame Sync, Clock and Serializer Rx0 t+ t6 E1 U* ~" `/ _' R
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 @7 y2 X3 M5 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 Z$ q5 [+ N- E. [8 g* {3 _7 wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" I' ~# O7 F" ?5 q/ m
| MCASP_PIN_ACLKX
+ K/ D7 |$ |7 t' [3 f: L| MCASP_PIN_AHCLKX' ^0 y8 X% W" M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# E, X$ O9 \: {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; f& d, f/ ?/ Z* h| MCASP_TX_CLKFAIL $ g0 W' `- f" x( g' [
| MCASP_TX_SYNCERROR
2 _) |- B, R. _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" \! M* Q$ E5 m4 c& i| MCASP_RX_CLKFAIL* n u4 o$ I5 d, M- f: D+ {
| MCASP_RX_SYNCERROR
* y: o6 h' M* z* W+ Y6 G8 B x| MCASP_RX_OVERRUN);! _. b6 b/ [6 _7 ~6 g* n
} static void I2SDataTxRxActivate(void)
4 t2 l3 ` ?! e) {3 z{/ \$ ?1 ?: @ P! f4 i4 o
/* Start the clocks */( P/ {5 i. R2 d* M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% \0 t: s. r* {, E9 ^6 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 _5 d* c3 _9 H) B5 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 q7 V7 a0 D- e7 D, M' m
EDMA3_TRIG_MODE_EVENT);
% _) S3 `& h& w8 K5 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; ~+ G. [4 y% H7 |! w: S; n/ r* C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* a7 L& Z" P. I" K. ]2 [0 y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 a$ Y2 E$ I( K# k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" a1 ^0 r5 @; g& [! k9 C- mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( P0 j5 |! i2 D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# a! {4 u. g+ O3 wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 i+ z5 f4 G1 d+ W}
; I7 S9 s# M: G s0 k- A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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