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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 O$ l9 d# q0 {. Q3 E c/ P
input mcasp_ahclkx,
4 E' U8 T& v' {input mcasp_aclkx,, {8 A/ U% X/ j Z2 w# k/ m
input axr0,
0 A& e# V7 J2 Z# m* e I5 I( ?3 ~
4 I! l0 Z9 v4 A* z6 }! L+ U& I2 Uoutput mcasp_afsr,' l& I# t4 l! s0 \
output mcasp_ahclkr,% d. O5 p5 V% t3 e
output mcasp_aclkr,
" `# N# m9 l& y5 V: B+ `9 a3 Y4 e, |output axr1,
$ b, }) x5 a9 j% C) { g& t assign mcasp_afsr = mcasp_afsx;# H0 e) H0 C. _
assign mcasp_aclkr = mcasp_aclkx;' H9 w+ y' f" m- w
assign mcasp_ahclkr = mcasp_ahclkx;
, F" T! a8 R7 k; u6 C. C$ @& Passign axr1 = axr0;
% [9 x) V0 C- v7 ^: t
3 C. I$ a% t% m( l2 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ J. t, P8 ^: q. i Tstatic void McASPI2SConfigure(void)/ ]8 S$ n: S* D# T b
{: W5 H4 d. o& s& N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- s( q2 b' N7 h; XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) c/ h8 k/ i& g$ n! aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' @7 k9 z- u* P) N9 e- DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( q0 W$ k6 E' XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( o9 E* q* c! j/ e2 w; @4 k7 YMCASP_RX_MODE_DMA);' ^& m- @7 W& W; ]3 z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 O; q9 P8 S- @7 B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& i7 H7 {5 o2 k) s; x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / S" x; M2 a: o* `& s& q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" w; z, X- u' YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % b5 p- a$ N( d; s5 V" n2 d _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: N+ }6 R& w, J; v) r4 v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) [) c8 u8 h2 N+ p% z% _0 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); [4 D% w: S* g3 V/ [- a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 ?5 r! s7 Q& \6 A: m5 ^/ l3 Z
0x00, 0xFF); /* configure the clock for transmitter */
9 s5 t' T# |, d: K! I+ XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( ^" |0 h+ U/ P2 ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 D, j9 C# v) ~4 L$ Y0 V+ ?' S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 Z. @0 ^- b, M0x00, 0xFF);' @+ |1 M4 w: N- d+ }( B
% C' n$ \+ C! R& G
/* Enable synchronization of RX and TX sections */
8 L: {* z7 q* y+ K% QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( O; L3 F# S/ N8 K1 \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% s, j8 @6 w9 j1 p9 X- L- j9 J5 z$ U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 e. X% u O5 G; y) P4 y. Z6 u** Set the serializers, Currently only one serializer is set as7 z2 I b9 l, |& c7 G* ~
** transmitter and one serializer as receiver.
2 u6 W, ^/ J# p+ T' | I# T8 W# Z*/
t0 E5 C0 g% T$ n! p2 y) zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- S! o7 }+ Y9 V4 b8 r2 l) BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 l6 A! J7 r$ x& R W/ \
** Configure the McASP pins 7 W' a$ G$ S3 o% t7 |
** Input - Frame Sync, Clock and Serializer Rx& N. D6 a9 a$ E
** Output - Serializer Tx is connected to the input of the codec . G8 q# |1 B8 b4 ~" Z3 W% `
*/( Y( a; C% n. A+ ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 W, K9 ~% k: o" a6 O# o8 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 T! n* T; f) ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: W8 ?8 d$ L; i( c1 ?# k, K& e& o; Z| MCASP_PIN_ACLKX
1 n. F: I+ l+ F, W! T5 a- || MCASP_PIN_AHCLKX
: s, M! q: k. z0 C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 V7 S7 n1 }; s5 Z( g2 VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & A/ Q& z t% F) P9 ]9 Q0 y3 J" J
| MCASP_TX_CLKFAIL 8 a8 l; o- i5 q+ q V. V: y; J
| MCASP_TX_SYNCERROR, F! ]6 I% J" b! r: q# P @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 j7 `) {. T" N$ W/ l4 u
| MCASP_RX_CLKFAIL
" r- {3 ]. J! ~3 u| MCASP_RX_SYNCERROR
. W9 I7 P7 q j3 E1 m6 ]| MCASP_RX_OVERRUN);2 I. s- I) n/ |' c+ t% L$ K
} static void I2SDataTxRxActivate(void)5 m: ?* L% C$ @) Q
{8 Y" |5 q: Q% U0 P1 H
/* Start the clocks */
7 u. \# f0 \' p8 J7 Q6 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# M+ e: h# h9 I% l( h1 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 o+ N; V7 U! z% d" s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ V, X: T' _+ O) y0 n- o# v
EDMA3_TRIG_MODE_EVENT);2 H8 W0 |5 o- O7 x1 @( N, \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 ~& g/ ~( B) u1 D! T$ V# p1 \ lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# d! |3 j8 i+ C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! v0 E4 z: R! e8 L) D/ Q1 J" vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ t( ^5 M* R, m: \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ M1 R, K7 F8 B: t# `5 P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ n% d+ F% [$ r' n: N" E7 u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# H/ V) O8 w8 z! [ b} % W5 B% X& t% J i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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