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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- N! m. o. h) }& w- p
input mcasp_ahclkx,
& S) o3 C. |3 E# ~input mcasp_aclkx,
% H; E: d& O9 X h7 [& A/ x+ W- ainput axr0,
, h* ^: f* C4 K$ z7 _* k) K8 j w8 F6 U. _ o9 e0 Z2 j
output mcasp_afsr,
- C& I% T. H8 T( ^; Joutput mcasp_ahclkr,/ w* [ Y E" l: B: @8 G0 i
output mcasp_aclkr,
: M% z5 ~+ `. \! l: d9 F) routput axr1,
) I1 |8 @+ @- `5 p assign mcasp_afsr = mcasp_afsx;
/ t6 I3 _* r: V" v2 h9 Cassign mcasp_aclkr = mcasp_aclkx;+ l$ F" \7 Z, L4 }- K: R, o# K
assign mcasp_ahclkr = mcasp_ahclkx;1 P; d( i- S$ S% G- l7 s% C
assign axr1 = axr0;
! q% ]$ o; {; k, @ P: Q, I% N$ l2 W1 n7 u7 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - ?. ^9 K* @3 u0 B3 [1 F1 x
static void McASPI2SConfigure(void)/ u/ c' `, k- x; U6 O. Y x2 J8 J2 l1 J
{+ D/ p1 Z8 L5 o' L3 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 b2 N2 }& Q8 H0 q5 f0 ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; [3 z" u: F- J/ HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( g, A9 ^/ R7 M, I' u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) R" H6 Y3 C/ r4 P$ v7 [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ~. ?# d* o/ ] g2 i# @MCASP_RX_MODE_DMA);
6 ^/ n. c6 W3 U! kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. s4 L: x; e; P1 y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 j% f) O- w1 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 ]. @2 N) ]$ _7 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& Q% m4 P9 U/ B: q* v. w# v& MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' c5 D) ?! g1 W3 d, hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& W. @+ z$ T& L% qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: s4 |' ~. H5 J$ M! @: q- P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' W, Z+ G3 ]% F7 S5 P) mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& ^% L/ \1 I0 [5 R& L( d0x00, 0xFF); /* configure the clock for transmitter */
8 I( p0 }) b* Q( CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. p3 Z6 e' S) P& J+ r3 Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 i3 y) W3 U- h7 N4 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ h& e# }1 _# Z1 G; l3 P
0x00, 0xFF);
) o0 R- Q+ Y* I- M
1 R+ _ ?1 c( C. U( `$ ?/* Enable synchronization of RX and TX sections */ : V1 C4 u( G" d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) g ~# @% r& d+ ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 }* o2 }+ g$ V `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 _1 x9 z& s' o* V0 T
** Set the serializers, Currently only one serializer is set as
. W- z) L) Z- g- P5 }** transmitter and one serializer as receiver.. R( }* x3 y6 q! `% a
*/
% [: Z5 J! N% g, w. _! uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* t( M3 t( j8 D, X0 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ p& H7 R9 @0 H** Configure the McASP pins & W- q$ o: ]. v8 V' t8 w
** Input - Frame Sync, Clock and Serializer Rx
/ D6 C$ H' l4 Z# s# H9 m** Output - Serializer Tx is connected to the input of the codec
f" |- J) q8 {*/( b c% k3 P1 R2 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ r- s; ], i( c/ {& }4 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 G7 y' n0 Z5 M2 m( W7 SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" H1 m! }" H0 |. Z% I
| MCASP_PIN_ACLKX& _, N# E% B/ G9 ~# L
| MCASP_PIN_AHCLKX
+ P' g" m# P. D" |( F+ C8 b1 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* g( H% M# j4 o; m# {# KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 ?' ]8 c; U* R) E3 J3 h( F+ r7 C| MCASP_TX_CLKFAIL $ ?) e+ u O9 i$ w. Y' u$ g
| MCASP_TX_SYNCERROR
( {' l! ?% p% |' w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. c- ]" z0 i& i/ S| MCASP_RX_CLKFAIL
' j" {; g" ?( N' W0 U1 x0 u, g| MCASP_RX_SYNCERROR
& ]( `0 C: e- Z| MCASP_RX_OVERRUN);
7 t7 ~" x0 F: x# |$ K0 h3 O} static void I2SDataTxRxActivate(void), X* S( X3 C9 x5 ?
{
, _2 m/ C/ y+ [; w' v1 W) G/* Start the clocks */! X# @: p6 h% C$ k% ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ _! A& b# b/ S& r4 w, i/ l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- K( O. b4 J A! z( \3 p& b MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 j& h0 C' z b8 T6 I4 B
EDMA3_TRIG_MODE_EVENT);
* z% |0 Q% V/ m: Z$ m6 b' Z; @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 w+ T1 S$ \ ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% X2 m4 l2 ^/ tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. p8 P% h1 z4 d! F0 y6 g+ H7 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; h6 q& m% d& k! p, [3 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; L- @0 o2 Q8 h* oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 F5 A( \( c$ a3 o2 I5 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 s7 { Z# a4 v% q( Y
} # P1 o8 J% _/ |$ W) z# A: Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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