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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ Z! F+ B3 e1 {4 A0 t6 B( n; Iinput mcasp_ahclkx,* J" }* ?: z& x9 [% P* Q
input mcasp_aclkx,* u$ C- Q4 f' {" d
input axr0,2 l+ N5 ?$ ^) p
# T+ K0 R# @' R+ X- W3 z7 Uoutput mcasp_afsr,
2 q3 y, Y8 I \. B# M h0 K- i( joutput mcasp_ahclkr,
2 U: a' R, C, goutput mcasp_aclkr,
2 p$ E( \) `. _) X! R, \7 T' Y* k2 Toutput axr1,
. H: J2 Z: E2 T M! p3 L5 x( Z$ d7 h assign mcasp_afsr = mcasp_afsx;
6 f. G/ N8 \! } qassign mcasp_aclkr = mcasp_aclkx;: X F$ L, n7 {& N: ^) K+ A. P
assign mcasp_ahclkr = mcasp_ahclkx;
6 x% W K; T' n* @% `" {6 W9 uassign axr1 = axr0;
* _6 O2 c1 a* G2 H3 ?6 [+ u+ g- d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% y3 e5 Y0 i$ s7 Q" R+ `! Zstatic void McASPI2SConfigure(void)6 R; v3 G/ m2 Z
{
8 N: d, @1 r7 b0 {3 J$ a! kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 M# f* ?$ ?* J1 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 g+ m4 o# g' }* G/ _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 J' V' t4 _& D, @: C" w& b, J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& e* w5 l/ V. H+ z0 `, k6 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! F) |5 R( s* y4 Y
MCASP_RX_MODE_DMA);7 D$ ]8 W D- `4 \4 U: G* j7 Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" }! I, T9 Y: [; `# {3 KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; F" |+ b6 ?& F+ W+ SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) e4 A* C; I$ z, o9 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, X- Y4 [- Z0 x3 a8 XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ K9 }# K- b2 v' c* y+ C. s% w2 r/ ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; p$ t/ _6 a2 z& d3 N, C( H) b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" I$ t8 V8 K, LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : V1 q- a- ~2 P) S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 c, ~6 w( u& P/ }0x00, 0xFF); /* configure the clock for transmitter */
& K Z6 H0 j! A. G1 e- a% w% @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ J2 i7 P. k9 o- N {. ~4 H' F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ k6 d' c8 n2 b! ^+ I' Q1 H4 n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. ]- H/ d6 Y& Q4 U0x00, 0xFF);
! \% I3 u- l8 B' Q2 b( v$ ]& f R: S" g O1 s2 s
/* Enable synchronization of RX and TX sections */
5 I% w3 v$ `6 O7 b" R( j% CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 L# T i+ |) M9 a/ W* n1 e3 w2 C+ ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% n6 k# `) e) O2 E7 T, { k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 W% ^0 \# w( C** Set the serializers, Currently only one serializer is set as
j# X, R* C0 r% u** transmitter and one serializer as receiver.
1 ?/ h+ r) d9 p( ^1 h7 c5 ?) u*/
0 ?- F5 J7 ~5 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 t' r5 ?# C3 X9 S% P9 G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 c' H: P+ D; M" l9 n" j* w** Configure the McASP pins + A' T# B0 ?" |& A: M( _
** Input - Frame Sync, Clock and Serializer Rx
# b4 Y7 x Q4 x+ d- z** Output - Serializer Tx is connected to the input of the codec
, d/ r- `) t6 ]*/
* x6 }+ M0 C2 U) nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ A% A" C% j1 Q _( n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' R% _9 H8 c7 b6 Z8 u" K( I3 @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# ]" l/ z- Y" i) O9 J| MCASP_PIN_ACLKX2 I0 Q7 T$ W1 \. D
| MCASP_PIN_AHCLKX) g3 d# x9 U* j# Z H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ \! x& N, c4 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* o1 p) d/ e3 `4 D$ l3 _! k. k| MCASP_TX_CLKFAIL / S+ g( w9 I/ r
| MCASP_TX_SYNCERROR
/ J3 Q. B, { u' m9 w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' e: R3 c, U9 Z) J4 l4 N6 X' X$ C) I| MCASP_RX_CLKFAIL! _* p3 x [5 @' \0 d2 G3 b
| MCASP_RX_SYNCERROR
& k: h9 ?! {. h4 a: f3 x4 V| MCASP_RX_OVERRUN);4 \* x& q1 Z$ C! |0 t
} static void I2SDataTxRxActivate(void)
S- P, Q( Q6 @5 t8 }9 C* _4 j# I& H{
/ C7 |; u$ a& @) D1 C. `# U) g/* Start the clocks */
8 K0 V* m0 [7 DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- Q( I$ }% c; I. qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# q, _% |, o% p6 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ i) o; h8 O' k0 N; R4 _9 W4 c# E* t
EDMA3_TRIG_MODE_EVENT);
; N' l! s. ?4 | L, D& \3 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 O, F5 y& e% T$ ^% u- J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, P# l5 A) |6 E& _1 X xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- W X4 v- p5 c% C5 B E, o$ wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' E" Y( i, x- r$ n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ X5 E( m/ [0 f% \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( s. z3 d* l6 c3 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 a' j; X0 I1 F} 9 x# t! _2 W- |( J- N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! U$ m% x7 A' T
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