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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 j4 J; ]& |4 M4 U
input mcasp_ahclkx,2 G1 H) y4 [- A$ o6 O
input mcasp_aclkx,
5 e6 p# h+ K% R: f; o# B* H9 Rinput axr0,, ^% C h0 H( N( y6 N
. s' _3 S0 Q4 N8 x1 d, Koutput mcasp_afsr,6 `9 h6 v: \% `& U; V
output mcasp_ahclkr,- q: W( z; G* B! G
output mcasp_aclkr,
5 Y7 M `. k* Houtput axr1,
/ |+ T4 s$ ?; c' x assign mcasp_afsr = mcasp_afsx;
5 B+ Z& N8 B4 D. ], J" yassign mcasp_aclkr = mcasp_aclkx;
9 L& M. L8 m: k; r. p. Qassign mcasp_ahclkr = mcasp_ahclkx;* F$ a4 u* f' w5 F3 \0 M% F
assign axr1 = axr0;
* ^1 B. o2 E& y! l, w" {
* a$ E8 O+ u ~1 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - A. p: T1 r8 Q3 N" ?
static void McASPI2SConfigure(void)4 N e' |" o( B! t2 t, Z
{6 [* }/ Z; N* L8 `, A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; S( j7 o) z# R, ^. X# \McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) T; N3 ^2 w% n. yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 w2 L% D' k5 y3 j. N. ]; ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ \, \( O6 {+ w& v$ \- O5 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; X" @* {( ?# N% L
MCASP_RX_MODE_DMA);
" L: r+ _+ d) |7 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 F. {9 ?; i( Q$ xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' j3 e/ O0 ?, v7 xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* d/ @- [% B ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 W6 H8 t1 `6 v- D: QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 ?! q' L5 v: |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: _' _ a7 V, u0 l1 ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' ?8 M5 [, a3 x% f3 {% O3 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# L- A( z$ g# j0 c6 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 m/ O7 z6 s5 Z: _
0x00, 0xFF); /* configure the clock for transmitter */
. n, f$ Q3 R! gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& u( M+ v& A3 b* N$ HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; N5 I( D( Y% S/ B# G; `* M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; ~. W. O- ?9 X# m# c0x00, 0xFF);
0 [" y" g9 w: t; E, h# g \/ \# y' ~: M8 `% b
/* Enable synchronization of RX and TX sections */ / a9 w+ {5 B# F/ Q# o! f R1 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# `+ ~0 A( @, d* `. p* f4 M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% f) X$ v1 H# O4 H3 r) M9 Y- WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 f+ S9 i4 P# F, ?' A* d% I" j* q** Set the serializers, Currently only one serializer is set as4 x, B q; F2 ?& j! U& V! o, z" e
** transmitter and one serializer as receiver.0 X: ~% r1 V% m0 L7 u
*/
9 \9 a* F3 A& L9 e5 xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: q" i+ K% O# Q G- ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; d, a1 z: g& ?4 t/ w2 n
** Configure the McASP pins
1 [& B9 ]8 d2 a** Input - Frame Sync, Clock and Serializer Rx$ x3 j' @% b# J% l
** Output - Serializer Tx is connected to the input of the codec 6 x8 ~) o5 y% A% Z ^* ?; C" H
*/4 x4 g* z- p. E t- d4 p3 D# s! c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; x8 h4 e: F: e$ |7 g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: K% m( J4 N8 T( t! h, W6 p JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 V! q+ c, ^' r, y2 ^
| MCASP_PIN_ACLKX, |+ _& l) `1 G# p% y
| MCASP_PIN_AHCLKX
/ t8 X$ G. p$ |; O5 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, E( z- B* e7 m3 TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. x/ N3 h# _$ j: P& q| MCASP_TX_CLKFAIL ) l- o7 a& m6 \. f! t+ c/ U
| MCASP_TX_SYNCERROR/ z/ Y; S) I, Z2 ]7 t* P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( m5 ~2 F- n# z
| MCASP_RX_CLKFAIL) C3 y L2 Q1 _& m8 y0 g# \
| MCASP_RX_SYNCERROR
: Y8 O0 }& @, N5 f/ @| MCASP_RX_OVERRUN);' u4 d+ Z& b5 c5 J7 d* |, f: g
} static void I2SDataTxRxActivate(void)) [+ `, m& D! `
{
% X9 d% V: S: V, D2 K( p2 W/* Start the clocks */& B" R& U4 }& x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! `2 `/ @; H/ M7 V vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 f. @9 c7 g# AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* Y- X( i3 T2 I+ dEDMA3_TRIG_MODE_EVENT);$ `6 {7 y6 R$ _7 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - u6 v/ Z$ J e1 h3 [2 ?2 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 M, h( ?8 D6 R+ W+ p& CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ Z ~! {6 |6 J4 Y5 l7 }+ F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 x1 Y4 h' J. X$ f/ Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 g( C2 O6 r3 j+ t2 z, yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* ?% ~5 D% b/ f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& H( z. W5 L; o f4 L3 c} 4 U/ w3 n0 \$ M! u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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