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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. o. p: b# V, Zinput mcasp_ahclkx,0 `" U8 v2 g, J9 N! e
input mcasp_aclkx,* q& @* p& s7 D3 d; N6 u
input axr0,
. t% j3 o! d+ ?( D/ P& v# F6 ]. o: ]2 [' U' O! A, m
output mcasp_afsr,
3 d* i3 R! W) o! c H4 E# `' r/ Uoutput mcasp_ahclkr,- [7 d+ m' x1 N0 |# v! h
output mcasp_aclkr,
6 c. ?5 B2 W" Z; s/ s joutput axr1,
- |. J/ f6 a r# w6 m+ `% {5 K9 h assign mcasp_afsr = mcasp_afsx;
& R8 \$ C6 J% q3 Yassign mcasp_aclkr = mcasp_aclkx;
, g. k! H/ p: F5 c0 o; W) xassign mcasp_ahclkr = mcasp_ahclkx;* w& u8 V4 U" y+ @/ P
assign axr1 = axr0; 5 S- O- o7 \0 H: m
. p. T7 S3 _( \4 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 ~1 Y X% Z/ v, a; _
static void McASPI2SConfigure(void)+ m$ g, _# w6 q4 Q- L# E f4 D: a
{$ N# Q1 N: j V& m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" d# |& A8 s1 ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 y6 F' _9 g. b1 _9 u: O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 j& [( S1 a/ Q3 G, c' `- p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 X1 J4 C3 g* F# m' n$ }) s# cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' z, m/ S3 v" h" w( ]: n+ T& @; }
MCASP_RX_MODE_DMA);2 d0 s& A1 l) _2 l1 R2 r0 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: P4 G! X2 ]/ c7 r. {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 @% g7 f. t/ z& I5 x) SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + o, F( s6 }) u9 ?* {! w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 W. c F# r# Y5 ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 T9 ?% Q7 H2 o# t# g9 B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 h; B8 `4 \5 L! N8 ? ]) E0 T* iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' m. `8 i; R* v. D& R9 ?7 ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % q# k, G/ j0 E8 |9 P4 ^8 a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% a* z! o7 w) Q+ a6 ?0x00, 0xFF); /* configure the clock for transmitter */
& d; l0 C% e+ d& P2 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 G4 E1 ^/ A4 R" ~/ M- f2 RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, Q: f" e. \" ?7 a; B9 k* _4 Q# Z) [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 z9 x4 A) D1 f/ D$ `
0x00, 0xFF);
+ R1 G4 i, S" w: c1 \, M8 R; P+ D1 n
/* Enable synchronization of RX and TX sections */ 8 b' S: v1 q; X! y* o+ l: k, C% E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" ?' e6 A* s$ J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 Z' w, D, i) f) W& T; k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: ~# Q4 i3 o$ \0 m+ S
** Set the serializers, Currently only one serializer is set as$ s8 E3 i ^; h3 W( \% l
** transmitter and one serializer as receiver.7 X( y8 s9 E! _- l4 |% \& @
*/0 h+ h- U1 l8 p( l, A+ }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. a+ ]: B: u9 S1 o+ o2 x9 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# \ M, z$ O' a6 G9 ~+ e2 j
** Configure the McASP pins
* K# x' G$ C$ k! E J0 g6 {** Input - Frame Sync, Clock and Serializer Rx" R/ }7 R0 A- O y( f5 h
** Output - Serializer Tx is connected to the input of the codec
2 V# k( N* B. R9 b% `, q*/
$ B" r& ~4 m7 ^, p0 AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ [) {# v# L# K% bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. z3 v" j2 }8 p* F2 |: D1 E$ b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 V* w) M: J( m3 X
| MCASP_PIN_ACLKX. L! r7 c2 m: y' W
| MCASP_PIN_AHCLKX
4 E/ c; M% |, U6 V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, d9 b! \- M. F( ~0 z0 ?& d8 v5 f' U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: [% G! N Z3 |9 l| MCASP_TX_CLKFAIL
; ?' a( T% p* `. m| MCASP_TX_SYNCERROR* j/ v& u% ^, I: r8 k( M; D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& z* P) b( H1 e; `& Z+ i2 W$ ]| MCASP_RX_CLKFAIL3 E: G3 o0 L; H$ S
| MCASP_RX_SYNCERROR / j) ^& T, ~: i: s
| MCASP_RX_OVERRUN);
+ z: q, y! h7 Y/ S. P) f} static void I2SDataTxRxActivate(void)* P. }! t' @ v
{" i" L9 Z2 B! N. g! f8 C
/* Start the clocks */7 e% h9 j/ o" Z! G" S+ U7 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 _' h4 k- U( _6 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' Q, v! x& X+ B9 \* o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
t9 l2 T# k+ X9 j. S% o3 v! d) uEDMA3_TRIG_MODE_EVENT);
[) l9 ?; R$ Y6 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( _* _; N- ?0 ~2 B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& e0 r! ]/ a' ^8 w$ AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" a9 V6 Z* A" b O& v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) X% M" q" u) [. G. N- Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 ^4 y+ z$ Y1 F) _+ e( x% B; \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! J3 \, D) L+ O/ sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' x; P9 b+ f7 J, M; _/ T
} 4 X4 C. U$ A" d$ L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " C' q9 J% I+ r
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