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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 z& `) i% ~0 _input mcasp_ahclkx,) o3 N, z( D" m! N0 _1 ?
input mcasp_aclkx,
4 b2 M6 o' v h$ o" @input axr0,& l- P9 U. v" i9 W' T
( i' ~5 ]4 E! x8 N5 A+ s4 soutput mcasp_afsr,# W" \4 C) L' F; I, ` p% k$ t
output mcasp_ahclkr,$ ?/ ?! [$ L. P) h
output mcasp_aclkr,
+ n2 I, `- }- Youtput axr1,' p! A- K' Y! j. f& a9 v R! s
assign mcasp_afsr = mcasp_afsx;9 R$ U8 g1 S8 D2 k m
assign mcasp_aclkr = mcasp_aclkx;
2 U/ U6 x, i7 K# K8 A/ @assign mcasp_ahclkr = mcasp_ahclkx;
5 r5 E2 K4 b$ J9 @& v- I7 Eassign axr1 = axr0;
2 f* v0 U7 j7 e9 C. _' J+ ]
: |3 Z# F; a1 E0 U7 W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 H) t, E! a5 \/ A: i" X: D: |* ]static void McASPI2SConfigure(void)
% R! A# \5 ^5 {5 U{# l$ ?1 ^/ f7 I: q I5 x4 a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 l- g+ x0 L9 v1 q2 o, k6 z; r9 }9 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 W0 @+ u7 |$ Q. ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 r7 m, x: ~ s% v2 ]: a' ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ l: _+ r2 `4 \) t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 _+ I# e9 h: x! `8 c, }, `MCASP_RX_MODE_DMA);% @" S8 L3 C/ U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 c+ z/ |3 U6 l' V8 F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 W! w4 |3 k- F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 Y/ K/ O( N1 @1 g! I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ }% U- N0 h% ~( l' [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. P, z& p _% ^, m7 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( j0 T8 J/ y' l3 W' C* q- N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 D4 A- G9 _3 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) P \# E6 b0 {1 D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ W) Z/ a8 V1 \ s0 ]# [ T
0x00, 0xFF); /* configure the clock for transmitter */
8 f2 b# {* T9 R( S) qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. m1 s! y/ _4 Q V3 B, B7 f6 O1 f. IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 j) ]1 e% e7 e1 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 F; D2 \- {' Z% ]
0x00, 0xFF);
: T" I& z @5 {8 R: R" q" _
% H8 A& n# I4 T# V/* Enable synchronization of RX and TX sections */ & L. c Y" u5 A9 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 F' {, V4 k( E' G9 L: h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 {' R( O. a% g$ h! d! UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* J% g2 n6 Q2 @5 U4 F( L8 A1 M9 W9 E/ l
** Set the serializers, Currently only one serializer is set as
: b o, g' m* g* |0 o** transmitter and one serializer as receiver.
4 \) j% z1 ?1 Z0 z*/
, m. Y2 ?" i; u% {- R( [9 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, o3 _: l& a8 k( f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 X( _5 d* L/ Y4 d* X** Configure the McASP pins 0 N0 t/ p' j4 {/ F
** Input - Frame Sync, Clock and Serializer Rx }; I# R. P' m* [4 R8 R) j
** Output - Serializer Tx is connected to the input of the codec & [8 c" e& j2 a% ]
*/( E" l5 e ^9 ^) |# w G' M' K6 ~9 g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 r" z h. C5 F( H7 z$ U5 M- m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 h/ d& A# K) f# u8 E' |5 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) z# d, ]* v3 C; c# P# ]
| MCASP_PIN_ACLKX
% O* _; e) {4 z( U. [| MCASP_PIN_AHCLKX( A* I0 N. Q$ `" M2 e( a$ q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ X# {& p# ?! q; i% E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , B8 v* J- O( A* ^6 P
| MCASP_TX_CLKFAIL
2 @4 N8 E. [/ D/ U! k; h( C| MCASP_TX_SYNCERROR
* M% b' N6 u- W: [, u" z/ A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( f' k- N2 N" V* X2 ~
| MCASP_RX_CLKFAIL- A( {% [5 Y6 K0 I& ?4 R) C
| MCASP_RX_SYNCERROR + |8 |! t( ^1 ^+ i7 J) h3 I
| MCASP_RX_OVERRUN);+ A* @6 h, P7 A
} static void I2SDataTxRxActivate(void)4 E8 A' r3 u0 I" F
{
]3 `- e* k" V. N0 Z/* Start the clocks */
* o$ V# q% o' U5 `/ r3 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, e, s8 r. s- v! m( `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' a1 w" y8 U' [7 |8 P/ `2 G2 w p/ M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 y8 S) L& ^3 }6 X* n# b
EDMA3_TRIG_MODE_EVENT);: F6 f: P6 \3 C* Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; X5 p/ [% o. S( n' H+ [$ REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 W* X2 V6 `; {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) I Y; I0 G+ C$ S6 p. pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* h' v9 k, M% _3 Z7 n8 Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( m3 k9 D. F9 j7 A# ~$ @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 s' l3 P9 l4 O# B# t1 L0 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
R8 `" h# K3 M% l* i# s}
% Y& D, ^* I y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 f7 \7 M3 R6 v' S
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