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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 |4 S+ M8 e N8 `
input mcasp_ahclkx,
' S3 i) y$ X1 g+ b2 e$ S# i: x) Zinput mcasp_aclkx,8 i5 J- b3 @+ e4 p' a( C
input axr0,) W* \2 f4 ~4 b( H
4 v/ V4 b; \8 C, V/ S" }) moutput mcasp_afsr,
5 U3 E5 r- i9 f M' S$ g ^0 K2 Joutput mcasp_ahclkr,
$ }% @9 n+ r; [4 v2 \" X4 uoutput mcasp_aclkr, F; [8 u1 a" q
output axr1,
, W. `0 g/ Z8 g& z# r assign mcasp_afsr = mcasp_afsx;
7 e, \ s6 R! Bassign mcasp_aclkr = mcasp_aclkx;
) P* N Q8 U! F9 \assign mcasp_ahclkr = mcasp_ahclkx;" ^4 Q7 k) f2 J2 r# O5 C& d1 _
assign axr1 = axr0; 2 r( ^4 A! p8 ^& z4 X) Q5 p
' R& E7 R m$ }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : t) O* l1 i2 g8 W
static void McASPI2SConfigure(void)
, }1 ^0 [6 J. k/ @3 [{: y) A4 S& b+ M1 t. I# E" x1 }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# L5 |: x3 d/ l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
?; b) p- O% f2 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. e, ^% @( Y. x% L+ v0 x" i6 W( f" HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, e% r7 S ?. b' U. A" d5 ^7 ?5 N0 e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( ^& [/ l1 H& n1 t. P5 WMCASP_RX_MODE_DMA);
: x: C- R' M, j$ iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ B, O7 @. z, q+ n* Q2 pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& _% b' ?3 N% D, D5 A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 v1 N3 x! m1 V5 b0 E( {3 P" U! ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 n, e+ Y X4 f# Z7 B( v( a! t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . T& b" R" H. W5 w; @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% Q) y* R7 z |$ l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ y. L, k0 X8 H. C4 f7 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! h% v. `* x4 WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: J, }6 {+ W+ l0 J( \* l# X0x00, 0xFF); /* configure the clock for transmitter */
& k i8 }( ]3 C6 d" W, D$ UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% _9 [; d9 @" l# C$ hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 G3 `* Z/ P# k) X& E6 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 k3 ~% ]; T6 Q# m9 B0x00, 0xFF);, j$ R! h5 g3 H- \' M( m5 [ b, |
& }% Q/ x. j, h |9 J( f! ?/* Enable synchronization of RX and TX sections */ ( Q. T% p( d" T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ H" T" X3 ~, iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& s% V, T9 q W" ]0 [% X @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( @4 G2 ?; G- S2 e6 l# |$ \7 x6 l' K
** Set the serializers, Currently only one serializer is set as
0 U0 e6 Z( G* k. M) _** transmitter and one serializer as receiver.
* k! D7 i: g% r" s& X*/
1 `0 P- o9 Q& O& e" Z( ]; e7 aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 Z9 Y9 I7 R! _. U' C/ h$ |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
F" h+ k4 |0 m7 ~; }* l$ d+ I** Configure the McASP pins 1 k. U% f7 ~6 N' B1 Z- [
** Input - Frame Sync, Clock and Serializer Rx6 V8 T* N* v% C6 C1 L% z
** Output - Serializer Tx is connected to the input of the codec 5 p; X( C% s. L7 l9 @/ |
*/" u, R% a( C$ O/ r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 R' |. y) Y3 X& iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 ?# x& W8 ? }5 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 E, a; o0 |" K4 l3 V| MCASP_PIN_ACLKX
% }/ V; p+ J1 d. L e6 L- h) C+ g| MCASP_PIN_AHCLKX% b$ c: m: c# W, w1 o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; A, J( {8 p. iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" o. s$ z1 G# l4 [| MCASP_TX_CLKFAIL ; ^# f$ {) ^* L4 A" {- `
| MCASP_TX_SYNCERROR
0 s4 i4 v3 I! a/ C+ }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 C1 c& H; N$ t0 {3 v. f. a. ^
| MCASP_RX_CLKFAIL1 N: u4 U& C$ K U# t( @/ S1 X1 V
| MCASP_RX_SYNCERROR
/ n9 {' V0 H. K| MCASP_RX_OVERRUN);; H# ?2 A8 n, T: g* v
} static void I2SDataTxRxActivate(void)+ o' T- b u0 u8 H2 ^+ U6 R
{
; y. z0 v) t) S/* Start the clocks */( a" V1 Y4 i1 V, L. }/ D; O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: Y: x% x* P6 P6 TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" W1 F* s" m* n: G- k1 z( l! PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 Y6 R" G' f1 `4 J0 k% k8 w: X8 k
EDMA3_TRIG_MODE_EVENT);
8 Q# J4 r' y" Y% W$ A' H& \! ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " X! ^9 l, P1 e0 z2 L k0 C( Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) P, j/ o4 l- x. w' k9 a: R6 d. t1 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: \ ^5 F. E* D% I4 E( mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) x* f8 W& X' gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 @$ H/ X k: R( T P' O8 Q+ bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% n N/ z7 v( i- u1 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: l& V( _3 ~0 v6 p+ o& B: k} 9 z0 J3 m6 h% i. f0 O/ J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 ?8 C( G! F/ T) j% I' B) e" @
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