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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( X7 m k; z2 ?8 m8 R& G/ P
input mcasp_ahclkx,( q* @$ S5 `! Q' O2 E
input mcasp_aclkx,
4 y5 C0 p) \5 m: k: {. U4 s; Qinput axr0,
& Z' V1 r. [& X( n7 x: K! @6 ]/ w# D5 L: X9 m( h4 ^5 j- m9 U3 R
output mcasp_afsr, k. C T- J( r& J4 Q2 C; ^
output mcasp_ahclkr,0 R" `( Z2 ~& }* f
output mcasp_aclkr,
+ \8 p4 }0 M7 |) q" E9 C1 Boutput axr1,7 q2 j7 d7 o8 J1 |1 [
assign mcasp_afsr = mcasp_afsx;
/ z7 u( y8 E+ yassign mcasp_aclkr = mcasp_aclkx;6 G0 s* f* p% A0 \0 y
assign mcasp_ahclkr = mcasp_ahclkx;
7 }$ u7 ]9 D2 \+ l' L7 O0 _assign axr1 = axr0; 7 P V" W% ]1 E* X1 F, U+ I+ w' _
8 \5 l: l* u4 X/ H9 K) I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 C' w4 F& N% `static void McASPI2SConfigure(void)( a7 B+ [! N9 u9 ^! t& a, ~
{/ X" d' ]4 }1 V1 d* q) l/ B1 \8 X2 f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 L% O( f) ?0 Y% W% z v, AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
x) m9 {5 ^% o6 m! I, h1 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% C, }6 D/ M9 ^2 j) {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: Y2 p! T: M0 KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) M! T8 m* D. G9 j8 l8 iMCASP_RX_MODE_DMA);
3 ?' N! m) h; F0 _- S/ WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! v8 L% \) K7 J0 A4 q4 `" wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! x; q' X3 U- t6 n+ G& wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / B9 e1 M4 r$ T% J& U$ A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* x5 F8 n" B e* T6 ]4 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: d/ U( Y5 Y0 x' t9 Q+ z" e. e: AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( H0 p7 t" Q9 M$ W m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' ]6 f, g3 b7 x* R* r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( N/ h1 v1 ~) V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 t9 b, {7 ~( Q, E' M2 J0x00, 0xFF); /* configure the clock for transmitter */1 {6 y% p. c. v5 a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ L9 m( A' C5 T* O5 Y' H' [4 y U qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* }: F' w# G5 w/ L/ E9 X% GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- O1 p# P; v- f$ B0x00, 0xFF);! l$ c8 F- r& k9 f+ U2 K. ?
# Y$ _2 n6 R! v/ p3 A! g; }
/* Enable synchronization of RX and TX sections */
2 K" P& y/ z- M: R$ o* ~. F5 y) uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; W& B% t/ r# D( u# A% M: M8 S' u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 @1 o \5 x, l& m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 O5 c4 V' Z+ D7 y
** Set the serializers, Currently only one serializer is set as
6 H0 o8 n# d K! z6 z& q; T; w0 l, Y** transmitter and one serializer as receiver.
- s' e8 ?% B h8 s/ U*/6 q5 {/ |& ^6 G* C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 D) x& N: T4 R( o1 D" O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, ], d. U2 L, d; K- j3 h1 o ~+ {** Configure the McASP pins 7 H, C8 n. z' f
** Input - Frame Sync, Clock and Serializer Rx
, `- }* P3 ]9 l** Output - Serializer Tx is connected to the input of the codec
8 s6 O1 N( j8 J9 t*/# c( n0 j) I) {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 q* M0 f# h) \% d3 ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 p4 g9 y. p) P* ?3 z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 P. C! W0 V x4 o| MCASP_PIN_ACLKX
7 `, Y) |. N7 A- V| MCASP_PIN_AHCLKX
6 v; B3 C* X i* v! M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 h- P4 L1 D( G4 E) q: H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 H, t9 N5 D# ^* z" T' f/ b! X
| MCASP_TX_CLKFAIL
1 y! b2 f( H$ ^: o| MCASP_TX_SYNCERROR
% I* T" C1 Q! g* }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 }" I; @# V) g| MCASP_RX_CLKFAIL0 P. D0 ^* r- s2 g2 D9 }
| MCASP_RX_SYNCERROR
( w% j; q) F: ~9 \| MCASP_RX_OVERRUN);
8 [" C6 c5 c0 M2 Q" y} static void I2SDataTxRxActivate(void)( f8 Y0 Q) d, S2 ?+ ^9 T4 {1 F
{
+ u' g6 y9 g, P* e/ |/* Start the clocks */
) b% A! f; L- [% l. D) ^ O5 v0 ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% j5 \; p/ y" u( h: qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 o/ n1 n5 Z; v. E/ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# _: N- |# T% ?% Y4 C
EDMA3_TRIG_MODE_EVENT);( f/ N: [7 i0 _2 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ f2 w: h( G0 U' {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% Z7 r9 I1 B( E- P2 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) x/ }$ s- z. r1 `/ Z/ F: ^' E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! V) @0 v% |/ G! e2 s+ bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* p: D, p, e& y$ q1 {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- h, g' M3 e! H2 e5 | OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& Q3 u( Q* h- f* d9 c
} - D/ ?" H c7 S4 F% a. V1 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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