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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 x4 b9 H& ?* ]' f& O$ s/ [% J
input mcasp_ahclkx,$ w E# q, X8 g8 d! T: N$ M. Q
input mcasp_aclkx,( @6 z" D' i' O
input axr0,
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: ~$ A- ?4 g( z' K8 Ioutput mcasp_afsr,$ x" I, w: g5 L1 J- u5 V) ^
output mcasp_ahclkr,
0 v* c6 X/ w3 ]4 joutput mcasp_aclkr,
l8 o% G2 S0 Z: J- o, Doutput axr1,$ V# d: O/ m8 E: S6 }
assign mcasp_afsr = mcasp_afsx;
, U' `* S* }/ u- v2 Yassign mcasp_aclkr = mcasp_aclkx;2 x9 o, r( n# y; j
assign mcasp_ahclkr = mcasp_ahclkx;5 @! y/ ^3 E3 B# i, [
assign axr1 = axr0; 1 {' Q, l3 z5 E* |, Y7 p$ R0 E
+ B, V9 k" G' P1 n+ N9 D7 ]$ n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % y8 u$ ?$ \& T4 V) _/ `
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% O9 ?( l& Q# f ]( x7 `1 ?+ fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 s8 T& ~$ T9 f1 T9 N3 O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( F0 `% Q. E% c2 w* Q! g/ `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 S+ Q5 T, _, K* |) |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# v, ?% I5 f1 H6 N n$ \- CMCASP_RX_MODE_DMA);
4 `5 H0 {1 K* N' A5 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: a" b' T* R* M# ?& r. g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 o# b9 |" f+ w! LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! a* L; d; ]" e% ]& uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( G8 P0 u; M# h' |3 M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 t* a/ @3 v5 P T2 G( J& A) yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 K- S$ L) N7 |6 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 x5 `2 }6 t* Q0 I* LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- I2 k) ? L- f, a; `* y/ R. DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' H& s8 T: N9 G( S0 E2 g+ h0x00, 0xFF); /* configure the clock for transmitter */9 M5 p4 c/ E2 n; @; C0 a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); s4 \# a0 {/ H; t6 _/ ?1 g. }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * X# a+ z1 ~! N0 Y' S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' B" |: j8 {& b; y9 z+ O0x00, 0xFF);. Z* i3 l* y- S3 q/ j2 ^2 \3 p _
$ z: @* ]8 d! t4 D: `5 i% ^
/* Enable synchronization of RX and TX sections */ 0 y! j0 {3 g+ W% X! a$ J6 F/ |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ m- I1 {0 p! S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 P( |6 d& M; n% J& Z9 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" A; [( P3 m( v9 j8 N* [3 d** Set the serializers, Currently only one serializer is set as
; ^3 r# U7 o4 V: |: E0 W( O& `** transmitter and one serializer as receiver.
0 M8 T: m7 x! @4 f6 F- w*/
+ S& ]4 E* ~ }$ kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ @) }: K0 B4 C& a! o `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ p, @2 b( F% G- M
** Configure the McASP pins 0 o' \+ i5 @- d+ w. f2 y! Z+ K+ h
** Input - Frame Sync, Clock and Serializer Rx1 U3 g$ ~+ J# N2 N4 r
** Output - Serializer Tx is connected to the input of the codec
3 v9 Q) p7 j; z$ y; C& [4 @*/9 ~% |/ r8 t1 v$ {3 h" P: A5 H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 [. w/ F3 Y5 H5 l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 s6 w$ P7 X9 I3 ~+ ]3 H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 X6 A+ S6 o6 z1 l" @
| MCASP_PIN_ACLKX
- Q6 I4 Z) W0 R" \$ L- L/ Q' k9 e' F| MCASP_PIN_AHCLKX& ?( l4 G6 C. @% W% ]' l" s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! Q) N& Z) R' C9 F% eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . t/ x# _2 n. G: q
| MCASP_TX_CLKFAIL
) q @9 j) V/ \| MCASP_TX_SYNCERROR
% B l! a3 n9 b2 |6 {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 R% x! c1 ?8 }) V' P( H& P
| MCASP_RX_CLKFAIL! K5 I; M f0 }& u
| MCASP_RX_SYNCERROR
1 {$ ~' P6 B+ S" G- E& _| MCASP_RX_OVERRUN);
. J4 J: w. K: J [: A} static void I2SDataTxRxActivate(void)
$ P) ~& j T* J+ Y{
& v9 e' d& Q2 f8 |/ b/* Start the clocks */
4 J" V8 {$ P% J' C$ vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- p+ [; K1 S& W% g* MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 C$ J. O7 }. m" M$ a& cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
Z/ E, b$ n* `6 O) Q6 bEDMA3_TRIG_MODE_EVENT);
; L8 H9 s8 Q% a& {3 d; a! oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 Q* `' D2 I% a9 T$ A$ W& QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
b0 B, P+ {& b# SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" y0 v8 `' W; OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* A- g3 x/ ~. G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 L, f9 q+ A( K& k2 ^! [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 {1 E4 f; _" T. X8 B1 @: O) IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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: f3 \* l' b& a: U+ M3 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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