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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ X* j% V- o- ^2 B4 T: o4 J8 J
input mcasp_ahclkx,) A5 z( r$ A2 G6 x0 n% _
input mcasp_aclkx,7 C% v- ~5 `3 h% c' _0 d2 M# d
input axr0,6 k3 t4 s$ C4 x: ^( K
9 [8 C8 T0 d1 j
output mcasp_afsr,* ^2 H. Y4 s1 V( _
output mcasp_ahclkr,$ Q ~! b( J" D+ X3 `( ]
output mcasp_aclkr,3 p# Y4 Z, Y/ w0 T$ e6 d% l5 Y1 K
output axr1,. g! ~- @ G R( x5 {4 s
assign mcasp_afsr = mcasp_afsx;
2 p3 O0 ]" ~" w j lassign mcasp_aclkr = mcasp_aclkx;
# {: c, m" d S D: gassign mcasp_ahclkr = mcasp_ahclkx;
, f# |- E" T2 v/ v2 u" N- Aassign axr1 = axr0;
. _# t+ L8 q1 `9 n3 X/ N; W: d3 g3 P3 g3 u3 B) |! H' H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. W) O6 X6 J# i D" I/ {- [6 Nstatic void McASPI2SConfigure(void)
/ Y- k+ k( q% m. Z5 V. q7 N4 [" N{' x1 p) T+ V0 f, E8 R( c; Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 m. ~; F) E+ T2 ^5 d, r0 ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- H) w0 ~4 ?2 v8 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 W/ @# `4 e+ `, Q9 MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// R% r$ ?& h5 L" S' i9 d4 s s6 {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; e; P8 o' D$ T2 O# y5 V# ]2 jMCASP_RX_MODE_DMA);" f& q+ Y) q' x7 e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 V. o& F; l+ `* N, |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ t# O# x6 O9 l3 h/ RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 j& M$ l9 [8 o8 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ R3 W8 n4 ] x2 Z! T, B2 p4 n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 V& h6 I7 @. B3 WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. J% C* o& n5 }( t, p8 i2 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( P5 y( b' [% |; a- P5 `9 k! xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 A% T, O4 {7 {/ J7 h5 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 `: B2 |) l( F/ U0 J5 F) B
0x00, 0xFF); /* configure the clock for transmitter */
0 n! k% l$ j/ A) cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 x8 i0 r0 J H7 m0 |3 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 Q6 ~' F; K2 s$ Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 h; v5 V* v# z
0x00, 0xFF);
! |# ]$ e7 J, I) K7 e) l2 u6 M( Y# H% a$ S, x
/* Enable synchronization of RX and TX sections */ , x1 J1 ^/ {% B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, M% i( l' ^# j, s& P% V# |" Q% z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 S- R7 u* B2 D- Y% JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! l: i9 O; o* ]: k** Set the serializers, Currently only one serializer is set as
" F, ?. z+ K" V9 y& D** transmitter and one serializer as receiver.
- `3 f0 z2 [5 v. n*/1 t0 H/ `% u8 t) b A0 A0 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) \' S+ E1 ?8 f! t* ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& R( F% Q% T m3 r# n7 p
** Configure the McASP pins 4 @: x+ X. H% P' q9 j) H/ H1 |/ G
** Input - Frame Sync, Clock and Serializer Rx+ ?, @+ p. {) k- y- l) ?4 W/ Z
** Output - Serializer Tx is connected to the input of the codec
. J& S! i: y$ G*/
0 B8 J: M1 O+ p ^; d, c( TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& C6 ^! m! y/ ^4 X% X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, x, ]2 ^# _1 ^- q) X8 J) k4 G6 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 u4 N9 y3 W3 N, z6 F1 p| MCASP_PIN_ACLKX; F7 j) g5 p3 I. s( U
| MCASP_PIN_AHCLKX& M7 Q* Z$ ]5 X4 V& [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& r% ^! Y0 `4 R# {+ A% l& F8 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) }) R2 f% l, r8 ]6 R: i h2 ^+ x| MCASP_TX_CLKFAIL
2 Z3 k$ T4 q7 D' i; b2 || MCASP_TX_SYNCERROR
/ [( y4 W. B- o/ F9 c# o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - B3 G6 }6 x$ S! p% r& g) m0 u
| MCASP_RX_CLKFAIL
" m, h* Z* u$ z| MCASP_RX_SYNCERROR
+ [3 z3 [ ^; V" N& d ]| MCASP_RX_OVERRUN);
- g, V: ?( W. f% J3 h) s} static void I2SDataTxRxActivate(void)
& V% g3 H$ [/ B/ N{
( A, C/ T# K0 s( G/* Start the clocks */
9 O' ]6 @- K! ~- s' i! x# F# nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* F- G4 u y0 a' \+ LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" `4 y/ Y. J, t& g! H5 ~8 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 o" j, n7 m1 G, vEDMA3_TRIG_MODE_EVENT);6 E- E( T" x2 @, }. `, k5 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % Q* I+ {) Y! G4 q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 E5 Q5 B( l) q" ~2 i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! {+ U; ~1 F. ?0 Z4 A* y$ R& P& FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 ^+ r; t9 [0 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 U; Z/ k8 y$ Y5 Z# G6 E* [1 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 Q" e3 d( @2 h3 Y3 o9 `3 RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 G1 [6 b- T2 Z$ k6 U3 I} * }8 K/ {3 Y2 [: H) A- O4 f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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