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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 K) c( w! {. k9 d# ginput mcasp_ahclkx,1 f$ Q9 p8 ~6 \- p
input mcasp_aclkx,
. y/ k9 p; O; d! h2 [input axr0,0 e( K' @' A- P2 r1 x
, _1 j% e1 H# t* E+ G& N# Z
output mcasp_afsr,0 H4 Y! d+ W7 q4 ]. i- E( T
output mcasp_ahclkr,
$ [; z7 ], z g2 O/ P% Soutput mcasp_aclkr,
4 s* H2 ]1 n9 p7 t7 @# Loutput axr1,
J% a w4 U5 l assign mcasp_afsr = mcasp_afsx;, F2 w+ X2 L& q m: Z+ g# X
assign mcasp_aclkr = mcasp_aclkx;
4 T/ q, ]% U3 Uassign mcasp_ahclkr = mcasp_ahclkx;, R7 ]8 t; Z3 X' b4 E8 E# B" S
assign axr1 = axr0;
0 W, s; ~1 P& P9 e4 j" I3 Z; M
; P# b/ G7 b1 ^8 A3 `# y$ T7 V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# W' h4 O( Z) R2 l# K) ~3 [& }2 |static void McASPI2SConfigure(void)5 f8 ]7 ^# ~7 f T- {
{6 p, [8 M" p$ T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& Y& y2 Y# p# t! O, Q: K; p& m3 Q* l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& l1 @# q7 [# z; @/ ~& EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& Q6 n# Y- K& U0 v) u* V H0 O+ v' ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! z- {9 z% h9 ~3 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 k1 H: ^; B* e" P$ x. u
MCASP_RX_MODE_DMA);
2 @0 T- H' e0 y$ V. u. m. Q( qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# m! T4 A8 |* V7 {0 A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ t% i8 s, ]: P4 Z" o. V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ j( l; w0 b; h3 `+ m" z0 j3 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* M4 R; Q# q0 ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) ~' O: d1 v9 T7 V3 \6 B5 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# B, T- `; M& K. ]9 S% e, E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, g$ s6 D! p& h% k0 Q2 [: {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) M2 m9 C/ q$ a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ x- N+ o6 x- I! S$ z% |, X0x00, 0xFF); /* configure the clock for transmitter */
1 l# G$ {) H3 k5 j+ K$ ]& wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# {0 G; D1 R, IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 y) H5 D2 J3 ^, A+ {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) N! w+ ^: u9 W$ ]' u! ?% b$ j ?0 }
0x00, 0xFF);
4 O( N! w M. x) P# D( J# x6 D
/* Enable synchronization of RX and TX sections */
1 @6 }( j$ U5 y0 V+ @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' C* s5 }0 L0 b" JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 [/ c: F; e" U/ E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ N$ G! c7 \& [# K3 J, }
** Set the serializers, Currently only one serializer is set as( v/ F: z* f" Y5 S
** transmitter and one serializer as receiver.0 m$ \2 V7 w! @) R: v+ g. B, s
*/
* B4 i& j6 p6 D& y1 T' B {! a1 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); c C$ i& |( {1 L' I0 f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 \/ }9 x8 e+ u4 T. w/ @+ F** Configure the McASP pins
7 K8 }5 z8 f$ k0 g9 o6 ]** Input - Frame Sync, Clock and Serializer Rx' y6 F7 B* u4 H
** Output - Serializer Tx is connected to the input of the codec
" j' r, _- w- M- f6 f% A*/
' ^5 k) p0 j/ D1 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' y0 [; @1 M8 h: o2 P6 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ G% k( T1 R) {' r; ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 y! f2 x- j h| MCASP_PIN_ACLKX8 A3 n+ K& r5 j6 Q
| MCASP_PIN_AHCLKX/ l8 F$ Z" Z0 ~6 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 z9 }' q, C2 m/ ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR g. ~9 V/ ]* W' Q/ p
| MCASP_TX_CLKFAIL 9 l9 v, B6 X+ B7 h' \" S
| MCASP_TX_SYNCERROR
2 G, x: G% S5 w& Z% r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 Q& P/ L! F7 P. A: g0 \0 w8 ?| MCASP_RX_CLKFAIL% s% A* \7 y! F, q8 p1 ]2 @
| MCASP_RX_SYNCERROR
' ^( ~7 L0 }! [% r4 Y# m| MCASP_RX_OVERRUN);% H7 z8 S' a! V% c
} static void I2SDataTxRxActivate(void)
. i3 e, i# J, o+ Y' f{
1 t$ h+ z$ P: v& t1 [+ \8 {/* Start the clocks */
) {. m- K( ]; y" ^# Q9 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 M8 ]$ f z8 D$ ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 l( m6 t% Q6 U' m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. l$ o/ q! O3 X! e TEDMA3_TRIG_MODE_EVENT);
3 _$ K. ]4 K" W2 H- I$ K; gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - S) Y1 i8 L+ l) \, Y# v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 h- \0 s$ q, U4 t4 P1 D2 H3 h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- X5 Y" r `. W) C' j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 \0 X# i6 Y* a% A4 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& k ?7 ^3 J: U* h/ W- B+ L4 m6 u ^0 s: E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( }) {) o: ~8 i4 m. [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' y4 S% _- t2 X @) ?* ^: R; p
} 7 w* |8 d% [. R* Y& h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : t' f4 {/ m3 c
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