|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* ^' P4 T1 U- Y5 |9 ?+ K3 dinput mcasp_ahclkx,& V" E( g1 O$ U# \% l1 a, Z
input mcasp_aclkx,0 x& ]) x- [8 v
input axr0,5 ~0 c; J( D3 k B: ?
' P$ {, v U- woutput mcasp_afsr,+ K0 h9 b, W3 t8 k! b5 c
output mcasp_ahclkr,
# T# [: p' o1 y% l7 d) Routput mcasp_aclkr,
3 W: Q; V$ x4 a4 l) y( Houtput axr1,# e6 ]8 R% M- D$ K# ?4 _
assign mcasp_afsr = mcasp_afsx;. e, k$ K" X" V3 \
assign mcasp_aclkr = mcasp_aclkx;' ]9 ^8 }! Z. ]. O' ?7 X2 i
assign mcasp_ahclkr = mcasp_ahclkx;
3 l# e3 A7 l2 zassign axr1 = axr0;
0 n$ T1 V( e, j# @& E& F# E" u6 y: u1 `$ G$ O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 {; {+ T+ r3 \4 H, E9 i- g
static void McASPI2SConfigure(void)1 `. I1 j8 b1 u) r3 _9 T
{- S. y" Q- v: P% Y) s4 t! ^; B" _0 g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 X/ q" X3 J/ E1 h' cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 m- f3 b. Y0 ^9 O; xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" l. v6 ?) l s$ A9 [6 FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( g, j W# C0 lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. F: N- d- c0 f# q) h: Q
MCASP_RX_MODE_DMA);. @7 y7 g3 n/ \3 D, u( d3 {1 v# N3 Y* Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& H% G# H& {) L4 ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" x. `2 k6 ~& v; d5 Z4 yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / n1 g2 ]/ Y. V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 O! E5 s6 u; [4 l o' lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - a t0 J! L/ _% r; ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ H1 U! B6 ^4 k) l+ ]& u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" i2 x d# B( v9 _! U: ^; a2 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ?+ A. r3 ]+ f# y8 A: C6 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ W: Y; F9 Z; i$ p- W
0x00, 0xFF); /* configure the clock for transmitter */
; N6 U/ H' W0 H* a, V3 oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 r' W3 x( O- d+ b, c0 m+ o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 x5 J! W& ]9 X4 u6 n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! z! u" g2 e+ {9 W+ {0x00, 0xFF);
. q/ G4 Z% r) ~* K$ `3 F& |8 M# u1 F+ f8 b% C; b& M
/* Enable synchronization of RX and TX sections */
/ {9 k0 N6 h% y LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! k; u6 w r2 |; d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( O! _% P7 U# D, V8 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* `2 M4 D3 P5 r5 k** Set the serializers, Currently only one serializer is set as8 f/ g4 i! U- F" j$ u! M
** transmitter and one serializer as receiver., e! Z+ ]6 g2 q9 \, k9 u
*/
. O$ p1 j9 [/ t5 FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
P/ g) Z9 x2 q5 j6 ~% fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 G4 `: r7 {! E
** Configure the McASP pins , g2 [8 H! S* V. e! l+ T
** Input - Frame Sync, Clock and Serializer Rx5 ?+ D4 K1 |5 G* `
** Output - Serializer Tx is connected to the input of the codec & |5 J! y7 g: X$ g# Z& `% [
*/3 @$ p' S5 x4 S+ e$ K; v$ b8 X6 v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& M8 f$ o( h+ P; y1 ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. K9 i( a" s/ o! S' I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: y( H( K6 U/ U
| MCASP_PIN_ACLKX3 Y8 d& _& o$ |- I3 k
| MCASP_PIN_AHCLKX
7 {. j) l7 t! [+ X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# ?0 U$ j- z& v/ `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' o, N' G8 k3 Z% G, ~! \
| MCASP_TX_CLKFAIL " `6 {$ N$ E! z, b" }8 P
| MCASP_TX_SYNCERROR# G8 G K8 t5 U' h( y. G9 J1 ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR o# x) [2 a5 f2 n
| MCASP_RX_CLKFAIL/ j. J7 m+ P# N5 p/ X5 x
| MCASP_RX_SYNCERROR , X" t& v. D. |: p; C% G
| MCASP_RX_OVERRUN);8 L/ o2 V* n; }" ^, }2 S" F
} static void I2SDataTxRxActivate(void)
3 f9 q& \0 f8 ^, z. p/ e{
- q) U) L3 b( ]6 k& X0 t" ?/* Start the clocks */ l6 ? T, S9 G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 p2 X* x" Y/ [* B% G7 v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 `1 p ?! `' R( `; d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 |( @1 A3 W2 }- i
EDMA3_TRIG_MODE_EVENT);9 V0 N% d* A( G: b6 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) T& ]. p# K y, C3 b4 T" zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; s- M$ R9 k% s. k6 A6 K0 w2 o! ^/ X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 m& E* f: |& \/ Q; i. tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( Z9 a: ~* s$ c! s) |; x8 d2 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& z# F1 V) |7 M Z: z( |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 W, B4 t$ i" c: T; q, H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, d6 i" e' P2 h- L L* a8 O2 y2 q}
i7 Y- |2 ^) V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & J H2 J, r' l* f
|