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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' z4 W% s- f0 i' G7 C! L. N) V' sinput mcasp_ahclkx,, t6 ?2 N) L# J- e
input mcasp_aclkx,, ~% o: W: d; v& J9 ~" b
input axr0,
+ U* d a% `& b$ p$ v. h" C3 t4 p: Z
output mcasp_afsr,* d) X8 e1 R! D
output mcasp_ahclkr,0 i. d% _; G3 |& e& G
output mcasp_aclkr,/ u8 C! b: Y& y( o
output axr1,1 T' K5 b2 B- z" U; Z7 u
assign mcasp_afsr = mcasp_afsx;
8 ?/ ~/ ~$ Q" x4 w4 yassign mcasp_aclkr = mcasp_aclkx;1 I7 s* Y2 |. J4 P: [% W0 ]" R# N$ j% \
assign mcasp_ahclkr = mcasp_ahclkx;
+ [* ~5 O0 o: I" p* jassign axr1 = axr0;
1 S% Z" H" V. w: ?
! W+ Q4 B- w( a0 d6 W! Q _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 `1 E4 v% _. D& t$ t" z5 b
static void McASPI2SConfigure(void)' Q9 g8 K9 ~0 v9 f6 M/ A
{ p8 @" @+ m" P7 k$ g) n6 k* z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 [3 J7 g' F+ D) _5 Y gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 E) }2 i) i7 }/ }3 |9 k) O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 m, t; c- b: y7 U- }$ L" V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" J9 b8 _0 U f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 o! n+ p+ C+ a! i
MCASP_RX_MODE_DMA);
5 @& M6 l5 K. zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& j9 D9 [8 R( X: lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 ?2 @& b x$ MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 B: H g: x5 I" A, sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 s% ] P7 k* p% t6 h/ \) [9 L' r2 [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% O" l# s; p8 k2 x# _+ LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
I3 v0 d6 E4 k& MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 E8 q- u- e j5 S! f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( |- t+ v" `( e' |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* c/ o& D+ r7 \7 Y0 ~: a8 x0x00, 0xFF); /* configure the clock for transmitter *// o8 I, J2 p6 H: e+ z3 n0 I( }1 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; o# |) \9 T$ b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : ~3 u" J8 O c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 x1 i* a! m7 f4 P1 t8 x1 r# P0x00, 0xFF);7 X3 W) e7 X3 f& }& [
7 H) N; E3 x& h& |% k( x7 h
/* Enable synchronization of RX and TX sections */
; K; M ^! Y: O2 v% v6 `* ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" d# p8 t u; p+ B6 q' A( `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- i' z9 O- |3 { P6 Y- uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& T }& a5 ^' O5 d** Set the serializers, Currently only one serializer is set as
+ n; t _' G& `** transmitter and one serializer as receiver.
1 p7 b2 v6 f" O- n$ Q*/; A0 ]- w, o1 u+ N2 x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 b# |7 v( q/ M2 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 V) Y1 ~ f) L. Y** Configure the McASP pins / A- S1 v0 o' Y/ {6 A- V( M
** Input - Frame Sync, Clock and Serializer Rx/ K" I2 H( a) u( N+ H' M
** Output - Serializer Tx is connected to the input of the codec
- F$ K- R1 J& ?5 q$ ~8 x+ _5 p/ C6 Y*/2 }7 n4 x( D* {5 {5 Z0 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 |+ `; i2 g2 X7 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! s, O% P+ D# M6 W, k; w- F, P' BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! Q) q9 K' r/ C7 g| MCASP_PIN_ACLKX
2 D u/ r6 D- T% \- b' i| MCASP_PIN_AHCLKX' u; d ^! O' y9 D+ K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 f% Z* b5 f6 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, m2 V% r9 Y) k2 L| MCASP_TX_CLKFAIL
* V0 @* s7 B t2 c: T| MCASP_TX_SYNCERROR
) {4 @% [# y! C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 C h2 v# K2 B2 f| MCASP_RX_CLKFAIL
! }) [+ Y# H ]6 d3 U2 T3 j* A0 u| MCASP_RX_SYNCERROR & l1 B+ j& b, W5 J8 x- y
| MCASP_RX_OVERRUN);
7 T) A( L+ N# ?} static void I2SDataTxRxActivate(void)
: {2 x# ?5 Q3 k& Y# {( K+ u{
9 h$ q. y, I1 s; t. I; n/* Start the clocks */
1 X7 n& o: G+ ?- f+ w" U1 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 v1 \% L `4 `( k( Q7 | EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 x! v/ Q o4 I4 V3 Y5 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 }7 o; q" @$ H l V9 N, l
EDMA3_TRIG_MODE_EVENT);
4 E* W b2 Q% B1 o$ e8 Z+ L; v3 p, FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - L. x. Y+ ?. M- y' e3 [- X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& f) {9 J5 C3 D3 k4 r( y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- y! _" ^. ~# U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& n8 Y% H/ A% x7 t1 W. }) s' [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. C4 m7 m2 I6 {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 ]3 _* q4 n3 h* `1 b! h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% Z2 [! v5 e9 `% x}
, D) U; Q, c! b5 n' ]1 u$ F$ y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( q/ t5 h4 k3 n" G$ Q
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