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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 {( I" P+ E7 x# \2 s$ ]9 |
input mcasp_ahclkx,
) M) Y% ~* P( S+ v$ cinput mcasp_aclkx,% c6 a3 O! [; L" \0 N4 U
input axr0,
. ]8 h2 Q; e, G: c; {3 P5 @1 q0 R0 x% } S! _) A- }, b
output mcasp_afsr,
4 b/ {& m# Y8 R/ |. Q) {- F# ]output mcasp_ahclkr,% M( J6 i5 v M& t1 s; L
output mcasp_aclkr,
7 X( J8 j+ D' t% Ioutput axr1,
( f( c' Z6 S8 w6 C# d assign mcasp_afsr = mcasp_afsx;
, a# g2 z0 W, b- a3 R/ w1 R- Lassign mcasp_aclkr = mcasp_aclkx;
5 [6 j! Q" K- x: I6 `) @1 U6 b! Eassign mcasp_ahclkr = mcasp_ahclkx;
* `, R1 I. ^) I$ x6 b9 J4 p$ U% _/ Jassign axr1 = axr0; ' e# P k" |1 T R1 m0 ~- m
$ ^1 r, S6 K5 x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 @+ h2 P& d3 _0 j8 K
static void McASPI2SConfigure(void)
! X9 E/ H' X+ n: I% V- I, \4 j{" y4 b/ n. S( f* B. {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) Y5 x6 p6 D" ?+ b6 G6 }6 {4 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" u" Y( J$ J. Y0 f4 f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! y& F) ^8 x8 t: a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 G7 J1 Z3 t) ]7 T5 I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* Z0 m4 M8 x+ C3 ^; N( l
MCASP_RX_MODE_DMA);# G: o" [4 }/ {( R, s+ i. d# M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- L/ h$ _, ^3 X) i* s9 H& fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ j: q0 t6 U) j, K7 |. {. NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. X j! |3 M' n% h& l( Y" k3 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ I9 S, e4 H, z5 [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
t9 T2 w3 B" L( ]7 E; pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 J# O! V! ^( I0 b1 X* \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; t1 w! I, u( `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 ]( \& K0 W6 Q. N, O/ g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 j+ A2 H0 j/ m0 M0x00, 0xFF); /* configure the clock for transmitter */9 h& h* [" B6 j0 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' t1 U- C' w) x' a# ^$ I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ B6 U1 u% o3 W1 |2 F' v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ \9 ~: r: {( }. O: E2 m' I& l
0x00, 0xFF);
1 g5 {0 M0 \0 |0 i7 o5 i3 n8 _. b4 A6 k* E8 o) q
/* Enable synchronization of RX and TX sections */
! v% @2 g( U% e" ?8 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- c/ H/ r0 V$ r* }# {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 F2 Q4 ~5 c9 h! ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- Q; G* E! A9 X& I** Set the serializers, Currently only one serializer is set as
, L- E4 R& i: ], Q- _! {** transmitter and one serializer as receiver.
! z0 C6 ] V) I, S( [*/
6 j! Y5 O; ]$ Z1 U0 ]5 d! q0 j. |+ ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 `, u; j5 d/ y0 s) Y' n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! M) I9 @8 q+ N) L** Configure the McASP pins
! d( |- [" I/ B7 V** Input - Frame Sync, Clock and Serializer Rx
3 X* W1 Y5 Z5 @** Output - Serializer Tx is connected to the input of the codec
1 K0 T0 k% h' j) i" [( M" G*/9 S( l7 A0 Z' u' g+ d2 w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ b7 u# _8 e& Y7 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ t9 I( e0 a7 c, qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, u4 ?/ y, b. L
| MCASP_PIN_ACLKX4 I" Z% q" f! r% O
| MCASP_PIN_AHCLKX
/ I, ^& E* e9 @( }- t; x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* K& v; u( i/ [7 _6 @$ yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) u7 g( t: E6 e. Z1 h8 |' E
| MCASP_TX_CLKFAIL
. I$ \: f' N# R4 P7 A| MCASP_TX_SYNCERROR
& k1 P3 e$ d' W2 @: ^& p( D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR O( f2 d; Y |3 h: W
| MCASP_RX_CLKFAIL
% P' `, p( R$ v) E [5 d9 k| MCASP_RX_SYNCERROR # N) K# P9 `6 B, E
| MCASP_RX_OVERRUN);
: e. g8 Y2 R: B: K} static void I2SDataTxRxActivate(void)
0 k( ?( }6 e+ @: I3 M{3 |+ B0 S! o: s% |$ @9 a( _1 ]" ]
/* Start the clocks */) [8 x" }. t% r# j1 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 P7 ?! M" _8 j0 P- n( H) V. _0 J1 Q; kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 [" [ _4 l" v1 q R0 u9 [: A! t/ g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 ]! z. L7 A- X1 n, h/ XEDMA3_TRIG_MODE_EVENT);
- b6 z- h# C1 {6 d5 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! W7 T; b' ?% fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# A b% X/ s2 I4 f) R% z$ p7 n) `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 ~, Z$ t. Z% J" @2 f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 y! i9 G9 S: Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 I9 a3 N5 ^) w* xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 }! j3 i3 }( W: x- {3 _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, Y" `+ k9 O- b5 S9 X, M5 F} ( r' d3 o8 A1 ]" m( ?" u& R% O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + v7 _8 H% m. A' w+ u" s# ~( e8 v
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