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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ } K' y9 o/ I. P3 J: v- r. d
input mcasp_ahclkx,, w1 C4 B2 [) h1 z! P2 s
input mcasp_aclkx,+ \( [( _) ~- E; K' f
input axr0,4 b7 k& P, h( K4 J8 _- X/ J [
/ a) ~2 o Q# z% W5 W" t# r# zoutput mcasp_afsr,7 c% d% N$ j& u, T
output mcasp_ahclkr,
& W! I$ s6 Q; e( G# ]+ voutput mcasp_aclkr,+ X. y; |+ g* | E) ?
output axr1,' t& _4 N/ J/ R v# Z$ M
assign mcasp_afsr = mcasp_afsx;
/ w, L5 _- q6 X" V3 Oassign mcasp_aclkr = mcasp_aclkx;
" t! Y$ o, A, p# {, D( cassign mcasp_ahclkr = mcasp_ahclkx;- t6 @* `+ D" j0 x
assign axr1 = axr0; 2 `* M* u# C+ V
0 `$ a# K* e0 P8 f4 T$ i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( E- c2 `1 R5 M7 k7 K2 N+ a
static void McASPI2SConfigure(void)
) \6 E2 ~0 F2 c9 r; n+ P! N{
% s' u, {2 f8 h% a0 P QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. q; i$ x/ p K& `. B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 q* c! N& z( L/ UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: v1 \' y* N! j: Z; K# ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// O7 E! _4 V0 h; @% G4 @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# p. D: ?8 p+ V# j" l+ G
MCASP_RX_MODE_DMA);- v# |0 @4 V! p+ P( e+ M- Q! C# `; y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' Q. x8 k/ q" G. D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. E* Z# U& \8 |& S' Z9 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* E q1 c3 R9 i: z3 LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 j/ i" p ~& ^6 I: i/ G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & N7 M. o) _6 {) ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( Y1 Y: ^: z. j1 j, g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! c K. v$ {2 H' }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + s# q3 W% `2 S% @5 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 }: h: j$ G: O2 {0x00, 0xFF); /* configure the clock for transmitter */
1 V/ e& `, d; _, A) @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 M6 S$ h) l3 D, Q# ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 f. O- R( T/ `* @& i' ]& E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) m1 }; W9 K7 D" u9 A, Z
0x00, 0xFF);
0 b* o; ~% ~. N0 c" T4 K2 E1 t3 B0 c" E' M
/* Enable synchronization of RX and TX sections */ / ]/ }* O# B) V7 }0 y, j4 Q5 F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' @( |4 C: |7 n, ^: X- FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 j: R+ q$ ^/ zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 }2 g! u$ M" k0 b. O Z& G** Set the serializers, Currently only one serializer is set as
6 Y. @6 q: e4 U' ^. J$ {** transmitter and one serializer as receiver.
- V4 X& c( b2 l, x! o% y7 q*// B: Z6 Y L) W9 Z% N) {( Q" ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ Z7 ^: ]( [" n; Z; ^3 ?5 sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
l9 J) E/ U0 b% N% r0 i** Configure the McASP pins $ I P% {1 A' i0 ?6 B# \
** Input - Frame Sync, Clock and Serializer Rx: x/ p2 V/ k7 R! `! u
** Output - Serializer Tx is connected to the input of the codec
+ Y1 {0 Z$ I, l% S*/
' z, m* t% `$ i; iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& k) ~( m, l4 c5 H r; w. k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! r& K# W: C4 b. O( J) ~$ qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; B- V& ?- U$ A. z9 K8 H6 K: \| MCASP_PIN_ACLKX. z+ \: O( H- x h
| MCASP_PIN_AHCLKX
/ I; e7 Z$ X4 N9 w U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 T( B, @( {0 N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 K/ l* \. f2 g
| MCASP_TX_CLKFAIL
* B3 k) j9 G7 n; A. l: ?| MCASP_TX_SYNCERROR
8 F% B3 p; C% B/ w3 Q- \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) o" y% ?( x i1 E5 Q- D
| MCASP_RX_CLKFAIL: h7 m' ^' ?6 A6 |7 E
| MCASP_RX_SYNCERROR
! B9 v$ |. [0 q| MCASP_RX_OVERRUN);
& ~9 F' z- Z4 D% Z} static void I2SDataTxRxActivate(void)
0 s# x1 y3 r( A5 B- M5 V4 @6 h{
1 m1 k, G% i. X7 n0 M& C* t7 e& w( F: V/* Start the clocks */
) c' ~9 T8 F3 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, \( e; _6 Q* i7 F, D dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 e5 N( Q9 J. H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ j0 g4 p9 ^. G9 V! W1 N+ M
EDMA3_TRIG_MODE_EVENT); \& E, p, M7 s; [/ C6 D5 ^% @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 ]- y5 D1 Q, A) h# ?# h5 T5 m$ MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 }1 ?5 p. E! k' s, _; Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 P9 K9 }8 w. x3 D2 u1 KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ W5 s* Z0 g! G( o: ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ u- S# _* F6 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. M* X: d5 e+ A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% @/ X# }& [4 T/ x
} % k; U. V6 Y# \& E1 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' @- @* a; I, ^ o. w+ U' O! T- o
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