MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
3 R% B" b0 I5 t7 R7 l6 kinput mcasp_ahclkx,
input mcasp_aclkx,
7 e& @9 P1 l6 r  U4 y& ^! ?input axr0,
/ P+ z/ A9 k0 {- a- n! r. X
output mcasp_afsr,
. w2 D* s: M/ A* eoutput mcasp_ahclkr,
output mcasp_aclkr,
% V8 W& d' I- u% r4 uoutput axr1,
' c9 J0 n6 ]5 i* m( p, m

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
" ~  }. ~4 h' r" }+ cassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

1 K4 G, y1 w" C/ N2 w
; a5 E/ r1 q* Y+ X6 m  W

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
- m5 d! b; v6 ]2 ~/ H' w* W& ~{
/ u* U* T% e4 E7 o( HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( r9 W6 n3 T1 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) ?5 w, }! k" Z9 ]0 {' r7 u1 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% T1 y; Q. ^6 @% s& ^) GMCASP_RX_MODE_DMA);
& d- @3 o9 M( e9 b" nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 H- [3 r% E6 D6 S4 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, o) J) J. n3 ]  M: t' UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 [) K  y: q. bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
- m7 L7 H, |* W. i9 y6 ~' JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 L* x0 f0 P, E8 E  U- u7 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. P$ e  `1 m$ BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
3 N& I0 \2 m5 {) J+ a
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
: @7 z# u/ A3 q( r8 i8 d2 L0 p** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
0 l% O5 R* L; |*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 ]* g" X7 n  H1 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
" ?: _3 X, x* d+ T$ r1 E, A9 g9 f+ B** Configure the McASP pins
3 S" E7 ^  U$ W% W** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 `6 M4 V, c& _& a' [- E7 |* K| MCASP_PIN_ACLKX
6 W) a# Q- e  W- q: s. y| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
# T/ p) X- E6 y5 v5 x& FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 I- k& {; Z! f) ?+ y- ^, u| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 }/ W: F: P- S1 w/ Y8 ^| MCASP_RX_CLKFAIL
) f0 w) `. Y7 B. f| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
7 G- v- r; t" m* w' C1 {{
4 w9 d4 z9 O$ I: ^- q- {. e/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
( s9 a5 \2 e$ R- @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# U" b+ \. J( z+ S7 L" C, JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
- }- ~! K5 @5 j- e1 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
6 G7 d0 @- [7 ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ E4 G+ M7 U8 S1 Q- f! Z% Q% z' BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

7 A& A% t! ^7 z3 c0 ?" u9 X

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

8 X, }0 ~- Q3 J4 \1 O- {/ K