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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 b$ k/ ~( a K7 @% }- _" _
input mcasp_ahclkx,, |- V' g) q8 w2 w% G
input mcasp_aclkx,
; \( t# f' K, v0 d; {. x+ g3 I9 Hinput axr0,2 ?: _* S7 @7 p% v( k% g3 G; R6 _4 S
2 ?) S8 U8 Q. t1 o# k# c8 `! W$ a/ I' X
output mcasp_afsr,
& ~$ U4 S% y% ?6 t8 C) L* \3 G, Voutput mcasp_ahclkr,1 O; [" r4 Y5 T q: U0 T: A; }; K
output mcasp_aclkr,
: Z. s4 O" C* P- k8 |" N- ~0 `/ Woutput axr1,* d6 T- b# g& j( x# y+ k. w ]
assign mcasp_afsr = mcasp_afsx;! Q7 y; _ z3 o. ?5 |. U
assign mcasp_aclkr = mcasp_aclkx;+ N e9 K, x& }! f) V% G
assign mcasp_ahclkr = mcasp_ahclkx;$ `6 f# x- ]) q( g5 @9 u, K& i
assign axr1 = axr0; % V9 T' ~" E+ v$ v
K, d* d5 H6 j" f) g9 }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
R5 T. ?3 v8 u& k7 h( X. i$ x% Jstatic void McASPI2SConfigure(void)4 Q/ A# x+ [5 {
{ u, C F2 R" a# } s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 ^6 f# D% c* D" g$ r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 n' O; @- U& h9 z! z7 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, i9 ^/ A; }* D7 B1 y6 I3 C' y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 d4 @8 J* ~3 B8 i4 ]% rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, H9 L$ u4 ^) Q9 H2 ]4 N
MCASP_RX_MODE_DMA);# W& I" S/ `! H. C% K% D& N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ^$ L$ w, |: R L8 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) M2 y9 j9 z! V( `3 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' L: K( n* V1 A1 w! j0 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( {2 \8 [/ R% R! e0 }3 AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 q5 n8 I! B9 y n+ S8 YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: W/ e- ^ w# O- n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- R( z' ^6 E, s8 y4 |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) c/ I m8 b) H6 O( hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 s$ ?5 w0 W( V' O0 W! [( P% L
0x00, 0xFF); /* configure the clock for transmitter */
$ F5 Q: p7 \1 n' U8 cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 P. }# D; }" X( W6 H& b* N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( H0 f1 O9 N3 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; W$ m3 x. J5 [& n8 |0 V0x00, 0xFF);
2 q4 D" [# e3 R4 l8 a) s U; l _. d7 O- w, V% Z; @7 R! z
/* Enable synchronization of RX and TX sections */ 6 U* t% B: g8 v/ d/ O0 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 a# D/ f, X$ g, ~1 L4 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 N j( i' Q: }) C- y! FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 H" j2 g2 E: `" h; n- F: ?) ]** Set the serializers, Currently only one serializer is set as+ D( u, I7 u# S: }% D( I+ t# f
** transmitter and one serializer as receiver.
+ }9 K% E2 M) ~: {, s*/. h5 v! Q3 X% n5 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* z* C0 k& v( ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 }' ?0 ?% d' G. n** Configure the McASP pins
( W% Z5 {/ C" ^** Input - Frame Sync, Clock and Serializer Rx" h9 S7 `7 @7 B+ H, o
** Output - Serializer Tx is connected to the input of the codec
2 ?/ @" E1 R4 \*/4 M. C& X% {" c! H8 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& E: N8 |9 W9 {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- a" u6 m4 n8 n z' hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 X8 O ?/ T0 ?
| MCASP_PIN_ACLKX. `' d6 C2 A5 R7 g7 W/ ^6 p
| MCASP_PIN_AHCLKX
! v# u3 i2 B5 s! F( N1 I# g1 Q* \- k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, |4 |, @# M4 B3 b* Z2 p6 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- x9 D: j2 q; N8 d5 z| MCASP_TX_CLKFAIL & U. F1 k7 z0 X9 r* H
| MCASP_TX_SYNCERROR
( `6 \7 h3 e2 G/ m0 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 u! V i" o/ C; s+ \
| MCASP_RX_CLKFAIL
0 J) b9 _& N+ R0 F3 `1 \; u| MCASP_RX_SYNCERROR
; ]" E& l9 B' H" z& _; c+ p2 A| MCASP_RX_OVERRUN);4 i3 m8 E, z# F! ?8 F1 M
} static void I2SDataTxRxActivate(void)
8 ?5 x# J9 C' E9 o7 a5 Q) h7 X4 L5 D{
, z9 h4 T v* B% Y4 z) X; [/* Start the clocks */1 a0 b( `2 k/ A. y: O$ U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ ~/ L1 D7 B" [+ B7 {4 A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 a& X6 p% U& w6 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# i0 i" n" a% o. pEDMA3_TRIG_MODE_EVENT);; X+ y* e8 P! S# j# V* l, `8 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 C7 W& c2 j& ?+ I' ~$ y) O# O5 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 S* b% ]4 r9 ^& V% {$ M& yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; s* N0 {, ]. ?) a- X/ Q8 n0 X9 K8 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 R4 v0 |' }% `5 @2 rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" w) q5 {8 |1 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- S. Q( D0 L+ X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. E* d7 G" M* w! ]2 G" C( q* e" K9 O6 w
} v* x" O6 G8 u5 Z, t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % a. y3 v2 a& y* q6 c
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