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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; G# }; _$ b9 K
input mcasp_ahclkx,) ?7 R0 {4 Y: {. ~: p
input mcasp_aclkx,# v- ^' j: Z H. o3 r
input axr0,
) M8 F( T( h5 U3 m. y' \
" v6 t, D. |! A4 t1 c$ p7 J, youtput mcasp_afsr,6 {% e& K' p' I! h% m
output mcasp_ahclkr,
! e0 n" M( A Q8 D) `: N2 U1 youtput mcasp_aclkr,
9 g/ w( ^0 K/ J* Z) l0 G; K$ P6 Qoutput axr1,
) e: m4 M0 q7 J/ S) N3 d7 u7 Y assign mcasp_afsr = mcasp_afsx;
( h& X# e$ ^$ t* ^assign mcasp_aclkr = mcasp_aclkx;
. {' u! @8 m$ }) l9 S% Kassign mcasp_ahclkr = mcasp_ahclkx;
& S% w: R7 A" h- L& V/ c- a, zassign axr1 = axr0;
* T# ]# |( Q; ], K( ^# u- K. b m3 o+ n$ v) o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 D* x' s0 m m" f# q; lstatic void McASPI2SConfigure(void)
{, v4 w0 q% z3 V3 }% {0 r{
% J" C0 G+ e# p7 Q# Z. VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: W9 B0 J- m6 |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 a. H- P. [3 W" ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: B- G* p4 H- A& e$ V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. ^3 S! o2 j0 Z& A8 I) n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ c/ K& p! n: |; c7 S
MCASP_RX_MODE_DMA);
8 m0 J9 x+ ]" K0 m" `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) |+ l2 D0 k+ a5 P2 DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 s7 g+ u# B8 h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, r9 ~3 j1 A3 Z/ v; VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 u! k. _/ e. \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # M) Y, y- n! y2 u# T2 e& z6 P `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! T# b, _5 w1 d8 j% s4 u; t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 H) w$ @9 c) ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , F) d" n6 t$ x U* W- [# t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. r% h) I& F! ^. o0 R' r; s) W; \4 X
0x00, 0xFF); /* configure the clock for transmitter */
% x; R! b/ ]0 F* _. i: F# NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- b: t8 }/ Z0 s$ |# y' G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" K# X( C, p2 ?! `9 D$ RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 I, r% K! H& Z* S7 d- H( X0x00, 0xFF);
1 X# F/ c; j" N7 V0 l7 ]3 D2 F3 t1 e0 [
7 e1 q' I5 Z. \9 g/* Enable synchronization of RX and TX sections */
6 M" g1 t u/ p ^5 kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 u s3 H4 h* ^+ p# RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! L1 A e. ?8 }' E: j3 O l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 m% k1 W3 F B1 |6 z
** Set the serializers, Currently only one serializer is set as$ n+ D2 w5 K& d, i
** transmitter and one serializer as receiver.
2 n& Y8 c$ J3 v. [*/
9 B! T- U( V" w' ^ b1 k* f5 qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; V$ A: t, X/ [* O. `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; j& c4 }# ~. x1 |; \2 [7 S
** Configure the McASP pins
! s; a$ ~; I8 F* n** Input - Frame Sync, Clock and Serializer Rx4 B2 e, J4 Z* @ G1 u
** Output - Serializer Tx is connected to the input of the codec " E0 B, t3 ]# Q/ M3 `
*/! Z5 B. Q- o0 @* B5 o8 `3 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 h. m( U+ |) Z# v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; Q2 W5 a( q5 r6 S4 L% ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- r: n ?7 J1 Q) Z& Y' ?0 R/ X| MCASP_PIN_ACLKX
. t8 @# l, E& I; _) V, c| MCASP_PIN_AHCLKX) i8 p0 G9 h, o- f# s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 _8 ]) u2 V( h$ R+ O, YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( N0 P( A" s2 G) H& k
| MCASP_TX_CLKFAIL ) r( L F: B4 K% \
| MCASP_TX_SYNCERROR
& ?- f1 M# P- q! _/ E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " R* N# s# z( d) `; L4 J+ C
| MCASP_RX_CLKFAIL
$ k. Z# c8 y( P* q' N1 P| MCASP_RX_SYNCERROR
2 R7 N3 z y2 `3 T& B3 M9 D| MCASP_RX_OVERRUN);9 c7 L& r# S7 W+ z
} static void I2SDataTxRxActivate(void)
4 ~$ @7 M w$ [3 S: ]' ?{7 D1 d* t3 ^7 B
/* Start the clocks */* ^" B! J$ a. A+ ~2 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 s0 C0 m- m. h4 Z1 O# Q- T8 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- a: F3 w5 b+ |, u* g5 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 S+ g$ |1 d9 }' o" K" B8 N. k
EDMA3_TRIG_MODE_EVENT);
6 C5 \4 N8 Y- sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ G! \7 u' h T# {, A& {, D% H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
q5 i2 [8 H! V3 i ^$ m" [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! y! u3 ^4 Q y: A! Z/ JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 l/ x- u. f# z% W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) P- o5 v9 |6 w: D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 _- O6 M3 v7 H' ~( XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 s* O$ j. I8 j# Q: g
} / l# i5 F: W2 c6 D4 A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 r! B" a# A& f' U+ `
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