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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," W: B5 D- f" b1 F; t
input mcasp_ahclkx,
}7 ]! m0 J. binput mcasp_aclkx,
* U9 o# r, ]8 F0 G% minput axr0,* [( T6 z: F; u$ l$ }+ \
- U& h# W% t2 K, r5 q; O1 B$ Soutput mcasp_afsr,# C7 \, s( F2 S7 S( Z: B/ c P
output mcasp_ahclkr,
1 Z. `, S! H$ h- _output mcasp_aclkr,
5 u) X( y3 k2 [; m U1 U* @output axr1,
& X O7 A5 d2 C5 v assign mcasp_afsr = mcasp_afsx;3 n8 W* n+ [/ A6 t$ B3 v+ j
assign mcasp_aclkr = mcasp_aclkx;3 e3 `& K0 c* W& ]& i" ^+ `! ~& I
assign mcasp_ahclkr = mcasp_ahclkx;
9 w7 D9 o! M- s' ]5 B7 g [$ A' F4 Nassign axr1 = axr0; & {8 P8 t% e$ L
- j% n+ r0 `8 k$ ?7 L/ X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % g0 j; P9 {2 P% n
static void McASPI2SConfigure(void)
d9 j6 e/ P3 N{
2 r9 |! }" }) k! p \6 x/ U6 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 h# V% m! K( Q& y0 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" v! S% R/ \5 z* ?# @: NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 W4 G' ]- l v+ n+ }: U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 L; Q5 i) |3 y, V" K. {+ D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ [) H; e7 [5 KMCASP_RX_MODE_DMA);! O' d+ I6 s2 a Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 ?1 [' d' }1 X# ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! p3 Y1 c1 q! H8 l1 k; ^+ j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 y2 t$ ]7 M1 n. u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 Z5 D' `) L; }4 E4 o- SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; X }& I% ?* |! m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 s7 W! m- f6 `9 {( v# BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
^0 U' W) t( u- `4 Y. @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 h. o9 o2 F4 \( {/ c6 d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 K* ~2 k) n/ ?8 T0 b5 d6 I: P
0x00, 0xFF); /* configure the clock for transmitter */7 v O/ U7 P9 G) R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: c' f. ?4 }: C( @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% W% M+ W; O( xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! F T9 }. r: @( d) t* J
0x00, 0xFF);
" | A n7 A. b! m. W7 \5 d* |, Y7 C( t7 o: y* F
/* Enable synchronization of RX and TX sections */ 8 N' w$ q' Y; x& ^2 |8 F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" s- B( I# ?6 Q8 N, o( b3 FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, c @& U8 d; d- Y/ K4 lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' L7 S; B& i4 |4 V** Set the serializers, Currently only one serializer is set as* } w+ Y1 M) n7 O t4 ^
** transmitter and one serializer as receiver.
& t' M6 ?- T. O- h% L/ Y% [*/
1 ~1 H+ f' A. u) a4 y- g6 k; UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 `! a( S& z2 `7 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) j. H2 R6 S2 v( m' `** Configure the McASP pins 3 r; m! F o) \' | X' Q
** Input - Frame Sync, Clock and Serializer Rx
0 A+ x1 O- C% }6 t8 ?" ~" W" w6 p A# u** Output - Serializer Tx is connected to the input of the codec ' k6 {& ^' F, W
*/( m! y _" |* q1 i0 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 x$ w5 c1 K ^+ G; AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 M2 x' [/ @; W. ?$ R: m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% J, ]/ ]; z1 f" m| MCASP_PIN_ACLKX9 |7 X0 `& E3 n9 `
| MCASP_PIN_AHCLKX
9 l( J" M3 t5 H% @- E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' l, R8 j0 g+ t$ b0 Y/ J8 ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) N; W3 _/ L& L. o6 V
| MCASP_TX_CLKFAIL 6 l- |7 }* m, L1 [6 f, u
| MCASP_TX_SYNCERROR6 L( |& `, S' {1 r( h* R* m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ w: l5 |' P6 r8 O; |5 x| MCASP_RX_CLKFAIL
# V0 H. s( c h) z, I. c& I4 _| MCASP_RX_SYNCERROR
8 N7 ^6 k4 X6 D0 S; q2 O4 J8 n' U| MCASP_RX_OVERRUN);$ p$ [' [, Z/ z: `
} static void I2SDataTxRxActivate(void)
+ H5 r$ x4 b! J' V& N) e& G, D{. Z% A# J( M, L2 S D9 n4 X
/* Start the clocks */! F. k: w! X3 O/ a6 `* ]& r& O$ L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% i) T6 x' g2 G+ {; y/ LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. n" S; f: u8 G; G/ z5 e: EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, ? g0 b' V0 s' a p$ z8 [! REDMA3_TRIG_MODE_EVENT);. n/ c5 x- v% F" y, B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 f1 B8 I U; _3 X8 C4 [# |' H; l: y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& H9 ^* h- V' c- E/ b# v$ t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- w- ~# Y- M% @4 ?# F8 w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 E) x% \" G3 w& M9 k) p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ N: N) z5 g. v+ Z8 w9 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 ~9 P# D1 k2 y: r- h/ s' q/ WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* r+ E* W; c$ ]% ~% s7 n
} ; d8 A" N7 I7 @+ l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 d1 M5 w% q/ V
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