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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ E$ E2 c) s' L0 ^' Ginput mcasp_ahclkx,
4 f& U, J3 q3 N( u4 {input mcasp_aclkx,
: W. h3 n( ?9 j/ {input axr0,
; N+ I3 l7 l/ a8 x" l6 @$ i! [! ~& Y+ ^1 q# d
output mcasp_afsr,! j9 f4 `# f' M' c
output mcasp_ahclkr,5 G7 F0 {5 E' ^$ Y
output mcasp_aclkr,9 q6 c# l- D9 W5 Q1 h
output axr1,3 N7 L4 N. z: s$ F: g. p0 [
assign mcasp_afsr = mcasp_afsx;4 g) b' L0 p0 l3 R X' u! U- b* D
assign mcasp_aclkr = mcasp_aclkx;
( R. b$ N( O# K* @: W6 t8 w7 P- Qassign mcasp_ahclkr = mcasp_ahclkx;; r" n( E9 ~. {" t2 y
assign axr1 = axr0; ; G) p. [) ]: y6 k6 W
+ v$ T, Q6 r; ^$ F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 X1 ^. D: ]7 t8 e/ M6 `0 \0 d
static void McASPI2SConfigure(void)1 N3 P' r" ?. a
{
! W P1 I6 y2 f) I" [! fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 K! ^9 ?4 O; G; ~/ H) s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" z S2 Y4 x0 [9 N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 g# x; M* Q$ W+ Y, A3 ^" ]' w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- p: j6 c, [% L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ k# w% i. [0 B& ZMCASP_RX_MODE_DMA);
0 M7 O# p0 C; P" hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' T# Z0 K! F% n. nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 v8 E, O T+ W ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; |5 K. C7 ?& ?) h7 `/ x& xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); e9 D$ ^. n7 B! c9 t' j0 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% j- ?# ~6 `5 ~5 }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ D+ d. d, ^! H9 g& w8 G( sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ b6 {& Q* U; UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% M3 j+ f# \8 a$ B: q% OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 Q0 D/ W& D' c' D+ l% t) }) Z" { K0x00, 0xFF); /* configure the clock for transmitter */7 O: G; V! e3 f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& z/ k- K u; E* g% o. c. fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, X* X: h5 `0 kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ J. Y B9 C9 g8 ^0x00, 0xFF);
2 M, F+ }3 ~2 m+ _1 l+ g5 A
u& {& H8 X' u3 o/ C/* Enable synchronization of RX and TX sections */
5 @7 B# t% d0 m( I$ W6 p' m% QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 q; p/ Q- j) K8 F% c, w4 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% N' g$ ]4 p8 P* q+ WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 o, M' L/ A0 p0 p: m- Y: L0 `" K** Set the serializers, Currently only one serializer is set as
6 Z6 S, p. P% h0 K o ^6 A** transmitter and one serializer as receiver.
, f/ R8 h z, t6 k1 ?( c*/+ x9 X; [+ `" M* P* Z, @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 O1 Y# l9 Y% J4 a h. U8 r/ a5 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" { d |, G! e F9 G- ~
** Configure the McASP pins
# F+ G; Q5 p6 e& W% u) ]( O** Input - Frame Sync, Clock and Serializer Rx
0 [/ |9 j/ O( n s** Output - Serializer Tx is connected to the input of the codec % R8 c" L8 [9 a6 i
*/6 r5 B p4 s8 G; G8 X5 f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, o; c2 k$ z, e" {5 I8 }% R; _5 {( {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% a1 l) A0 _, C! u7 j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 m' J- ]# z3 o& s/ S8 u9 C| MCASP_PIN_ACLKX% y& v+ N- r: \3 R
| MCASP_PIN_AHCLKX
+ Z# D: D! x6 L0 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: W% m+ Y. q( y; L) h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . d) @" {: a" b. g+ e
| MCASP_TX_CLKFAIL ; C7 N) j: f: T8 C
| MCASP_TX_SYNCERROR
7 X; Z0 e) s' O- U; g; \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ l$ x o" o" t) {| MCASP_RX_CLKFAIL% `$ [% X4 x5 M2 n
| MCASP_RX_SYNCERROR 1 k1 z7 \8 M0 b2 h+ D: a6 {5 [
| MCASP_RX_OVERRUN);9 q% s7 a( a% ]& k! `
} static void I2SDataTxRxActivate(void)7 C! E3 W2 K6 Y4 x
{* P( w7 Q3 n. u# ^7 d+ [; F& }) i
/* Start the clocks */8 w4 ^+ j" p; [; j K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ |1 Z( U/ j% K) v" M3 p* t7 J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* S* ^# S# X0 I9 F( [* L, J3 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
Q# f1 c* X- q" ]' o. |EDMA3_TRIG_MODE_EVENT);
9 [2 f! N a! ` T3 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & i" Y1 O2 C3 M6 ^5 }5 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 i* ~8 g k8 U, zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ A3 w! c2 l$ g& y; _& r9 G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- p5 h* K' ^/ c( N: ~1 u3 W4 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; O0 g2 F( d1 }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 U/ H& T3 R7 L& U; c1 c) v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' I5 W7 M, i+ `}
* i8 g0 `5 \$ Z1 Q1 z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; b$ Z F# f# `0 v
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