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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, v# H# \8 b1 a* e) W
input mcasp_ahclkx,
& Y8 F5 x/ I. F6 `input mcasp_aclkx,+ a# |. I" S; s% D' v0 s) n. K
input axr0,
# G; [- |. {# D& v7 x7 }. K" r; B' @9 \1 p9 D8 I2 }) s& ?
output mcasp_afsr,1 V/ G3 ?& o& ~ Z
output mcasp_ahclkr,
( D4 W! `7 s% ^% m7 P! K" X O$ xoutput mcasp_aclkr,
+ d% }3 N9 C, ^3 M0 x% J* t( Soutput axr1,& c! S! G p" @
assign mcasp_afsr = mcasp_afsx;* E& l8 q- V/ {, j) {" D
assign mcasp_aclkr = mcasp_aclkx;2 V8 X0 [& S; f1 n2 H) t
assign mcasp_ahclkr = mcasp_ahclkx;
* P& Y. R( h7 O; N) H" m9 f' Oassign axr1 = axr0;
, g4 L% N, `6 H p7 }* d4 x
2 o8 b, k6 P: @/ R6 u% D T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! B! ?8 _) \6 e. u* M. S
static void McASPI2SConfigure(void)9 t# T/ }7 N! u9 {- _) L- ]
{8 T$ o2 S. O9 k3 u2 F& B% A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" y9 h% v" d$ o! N7 sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 @7 s& M" | M2 j0 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! M, G3 x: u6 y9 P9 vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" Z5 \9 n0 T; z& X2 M" X0 g+ w7 h1 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' N) G [ `2 [6 \; M
MCASP_RX_MODE_DMA);& u' e: E6 U! Y& i1 m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 }* }! F, |& s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 z& ^0 s) \0 p2 M! JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' h1 U( H# h; |/ Z' v; _6 r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# d. S$ b( i, {" P6 d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 S: u& N3 r; ]: C7 g1 Z& Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ F" z" Q2 D- Y6 ]! z5 v6 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; }, m; D; M+ R8 b6 V0 yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 d- A2 p) O6 m }9 i+ RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; {7 w4 t8 {/ C7 a$ U- R
0x00, 0xFF); /* configure the clock for transmitter */8 m: L; u# ?1 r# ~( v; X. L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' _# Y. @7 t' C4 G- l VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 s( D: [$ o4 ~/ w2 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 f) v) y' ^( v0x00, 0xFF);, Y- D- K. A: J1 L3 B+ x
0 w o* Z: M* R# w! N! Y) |! A% M
/* Enable synchronization of RX and TX sections */ : T% a. a( ?! }2 w( _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 R- B; |4 o- M! O7 P9 UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. q7 N( k' Z6 P- K/ e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- [& Y9 }8 e2 Y1 w \) }, m** Set the serializers, Currently only one serializer is set as4 a- d) q# v0 [: X" s" c2 _# M
** transmitter and one serializer as receiver.% {- x2 o% D8 K* R2 E5 z. f& C+ _
*// T1 N4 u& N7 I& d0 F( m2 `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! I7 a7 Z# {& V: w( s3 d" A8 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! M# |9 L5 f& O. B
** Configure the McASP pins * E* q% p9 D+ a1 N& c
** Input - Frame Sync, Clock and Serializer Rx" Y4 b+ }% T- X& n6 v3 a# F
** Output - Serializer Tx is connected to the input of the codec
c4 Q+ j# z% {6 Z*/
* P( j/ m- l O2 I* Y2 j' j5 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& o4 r3 i9 E, L3 r" v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 p9 r* L; D6 y& @1 D8 C5 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 H! o. G6 p1 L$ _| MCASP_PIN_ACLKX
: f$ `* G$ E {$ K0 l! ]. Y| MCASP_PIN_AHCLKX
4 {; t q( U5 M& j3 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ s/ `- J6 T. d1 R8 k+ A6 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. U$ N0 \, Z& J6 [7 a3 Y, c| MCASP_TX_CLKFAIL ; o: L% y I( F, o: Q
| MCASP_TX_SYNCERROR
/ Q+ z; f2 \, X4 @% Z4 `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 s4 S. a! |3 Q j0 y ~( j& Y| MCASP_RX_CLKFAIL7 } K* x1 l$ e5 h
| MCASP_RX_SYNCERROR
6 n3 y: C, M+ N5 c" ]- o& R3 @1 u| MCASP_RX_OVERRUN);+ h3 q% o/ S+ s {3 Q1 A
} static void I2SDataTxRxActivate(void)6 j0 p. ~. q; X9 [8 c$ F2 i
{
& ~0 ~/ |3 `5 Q8 r9 t) G. m2 k) j/* Start the clocks */
. I7 b% e& L' H9 |6 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, [% \! z7 [/ `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ @3 P z) _3 E9 E. s- J5 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, B# U2 q* H! [) B
EDMA3_TRIG_MODE_EVENT);
6 L' g1 p, m( f% q4 X( A6 V0 l( U8 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # B% N( l& W7 z, G; f8 P$ Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 x0 u% H# q [) TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 ]* {- V4 |6 h7 O7 l. `5 F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% k+ B+ m* g% z2 M+ ]% W& _, j1 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 d% i0 |7 d) @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" s2 M! `: m9 n, W' h6 a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ U' [& g' }; a4 @5 `} 7 j& ^, @6 t4 U$ O% @ W/ E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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