MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
/ `3 r+ G% q1 E( k) v$ tinput mcasp_ahclkx,
" ]* ?% Q1 u# t! @' V5 finput mcasp_aclkx,
input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
9 x3 }/ Z: Q$ h: boutput axr1,

assign mcasp_afsr = mcasp_afsx;
( p3 e, s1 [/ W( X1 Z9 @assign mcasp_aclkr = mcasp_aclkx;
& y) [: M8 q, H6 d7 f. A3 Yassign mcasp_ahclkr = mcasp_ahclkx;
7 P& J+ {( u; y' }0 h5 J+ U# nassign axr1 = axr0;

0 K( r& L. b/ A6 k# X( F8 ~
* X' }/ R$ h: E

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
' I6 b; g  t% {9 F{
7 U- y5 e7 f! \2 \* jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ v( [3 c, Z3 l" w% V. WMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
1 q& l7 c$ R% Z3 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- Y% R( p0 _6 D- l/ L4 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
" Z- O, G$ x6 A4 T& pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: p3 e9 Q# V) r2 XMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ E: h: I: y9 C5 `: V8 f7 W! j; CMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 H/ v  {  G' J5 O5 i6 dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 p; Z! K; K3 |- m  o! {0 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 Z* g5 q4 L0 f7 P  r1 CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 s+ `2 F9 s* W; N5 K# Y: NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 `2 d% o3 F+ x, [3 f! Z; d0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& R6 G1 a+ O; ^* L" T3 [  b7 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 \* l0 J6 [5 k: G1 f, I2 o0x00, 0xFF);
% W, V! C# D2 T. ]3 p+ A
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
) h3 v  G3 M! a5 P! M" j9 tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
5 C5 |) L$ {% `' `** Set the serializers, Currently only one serializer is set as
7 T7 D! h$ e7 r- ?# N; V8 }+ d** transmitter and one serializer as receiver.
8 M5 x: T9 g" n; D$ I*/
) x6 D& A8 g: ?) n* e0 cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, ]; [, k: k) {: kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
6 P& [) b$ Y) T( w0 N) c: E' _1 \/ u** Output - Serializer Tx is connected to the input of the codec
: s  d/ y% Y; O' Q' u" n! U# |*/
$ X$ H$ d! `' M: q. h" PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ U* L" S# x) }9 [  R5 M- fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 G% k( c" B5 \: ^( Q  L2 k: bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
8 O7 f* X* Y1 s0 Q| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
. t3 m* j; a! _* K# [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
: K9 y9 [3 }! i9 ^) }  b0 \) n| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 ]8 ~" j& T3 j6 O3 n0 j: G| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
/ o8 Y; n+ f& c* i| MCASP_RX_OVERRUN);
6 s& [6 i$ o' g& R}

static void I2SDataTxRxActivate(void)
* Y' o: ~" s6 _+ H4 p# S{
/ v! T6 M1 B9 x8 C/* Start the clocks */
  a! ~( w7 I) i; Q( AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
2 S( r: y' x( o9 q! E6 w, {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
* r0 e2 B, ^, k& @4 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
& m9 T, `- e8 ?$ E  o1 @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
% p) M+ e2 k, u. Z7 |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 F: u+ E3 M% }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.