MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
% R3 i( y* T! k) {' b6 X! t5 winput mcasp_ahclkx,
5 a2 w/ K: c; |7 W1 V0 Sinput mcasp_aclkx,
input axr0,
8 K2 W2 X0 `- e7 c4 m1 k, ]
output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
, o9 C$ F8 _1 }2 B( `output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
3 t2 _0 Z5 t6 U- ]# Q# c1 Eassign axr1 = axr0;

8 c3 K9 P! h& y1 {. {
3 ^( _# ~/ o# Y) {6 `

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

$ R) A2 h( q8 Z

static void McASPI2SConfigure(void)
{
, |* K; D6 t- G8 m* C: F% oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ I6 d) J5 m" q9 K+ |+ Q# yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
/ h) A( p3 c7 N+ \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- k* o: g2 G/ N8 Y# c$ jMCASP_RX_MODE_DMA);
8 {7 L6 R3 a: ]$ ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' e) `2 B% S$ S4 ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ m* `1 T& |7 ?! N3 u; s) s! U$ ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 ]# s3 O4 p* m  Z+ p: g3 @" i1 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 Z5 }7 R  F9 g" n' {$ P% k' K2 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' T2 g! v1 u) }4 e0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! G2 C; R' o2 p9 X% J+ j- W4 M6 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! R7 I. a% R8 l% UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- Q( W( k& ^7 }- U  ?/ U0x00, 0xFF);

) O6 G/ x; f! F! t* z3 S# K/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
. h' L  M4 ~# \+ u( @; @- pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 k( S- ?6 A. ^* w% H8 u- Q# _  bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
( w* A- q: V, B1 [6 s$ }5 E- `** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ V8 H# c9 p0 ?5 e5 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
6 e5 k: ?. S$ C+ M5 f; A% ~** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
# r% L0 F% E1 z, r; a/ d** Output - Serializer Tx is connected to the input of the codec
" I5 Z5 `8 }5 i3 W*/
) {/ h4 t  I- _, B/ k. Z8 y: ^+ XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) `# m: u( e& J& ~/ v. OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' n0 c# e' {  k4 p" `| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
  v7 ~6 F; t( n/ d5 M| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
3 w7 |" N( u# E8 c( C| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; i( T& ~9 [2 w5 o0 `| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
4 j9 K* ?* O& |3 ^' o2 t$ G| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( N9 e5 ~3 q' G' ^/ JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! P7 ]7 V* a  d9 L' r" G7 YEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; S( {+ z4 V2 y) Y4 h% H}

, Y4 H2 Y; U: R' ?: f! s* ~3 o" K7 P

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.