MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
0 D9 G2 P- {8 f& Qinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

0 G* F& q* M' M' Y1 Q2 Woutput mcasp_afsr,
* v* Z% e- k7 f6 w: ~3 b$ Goutput mcasp_ahclkr,
2 _/ b4 ]- z6 A% b3 [% Doutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
" e) k  n( J: f" u2 [& _assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

: ]  h; c5 Z4 x% e5 h
$ T: P: A# e0 g+ i+ g/ a

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
4 ]4 k0 i, g: B0 dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 X- ], A3 u2 [. @! ~0 e# i$ [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
  Z! F0 j9 R% _3 `7 K8 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
  s- s; L+ i2 N- ]MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! t0 p. Y2 h. {, v7 E; \MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ F# k4 s; v9 V. U- z& {) CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( A7 k) ?5 q" x- N5 y- \+ N: NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ P+ Q/ u' t& \% W+ f+ {5 r3 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' Y! F- U9 a( @; i0 e0x00, 0xFF);

/* configure the clock for transmitter */
7 D) Q6 J1 N& \5 Q) @5 @4 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: [1 I, }4 U5 i4 w2 f, M0 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 y6 }; c- k$ y/ BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
/ v: V' g9 G; U5 M; ?" N9 M
/* Enable synchronization of RX and TX sections */
8 a; K1 B7 w  h' i, rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 p; f( m1 p# d" }( C! zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
  k0 N+ D6 e4 z* O. n*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
4 `! E9 z# x1 u2 L* `** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
3 V' c4 t$ h" t, q*/
- h7 S- ^* K! H. l2 _, kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% M" M# b! Q/ N: Z. |0 H; PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 T, ?. [* d8 K4 V2 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 @9 N4 D# L# V" |* [| MCASP_PIN_ACLKX
+ s: \1 L" l! _2 T. V| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
$ S  ~6 N! E' u2 YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) a: q) t! {) ?  s" S| MCASP_TX_CLKFAIL
7 u5 P* \2 M% v| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
$ n8 E% m& y* D% O% t| MCASP_RX_SYNCERROR
5 z8 m+ u  R5 o( A6 K7 e| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
- I# t5 c% z2 K7 P2 I+ m, O/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# J1 ~4 |8 d: _- G! CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
7 L0 r3 g! z' }& }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 a' |) `6 s1 P  ^7 l3 ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
& b$ x9 q3 i& A' I6 TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
6 D& w0 V" ^" }' ]7 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 @* Z  h3 Q5 o# IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% I9 b$ a, E0 V}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.