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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, F, V; K; K. e$ Z# t; t
input mcasp_ahclkx,2 Y* K5 K" J% h8 E
input mcasp_aclkx,2 r& E0 a# O( f6 d7 O8 E
input axr0,
7 y; h5 h2 J4 ?0 J; h& \5 T3 e$ Z$ N3 x( K1 q8 _ m
output mcasp_afsr,
2 Q* M! H9 W6 P* ?; G: Youtput mcasp_ahclkr,; p$ O: P+ U% v5 Y! M
output mcasp_aclkr,/ ]- a2 W# A7 W' \- w6 N0 g" Y
output axr1,
, g6 v" C% ], \' ~" S8 k assign mcasp_afsr = mcasp_afsx;
$ P9 Q5 j* M' u+ \9 \, U$ ]assign mcasp_aclkr = mcasp_aclkx;' \' Q5 M2 m# ]2 m4 R5 @3 [
assign mcasp_ahclkr = mcasp_ahclkx;
. {- S$ m9 ?: l8 f! l0 wassign axr1 = axr0; 6 A2 L) L2 k7 k+ `
9 o( U. \; X9 x* O' t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 D: x: _9 V6 W, L4 r2 H. J: u& s& m
static void McASPI2SConfigure(void)" q: Z% G8 {- o7 ^
{
- f, I$ n2 ]: }" p0 x' F* WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 c* t; V5 B$ @6 L4 i8 m7 O3 oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ [: S; A' n, p; J" M9 l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# @5 Q: g: o5 j# X0 s, sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. ^3 f, |% @. p2 x% g2 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Q7 M5 u- _+ ~0 c/ n8 x# oMCASP_RX_MODE_DMA);
4 j% S! o6 z: jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ z+ O5 A0 a! [3 {5 G* nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" b$ A+ E( k( H7 QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & ~; i5 T' M ?2 Z E' Q+ \' U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 y6 {$ L# F& n# R+ r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( V" b4 W* c; h) b" _0 U$ i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ q3 q( ~0 C6 Y( FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- F( C1 T; ?" ~0 C3 u1 P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 w2 ]# f$ F% l8 F- R6 r& ~" m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 ~3 V* b) c& b9 e# l- ?
0x00, 0xFF); /* configure the clock for transmitter */
. H: K2 L) O5 FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 v4 ]3 ^- x( E" s0 j* l0 S4 fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 ]. a6 i9 J2 T; S0 M: `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, f. n3 s$ R( t% d% ]$ W3 ?/ p2 o! H$ k
0x00, 0xFF);
; \7 H# u+ d4 [' J( g
( U' o3 P) _! [- p/* Enable synchronization of RX and TX sections */
% o- v8 y/ A0 q& N& P& j5 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* h% M1 d% X) O$ q$ m* N% [+ @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ l0 S* c/ `" s5 G3 Z5 q! Y+ R7 V8 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 k. z6 W& z1 o s, G** Set the serializers, Currently only one serializer is set as
|( ?, K" S: [; W- E# v( y** transmitter and one serializer as receiver.. G+ r3 D% _2 w, b- z) ^
*/
" Q) W( S, U2 g+ EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- ^6 M& L+ d: R7 r2 |0 VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* t ?7 j0 }" r8 w** Configure the McASP pins
3 `4 H- j( h7 o3 e9 O+ e** Input - Frame Sync, Clock and Serializer Rx
* s: B- j: y5 P$ [** Output - Serializer Tx is connected to the input of the codec ; P y( [0 @1 ^
*/
3 V; `# u- u% iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" ^- \1 H/ F9 B! e3 q s1 e H( RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ H5 M) z( r8 t$ P4 p- }1 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ T+ i4 H' U( B; q5 o% w| MCASP_PIN_ACLKX
3 x, ~$ h4 W* d0 r| MCASP_PIN_AHCLKX
( }' ?- {2 b0 M' I1 w& j1 R1 J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 x/ m2 n; K( aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 U) m4 a" g4 Z# O/ g% Y| MCASP_TX_CLKFAIL
. p6 r: u L0 t: C| MCASP_TX_SYNCERROR
+ S, q) X2 _) N7 p- C. h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& w4 D( n7 h4 P% q4 n6 N; || MCASP_RX_CLKFAIL
) w Q8 ~7 i! `4 Z# I| MCASP_RX_SYNCERROR
$ u4 w; K8 A6 `. Z2 v) P| MCASP_RX_OVERRUN);$ K+ z' q- T' o8 q. g9 Z
} static void I2SDataTxRxActivate(void)$ ?, i0 q- k( {% ^. w
{
8 p- t- f" i. U# q, N/ ]/* Start the clocks */. K, B" F; {" b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 O/ K( U P$ CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" K' G* O& H2 X# v* `# L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" |) j' `* \* H2 bEDMA3_TRIG_MODE_EVENT);
5 K! L* j# o% O! M# j- V# a lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ v# j. Q6 v i" e2 V0 {3 T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* i2 q# F; r; M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 M/ a% c) ~7 T0 }' G# j4 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 x- W' Z1 P6 y6 n. twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 N/ f# i4 o; \; `( ~; TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) Z* C' _- t6 ]5 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 Q j1 j6 \* J: j! Z7 X
} 0 ~8 y& r: N# G/ S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 h0 H ~& ?8 l% F
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