|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( t7 B/ i7 O* Z j5 y4 Y+ x. Binput mcasp_ahclkx,
9 a- h) n' h& q7 X4 C% Binput mcasp_aclkx,
2 j. Z% V: I o6 \8 y/ `* |input axr0,
8 U" Y% H" \% ]7 R: e+ a% B6 S U, _+ j# h
output mcasp_afsr,! @$ e! ^9 l9 _# _5 o% R+ h
output mcasp_ahclkr,
* e" g4 H4 @$ m, M3 {. \' ioutput mcasp_aclkr,$ G" Q6 ^3 u: W( O4 [9 Y
output axr1,
$ b2 |) M9 k8 B assign mcasp_afsr = mcasp_afsx;" `5 J/ W% {$ Z [
assign mcasp_aclkr = mcasp_aclkx;
6 E0 B/ D7 z: h0 ~assign mcasp_ahclkr = mcasp_ahclkx;1 o$ p# r' Z9 G* u7 _
assign axr1 = axr0;
6 K4 T( y s- h" c$ C' K' F, w& X3 ^: S, I6 C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - [6 M3 R: A6 K* i2 Z9 C* C N, `
static void McASPI2SConfigure(void); B& K. p; u0 d) e2 y0 Q% D2 m; w/ w
{% w: D4 v$ d8 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( j% I |. T2 O g7 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: _4 E* {( Z' X6 `- g5 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 c, S0 D$ e, V# D! g( I* N1 p& t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 g Z r2 y8 u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 n1 B$ z4 n) q4 Z! C1 J
MCASP_RX_MODE_DMA);
" h4 |2 j8 M/ i" Y% [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) U k/ l ?( T1 J1 | R- ^1 {& RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ y* x% T: Y P2 Y( c& t8 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . G; I5 n1 ~! T: t6 D0 Q( M5 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 R0 p' K' l6 ?4 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ [2 b& ?8 B4 B4 WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 l6 U3 Y; x+ O! I8 R4 E/ N+ p9 fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 a& ?" v; l& k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) M' [# _$ ?7 k4 n) nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, f! ~2 d4 i& ]0x00, 0xFF); /* configure the clock for transmitter */
1 O; B j- Y }+ g5 M: A# XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! R5 M, w. ^. M0 g7 t vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; M% j& K* @0 h8 T" {) F$ BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 U( b, j% ^: X; T9 N
0x00, 0xFF);
$ n! l* @+ u) q, c" I$ s
5 L) a$ \ L/ M' o) G( V! Y, {/* Enable synchronization of RX and TX sections */ : U: R! q) F! }: n! r0 J; u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ p* s2 s2 e! u% ^. \: Y* y, C8 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! e4 h; a$ d% w9 j9 R5 a( e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- U3 e! j& i: f. i E* n
** Set the serializers, Currently only one serializer is set as
( C) f2 N# L! J( M** transmitter and one serializer as receiver.( j* F0 t+ d% k4 F
*/
2 G2 Q' \1 |6 r; `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% A8 Q' v; I% C3 ]- M/ v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ j4 K& x# K& F2 x& F0 f$ q9 Q& |
** Configure the McASP pins , k* U( Q. J+ w
** Input - Frame Sync, Clock and Serializer Rx
8 @; L# b8 @& ]. T. I** Output - Serializer Tx is connected to the input of the codec
9 j5 }# P9 _+ t*/
1 T( Z8 u. R+ R+ W( oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" R" Z( c. B8 }5 e1 `7 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. F# x; ]1 P# N* _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- @& S, K) T, p; J3 L c
| MCASP_PIN_ACLKX) [8 \3 {/ q' Y0 }/ L/ S
| MCASP_PIN_AHCLKX
1 E4 y% D6 N) s4 }% \4 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ L; Z G9 e' F6 y8 r7 G+ y8 {+ U) kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " x n# G7 v: Y2 z, J
| MCASP_TX_CLKFAIL
" ~! L* O0 Y. s/ B" ?7 B4 b9 Z( [| MCASP_TX_SYNCERROR
v5 Y7 Z0 I' p9 [3 _9 i) C' A) M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% P# d# n! W" b0 a| MCASP_RX_CLKFAIL2 A& O8 s8 D6 Q3 V7 B4 T8 b" Z
| MCASP_RX_SYNCERROR
5 h6 t9 L' l3 L* `. Y3 l| MCASP_RX_OVERRUN);/ `6 z% L# V; W, c& w
} static void I2SDataTxRxActivate(void)4 Y- ~) A1 g) b6 i5 H
{
+ A5 a5 b1 ?0 _4 \5 N/* Start the clocks */
) U R; u' y( p5 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" _9 t. l5 I, U$ Z6 {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" L/ i8 d: ?. p8 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, H, u0 q& A( r; kEDMA3_TRIG_MODE_EVENT);
% T* S9 \4 j0 m) }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% y8 U; t W9 h |1 T8 nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' H* {9 \# t/ s, F& zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. @! q2 h3 o' z0 e, }/ [5 }$ Z+ ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// {( a/ P9 r, U0 A- d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 n- H7 e( ~2 f- U% m5 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ l0 C. S& S5 ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' y; y4 y, r1 s& L6 {& F}
7 H- D) j. C8 [. f, v, T2 E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
+ t, Y! e( c. I5 M3 B |