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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( K2 B; s; Y3 I0 L+ ~& _
input mcasp_ahclkx,
/ c; Y8 e% J0 z3 I, v* F5 J8 yinput mcasp_aclkx,% k9 P3 Z5 p: w4 Z2 \% c
input axr0,( {. `; J( Z; }. a
: z. C ~7 d5 l' u: |% }
output mcasp_afsr,
4 i3 Z3 u; K/ O* @5 _/ o5 E& Moutput mcasp_ahclkr,
) h" W* l, r+ Q# y$ Youtput mcasp_aclkr,
$ j! W/ v9 S4 M" Loutput axr1,9 |$ e. E8 D0 X
assign mcasp_afsr = mcasp_afsx;! V: S5 O6 ~- o& y$ W" |$ U; }
assign mcasp_aclkr = mcasp_aclkx;
$ N1 Y" N$ c+ Q) Oassign mcasp_ahclkr = mcasp_ahclkx;
2 U5 s' ?( \. V( e4 aassign axr1 = axr0; 8 y) h2 K; {( b8 m2 x8 G
- V! q/ P% m( g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, h; Q8 m7 u( O2 n* V: rstatic void McASPI2SConfigure(void)3 [7 c: H6 W; z2 m5 B
{
$ [. Z2 R; T+ n/ L1 x- V& e3 z3 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 R7 e1 _9 _ I* a( dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 J- ~! V- C d, b! c3 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, w. D1 ]3 ?4 I; N. O4 S/ R8 B% ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. g) e/ v, A8 D" C; X4 c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 `* ~% f% i v: _9 S) iMCASP_RX_MODE_DMA);
, j9 l6 J! w8 f) q7 t1 j a" iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 l8 e" d$ f1 C+ N- h0 D% CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& Y d) n7 g- r* _2 G4 H3 k8 sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 K1 R. Q7 S8 ^! `! F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 |) q3 f9 }1 z1 s* \' E0 h) l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' j h0 h7 `& a( j6 j c( l+ I$ vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& B" M& k- T* s9 b- }( nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 H- \1 q' k4 G% P( \' m! w& w' z) g, _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" I+ e. l+ a! p* W0 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 c: l5 C3 v8 q2 m0x00, 0xFF); /* configure the clock for transmitter */
7 V5 Q" B# k; M" ?6 Q/ h0 c) JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ G3 @. C% _4 I* y$ C, iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 y5 R" k, M$ E1 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ n, b2 n, [: j0x00, 0xFF);
Q7 V; l8 v! F0 ?
8 O" p, L; E! a( Y, w- S/* Enable synchronization of RX and TX sections */
, Y5 g& a. _' Q* l H$ R; cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ j$ w) p" Q: X" H5 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; K+ T& I1 P ]5 J+ }$ X# t8 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 Q1 H; g% Z. l7 X9 Q4 T4 W
** Set the serializers, Currently only one serializer is set as
* o$ A! K$ |0 l** transmitter and one serializer as receiver.9 g. k. \$ U5 d" ?* w
*/4 K; G1 c K7 ~2 T i J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- u0 N+ L5 o! c3 S E! f" U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) V7 B$ H. O, C/ c) w! ?
** Configure the McASP pins 0 [9 A) X& Z8 l9 ^, [4 W( O
** Input - Frame Sync, Clock and Serializer Rx
" {$ U7 ]$ ^. Z; d2 |; w3 o2 A** Output - Serializer Tx is connected to the input of the codec
0 E6 o# h- \/ f0 X% l' i C; G*/, z& |) D- _0 A2 f* [7 U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: j* r. V( K" p. C- P1 U% zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: x( ?2 z& L, {/ W4 P: T3 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* E3 ?9 `3 n! G8 M' W| MCASP_PIN_ACLKX
' u+ {7 y% ~, I: \. ?| MCASP_PIN_AHCLKX% _6 @' n& F+ W4 m* t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' B B4 I5 w/ k/ X7 x5 g/ AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. q( R: ?2 A5 a! m3 b| MCASP_TX_CLKFAIL # K& v, `! L. V
| MCASP_TX_SYNCERROR
; i6 h1 T- s" Z @# d5 W! X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 a7 ~" W) P' {$ g- R
| MCASP_RX_CLKFAIL* U& B$ L- Z4 |
| MCASP_RX_SYNCERROR
% p* g1 u8 T7 a( F) L# @| MCASP_RX_OVERRUN);
8 o" g4 v6 I+ J# a" T# p} static void I2SDataTxRxActivate(void)
* h: M* h7 p w; K% f{
* x, P N0 |' s; C1 q, N2 z/* Start the clocks */1 f3 Z$ ~6 F8 U: `9 U. ?$ n( T* f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 L& C7 z5 L9 n3 [- }, r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 V& B2 h( R* j3 A# Q" `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! F9 G# J5 O5 \6 `! Y kEDMA3_TRIG_MODE_EVENT);6 i+ Z2 m1 t0 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, n- X/ b% ?+ {! q/ nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, X2 ~! D4 E2 n/ F* D5 l6 TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' S8 {0 ^. Z9 Q/ i8 q/ g! uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ k1 v0 P5 I1 ?% }3 o2 \: _) S- X7 U3 Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) B5 q! j, u" `) Z, hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. f) x4 X+ a- p _$ i1 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) ^; _# c0 y+ ]+ h/ b/ O
} $ W9 S9 ]1 C: a5 g. X5 t' ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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