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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 X$ v1 Q3 x! }9 I) d! h* `input mcasp_ahclkx,
9 l2 |% M: j. e+ I/ hinput mcasp_aclkx,
/ L0 _2 h3 [" d1 q" x2 Ainput axr0,
) {7 F0 b. B& p4 w, k. l/ e* P% ^1 d" H+ P6 i- G
output mcasp_afsr,
/ e" r& B6 C9 j/ X% _2 {6 u/ Woutput mcasp_ahclkr,; y' r! {4 H( J- l K9 g9 v& d- |
output mcasp_aclkr,
2 k0 d. h. G2 `& {; {3 ]output axr1,0 ^# Z* e5 [1 l
assign mcasp_afsr = mcasp_afsx;+ T/ x( [: |, F
assign mcasp_aclkr = mcasp_aclkx;
6 d9 \( y* t; N$ ?/ A w6 }! Zassign mcasp_ahclkr = mcasp_ahclkx;+ R4 N* h5 C1 A$ x' L
assign axr1 = axr0; $ O9 g+ j# i- i, ?
% f. m8 S7 H' C) @3 `$ [7 w8 ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 Z D7 H9 F Zstatic void McASPI2SConfigure(void)
: q" m6 |3 k( ^. _7 `9 Q* ?{
t4 d* K" r% B8 V; V5 l8 w7 |McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 Q1 o/ p% J* o8 r) {# A7 k$ a$ E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ B# s" ?; A1 k& H8 X4 E3 S9 ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, ~2 X0 Z6 i% C- X. G; h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' i3 X8 R7 R+ V7 A7 X: |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 y0 _8 v: r% ]4 X
MCASP_RX_MODE_DMA);
. |6 Y+ L' ^* A8 E& DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 l/ n4 r; Y! |& X4 o& U% y3 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 Q- ?# t# _4 M: {" LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 T- o: _; X) U" f. E, o5 hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 M f& @4 s/ G. W( A9 k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; o, P! [2 L4 R0 e% Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 }5 C$ } ^5 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- S9 F$ b% J; {! u. h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) c' m( b1 D; y1 Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ A }( Q; |% X1 I) G8 W) `0x00, 0xFF); /* configure the clock for transmitter */; i5 T; J1 b1 H! P: Z* I) S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 K1 K8 S" G7 o2 n( a( y0 f" \, CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 Y# c, a) x* D% l) n7 v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: Q" K: a2 c- T' A" F
0x00, 0xFF);$ ?: J2 T9 y1 R1 V! S8 P/ O. w
( ^# j9 j: `- @3 m- s- X
/* Enable synchronization of RX and TX sections */ 2 \. s# } q+ R9 K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ r6 d- C0 J5 W( n$ a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* Q6 E- e s! d' @: L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 E) V- t9 E6 G5 \' e
** Set the serializers, Currently only one serializer is set as
% G" S0 ~! L6 e. t: }" ~** transmitter and one serializer as receiver.5 P; R' Y* U' F( k2 E
*/, U$ Z7 v) [& x) Z: W# G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 u+ c Q3 V- [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" m" P- d# l; R4 ?! C% S** Configure the McASP pins
: h* L7 Z& u! F, i; n% S** Input - Frame Sync, Clock and Serializer Rx
4 `& E5 {! E5 ^) e3 U; p" P** Output - Serializer Tx is connected to the input of the codec
$ p1 d) i+ z7 R L; W1 F*/; L, R4 [% _$ h y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 a$ `) P z$ |" y( F4 rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 v, l2 I- l1 y# ^! a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) f8 _# B' J8 n) C: h& O| MCASP_PIN_ACLKX3 w9 {) ^- D4 f c3 c' u
| MCASP_PIN_AHCLKX( _+ ~; {) [0 F- w' T: ]+ l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, y6 a" S- w2 ?- ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. ~6 x) g/ Q8 p2 G; t& ~" a| MCASP_TX_CLKFAIL - W) z; {/ B. t% V/ s& L- @
| MCASP_TX_SYNCERROR
+ m [0 x& E" `$ D- b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : k: D! m9 K+ S, N, _# ]
| MCASP_RX_CLKFAIL
2 b' \8 F2 u* Q" `( q| MCASP_RX_SYNCERROR / m# S- E9 v0 G% J7 n
| MCASP_RX_OVERRUN);
4 `% B! K- l: E) j8 k# _! p$ ~} static void I2SDataTxRxActivate(void)
# W9 z& p/ P* W{4 ~! h, W0 f, R, X$ Q$ r
/* Start the clocks */ H/ c, B5 I% ]$ m0 C7 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 C- O5 _4 b. o- E! gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. F' h1 V2 ~% n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 `0 a( s$ `6 ]EDMA3_TRIG_MODE_EVENT);7 A( A/ y+ k# N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* \, e6 l; m, S- m3 bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# P7 o4 I' c7 R2 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ u% g4 f W( `( B) Z G' |7 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- B! V. m" N+ h' X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 J- Z# \1 b5 R7 O0 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. k7 s W3 c0 p1 @1 ?4 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( A4 z4 r9 G) P& g$ s6 g* M}
2 U# x y0 S8 s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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