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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- T# W) ?. V- }+ p' l: g
input mcasp_ahclkx,9 R; m% j8 ]6 B5 w! i5 ]
input mcasp_aclkx,8 E- z, R7 c; r- V1 L4 T
input axr0,3 ^& E5 B- t' e/ [5 N# ~% w* {
# G4 @% S$ v/ |3 ^output mcasp_afsr,- E4 z, q. E& M3 D, o: t
output mcasp_ahclkr,) X) V8 m9 V- m! b6 [
output mcasp_aclkr,
5 q/ L8 Z b8 Woutput axr1,
( s, u! b6 D c1 G( b assign mcasp_afsr = mcasp_afsx;
: t- \( O) T6 k! Y. c- oassign mcasp_aclkr = mcasp_aclkx;) D5 P1 I) j4 z' F) ^
assign mcasp_ahclkr = mcasp_ahclkx;
2 F* F1 r% b' l: I \7 rassign axr1 = axr0;
* u6 B- _1 U' K/ o: g' W) ^* z8 g# H3 A# A( d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 S2 V, _; ]/ D# o& o- i- f- y( G3 Estatic void McASPI2SConfigure(void)6 \: I7 ^: g: G
{2 ~% ~, r: P4 U P- W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
S# Y& L9 u9 MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 J$ b2 N! s# |% b' i# V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 c1 ]* K% t* Q: x) M, x! J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; a3 p/ m0 Y6 o* J( G* h% S! F3 H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# r" C# x2 P! u
MCASP_RX_MODE_DMA);
6 a7 T4 }" X2 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* R$ e/ S) W- S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) ~- n8 o6 i MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% b' M0 u; d) E7 E3 a9 P1 Y9 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& b8 k' H6 G9 T5 A9 m9 q& d, rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : ]* {- f# G6 B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
p7 E8 |$ ]2 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) h5 [# G* |# i$ [- D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 K" t( `; G3 V& A4 l6 O, {3 R1 d3 o/ h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ p. t" J5 F2 v
0x00, 0xFF); /* configure the clock for transmitter */
- z3 O8 }+ A8 }4 a1 x* |( LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( g4 q" ?& {& T3 u3 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) R' C' l+ f$ E; tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& \* z' _+ O2 P5 N- C- ?
0x00, 0xFF);8 O! q9 u6 [" l5 ^
6 p, C+ o W5 ?
/* Enable synchronization of RX and TX sections */
5 x; ^! K$ Z4 [# LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 J! H* e, w0 ~6 i6 o0 s% ~& ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 n" ^" Y4 m, QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 u# B. `8 |; f" l7 y8 s** Set the serializers, Currently only one serializer is set as
% F2 @1 _+ m# h0 {** transmitter and one serializer as receiver.
+ V7 @! y- V* p, m$ Q( f' T*/
0 Y- a1 r4 {9 {/ K/ dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, G/ z$ K+ {5 f: M1 AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; h- J) u+ X( B* x9 W: `$ ~** Configure the McASP pins % P% _; {$ l3 {6 z# n5 Y% x
** Input - Frame Sync, Clock and Serializer Rx) Y7 ~% k, v% n
** Output - Serializer Tx is connected to the input of the codec
X, Q2 R' z9 ^4 m- Y*/
1 @, w8 Z: b7 c: B* CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* | S. p$ s2 |3 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 d& b' Z; m) P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- j; p: h9 E- r* q, D- o5 a
| MCASP_PIN_ACLKX0 S+ x4 W0 b3 w0 I
| MCASP_PIN_AHCLKX+ h D8 w* I7 Y; M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ Y$ f% r7 G7 T: @8 T: d0 B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 M% m: }& C* Z1 x% `
| MCASP_TX_CLKFAIL 5 {8 |1 ^- U4 t; b1 F+ L
| MCASP_TX_SYNCERROR, Z6 }( b/ G! G" L0 _9 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 ]" I1 s Y8 a4 D- `9 h" \2 i4 q' ~| MCASP_RX_CLKFAIL
+ i, P( e+ p& s4 S; Y4 P( z9 d, D+ || MCASP_RX_SYNCERROR
& n& ~( Y4 G V+ R| MCASP_RX_OVERRUN);/ v0 w% s$ X9 x+ [# [2 D- e
} static void I2SDataTxRxActivate(void)
4 \4 p3 k) S7 N$ c3 J{
0 ~- `& P2 Y2 Z% ~/* Start the clocks */
' j# I0 g* R: b- Z* {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# w9 `( s& C3 j6 F: U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 Q6 n6 d$ {/ I% A5 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 O7 i! x3 G* K3 \% D
EDMA3_TRIG_MODE_EVENT);
; R/ D" R3 R9 Q9 W' u& G+ ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 B: \- }: {7 d3 `4 ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ V4 u9 Z/ M8 i& i) nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 v, R2 H: ]$ ?$ Y8 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; Y# `& F1 a% @( s; Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 b f3 m. V/ m$ z# o6 d( kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: w7 c0 F6 U# R+ j5 J. R; ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, k, k3 S$ N0 x' F- e3 Y
} $ [& D7 E2 q: B/ _' E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 p4 a c2 _% q+ N9 m i( @& E
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