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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( {& }* B4 _5 P, q4 E/ G0 x6 [input mcasp_ahclkx,+ P( `& ~* C9 i
input mcasp_aclkx,
2 C, u5 P8 n# u# U8 Vinput axr0,
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output mcasp_afsr,) ~9 T. P& i8 e7 n- S& V: k |" ~7 R
output mcasp_ahclkr,
8 Y: ?; y! g$ Y' F4 Moutput mcasp_aclkr,% a* q3 E1 y* q* U
output axr1,4 O4 {1 G) H( A9 |2 ^! c0 l
assign mcasp_afsr = mcasp_afsx;
2 J* J! d9 D9 D& N4 Bassign mcasp_aclkr = mcasp_aclkx;
, x4 k7 g5 r ~: eassign mcasp_ahclkr = mcasp_ahclkx;/ I; O/ F; ^9 l
assign axr1 = axr0; 7 |, T% h; W8 Y6 x7 M
) Q( V! J0 L" i! c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 O. v; W p- X9 P% d
static void McASPI2SConfigure(void)1 ?; d5 R7 O. b# N
{
4 ?1 D* ?$ l2 \5 \5 Y" JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 {1 x" J& p6 y6 X% rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. h, a$ \$ N6 ], s# l3 P- Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ W, u5 B0 |8 I9 S+ p* {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 M" X F7 Y9 I; X% d4 K" x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ Y/ S+ j* x0 x+ z' T [
MCASP_RX_MODE_DMA);+ a' ^- m2 f; R' A4 s. H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* c9 [- c8 y9 A/ ]/ x9 c) l. H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! S' b% s, g( D/ {) b1 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 K: s# F! z8 q7 t) g6 k) v5 [+ f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. L, J2 D* g! z2 y$ ^, a8 QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, M7 J7 A% G8 M5 l! PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 Z1 ^' y0 n; H7 H% X; LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; j) M3 u: S! R# u3 G$ B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 f9 q" J* q2 i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, @/ A l4 g# F8 B8 A
0x00, 0xFF); /* configure the clock for transmitter */
& u4 |" h4 `4 V! Y( NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& ?* `2 @% o) `" o& {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! ?( t' T: q+ G+ t, ?2 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 T; l' g" I* A0 N
0x00, 0xFF);1 b+ ~7 l: C8 _
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/* Enable synchronization of RX and TX sections */
9 |$ T2 G( e9 x0 H: uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# ~" m' \. f# A; j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, P3 S$ Y* z9 e( W. ]3 Q. R, g3 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% m9 Z& C7 }; K** Set the serializers, Currently only one serializer is set as
" v0 x# n# b& q" g6 O** transmitter and one serializer as receiver.
$ M6 {5 c( L3 o* g% Z; C4 T2 D*/8 f. c6 n6 D+ ^) a9 i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, H; b4 _( D' {% h% T/ D4 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 ~$ O7 Z3 t6 R4 P: _# ?** Configure the McASP pins
5 X2 S& G* o& ?; W: f' X** Input - Frame Sync, Clock and Serializer Rx; n5 y5 s% c# T; t8 W, o
** Output - Serializer Tx is connected to the input of the codec 0 F, z1 j/ Q0 F5 l4 V
*/( n1 L* M: _, [( s* X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ b! j, C2 S- }: ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 K+ J Q4 E9 Q$ f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* t" w+ H6 \0 c, }8 j# c1 \4 P& Z- m| MCASP_PIN_ACLKX
! `" b5 U. O' r/ X$ F( c| MCASP_PIN_AHCLKX
0 N8 w6 o9 O) t0 X* t) J' _% U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& a" C) G5 p: I9 z* FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& d/ K E; X' ~7 o| MCASP_TX_CLKFAIL & q; }8 C* b; v4 |6 ]" r3 |
| MCASP_TX_SYNCERROR
& c9 R) ~7 A( j! r) ]! t2 Z4 V; y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 c ^) a7 C0 ~/ F; _| MCASP_RX_CLKFAIL4 ?+ e+ C3 o% _# V% V% c1 [
| MCASP_RX_SYNCERROR 1 _% | X. K, g8 b( S" s
| MCASP_RX_OVERRUN);
, `& q8 s3 `1 G8 M1 `5 W7 q} static void I2SDataTxRxActivate(void)$ S9 r; H& M9 N3 |- t4 l$ V8 `) l
{' y: ~" v2 ?3 T" R9 h% ^0 @5 a% _* o
/* Start the clocks */9 h, l! u! D7 ~* T: S# u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& `3 \' U0 D6 I8 @! @1 z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 ?1 |( I" b& n2 g# b0 L3 s! E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 G! l" U$ L- L2 TEDMA3_TRIG_MODE_EVENT);
- v+ q8 b1 g! {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 ?3 b! a4 E% lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ F8 o8 t$ O- l, Z) {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" ]0 V5 ]. G. L' `7 r6 WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. W/ s+ ]( g+ ^* @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 v, a) v2 l' U6 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ U; K5 Z8 n5 P# D7 o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 X2 ~1 e" x* D, Z( z} ) `. i0 G9 \+ f& ~( z+ r9 `' C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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