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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" C* M: G; i3 e: Q% y Jinput mcasp_ahclkx,8 `# E2 P7 L- [( [- T4 K p! D
input mcasp_aclkx,
% c/ N) v) C8 P# Oinput axr0,
7 |/ m5 ]$ u! T) w% G
' j q% E6 M1 y+ @9 l* boutput mcasp_afsr,) C; b/ D) a7 x/ f+ G% O( e4 ^
output mcasp_ahclkr,
! p: w4 ]5 `- o* i7 p: T. [output mcasp_aclkr,: {2 b/ n3 d6 k) A7 S# q1 }7 h5 e
output axr1,/ s: ~7 L, {1 s$ o" H. K& u
assign mcasp_afsr = mcasp_afsx;
# i8 N" o) M% H2 k- G; eassign mcasp_aclkr = mcasp_aclkx;+ y4 z4 u% l; h/ w/ v5 A/ w' A5 _ z
assign mcasp_ahclkr = mcasp_ahclkx;: \7 ^) k X7 t9 L
assign axr1 = axr0;
0 K5 ~/ x8 ?3 [+ K! W e3 \6 d h2 B, M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 F. N6 H4 t& r, {- ^static void McASPI2SConfigure(void); e) D: {$ n5 u$ d/ G
{% l- a c+ K6 Z8 P+ S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 k2 Q0 a9 }! {: R9 U, M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& s8 f6 {( v. @* F7 a. G* a/ M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) w* E( p7 F( v( l* m3 k' E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 u6 |9 ]/ q- T4 n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ b9 v+ _& y& U9 ?4 }
MCASP_RX_MODE_DMA);3 p- }4 X* R: C6 }! Q, W$ s+ [. i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* k4 |8 g h! \, F( K6 x1 wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 P& Q3 g, W/ D5 R& J# k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 _3 \. G$ ^, n! Z" I! `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 n5 G6 ?3 E5 k) R. A4 ?3 e0 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 n) H- o. ~$ p9 UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' B- v+ k" d& k+ C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. }# W" O, g8 c+ y7 ]) zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 _! m' J, l# {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 Z+ f* j" ^1 y' G0 q9 v; q0x00, 0xFF); /* configure the clock for transmitter */: g2 A" {) q% M& I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 ~4 X$ P, S2 K5 G- ~5 ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; C! G* Q0 A6 ~' H. q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 B( T3 a9 L9 R, u3 {
0x00, 0xFF);
1 p! M4 @# G; ~* ~% q+ H! M3 @$ V* }. }7 K! M
/* Enable synchronization of RX and TX sections */
" V( W+ P# _4 c4 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* Z0 o: S4 g; c7 G% E9 [0 W \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ J2 {7 v; x/ ]: B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 r" A( `6 E! {: L; V" I
** Set the serializers, Currently only one serializer is set as1 z7 ?% [, q, E/ Z% S3 N
** transmitter and one serializer as receiver.( ]( v1 D t* ^% j3 J1 z$ z
*/6 }- g. g" Y7 A" x: r9 O. f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- x! L$ p/ `+ c7 B% c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; u; @# S! v# }6 Y- _, L** Configure the McASP pins ' o* t1 I7 K6 f* L
** Input - Frame Sync, Clock and Serializer Rx0 I8 R/ y) D; t2 w
** Output - Serializer Tx is connected to the input of the codec 9 @( w$ V2 B# s3 B6 p# ^* P6 [
*/' p$ i- @& A2 O. y4 v. {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ G; z( w8 M, WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- o9 ^6 Y Q$ }7 b4 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 o: L5 B- n9 O1 ]/ K3 ^) |1 Q| MCASP_PIN_ACLKX
1 w% Y4 G0 X" R% G* H" Q| MCASP_PIN_AHCLKX
. U* q$ } Y& {) Z/ q# ~3 X- U% }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" O K+ I. c0 a/ H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
k; M, |$ D( b' P" R& b0 P| MCASP_TX_CLKFAIL 1 M- f1 L d! D1 r: C
| MCASP_TX_SYNCERROR
% t$ l8 w( R% ^* }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 O; D7 e* _# T N
| MCASP_RX_CLKFAIL5 H! h; V5 _, `
| MCASP_RX_SYNCERROR ! K4 ^' l' R& z+ t8 n% T! }
| MCASP_RX_OVERRUN);7 d+ F4 u( X) p( G2 B% ~$ J
} static void I2SDataTxRxActivate(void)
+ W- _/ E. h$ t' I{
+ e: g* {1 ~$ f2 |2 Q/* Start the clocks */
: R4 M# z2 b! n# J5 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( i+ R0 i, u. L4 @5 n( s# j1 A) W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// v( m5 o% K- S1 \0 o/ ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 n D- x) ~0 [# F! N) H" |EDMA3_TRIG_MODE_EVENT);
- U% \; B/ E6 Q2 p1 B4 @) p, |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 H: J# O2 ]1 x! \9 ?7 N2 d" M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' y. X2 G4 t9 FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 {2 v, h3 Q% N# IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' w$ _8 C6 m$ f( _2 ]) bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& Y2 g7 f. ~! y- ]0 }: j! K% d4 O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- n6 S* b/ \: t/ FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 q+ G. e7 K" z8 c6 y4 ]- T}
" n4 s* n$ I% z; `$ c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / a) l0 _3 q5 l- _6 e- f0 b
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