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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 W1 x y4 M3 e
input mcasp_ahclkx,
: C% e& z* r' g' I+ dinput mcasp_aclkx,
' X! v4 O8 a) z+ J* dinput axr0,5 y9 ]! x- z8 k1 e
" q! a! \4 Z' X& P. p h
output mcasp_afsr,
# Q3 a! r$ g: y# w$ soutput mcasp_ahclkr,. M x( c# m$ p5 t
output mcasp_aclkr,9 t* v T' n2 V0 X ~" l
output axr1,
6 n V5 ~$ R9 q" p! P5 |6 c assign mcasp_afsr = mcasp_afsx;
; o% X: w# @) d+ F8 [8 ~9 `assign mcasp_aclkr = mcasp_aclkx;0 U, q: C6 m; s: Y
assign mcasp_ahclkr = mcasp_ahclkx;
& R0 V- I9 u/ [1 P" P& o: t( Uassign axr1 = axr0; 0 C" P9 {3 } d, [1 l7 z
5 k7 j/ E' H2 G! r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 k3 w8 D' z5 c; h; Dstatic void McASPI2SConfigure(void)
& D7 v& H/ i0 h# N) h{
% O- P( G P' |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. @6 J" m+ X! p* q5 A- MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) E6 x7 i$ t8 ?1 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 C3 A, N- ` F M7 A. b7 S" s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* a( w# P% _; j2 O- @( o" [9 PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; D' n& p! t, |' \5 k' `
MCASP_RX_MODE_DMA);
0 ^5 P; j. V& K& X/ w+ T# OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% E5 n3 c7 W- a: v L! d; aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 ?) `: ]$ m2 {' Z' C7 K% a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) r: O0 m, q# z2 |& @4 FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( ~# f3 h0 D% L# [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# O5 Q! x8 L/ LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 h0 A3 ~, _6 K$ ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) Z# v& j- a6 p1 b1 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ X' h' L* f3 B9 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; z. ?! s" A% C4 o0 y9 [
0x00, 0xFF); /* configure the clock for transmitter */' [7 R5 X4 N8 e4 r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- {5 c& R/ \& p& R4 T1 a% x9 |2 y/ MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 ]/ |8 `: y! K: z$ `$ nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, O. t* a9 e9 ?+ t
0x00, 0xFF);
2 s/ X M ?* I& t) g, a; ^) s/ R: d( Y1 m5 H- m/ w
/* Enable synchronization of RX and TX sections */ ! Z8 e6 k: i* }; i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 x- m9 ~: O' H' o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& I, J. `1 o& j3 I7 ^0 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# ]2 \1 u$ D, n6 i8 C( g
** Set the serializers, Currently only one serializer is set as
, w+ j3 }) v2 ^; S, R** transmitter and one serializer as receiver.# C; e( q* u t: q. P* u6 ]
*/, q* Q4 A& h1 p0 S/ ?% | H0 P) |! `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- x3 f o4 V- n* D& dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( `8 P( I0 P( p# O# B+ Z
** Configure the McASP pins
, e! s% x) k& Z$ N8 q** Input - Frame Sync, Clock and Serializer Rx7 c- g8 s% e7 C$ `& Y- o
** Output - Serializer Tx is connected to the input of the codec
; a/ z s1 U) r1 I1 z3 a*/; {+ C! O1 N0 l0 L! W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. q' {' W0 w. G# P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 Y( W5 H5 S6 D! y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 x% M8 O1 b, g. m& ?- ^2 ^. J
| MCASP_PIN_ACLKX- Z- Y( H! t" l6 l" y
| MCASP_PIN_AHCLKX) z1 G8 }" `& E2 b( `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; R/ l0 V0 X9 D; z+ NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : k2 Q" J- K0 d( h% A1 h& F. U# Y
| MCASP_TX_CLKFAIL 9 s6 H! s7 R4 f; c5 D
| MCASP_TX_SYNCERROR0 }' Q+ o6 q7 i1 l/ a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , G5 F* J) `8 h- m
| MCASP_RX_CLKFAIL
) l" {$ A& |5 ?8 x| MCASP_RX_SYNCERROR / }/ k+ I" e3 {' [, k# W: B5 ^* i% ?
| MCASP_RX_OVERRUN);
5 V# `) K% b2 x! U; i} static void I2SDataTxRxActivate(void)9 s. ~; }* g9 K/ B
{
) Q4 ~! Q9 c0 [' q1 h7 K7 j/* Start the clocks */" u! b3 E7 b: e4 M* D% m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 z$ h! @9 A1 o8 {$ v. u! qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 X5 n0 F5 t/ w7 p! v0 g% u) F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ w: B$ M! T1 n/ E# a1 B. m
EDMA3_TRIG_MODE_EVENT);
- c& m1 ]" a! ~: c$ U; J/ Z* j, ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 p5 T7 C$ b* A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: {8 @/ J8 y/ s2 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% m& Q* v C5 @, V+ oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: j8 P( l/ [6 y. E' B" X8 _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 Y' i+ V7 P; n7 A7 I, m1 T- EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( i; c* e1 s0 Q0 z3 mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& r Y( S6 a0 u7 l} 3 z/ B) |# w$ |9 y' k7 g2 s- x9 f7 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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