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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 x$ D" D9 x& P1 B5 j+ \input mcasp_ahclkx,
~8 m( b6 d2 ^0 sinput mcasp_aclkx,% X* U3 L* s6 F- w2 Z1 `$ }# [7 L
input axr0,
+ \! N# q! C$ ]4 P( m) q6 }& A# B6 v- u0 {' n0 n
output mcasp_afsr,
7 u; o0 c9 m A( c8 moutput mcasp_ahclkr,
: e. U+ h2 j2 I0 f. T$ S9 `9 Routput mcasp_aclkr,
4 Q& A0 A0 _) k$ I! M* t- y' d a$ routput axr1,
2 O/ p2 U" J4 ^; N assign mcasp_afsr = mcasp_afsx;5 ~% a+ X: ], b0 P1 e( z- i6 b" Z
assign mcasp_aclkr = mcasp_aclkx;& t7 Z A& N5 i( T* F/ f
assign mcasp_ahclkr = mcasp_ahclkx;9 c% k5 ^; v$ K8 }2 o7 U Z
assign axr1 = axr0; * f2 S9 W9 _" ~
0 ]( x- J3 n/ T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , J6 I: B% K; E3 \# ]2 {
static void McASPI2SConfigure(void)
* g4 F$ b6 q$ M) \6 W) x* V% c3 G{5 }3 V- i% }7 E7 j, i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- M& |' z5 n$ s. U/ o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 ]. E* O2 {( Z/ J5 d- wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 ~& e) G) ]% pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( G2 w$ a9 K3 v t0 W, |& a, UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' Q+ e" B- @) h/ u! C. m: t2 z& tMCASP_RX_MODE_DMA);0 I# a. u L! p: ]" k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 S z5 u. |) J" W4 b, d- KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 k8 S0 s' c n* z& {1 }. T; RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 g# f* }* c1 B& \7 A* B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# b2 Z+ d) [" T4 O% t% Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # D4 w- d, S+ j" R1 {% B9 x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. {2 b3 ^* Q& X7 aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ V8 ]% B0 Z4 e% X' `; O( x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 A9 F! f/ T7 w) [8 j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ n' X7 _ V) k7 t, E. t0x00, 0xFF); /* configure the clock for transmitter */! j4 K& h/ C4 u) b$ n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# g1 @0 [- w4 o/ i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % s# y# i; t( i- G/ a9 K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
Z2 ~. i/ c, b0x00, 0xFF);+ n& n' _1 w% e& Y: \" _6 F D) m
, o3 l3 W5 t' _. p2 O$ i. F/* Enable synchronization of RX and TX sections */
% S& O' e' A% w* _& L6 F" N2 ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 H- x; B6 M2 Q7 i9 x. P4 r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 [7 {+ D$ _# F& z9 q# Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ c6 Z. z; ^+ N! J3 ~; e' B** Set the serializers, Currently only one serializer is set as
2 g! ~) ^" l$ C# e: o** transmitter and one serializer as receiver.
% k. U/ J0 G+ f*/
1 N' R! ?6 V! d, [4 s) }2 Z6 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ M0 J; \% {7 ~, _! R3 V6 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" ~/ R' \1 ]0 I0 Y4 l3 |** Configure the McASP pins / A: I. g' L t
** Input - Frame Sync, Clock and Serializer Rx! x6 O9 B! c, G
** Output - Serializer Tx is connected to the input of the codec
3 d' }7 o, d3 p/ E" Y7 ]- P6 X*/
5 [. N/ C! q& v& f; Q" v( u. YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 d" B$ C6 c7 P' q" `) c; ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! M! ]; X, h; W4 V. w7 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 w8 q' d2 B6 s" l
| MCASP_PIN_ACLKX' @6 U3 w m; P7 W
| MCASP_PIN_AHCLKX9 T/ d( u& t1 O2 g; Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# w' o6 b; Z4 _8 G, h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: T3 o5 W! E7 h4 G; r| MCASP_TX_CLKFAIL 9 C; k1 o) `5 @
| MCASP_TX_SYNCERROR( ?" k: u# D. g2 m2 X$ F" N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" o8 H# h4 A8 q+ w" K. t# \7 m| MCASP_RX_CLKFAIL
2 q, D& ~; ~+ N; Y/ F7 f| MCASP_RX_SYNCERROR " X, z9 d0 X! ~- Y/ W, }
| MCASP_RX_OVERRUN);& }9 Y" _0 z5 P/ ~# d0 C
} static void I2SDataTxRxActivate(void)
' j5 }0 Y7 P: f4 m5 N2 H& d{
3 i2 W1 x `3 m- w9 e/* Start the clocks */8 E1 ]: F- a& i2 ~& G" g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" ]" s- x C/ {) BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 h$ v+ ~' z$ \6 `8 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( |+ ~" R) {( D3 e! MEDMA3_TRIG_MODE_EVENT);6 g2 m! P! F. q; W4 d; J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" }4 U; E3 B3 S1 E- i' REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 C( c8 f& @4 j0 m' T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( _5 O7 B' ^9 f, D2 }* ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* E* \/ L* f( g* M* h' uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 ~& H4 ~- X" T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 N6 ~0 I8 X Q) {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 g& g4 ~9 f" I! V: x
}
; N, \" T! i( v: e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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