MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
8 {& }0 w0 X7 i% D/ ~. H
  k- n) v: P1 Q8 `output mcasp_afsr,
7 |+ e; @: q( Qoutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
. ~" y" y" Z2 }! o- j3 S5 J5 Yassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

/ J9 O6 R( A9 }* |6 l

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
5 W- g- e; b: V! R! n- q# z8 ?{
' ^9 o$ w3 r% EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
: Y& \6 F% x. i! Y1 `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
( Z* B- u4 m; }" X. {+ D2 R4 P  CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ _/ Y" c& Y8 m9 o, O6 j# f2 z6 OMCASP_RX_MODE_DMA);
& P9 h" W) e6 u6 c3 qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 I9 K  j; y5 o* U, V- ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; @3 M6 U2 M) o- e# wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* d5 h3 i, k7 t. |6 }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
: B: K" n" n7 i: r1 lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 x, I3 B) ^9 C: `. w4 F: l+ |- r2 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 B! m6 [+ V: d6 W! f' E2 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: ^# Z0 y) ?3 d  U0x00, 0xFF);

/* configure the clock for transmitter */
7 ]" ^& [7 ?! i, _4 eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# E8 F5 A3 m5 u0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
; f% |- P" h. r5 e+ S9 MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
, m8 a) c: `1 V: HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) j8 Z$ k9 \# r9 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
9 r/ A8 C. \. w8 A( y3 @! B% ]** Set the serializers, Currently only one serializer is set as
0 a1 f6 r! a: o9 b- e$ t** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- Q# ]# ~! ?. QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
7 B) U# t" Y5 x" V** Configure the McASP pins
4 w7 ]  D, Q- `$ O: V' j, |/ _** Input - Frame Sync, Clock and Serializer Rx
& D. [( S6 [9 r# a, e** Output - Serializer Tx is connected to the input of the codec
  ?2 M; Y5 G. _  k/ W! ^*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& s% Z3 B# e2 ~' e( `# f  T8 B: jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% }+ v1 a3 M9 ]; }+ f/ U9 Y% ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
7 Z0 O$ B+ l( B1 H+ \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ @* U' l( c# c# p2 f# N| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
8 @8 x- V% |% i8 ~) F! Z4 A1 T| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
+ _5 L) B" S5 C+ [' J& ]/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# k2 Q, t: {4 H  nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) ^: _' R! X" B, G1 KEDMA3_TRIG_MODE_EVENT);
7 \( L# H! S% Q% f  OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
, S& s+ x/ x; U8 V0 u7 A0 ~* d7 H) ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
) J; m! ^$ U8 m- h$ d+ p% Q6 n$ xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ J% Y* x2 V& m  F; V+ ]% TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& Y$ @& r$ q6 H1 Z* A+ w: t/ |* m}

: Y( t) `$ H( f! }$ ~

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

  U! `& V! l: ~+ X# L1 |4 {