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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, h0 L( r% W, g6 Dinput mcasp_ahclkx,: h- Y$ Y y t7 ^! e2 B. P0 c
input mcasp_aclkx,
s) a" ^4 ]$ e' U, |input axr0,( l- h( A# b/ d
# }7 U7 I( H6 \1 n
output mcasp_afsr,+ \# z1 `) X- k3 L$ y# `, M
output mcasp_ahclkr,
5 W* y; E: L8 g. W% ` h `output mcasp_aclkr,2 {: U2 U+ j9 x. V0 C P9 F a4 U* V
output axr1,' [, z: o/ S9 M. ^1 W" y0 W c& F* X
assign mcasp_afsr = mcasp_afsx;
3 ^. V! W. n* Z: _* q+ F' S Z5 Wassign mcasp_aclkr = mcasp_aclkx;% Z3 d% ?3 h. e
assign mcasp_ahclkr = mcasp_ahclkx;
: ]! D3 ?3 C* K7 \: nassign axr1 = axr0; ( Y# }1 ] r1 p
4 b5 [# @. u) J$ ~$ ]$ x8 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, K* k. K! D& a$ u9 F$ f+ v" Zstatic void McASPI2SConfigure(void)
: A$ k) E. |4 [{4 A; J/ Y% z) W* Z3 i( E3 ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( B# I4 a( y# z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 ]/ X# f, k$ E. ~2 K, S/ ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# k: f' I& _& m" @5 l* ]+ zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# X H) B) K; m/ p/ k$ S7 x7 `) ?7 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% f8 W. p2 J% {4 |! s! x
MCASP_RX_MODE_DMA);
) ^' y% F( x" K# s# f! jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- c a& C* H' h" W8 k/ uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ u: }( ]. O, L: T( `9 X5 w- s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) @0 [$ B: w' S( }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 Y" @. e7 Z. k/ A: O3 `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 l4 M& @+ q( f6 T) t" a& A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" j5 z7 Q3 a* f; a5 z `; f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% ^2 b$ |+ m/ k: zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 E- X* q( b; R3 oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 C# e" T1 W* L& W! T0x00, 0xFF); /* configure the clock for transmitter */% E: X8 O; C H4 K1 ^% _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( J; W: ^( J$ c( R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; _7 D x s' c; B9 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# P. d+ `$ d Q. I, b0x00, 0xFF);6 j9 P# w2 U" M0 H4 B- b: x; J
5 |( M: l$ F3 _6 |# p
/* Enable synchronization of RX and TX sections */
& z+ m2 y6 r5 E8 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ f% X2 G, L0 O( ~# I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" f: z' w! f: J; d y) oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 ?$ P6 ]; \) y$ m** Set the serializers, Currently only one serializer is set as1 p. [+ H( q: K4 R6 G0 x
** transmitter and one serializer as receiver.
2 ?! t, a4 s. S% I% ]- O*/
5 B3 m- P. R! @9 R1 vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* w! |; C& `$ [0 G* v$ Y6 k; HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. X; w6 H2 {5 c
** Configure the McASP pins 2 T% [" D/ \% Z( k# n
** Input - Frame Sync, Clock and Serializer Rx
. ]1 ?& Q+ u. r W* G) q** Output - Serializer Tx is connected to the input of the codec 0 @0 N# f) [1 Y, \9 R) Y
*/
! B7 `& z% z+ i% `9 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ ~3 M; o: U: B C$ v N- W2 j9 w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 G" o; w; P7 AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) d* k$ w# A9 s6 O: F0 b| MCASP_PIN_ACLKX
; g% g9 [% _0 R5 M" E| MCASP_PIN_AHCLKX1 g. Q, ~0 p& z0 _' ?# ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& _/ X/ {" X* Y8 I* W0 I( w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : y0 V$ ?& S5 d# A- e _2 n9 `
| MCASP_TX_CLKFAIL
, U m8 h' {" A' c7 f| MCASP_TX_SYNCERROR4 {( H" i* X. g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' e* ]$ W5 p' v( c A3 G| MCASP_RX_CLKFAIL
7 f, d1 I3 s1 M4 G| MCASP_RX_SYNCERROR
9 _8 E0 ?# Z6 G& p8 t" b0 U6 t+ Y$ n| MCASP_RX_OVERRUN);
|( x. L# x$ B+ t& K: w2 V} static void I2SDataTxRxActivate(void)% O* D# {/ Y7 z- B" P. ^. a
{7 |, M2 w. c4 @/ t
/* Start the clocks */
; t( h9 `- Q; d7 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 ^' A$ D3 y7 U9 w- H |. B2 p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. K/ h" S- `$ @& [$ H, m# `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ L9 R6 V, K# I2 ]- B3 W! N
EDMA3_TRIG_MODE_EVENT);
( Q/ u8 @* o( Z# G' BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ \0 w9 l4 i: k! G: j) zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
}% {0 N# l3 @7 fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 B" I- L5 N$ h/ H! E6 p# jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! r. _5 }4 C+ Q0 g4 lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% g2 _1 m' U% j2 d2 h Z& D( hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" a6 S/ H6 B0 I L1 ]! e5 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* f: u0 _. h! e7 l7 }
} ! N7 B# _* s" Q3 V" f" v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . e# X6 f7 K( R# s
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