|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 [, w! o, M Q, v& A t
input mcasp_ahclkx,
9 _/ ` Y1 i4 u: ~$ N& V0 u# N4 c4 |input mcasp_aclkx,
7 P3 s- V8 S0 H6 P, Y7 Sinput axr0,
; C1 o5 N% a, X/ C+ R# {4 I% @+ R ]2 y: s" ^
output mcasp_afsr,
( E i9 {6 `4 D! W( K: s5 loutput mcasp_ahclkr,
* R3 O. Q0 W" E1 p+ {4 g, Woutput mcasp_aclkr,
2 X- t$ i9 x' {3 I; h! aoutput axr1,
& ?0 E5 q# `3 X assign mcasp_afsr = mcasp_afsx;& d' [, @) ]1 d$ X5 \5 q6 l
assign mcasp_aclkr = mcasp_aclkx;: u: H9 Z, ]# I; |( R
assign mcasp_ahclkr = mcasp_ahclkx;
2 a' W# I/ {) p" y8 i4 zassign axr1 = axr0;
1 S1 O7 u% `3 f4 J2 O n: ], P! @: a, a: Y1 A) V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 B" L0 w+ y. ?" D) e, z4 M
static void McASPI2SConfigure(void)# w1 ~2 g* M, N6 f; w7 \
{
# S& K6 y- d" i. V; d$ KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. B7 G! |/ [& `& r! W! S! CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: S( f) x9 v/ o$ vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 ]/ k9 v6 a) q) p( e9 t1 W9 |# l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, a& c+ W% a' O; V& a6 jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 d2 O7 R6 j8 F: KMCASP_RX_MODE_DMA);
4 z$ \- |( b% M* h$ ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 s7 B M% w+ E8 j$ kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 X! _) P% T6 R$ ~1 M5 w1 K f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& r3 W/ G6 |6 @" SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ }# v0 y) I% ^# G$ x6 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# q* e6 e: u+ f/ D4 QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ O3 M" P! h$ H3 [% S* m. H' mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# u/ g( m0 {( b1 B) bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' q- K4 e( j# @* ^9 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. [0 p9 }" W7 S& z5 @
0x00, 0xFF); /* configure the clock for transmitter */
1 S, C. `% E4 E3 G% W: `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 ^" U" m- M; s- b& U! T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 Z% I8 k8 S7 y) E+ l eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 i' \ r9 c6 g% u% K4 W) Y
0x00, 0xFF);- N" z6 ?7 `9 B) H# ^" O
^* r7 w6 Z+ I% @" K# m: ?1 s/* Enable synchronization of RX and TX sections */
F! L* B( f# l9 \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, y |/ N" B# K H7 F' c% M3 lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) X- |- ^- H& s4 t5 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 F5 t$ r) [" G# L2 H# T
** Set the serializers, Currently only one serializer is set as
8 R; b0 h8 g0 w4 S0 C2 z' U8 ~0 C) D** transmitter and one serializer as receiver.: T; y5 Z; K# S1 z- D
*/1 a! f+ Y: {" w6 |5 d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 A! Z1 q5 ]0 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, A. v2 Q! _2 t0 G
** Configure the McASP pins f# V5 v0 A& i2 z% v2 y
** Input - Frame Sync, Clock and Serializer Rx. V9 K6 B7 G7 W' _# Q
** Output - Serializer Tx is connected to the input of the codec
: ~3 g2 Q& ?' J `- @& z" b*/, P) ~3 m+ R+ E0 M5 I+ B) p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& t8 D& v% b" Z0 J, R2 v0 q" ^% PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' |) r7 E$ o: \: K# c. pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: G" U' N0 n9 D- W| MCASP_PIN_ACLKX, V7 N# m0 J. E2 A5 o4 B$ `
| MCASP_PIN_AHCLKX# s# V/ _, s& }; [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 B$ x" r" L4 n; m; wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( U/ r7 Q( ^! r; f5 F- E. }' f6 `| MCASP_TX_CLKFAIL " q- M5 P1 }/ l. B
| MCASP_TX_SYNCERROR5 F# i+ Q3 r; H# @- f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 B5 d; k6 B+ _' z
| MCASP_RX_CLKFAIL
! z! s; b! S* C$ _0 p6 H| MCASP_RX_SYNCERROR 1 Q! }- l6 [4 J! |
| MCASP_RX_OVERRUN);
$ J4 l; Y: u- y} static void I2SDataTxRxActivate(void)+ a/ I T( b5 ~1 A
{
: {+ m0 }, T& F5 w" l: f/* Start the clocks */
" s4 X3 V$ n! m+ OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 Y1 d6 t1 q/ |, S# i2 ~7 K) c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* E' |" H& B* n2 K: G6 b" r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; g l9 h; N' y% c/ g, c1 J9 j% T% {) ]EDMA3_TRIG_MODE_EVENT);, b5 s& `0 A5 @! D7 O& D& ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ C) q0 q9 U5 G' O% h" LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# c& \. ?, O, I2 H1 V: A3 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* u5 N, j3 Z: N( L2 `, i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ l/ {# { V- I& p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. r0 P1 r2 f5 q9 ~3 U/ E% r9 b5 ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
u: l/ f; `+ D9 T2 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' F' \( ~9 n M}
* U2 H7 Y6 m5 X% y6 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 N5 t4 ]8 U* V2 w+ _ |