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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ {2 e, m/ b. k4 `3 ^+ O! f
input mcasp_ahclkx,; R# h9 ^. Y+ b& B2 I) o
input mcasp_aclkx,
3 t0 v& K) W. Y7 p1 n5 H# Minput axr0,
( _4 @ P$ ?* y& h% y J( x$ |
* g, t% f" c# k& G- F6 b& J& ^ |output mcasp_afsr,
' M1 o y( f$ s+ r) U" koutput mcasp_ahclkr,. }5 Z, N$ f1 d* O8 ^4 k
output mcasp_aclkr,0 O r6 g, ]$ N" k4 o
output axr1,
- @5 Y. H+ n& m; ?7 t/ z assign mcasp_afsr = mcasp_afsx;
! p: J" {/ G7 d2 j5 uassign mcasp_aclkr = mcasp_aclkx;
8 c$ s; i! u$ I2 j& qassign mcasp_ahclkr = mcasp_ahclkx;6 X6 [5 T3 k; O% X# _, M9 t
assign axr1 = axr0;
+ W) {' k4 H+ V) q. k5 `, G* j7 _
9 K* n1 e- K7 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 _ U, o+ B( @% A8 Z5 i* r0 h) B% f
static void McASPI2SConfigure(void): z; C. I& @7 {; o9 L9 B
{ G6 E3 ]$ M3 h+ `/ o- b* w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
^4 E8 r5 c/ F, X+ qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 E1 o& o! s6 v# S6 {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" ^/ V7 i V7 Z* a- @4 f1 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. ?, ~/ p: }3 F d- g3 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 i1 T' @ I3 @( j- UMCASP_RX_MODE_DMA);% Y# N4 M9 f( {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ y4 }! n5 F0 k4 L! o) yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 [' ?0 k( g+ s% a; ^, E" K) M( NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 q/ }. \: c* WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 v' y4 K; U+ S. P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % q' p$ w N8 k# I; Y1 K0 V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& L7 U# {9 x4 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% K9 U. H$ W4 W( {5 f7 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# s3 Q$ R( E s5 L) M2 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 N/ x0 i* I2 N6 o0x00, 0xFF); /* configure the clock for transmitter */
2 |8 `/ T8 X$ bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 U5 z1 C: l2 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 D! f: I2 |, S1 ?. x3 nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ H) I7 k: L+ ?
0x00, 0xFF);
, }& V# K, R" q F) |* V: L9 B5 Q* p% w' r- l+ `
/* Enable synchronization of RX and TX sections */
: T% V7 X* ?' E% v. dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ R. n0 \1 `" G) k6 c R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: ]& U6 g2 b4 y& H9 T+ Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- K9 K3 ~1 Q* n** Set the serializers, Currently only one serializer is set as9 q9 U6 e" ^; a% n: j5 ~
** transmitter and one serializer as receiver.
% q6 E5 L% m4 ^( X$ O. n*/" I! _( t. A9 h W- G- M" j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' A9 a: x0 v( R, w. M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 [! V x {- m8 n
** Configure the McASP pins 1 m I( z( K0 M; ]7 `$ i6 I( W
** Input - Frame Sync, Clock and Serializer Rx
+ c" p( z( Z& \** Output - Serializer Tx is connected to the input of the codec , o( x* _- }! a, Y* {& c5 |* {, s
*/ t# Z2 l0 a% r7 d: p% r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
g. \+ M L4 E6 f% @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 p# v7 a0 b4 F, c, z- k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% {8 d# E5 e6 R) p
| MCASP_PIN_ACLKX) y* s r1 ?% [- w, Q
| MCASP_PIN_AHCLKX1 c5 t$ k: j' S, b6 `9 V6 X" X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# c- n7 j5 C1 O! i0 b1 g8 u1 Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 F- ^( D2 O J1 B& B| MCASP_TX_CLKFAIL
# v/ L$ Z! t/ x| MCASP_TX_SYNCERROR, _$ q: I: ^0 ^ ~& ~ j" l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 u* T+ T% ?! l/ P% E1 r! X! Z0 l5 A
| MCASP_RX_CLKFAIL- g* U0 ^4 ^- G
| MCASP_RX_SYNCERROR
M3 d9 N$ ]/ Q. L- y! T1 h, v& t8 F| MCASP_RX_OVERRUN);
- e1 D. t: E7 _5 B} static void I2SDataTxRxActivate(void)' k9 `8 p- N6 i( e
{( U3 S) h, X% i, N. M9 s2 ]2 d
/* Start the clocks */# j& O7 d. B" e0 J1 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 v3 J4 Y, _0 |6 B; a3 X# ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! n/ r! b+ O# VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( y$ \1 V$ W2 d% O% CEDMA3_TRIG_MODE_EVENT);
- F) G! Z0 ]3 [7 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % l8 j2 h2 T5 |' X9 c6 `0 Y T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! z- g/ k5 }& ^$ `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% w$ `' ^) N. I$ a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 _, J' c7 d2 g6 Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 |% x" E, F" {. W( M& [( Q# R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
m) I9 h& B/ w- G2 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 a' h7 ^2 _( i) L6 o7 G} : q8 y5 A& \, A! g6 A! p" N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 g/ }9 l2 m/ Q% P, {' ^: W n
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