MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
1 R) P' x  J+ f: Hinput mcasp_ahclkx,
4 ^5 ]$ G) f+ Z3 n; \input mcasp_aclkx,
6 @+ I+ C% L& z  `% _input axr0,
' C0 P- s! j! i* K- \# U. z# q; U
5 m  R2 X8 R, u4 M. G" koutput mcasp_afsr,
# U. y. a  J5 d: T) N1 g) ]output mcasp_ahclkr,
# H4 g$ N; J1 e* t. c& }5 M) s6 `output mcasp_aclkr,
output axr1,
; Y. C4 X$ Y% }

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

; H  b0 F0 m" _: a% @& l* U

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

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static void McASPI2SConfigure(void)
. M5 W& T( h; n% X/ C8 A3 J, L{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
, ~5 b% P7 i3 Q+ [: HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' f, y2 W, p' {+ l8 _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 b9 R. I+ D/ F5 nMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 Y" E: @3 S8 F0 i; {2 T! X  FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 E+ ?( b; \) o8 ?( CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 @7 ~1 C& }" u  OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% ]" G6 q; f. @0 _3 a2 VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 n: e: [' |2 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. {. D  c( |( RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( M) Q/ `+ c: a( N* Q6 G0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ u, ^5 I5 w3 A; c  B  UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
7 s8 C, u. e( U; a& C8 @0 c; JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ s6 ]7 V; a7 c. IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
/ `9 S2 i5 c1 n** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
( S6 P; `8 \) w2 C: W8 I** Input - Frame Sync, Clock and Serializer Rx
2 c# V" G5 S& {0 c# e** Output - Serializer Tx is connected to the input of the codec
8 \' X" r: G6 u# y*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) Q  S9 N0 G6 s6 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, i" x  J3 D5 g( }7 K  l1 p| MCASP_PIN_ACLKX
9 w+ g5 O! U" o7 C$ g| MCASP_PIN_AHCLKX
! G/ V1 }2 t0 B. e6 a. [% w* G| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
! R( |/ _" P6 g4 r. b| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 L, f/ U$ N, z! f/ Y; x| MCASP_RX_CLKFAIL
3 C; g& z5 j! h% I, h| MCASP_RX_SYNCERROR
# Q; u) ]3 @* E. k7 ]2 S) o0 w) W| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
* ~$ R7 I) x+ n: }- W3 L/ s2 c{
2 u3 q  H6 G+ A/ i4 h/* Start the clocks */
* g& X# P# I4 ?+ S8 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
+ P. C- N6 Q" x2 D& g9 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 i7 H+ Y4 s; i3 u+ }: KEDMA3_TRIG_MODE_EVENT);
+ y( y0 `' t- m9 R6 y: f* [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 c6 h6 p7 i! |7 X: jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

) _2 Z4 \+ N) q( C

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

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