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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' A. s4 Y$ X4 j3 J1 {, t
input mcasp_ahclkx,
P6 D8 g: J3 ~- G3 winput mcasp_aclkx,
6 f! f ?# l: i3 h6 N4 I7 yinput axr0,
W9 h' l' [1 A
' c$ ?+ A' U( r2 Youtput mcasp_afsr,
/ `9 j+ a' U% z& Goutput mcasp_ahclkr,/ @5 N2 D# T8 Y' w4 ]7 a& z
output mcasp_aclkr,
6 _7 b: |" `" G1 o: G0 a/ @output axr1,
% y7 o i* e+ W C, D3 L assign mcasp_afsr = mcasp_afsx;% h" E3 F" n0 i9 K4 ? S
assign mcasp_aclkr = mcasp_aclkx;
/ `, G3 H" x" Nassign mcasp_ahclkr = mcasp_ahclkx;# x4 r0 {! c+ m
assign axr1 = axr0;
K; L' ^1 s' l& W- I
Q) o2 N/ W# A% ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 h+ f' S ^& @2 b0 s9 vstatic void McASPI2SConfigure(void)
. F3 Z- h; N# ~7 t- n2 a: B{
8 X% I2 X2 e( ?- ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 E5 P0 T$ A5 k4 q6 g: mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- y7 ?( Z* k, s! [9 O% r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ u/ t f2 G1 S% g7 U! ~5 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 O7 j" w7 ]9 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, e( F% I# H7 B" k4 h0 Q
MCASP_RX_MODE_DMA);
8 r: s) ?* k; Z7 n% uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 Z" ~$ t8 U% o/ B. O0 Q2 AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 u1 o# P! |( SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 v- p! |5 h# ?: \: ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 q! I! L6 d" X* }: { ]5 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ `; d. Z, v8 K" a, W/ OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ K4 E4 J9 D8 n" mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% r9 r8 a) J( d: R0 IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 A; W6 C* a3 a8 s, p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, D+ V$ L/ @8 z% q, L9 ~4 r8 c( a
0x00, 0xFF); /* configure the clock for transmitter */
& t; Q4 O4 P9 i1 PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* _& q0 X4 f9 Y, vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; P U; A' y# I |+ iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% _. ?. L8 ?1 }. E, V4 T
0x00, 0xFF);
* _$ _# o. V1 @4 M+ c! {; ~/ g' f8 _% F) C
/* Enable synchronization of RX and TX sections */ / K3 c0 h% C# H; x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 J9 z* K1 [+ p2 K+ u* EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' I) W3 `4 P' H3 `: i5 Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( i9 T' |( P: G9 _ c" f** Set the serializers, Currently only one serializer is set as, P" N* g0 G. G3 N r+ A
** transmitter and one serializer as receiver.6 x/ m; w* ^: s6 j" `
*/9 x* T/ \$ T2 W0 Y; F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& i! }0 L% O! I9 u7 ^; s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 N/ n- D) g- b& F- d7 c
** Configure the McASP pins . P$ G. ^! T& Z$ O
** Input - Frame Sync, Clock and Serializer Rx
: u4 z. w. E5 P4 O) l/ q** Output - Serializer Tx is connected to the input of the codec
% `$ S0 @/ D4 T/ t' Q* W# D/ q*/) g9 D P5 I/ r; u. H% H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, U. c$ E0 E$ b, @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) ^. [# o3 w1 |7 K4 C* H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& ^8 F% z' o; Z6 W+ w; f
| MCASP_PIN_ACLKX
# |. _' v( _, ?' \- }; m2 `- Y9 j| MCASP_PIN_AHCLKX; F" f- W& o( I3 _+ J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% G- ] {) a- h6 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . _0 X }" O! S! j& ]
| MCASP_TX_CLKFAIL
0 `, V" O: k0 P1 E% `7 u2 X+ g| MCASP_TX_SYNCERROR
3 q5 ]3 R/ V1 ^* T( d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ N7 D- V$ B6 a) G
| MCASP_RX_CLKFAIL
% M+ L1 o& w* k3 ?, I| MCASP_RX_SYNCERROR
8 t0 q2 A( q* H% f| MCASP_RX_OVERRUN);% ?$ q2 l: h2 `7 Z
} static void I2SDataTxRxActivate(void)! o1 O+ a' @& {. T' a+ F0 _
{
9 l& z( O2 m/ Y- i% x/* Start the clocks */
9 C- V9 w I, S. I, H! h; ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ ]' C" K' R& D/ F" @* i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// p9 x( S* `) w: r7 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ _4 _" R( h( X5 r1 L' JEDMA3_TRIG_MODE_EVENT);
5 F" k) p0 K, w5 u! G3 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! L% w, |& b4 ?& ^) fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' @6 [' G; w* }8 G$ Q8 p+ |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" |2 {5 a/ p7 u% w6 A8 K9 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 M! S7 S) L8 b! E6 rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; p X7 u' G4 ?, I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: d ~# @7 w! e3 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' R9 }7 }6 g" Y
}
( p. e4 F: {" f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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