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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 o* V" ^7 g! P1 v
input mcasp_ahclkx,/ X: P) {5 d. ]* M8 B
input mcasp_aclkx,
+ P' O' d# U6 y- Z& l' S! dinput axr0,
: r8 `# B+ f- U1 E1 C% b; t4 `8 L# @! G0 H, b2 v
output mcasp_afsr,! [& v8 T- m; d
output mcasp_ahclkr,
$ u3 Y* a) P* p1 Moutput mcasp_aclkr,
- [+ ]! `0 Y7 F6 |output axr1,
# s( k7 a: v: w0 W! j, I& s assign mcasp_afsr = mcasp_afsx;: N) J4 g# ]5 `; t/ A
assign mcasp_aclkr = mcasp_aclkx;
: g$ f1 ]! b9 v2 Z, \assign mcasp_ahclkr = mcasp_ahclkx;2 i2 K+ L- ~: w
assign axr1 = axr0; * N% L; z3 q+ c& F& ^5 l: c. C
( o5 I5 f8 p, d5 w. Q/ o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 `) [5 e' `5 M7 `2 Y8 Z
static void McASPI2SConfigure(void)- z3 j: O+ X }9 O* K4 q+ N
{
! N* Y& k2 e% }McASPRxReset(SOC_MCASP_0_CTRL_REGS); j: U o! i) m; C3 K; n- W# \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 p& c1 V; f( Q. i- P: i" o# gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( ]( ^, `9 ~: w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 A) A* s& U. a+ ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; D6 C) c+ Y+ a
MCASP_RX_MODE_DMA);% k" Y, ^5 _* @ r8 s5 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% k' C# p; j( ?* h) d w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 K0 J5 ]2 G* Y) H7 H( p2 J3 o' y. ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 P7 F2 i6 W5 q: I7 _( _. zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, H B; X5 Y% L+ B* x- cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ }; M" ~) u7 w( ?8 F2 w! DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: N* }3 f6 J5 V5 ]; D D9 W- R- s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( g8 p5 b, E+ D _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / G+ W9 B& v- R8 J5 r8 t7 \, a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& ]5 I% O- V# Y) e# k
0x00, 0xFF); /* configure the clock for transmitter */1 ^" F1 P3 s0 |; u0 W N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; n1 x3 o7 i5 k1 u" ?: y3 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 I7 Y# x2 O. m$ oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 Y) }4 s0 n! U$ `$ o0x00, 0xFF);2 X" L7 u5 H+ P. b3 u# j: @
* k/ X; [# W ^2 y5 G
/* Enable synchronization of RX and TX sections */
3 Y- B9 Z# }$ X2 |9 Z9 ]; g) _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 O g( v; Y' Q8 R9 u5 G5 p3 e- @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
f& T6 R0 R* X6 K# FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; y# j6 N" t% F. r& T. c
** Set the serializers, Currently only one serializer is set as$ P& k* E' G5 P5 V; o
** transmitter and one serializer as receiver.0 M% X; a: l a$ N
*/' J6 d/ k1 S+ g9 U4 k3 z& u e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! y% N, f0 D; F; Y6 E7 K0 SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ z) l7 a4 s! P5 o/ p; i6 w' G** Configure the McASP pins
9 p* l) c3 f: |% y0 j; I** Input - Frame Sync, Clock and Serializer Rx
6 V1 y6 i5 Y7 P& K5 Y7 ]6 o% c** Output - Serializer Tx is connected to the input of the codec ) C9 v% C3 J( t- s2 j' A
*/9 M, F8 I# S( x' e( ^" n" r1 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# \8 I+ J. g# l- f6 P. q; _2 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, N1 f/ T& g# n! d1 y1 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX ]# `: _5 V d5 H% t
| MCASP_PIN_ACLKX0 A+ D2 M6 w# }! {# c' j, z# W
| MCASP_PIN_AHCLKX* ^- c! v8 }3 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# `" Q0 X, I7 c1 j: QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' d" ^% l& I& a4 H$ L1 @
| MCASP_TX_CLKFAIL 7 `7 Z& c5 [' K) `2 v" _
| MCASP_TX_SYNCERROR2 A. K. d# ?6 z% O/ S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- d8 {% C* X! f! z4 n5 R| MCASP_RX_CLKFAIL
) A6 f- Y9 @1 [ N| MCASP_RX_SYNCERROR
: i x* v$ ?. \$ A. l| MCASP_RX_OVERRUN);0 m0 [) y. U0 a: Y% e) A* d$ f6 b
} static void I2SDataTxRxActivate(void)0 M( U( [7 g" M
{
2 \, j" r" H/ B5 }# C2 p/* Start the clocks */- z. @& w# _3 U8 ^* W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, a! G- z8 k' u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) X. q! w" M2 _7 H) i4 ]/ w) T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- d: |- Q) t4 K% n+ I1 `5 DEDMA3_TRIG_MODE_EVENT);/ K$ b1 |* `0 S- r8 e! D5 ^. X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * @5 ~& I1 t" e8 ~; F0 ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, F5 M' z- ~9 |! E @3 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ i" N& R j. c& ~% U" {4 iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 ~) o- ^( k- D- r1 H" O7 [, Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// O" _9 E' k4 G2 \0 `# A7 M w( r y- s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- \9 C) l2 Q; k8 t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 H3 u& M t+ a# o5 u/ c5 w; r} ; n! ~6 t; ?- Z. K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( W/ A" M: \! J7 O( n, N
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