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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 m/ l4 ^6 J0 T8 S& R. v) E8 z4 \input mcasp_ahclkx,* ?; `0 q7 S' N7 @! V- G
input mcasp_aclkx,. c) x2 ^ y+ ?7 m$ E; H
input axr0,9 _ F3 L6 K1 o- U
* V0 M" k' i2 e5 G Soutput mcasp_afsr,) d& p/ g8 L3 Y7 o( l% U( ]7 R5 Q, K! X
output mcasp_ahclkr,4 ^& \# Q U) A
output mcasp_aclkr,
% c! N9 z& U o/ Loutput axr1,
% ~1 n _3 \' o) c assign mcasp_afsr = mcasp_afsx;
" Y Z$ c* _" Rassign mcasp_aclkr = mcasp_aclkx;
9 v$ \, Y0 s2 A, R& Lassign mcasp_ahclkr = mcasp_ahclkx;
- T' [6 P: o: l! C) ~+ `assign axr1 = axr0; ' t. A& o! l: K( Z# S8 H
+ F; J' h/ f& j2 ]7 z+ l" Y9 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# ~% x0 A# c, t. j ]static void McASPI2SConfigure(void)
0 ?/ H; v8 J# i* x& h, N; F{
2 k( J% x$ Z6 u F+ \+ V' _- lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 W3 o, S: o# W) G2 R/ b; `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! r- M. v; O! a+ o, O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 Z7 \2 L1 l- D3 N7 G& X# pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% }9 D6 n. v/ D& e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 z" z! @7 _+ B' s- J6 lMCASP_RX_MODE_DMA);8 Z: f. d' ?9 t; m/ b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 Z) j, a) v+ jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' @- B: g8 a7 b, F/ s- v, y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, u& b2 e6 l' O; m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; A1 O K! {. T) E/ GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; m9 Z1 A# I) M( e2 |* ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 ~) M# s. c: Z4 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 E: B/ A" w3 K/ ^, p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 V! h" ]$ l G: R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 g4 ]! |$ i7 r- Y; k8 x9 G* V! G0x00, 0xFF); /* configure the clock for transmitter */5 ^4 e. p1 Y4 s# M) b& g, P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ h) Z7 B- E8 z' PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 z8 O N4 n Q: |' z$ n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ h! J, d; S* g. ^
0x00, 0xFF);* d$ Y$ G4 k$ c. q- p9 ]
7 [: m3 S$ j+ Y6 q1 [* D+ Z/* Enable synchronization of RX and TX sections */ , l7 a; q4 H# j% Z) _& \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 ?& \9 a$ f! \0 r) d" B8 L, IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; `" N3 w1 Y5 G) Y4 b5 G# xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 g Z7 t( q" g: @$ t
** Set the serializers, Currently only one serializer is set as
( w& K* Q h8 j: l, R** transmitter and one serializer as receiver.5 m* m) P* w6 p J
*// |' Z) |9 ~/ O# W' ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 z6 U% H v. z) U" u! HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. y& \6 a( Y# V6 c/ l7 }7 M( g
** Configure the McASP pins
& K) H, c' R! I4 D8 ^: W2 |! s** Input - Frame Sync, Clock and Serializer Rx% c* G0 t! Z0 z/ {) Z
** Output - Serializer Tx is connected to the input of the codec
5 \9 J$ o+ `9 t0 G3 O+ A*/
, x" [& }: ~# x, C. G# m# rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! w2 n2 c6 o* A2 ^' J( ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! W h* T& p5 E1 b9 m, mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& r4 `) L9 g8 D$ _5 F; Z5 R
| MCASP_PIN_ACLKX
0 e- I; ?) D; S" c n| MCASP_PIN_AHCLKX$ \( ?( z. J6 d0 @5 K$ S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) ^6 t* h! V3 o* Q3 C x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
r+ W8 Y& G# g: r| MCASP_TX_CLKFAIL ' _1 }' ^" Q, D S
| MCASP_TX_SYNCERROR1 o1 p) I3 a/ h* U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. S5 M( k, H( m( [& v# q6 K& s! o| MCASP_RX_CLKFAIL
2 H4 i* B% t/ [5 L" _6 D! p0 b6 H| MCASP_RX_SYNCERROR
4 T T/ s Z% |/ W2 |1 d) b. T+ ~1 m| MCASP_RX_OVERRUN);
+ f; W, _% h6 R- ]! z} static void I2SDataTxRxActivate(void)* l5 e, F. Y. [" z2 T- \
{
4 |6 g+ B, B- o+ @+ X/* Start the clocks */- W3 ~, P* g1 B7 z2 H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 |6 t4 c( U4 }# A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 s4 d2 X5 z: hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( [" T! \3 |1 H, ]7 E; E: j
EDMA3_TRIG_MODE_EVENT);
. W9 G9 d$ s8 W8 D5 ]; UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! f4 b* v( S- b2 \# Y0 eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: m: E* b% {7 n9 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, g. y5 \% W, P( H. ]& |/ H: B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% ^# T8 B6 k7 ]. C& cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. a' O3 b P' z6 UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ D" t. h+ s9 E% h. ^1 c5 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* O$ z) [. m& B
}
) v5 \# k9 s& [9 z; ], t; V' c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - u4 V# [6 r- M- O* q
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