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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) A' ?# Z: ^( s9 D) }input mcasp_ahclkx,& ]5 I" [2 J8 o2 J
input mcasp_aclkx,$ n5 J( r7 b! J1 u& z5 g) U5 r
input axr0,
: B. p( \) J6 q" J* O& }8 M
; D( `: S% K% z) Z5 houtput mcasp_afsr,
) H m* m; c, {- o7 h) foutput mcasp_ahclkr,
& ~+ o9 E' v7 F" _$ Boutput mcasp_aclkr,
5 U: t3 x5 q7 N) S8 I: Zoutput axr1,
6 K1 ~3 U# i$ N2 x. Z assign mcasp_afsr = mcasp_afsx;. E3 ?6 L$ p/ s* @6 s( X j6 C F
assign mcasp_aclkr = mcasp_aclkx;7 o$ Z5 n9 p/ _ o8 H: G
assign mcasp_ahclkr = mcasp_ahclkx;
; B. `7 j, i% o" @7 K: e+ a% xassign axr1 = axr0;
0 L* l3 ~7 @: A7 x5 n! g4 |: v: n
1 D$ J, `; M* e4 F# I+ N/ A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; [0 G; k% |4 ^% Y/ \; ~* v/ {
static void McASPI2SConfigure(void)! ~" |. }# G/ a _
{: Y) \9 }8 j3 F# z8 }! l3 D6 |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, b) x( H8 {! e9 z$ L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 I4 G" O; K' IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" O& H) P) ]( k, [) ?$ UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 _7 }: Z& k1 f( o1 ^6 z% W. T- {. `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 l% P3 C. K4 m
MCASP_RX_MODE_DMA);: g- S5 M" o3 C8 d& l0 J5 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* S u# d& K- BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 d( M6 p( M7 n$ v) a& p2 b: l1 B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 m. [% h# X* \8 y+ z5 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 m$ M" O0 a. A; a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / @* n5 Y/ ]) ^! S* ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 ~& x, m9 I' Q' R; ~; FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 e$ E4 D" V l- K7 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) K8 C# I% X. x9 V \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 X8 ]& u# x! M0 u0x00, 0xFF); /* configure the clock for transmitter */ E5 L$ F: j, P* ~ K% g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; g( a9 x+ Q% C. Z9 a1 C. _+ C1 GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 i$ D. F1 N, b+ k- T) l, LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 Q. w( l8 {/ z+ h
0x00, 0xFF);* ~1 k. T; Z8 S. K+ p
% y5 z$ v8 R Y' U, a" p/* Enable synchronization of RX and TX sections */
0 Y' z4 }! d0 W3 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 T! g7 g4 `& U6 [; x5 w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 f8 n+ F" B0 H& V; n) z( wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( ^0 f2 \ C7 w' B* f% x: E
** Set the serializers, Currently only one serializer is set as3 g2 B ~6 f/ p
** transmitter and one serializer as receiver.
/ S2 J5 \) Z. [% @2 D, t9 I*/& x1 x- Y( r* f' P C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 x! e3 e: v/ ]- bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) H W* `+ j! L8 G4 [' s** Configure the McASP pins 0 b+ g, ~; G! ^! e
** Input - Frame Sync, Clock and Serializer Rx& f8 W \4 ?& k& `: O; o) g
** Output - Serializer Tx is connected to the input of the codec
" c! i' _4 z* i( z' I( \*/
$ r+ q& }; t. U: v- m l5 WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 X* L8 V) e* s' `9 P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- d9 R$ @0 Q9 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# V: E2 K: F! g
| MCASP_PIN_ACLKX
4 Q2 U. y2 }/ |* a+ d| MCASP_PIN_AHCLKX W# @8 `7 L: \0 t* Q$ V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 Z2 {# k1 X# Z7 nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 w) `* h2 r0 r, c| MCASP_TX_CLKFAIL
7 L5 o& n1 C! ]' p+ s/ W| MCASP_TX_SYNCERROR7 }4 m, a4 [ M. m3 j5 O" H% E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 R) I% [' r/ ~1 E4 S* S
| MCASP_RX_CLKFAIL
* u; e5 e3 C3 y% Y| MCASP_RX_SYNCERROR
/ E) _4 V$ G: t9 W) z| MCASP_RX_OVERRUN);
- s9 K; |, Z' e# [} static void I2SDataTxRxActivate(void)+ O" p+ W- B+ W
{
8 k* s& o8 C1 r( y+ }8 m6 P8 C5 C/* Start the clocks */
: j9 }2 Q3 X# _% Q& Q( |% C& \1 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% c, K, ~: v" }# v" }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& q- ~+ j# [- H, d+ ~! J" LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ e& p/ g2 ^, T/ a0 {3 B; i
EDMA3_TRIG_MODE_EVENT);+ I) f' F5 j- q/ v) A' K" B" w" {7 F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, g0 e( S; {- j) X; ~7 d/ I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 C* z' ^7 J5 ?9 G6 v1 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' f4 j; A8 _6 s) a7 Z9 M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 j& T9 m6 X4 j6 q# ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// j5 |: M% B9 h$ Q7 M. z+ y+ Z9 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ T2 ^9 [) j) N r- t0 N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 g7 o( Z( [- j! f* J7 l2 p( c I- D
}
V& h: X4 ], M8 Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , e$ o" W) O# u) m& m& C2 a2 j; M: S
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