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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 n; \5 R& ~+ H7 D% o( s
input mcasp_ahclkx,
: L" t9 o8 x8 q% C6 R- Binput mcasp_aclkx,2 P6 B6 `# }+ u( j) o1 ]: s
input axr0,6 L6 F) {( r; e2 \- \% B0 R
, B4 \% F# Q" A/ _+ Noutput mcasp_afsr,& l5 `* g y l* f
output mcasp_ahclkr,
: S: G# m3 V. Q% x7 T4 loutput mcasp_aclkr,2 n9 h& |* s' s4 ~# j
output axr1,/ H, G3 g* j; C9 N- i# ?
assign mcasp_afsr = mcasp_afsx;
4 b& g4 h. u5 t8 \+ S( passign mcasp_aclkr = mcasp_aclkx;
& T, Z5 X) F& d- N6 X* @9 passign mcasp_ahclkr = mcasp_ahclkx;
. t! ?$ |" `1 R$ J# Yassign axr1 = axr0; , ^; E( H% {7 g8 G. c, I) u4 s2 W
* |) G$ X) v9 A. y. P. n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" Y$ \8 r+ I& Wstatic void McASPI2SConfigure(void)! R1 L4 p k; R' i2 d9 B
{
' l6 Z. A5 Q& G; k' S. oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& O* l3 e2 s" a1 M- G/ h. V1 iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 ?8 C# b. Y* ^$ \4 {( c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. Q# V1 t9 R' q& p, W+ AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 f* Q4 s @8 F5 {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 _, P5 Y) y( |- l" z) y
MCASP_RX_MODE_DMA);: I1 j0 |/ B- u+ M9 s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ a: f E# S; Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- z' J# T( L" e" X- K" t. {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % s; I: g: t" d H' ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 {5 e5 {% L0 h' YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ Y* F0 ^0 s0 \ EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 s& [3 D# f' A8 zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. V; S: H2 }+ i' x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. l4 j! d; t4 |7 M& ^" S8 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ v* B4 \- f. ~+ p& v' I. ]3 n9 {8 N; ^0x00, 0xFF); /* configure the clock for transmitter */+ k/ P& F1 e( U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); d8 q0 @% g+ e6 k6 |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % T; a6 U9 M5 J- W# u) s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# U. F8 S& ]# k3 f+ n0x00, 0xFF);; T$ G3 P# N" M
' M3 l# H9 }4 u/* Enable synchronization of RX and TX sections */
/ o Y. d* L. H; zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ V& _: Y/ E* E! K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' X* \2 N# v! }6 k ]; R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* W9 c( s* D2 W" G8 X
** Set the serializers, Currently only one serializer is set as
9 P+ `: R4 W+ F** transmitter and one serializer as receiver.
% O. ~% B! T p" i9 `8 U" D. _*/# W4 \6 z8 n- }( }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ ^( k1 g7 `: |$ f; U3 }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, s D7 i1 M) r# q9 L( Q# J** Configure the McASP pins 8 i" @) p) _3 q
** Input - Frame Sync, Clock and Serializer Rx
1 c" m4 R6 G% N: e; t/ c** Output - Serializer Tx is connected to the input of the codec
/ y' K0 D7 G1 k& j*/* V, G6 M0 R7 t+ W9 d- _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 v e% b- i7 K9 ^+ Q; w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# j0 B& h2 E$ @& _. [# e; _; D; eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, r4 ~9 a1 @1 L/ \% p
| MCASP_PIN_ACLKX' w9 T6 t- Q" J% Q3 P
| MCASP_PIN_AHCLKX3 l3 X M. {& S) b4 l1 b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' T( K- c" ~5 y. S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
R1 b( T5 p f3 e) N| MCASP_TX_CLKFAIL 7 G8 u1 |1 f* \
| MCASP_TX_SYNCERROR
: v7 o9 Y9 V6 S/ D- m' i+ E: b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 @. ~% p# `( e, ?- f! s* j% u
| MCASP_RX_CLKFAIL
5 V- a# a" ^! @; X2 ~| MCASP_RX_SYNCERROR
, l' i/ s" S I' I! V' m; A7 M& N| MCASP_RX_OVERRUN);1 f+ x2 I% j7 ]2 h: Y; w" j
} static void I2SDataTxRxActivate(void)
$ ~% o' G0 G! V `{
1 E T+ J9 M& X3 y/* Start the clocks */
3 Q. U# z. {2 N5 R7 \( T4 q# O% ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) H! ]( V/ t3 T) o( A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( R9 }8 d1 B) u3 D6 e a. a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- `: G# f$ ~6 \( {1 ?+ OEDMA3_TRIG_MODE_EVENT);
A! d2 Y# ~8 h5 T0 T0 X% n$ fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* t2 v* G( z( v2 I8 B/ ~7 ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- c" a- Y, N" F% A+ e! yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' a9 T/ I/ u- C6 `4 w# s* q/ Y6 {) {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ k$ v( q, [ C, ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( [( \% ]+ g( _3 v0 f: X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& G4 n8 k7 t. j7 d/ h! }- e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ E, [% @7 c& @: b- `3 Y
}
7 Y1 ^' N* L# \' d& {2 k2 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " V# V e8 f ?( [! A4 n* w
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