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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& j0 O! s* T' `0 iinput mcasp_ahclkx,
" g. M1 y7 J6 P: K |4 Zinput mcasp_aclkx,' |7 x4 D; o3 z. K8 {
input axr0,
* G; h Y# v* a& ^0 r" x/ C% z0 m& Q6 a8 [
output mcasp_afsr,
$ U2 a/ h# M& M! ^: z( Woutput mcasp_ahclkr,
& X1 W5 n' q! [' j" c& D6 E; Houtput mcasp_aclkr,2 m- W# T: O5 B; d& G" Y u
output axr1,
) U4 K3 H" w7 A& i" y assign mcasp_afsr = mcasp_afsx;
1 y) @) ?0 E" h' g% nassign mcasp_aclkr = mcasp_aclkx;6 z& ^2 O5 j1 T, |: k5 \9 s/ l% G
assign mcasp_ahclkr = mcasp_ahclkx;
! u R. ~# k$ [0 m* Q% p# h: Cassign axr1 = axr0; + E& [: b" k6 w6 u
3 J8 L! i! b% k6 A" y' Q8 n8 k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' T! S9 `; {% [1 G9 cstatic void McASPI2SConfigure(void)
) I" V9 l0 k) e% I$ F- |{
9 V0 {$ e: U/ ?, d$ T! n- mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# Z& G2 i8 h& g8 P, {9 n$ Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 `2 s/ m) ]/ i$ m% MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: R: l# I! B8 w$ ~7 I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- a, s1 e w6 f6 G# B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% W# K7 \+ ^% x% |+ ^ d- IMCASP_RX_MODE_DMA); _# F! u6 b4 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 w; Y# h$ C( v( V& a8 ]) FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. j% N: X: T! q& d3 Y9 y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 n" i) O# c. YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 c" G' C. G. ]2 V' f8 I6 c6 l/ ]$ YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + k# @3 O7 I; S4 I9 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 B) Q5 Q$ H+ l& J# G' n4 H; b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* F' P6 w' i# w% K! s5 zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ A! o' M7 J, l4 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, Z' P2 ~, M0 n' ]) T0x00, 0xFF); /* configure the clock for transmitter */
& q1 G. K# C7 FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, j/ b4 h7 H4 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 r9 w2 S) } WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% |/ @0 L# K( s7 K
0x00, 0xFF);! E8 X" @+ J3 w5 d* `
8 H% p1 d, n- z7 U8 g1 S
/* Enable synchronization of RX and TX sections */ ; I$ l! O7 n; t# w* R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 T# O4 G4 T4 hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ j( `5 Q W3 P* oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: [& D8 H, G9 ~# c! h
** Set the serializers, Currently only one serializer is set as
% u: \% x5 q3 d8 J% o$ U3 V0 P% g** transmitter and one serializer as receiver.3 o4 r( O0 x+ o; n7 t
*/
, S5 g4 ?2 b1 p6 r. z& `' p4 ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: R( N, Z! o6 S4 @! hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ r! E* d- d y- K4 l; L0 p) u
** Configure the McASP pins
+ X6 t) r5 j) _& g** Input - Frame Sync, Clock and Serializer Rx
+ M8 z4 A2 T1 Y b1 W) U** Output - Serializer Tx is connected to the input of the codec & g2 `, J* r0 _0 S
*/
9 L1 U) w/ E% ~# M! [" MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 b9 E9 Y( Z+ B1 Z4 \# h# u/ x# L% Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! F- F5 H% i+ S0 g- e* P; V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 k0 d! q) x# n5 p: k2 g' N* ~1 W| MCASP_PIN_ACLKX1 K6 q3 R0 o" k# ^, m) [3 a1 i, C
| MCASP_PIN_AHCLKX% L# z3 w0 ?- P: I$ {% B& X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 ^- ?# ?3 m4 g/ ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 u9 X( t. ^6 r$ D; h0 Z# @6 E1 ~" Q& Q| MCASP_TX_CLKFAIL
3 x" d( {6 p$ O- w- {0 Y& j| MCASP_TX_SYNCERROR
! Z7 x; \; X# M; q1 H) y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! w$ x, U9 X" q+ [9 f1 Y. g
| MCASP_RX_CLKFAIL. V+ q; T/ {7 M, j% h
| MCASP_RX_SYNCERROR
?3 Y$ g1 u5 Z, W8 G| MCASP_RX_OVERRUN);1 u8 m0 ?! F/ Y6 t: k7 c
} static void I2SDataTxRxActivate(void)5 F% t6 D) `9 @/ `0 o( x+ ?% j
{
" n# s( l& e, x$ F; ~2 l" p/* Start the clocks */
) d- x5 \0 I) G r6 T2 ^9 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ {. L* J* ^1 o& h# J* [( D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; O1 C" m* |" n( D+ REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
L1 J5 O0 s. b% L, d7 t* n' ^EDMA3_TRIG_MODE_EVENT);
/ ~' p8 t7 s& |7 C% _, tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* _* b3 r" b; S2 d/ lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. U6 A# p9 f) A* U) t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 J4 K$ t5 w: q# b( _/ D1 ?0 u8 p+ bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! H8 M& ?1 P5 U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ _1 @4 H0 R6 w% J# e/ Y: n3 L0 E. JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); ^, P' y( X- [' l, ?( c: `% z3 z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" ]8 P7 a1 q, P; J9 t
}
n7 _! Q# m& j5 E) y* t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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