|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) z. `7 f; N3 p1 F* u- Y
input mcasp_ahclkx,# o M1 E; Z$ O, g T
input mcasp_aclkx,) E& Y0 D: G, ^3 J
input axr0, v( v' F2 i+ o; f" U7 A
2 O1 ?3 D. X% v# g) Moutput mcasp_afsr,9 b; x1 W) A- q: `
output mcasp_ahclkr,5 ^, B1 {4 |2 ]# \4 {, }
output mcasp_aclkr,
4 T9 |8 W, x3 d1 B+ s9 {. b2 aoutput axr1,
- s8 X: o/ ~" \ assign mcasp_afsr = mcasp_afsx;2 p# S( n( C8 O1 p4 x1 H
assign mcasp_aclkr = mcasp_aclkx;
# M. I, w5 K2 Z6 B& B; |8 ], v' n# fassign mcasp_ahclkr = mcasp_ahclkx;$ S5 V! V3 J0 S/ ~
assign axr1 = axr0; ) D. p$ x0 \, `& u. Y9 |
7 G* u% G) G( C S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 a+ K% v8 n" ~8 k+ @
static void McASPI2SConfigure(void)
% w3 y" L [# l. E+ j. z7 a{
" |8 O* G5 I) K4 j, u) zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# h" |# y8 Z K1 K1 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! `5 K3 |0 x- d$ b7 v+ e$ {+ r. l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) |3 |0 T5 s: ~; v- y2 ?4 | H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 W" D4 q5 B' M# K9 A% k* IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 }( ~, d6 Q2 }; n; A* _7 o7 Q! R
MCASP_RX_MODE_DMA);
& N9 \1 A0 }* ~3 d- VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( N1 Z) G6 w2 k2 b7 I9 ]$ P# n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: z% v$ t, R8 ~+ c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : Q+ G' [& h! k7 j* Y- f& m5 W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ b( O2 I/ [7 t: y+ VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . m8 w: c* n( C. i8 N6 {0 A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ h X. T! r' p/ a/ W* R5 ^5 q3 t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& l3 H! b# L, q0 w$ z, c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 H2 _3 Q$ G0 F& mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: s1 W# }4 ]4 }7 |. I
0x00, 0xFF); /* configure the clock for transmitter */
1 s% P0 h' S1 M# O5 _8 c& AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 m/ @, ^8 D" @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 M( k" H) X) ?4 l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, g j$ S f- I# ^/ k3 @0x00, 0xFF);: Y1 F3 k* D3 |; S1 N) a
% z- l( {& R# o
/* Enable synchronization of RX and TX sections */ : ? T) ^ y: _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, y1 m* r8 m! M+ g, m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 R; J4 g& Z* W8 n# N; yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 G6 s: m- r5 d2 e$ l" o
** Set the serializers, Currently only one serializer is set as4 w' K' g1 ?9 t0 z8 C
** transmitter and one serializer as receiver.
) l8 \! [% e$ E; \5 e4 x/ H*/
( {- P5 s! L/ r; n+ f. UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 w( x. G6 \6 r4 f- jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 [% r1 A' {+ m** Configure the McASP pins ( n& N. Z6 o. n; i
** Input - Frame Sync, Clock and Serializer Rx5 k% i# ~' M) u( A
** Output - Serializer Tx is connected to the input of the codec 1 w0 t& }+ [# j$ B
*/7 R" X, Z9 I' G! G$ h) Y# P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* S% F6 }1 n/ `4 J- Z8 k9 a, n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ J& T1 n) u- T! kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 e! f1 Y& w/ F& d8 W3 Y0 d| MCASP_PIN_ACLKX7 Y2 x3 c( T, A0 a; C/ i
| MCASP_PIN_AHCLKX; Q. B% ~3 H& q; X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. t) b, [9 y. G) f% S( GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 z8 u/ `- u: Y$ x, w
| MCASP_TX_CLKFAIL
* T# I/ s0 Q8 G. T" O& B- m7 z| MCASP_TX_SYNCERROR: G$ j0 }* K. T9 N. n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 ]! l9 E+ S5 B, `! h7 X| MCASP_RX_CLKFAIL
6 I4 a$ ]. q- i* _| MCASP_RX_SYNCERROR $ t3 V6 R" e! b3 ` c5 q: x. Z
| MCASP_RX_OVERRUN);
7 }4 C0 P V- T5 u& c5 \} static void I2SDataTxRxActivate(void)
1 H( }; H3 P7 P8 Q% ? K' Y{& |$ V) j9 Q& j
/* Start the clocks */
! q! t: U/ i# mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 F$ T4 {# F8 ]( kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) W; @$ [" f) c9 @& ~, z. h; \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, T) i1 n+ V h) }* i! h* E# I
EDMA3_TRIG_MODE_EVENT);/ Z) _/ M9 [; ]/ b* f9 N J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
B! H- D- x8 e5 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ W) E: z) K2 t. y! w8 g; mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& T! o6 o1 N8 g& K8 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 O x6 w0 I$ I4 T2 s3 bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: u+ p& x" @1 Q0 M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 X- y' E+ {- I' e; S9 o7 l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; \/ b7 m4 w/ ^4 a}
6 b4 x2 e) _- ?) ]) |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ a: E( n3 N. s: ]$ { |