MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
' G  ~- d) x* @0 h) S4 Pinput mcasp_ahclkx,
input mcasp_aclkx,
! I' s) C  {; h0 \, p' f; M2 {input axr0,
$ L2 f; Z2 L$ c# M
output mcasp_afsr,
) m# S4 `9 h3 Q$ X5 S; s) [output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
+ H- a( a9 e3 W4 F1 r4 p1 Bassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

+ K, l3 e. x, z9 b2 x; v2 R( z
! [' t0 p" M# z0 T; T

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
9 C- ]9 p  R/ Y  r6 b) _, P{
/ |3 _( j5 C3 S: b% n$ S8 C: }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 @- n2 w1 |6 U/ v; l4 @, h/ JMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 Q" @' `' A* MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
7 H" h) J  A/ n. k  `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# c$ x2 ?) t9 o' M! |, a7 jMCASP_RX_MODE_DMA);
/ M: U# u' S6 G6 x5 ~" `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 Q" X9 h8 Q0 O0 A6 oMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 C2 N' _' q: ]5 k& XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! f5 r: }% q7 E2 _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- j7 p+ k/ E* yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 ^8 K8 [& T/ O7 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ k& A. v) p+ m8 [. h' \. C/ R0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 c+ v. N5 u& r7 ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& d3 y8 m; F5 T8 b! Z8 G# R" t! b0x00, 0xFF);
7 `" R& F: i  L9 m
6 v4 H4 S+ r: G+ ?/* Enable synchronization of RX and TX sections */
( w/ C3 S' k4 y( |# o- q& l0 g* mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% b6 s$ K( H7 x( `, f3 i% }; cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
$ C( ^# G, O' S6 J7 }8 {  P** Set the serializers, Currently only one serializer is set as
( s3 t% l2 g9 I' r** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
+ {& N/ X/ L- _. c** Output - Serializer Tx is connected to the input of the codec
+ z+ W& V. J+ H1 r, C  Y7 P% R*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ r5 S; k0 j. B2 Z% j; ^4 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
, i& M- G4 c" y4 [( g* b3 B8 q}

static void I2SDataTxRxActivate(void)
{
. {' w9 z: ~* Q8 A' r; Z/* Start the clocks */
2 R, [; V: k7 E4 o6 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ k8 |3 l* _+ J/ i* y4 k% S) f5 GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) y/ I6 n- A* j6 G9 d, u0 L& ZEDMA3_TRIG_MODE_EVENT);
- [+ v2 J2 \: X0 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( {0 Q, E% \" C$ x' h. ~5 s/ i, AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
# z( t# N. l0 G. x" I7 VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ v3 @( ?/ C+ m* P. c. UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
+ o' y( q) D' s7 swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
8 C, S, D3 z0 s  B" V& X$ hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# @5 O" u' N6 V& b  D: t, J}

0 O# F6 Y0 D* M9 E6 M3 c

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.