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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ G* i$ P9 z: `3 @1 V( t7 [. E; \/ O
input mcasp_ahclkx,
" j2 N% H; I4 C7 U, s0 Oinput mcasp_aclkx,# B1 m: W3 i; Z2 q
input axr0,
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output mcasp_afsr,
: G+ i1 V" y" \* V1 }" k/ Coutput mcasp_ahclkr,
W6 |; G' v- N7 K7 U- r) f4 Goutput mcasp_aclkr,
9 M% m) U7 i9 }" p! i2 {* Aoutput axr1,+ g: K5 p2 U9 C
assign mcasp_afsr = mcasp_afsx;
9 @# T+ r/ n5 z3 Yassign mcasp_aclkr = mcasp_aclkx;& z% x) F/ Y; k. h5 N7 C
assign mcasp_ahclkr = mcasp_ahclkx;0 c: Y( Y2 u5 i1 B2 a
assign axr1 = axr0;
* O- y/ \& m: X( a$ i H) ?/ V& K; z1 H2 p2 {9 P$ ~# g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # p6 h8 o9 r) ]- X% t0 Q$ r
static void McASPI2SConfigure(void)8 S, H. S1 z6 c+ M5 }$ f, {6 o
{
+ g' f8 _/ H( Z6 u f" c$ C0 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 C, A! M/ m( O0 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// _+ O% u6 Q' n, Z5 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 X; ?* s9 y7 k+ H, D/ EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. f3 M1 a5 N' pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. z9 I3 o8 \2 M7 U: UMCASP_RX_MODE_DMA);
5 _1 Q" U' w. @2 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% @$ q0 k" i& }1 y6 D4 G, _# P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& R* w) M; B0 z0 Q C( D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 o. e; J9 A, eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. A; E0 T9 g, z+ {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- k8 S+ Z) p" C! |- h% dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 ~( \( x4 f1 D" X) B; l% j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 @$ Z) @& M/ |1 j; x8 x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " v- j* j) a" i9 j( ^! j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# S' q5 H# v/ ]/ u, [4 P
0x00, 0xFF); /* configure the clock for transmitter */, ?# z1 z5 U: q5 j8 k* y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 `3 F/ |4 a7 z" ^8 p. x" Q0 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ N( S1 f* G( d' L- h7 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ J6 M% w7 t! E" z3 v& B4 h) q0x00, 0xFF);% k2 e0 P) d$ ^6 Y$ Y
: A4 R5 g" t9 K, s1 ~) w1 K/* Enable synchronization of RX and TX sections */ t: }& N" j" c' e+ H( U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 \2 \; C9 h# `( @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& e$ U4 `0 |" J7 E/ IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. } d# V/ y2 G# u
** Set the serializers, Currently only one serializer is set as
7 M! o. ?* p+ X" {% @6 @/ y** transmitter and one serializer as receiver. _8 H) |5 l) A' z8 X" |
*/; h& A" U8 q' s- T9 H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' b8 `) Y) k1 e2 P6 B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 l) M0 h# P' F) j/ r4 t** Configure the McASP pins , u( U+ M( K9 N
** Input - Frame Sync, Clock and Serializer Rx# Z! s8 N, b) }) K5 Q, U
** Output - Serializer Tx is connected to the input of the codec
/ X1 S% E' w7 p*/* `; g6 `3 v# i8 z+ o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% K/ G) @4 ]1 g; y2 V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) r: e0 I# @% ]9 i/ [9 j U l/ ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 N! p! R- m1 ~1 E| MCASP_PIN_ACLKX' B2 e8 i5 l6 ^0 e# _
| MCASP_PIN_AHCLKX
/ |$ i) F6 j2 R- d+ s f2 u7 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 t8 A# B% @. P% g5 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 B3 y- W5 f: C: N$ |( v
| MCASP_TX_CLKFAIL
& _1 E: [$ }( r+ ?, J| MCASP_TX_SYNCERROR
% s$ C' O4 X: j& [8 k& T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 S: F" [3 D# }1 x7 t! ^
| MCASP_RX_CLKFAIL* u! h! d! J& B* h
| MCASP_RX_SYNCERROR + n* o5 h; `( \8 c: w. u# @
| MCASP_RX_OVERRUN);5 v' q4 i6 r3 g" Y4 c u
} static void I2SDataTxRxActivate(void)7 r9 g, |- L4 b6 ?8 O- m5 e# u6 O
{
7 L$ S. M. j5 C7 Y# ~' C7 ^/* Start the clocks */; e' a$ h: X0 c! y/ C5 Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- @0 g) W0 T: j" W8 V% XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! d0 X6 i* o9 S$ X: _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; o7 i! k: z J: h3 V' ^EDMA3_TRIG_MODE_EVENT);
& [. @* S0 ]- ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! R7 s' W. p; R$ ^3 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' ?) G8 N w+ D6 D5 O* lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 k' k3 h/ w, k' Z, \+ R! P. E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ n8 g9 C1 j6 T Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) @( d1 V% x6 @0 c0 S; lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* J! r) _6 J, l$ e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 N. `- z8 W$ b: I' P0 W/ T
} 6 F- h0 V ^) y7 S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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