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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& F) n7 Y7 g$ U9 B0 D: binput mcasp_ahclkx,
+ \7 g' w! k( g% U/ oinput mcasp_aclkx,
, J a% |0 f& ^input axr0,) H1 p" _1 Y v) `6 g' F
3 K2 H& {% P0 q$ T! d2 eoutput mcasp_afsr,
$ d5 _- p4 V# T* i; N" @4 Z; toutput mcasp_ahclkr,
4 J4 F6 h# w* g( ~7 xoutput mcasp_aclkr,+ S9 m+ x8 h0 Z. |7 u
output axr1,& R3 H: _- Y3 A3 W$ k$ B" }! G
assign mcasp_afsr = mcasp_afsx;: D% P( G& ~4 _" _
assign mcasp_aclkr = mcasp_aclkx;. _/ `# e) \$ _% A+ w! j
assign mcasp_ahclkr = mcasp_ahclkx;* v+ J% j4 F% U+ f
assign axr1 = axr0;
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# H; ]# l8 V% l: }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" g/ l: y0 S. e" W4 g4 z" ~static void McASPI2SConfigure(void)
8 c8 g7 }$ D; n4 o/ @5 O{1 T: ^0 k8 {7 i5 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 E# L) L( f. ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ X5 P% P; @, B6 h+ h; O2 U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# F* E2 l, \5 O' cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& ?" Z/ W9 X: l3 J* Z# [* FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ~" J; h; `. Q: L J0 gMCASP_RX_MODE_DMA);7 E- j% S8 o5 \" ~7 C, A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 M, Y7 j& m3 P$ G2 l1 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( R2 b* F7 ^( d$ KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 n# B; v) \9 A! y+ C% n2 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, R& ^8 X: ?6 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' B' Y# S% X* Z. ]1 a+ WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ V3 p2 j5 {6 W# OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 A7 M3 a( Q+ S6 _3 T5 QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 g" @5 Q2 U& s, s% b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 s8 f7 z3 h) q) c. l0x00, 0xFF); /* configure the clock for transmitter */) ? Z0 w+ g: O2 `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 v. K* ]* P' Y4 ?. [9 |% q$ a4 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( r, m. J. ~; @. lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 j% [3 S! F/ T1 Q0x00, 0xFF);7 L) Z; u* J" D+ b' u/ v
6 w+ A) j4 u% k2 b
/* Enable synchronization of RX and TX sections */
" M* b* w7 H% MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ M0 I- r0 _ Z. \9 L! p* N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: v1 Y; ?- B ~ d7 |, a3 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
M; s, ` E! T' w6 }* A** Set the serializers, Currently only one serializer is set as
2 D. d, M! z( ?+ X) C* a) j5 ^+ a9 M** transmitter and one serializer as receiver.5 ~$ ?- [" j8 h' N) f& V+ U
*/0 t' {0 `* K6 N; i, R. Y) {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 ?' t2 u/ V) e+ W/ l1 e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 k+ p2 c7 O* K8 `
** Configure the McASP pins I8 } ^, I( Y
** Input - Frame Sync, Clock and Serializer Rx
/ P# e& F8 {2 w) a2 b** Output - Serializer Tx is connected to the input of the codec
7 ?+ b9 j# a6 U. b. k- F5 |*/
, G0 v) }. ?; N6 D) yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) E2 n" w( D( ]5 l4 b+ I& Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 I/ |$ x4 w& q% e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. k7 Z) J: e$ i
| MCASP_PIN_ACLKX3 d* R) O9 i2 y
| MCASP_PIN_AHCLKX$ P' Y) Y3 d- b# }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 w8 n2 ^2 n, a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. z& ?& v$ |2 R; l# ~! M ?| MCASP_TX_CLKFAIL " [' S) v2 G: z! Z$ ?; F
| MCASP_TX_SYNCERROR( y( S* m3 N) ?* \7 T8 O& v/ Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 J; ^8 G. ~2 ^9 A) m. }+ s9 k M6 ?! f7 e6 N
| MCASP_RX_CLKFAIL
$ |( K- {/ k! S* ~| MCASP_RX_SYNCERROR ; j. p- u+ a" V, k! h/ i/ W
| MCASP_RX_OVERRUN);
( n1 `' I' D1 \) X5 ^ a} static void I2SDataTxRxActivate(void)2 M: W4 X9 R' u+ z9 i7 i
{( E9 t4 Q% y! @
/* Start the clocks */
) ~& ]; W$ Z( x; dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; R c6 z: F3 M" \# o7 u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# F" p2 a; N w; Y" T0 o/ |& A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% A, J% R; B7 d t% M! S6 [& L
EDMA3_TRIG_MODE_EVENT);1 _! ? g+ L4 O1 y2 ` p1 w$ U! y9 d7 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( j1 `" Z8 {" x* s" l% ]5 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ ?& f. ` ?/ {/ ?+ E* V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# s% W: P! {) B/ }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: |$ `' j- D1 n( D- E3 [' |& bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ q0 w4 Y" b6 O/ v+ }+ `5 g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% o; ^, R. b8 K, g; OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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