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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: P6 ]/ ?6 M% | x' `: Z3 [input mcasp_ahclkx,
, c0 | A% r+ h1 d1 s% i7 T. |3 I# }8 ^input mcasp_aclkx,& L8 u( {! h1 `( J
input axr0,
! L5 M( R" y) e; f8 S5 d- ?4 \5 A4 s# V J, L
output mcasp_afsr,- ]5 Y3 D5 G- `3 {6 t z
output mcasp_ahclkr,
0 ]3 {" q9 [3 ?0 S' ~2 K& W& P* foutput mcasp_aclkr,9 i. X( [* l" K5 I0 A9 J4 `- T
output axr1,0 ~$ u, ?* M, F
assign mcasp_afsr = mcasp_afsx;& e6 K2 k; N$ j
assign mcasp_aclkr = mcasp_aclkx;3 V& d3 S. S1 P" O
assign mcasp_ahclkr = mcasp_ahclkx;! A M7 {3 r4 F- X" I
assign axr1 = axr0; + T5 t0 X6 O5 b- M, J* T
/ Q" K6 F2 h& I% R! f) z# {! R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 g( g7 l. v' f0 I1 j5 `3 C2 F* N9 ^static void McASPI2SConfigure(void)
) y* B! R" r, ]2 y H, ~{( X. L( O( m) p$ _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 p1 g& f' }0 {; n9 y1 p: d: cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% R& b% q7 P1 J# j' z5 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 T: D" M. N" |4 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* f3 L: ~2 T; V: r- Y- XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# i0 z& Z: |5 Z9 N8 U, H6 ]2 pMCASP_RX_MODE_DMA);
/ N, \2 h# }" L8 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. _ u; \8 N3 M* [+ I& l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 J7 K# x: a' \- r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) o0 d6 j- g4 Z- OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ o" E6 E9 x# r& ^* D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 t- K/ Y1 d5 X8 M* l# l1 pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 h" P: e1 z- ^' \6 F4 ~+ Z8 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& t. V3 d. e4 G) l6 \, C4 i+ TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) s+ g2 y4 f7 b" k9 Q7 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ O9 P# z6 s; ?" g& B
0x00, 0xFF); /* configure the clock for transmitter */8 v4 L1 ^+ m) B( D. ?; K0 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 z1 J9 u Y, v9 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . U% V6 M0 D0 G2 t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 U2 ]; o- t7 V% @* O: A) f. q0x00, 0xFF);6 A7 O+ L! d1 f4 u2 J" c. ?
5 @, ~9 j" \. C5 L8 z% {
/* Enable synchronization of RX and TX sections */ w( u. t) S6 c# P$ A7 ~1 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- i2 k% |- v3 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; L- q% ^5 n4 L. Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 T' W5 F/ e0 Q% a** Set the serializers, Currently only one serializer is set as
% ^* @) N" z/ {# z** transmitter and one serializer as receiver.
! J8 O. t9 | {8 X' p9 X1 r*/
$ D$ J# Q6 T) [1 h, `2 xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" W' j) K3 _6 z8 G: `3 ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! {! T4 f1 [2 S; P& K** Configure the McASP pins
3 U+ n1 e2 i' j! b) e** Input - Frame Sync, Clock and Serializer Rx0 ^+ h' V% V$ V7 V0 ^7 H
** Output - Serializer Tx is connected to the input of the codec
7 u0 R4 B( _1 M9 v% @2 R*/
' i Y1 Q: s B" Z0 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
^; r6 x9 s/ g( o# JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ j8 A2 \/ N6 t0 z! F# H7 a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 T8 z+ D9 x% I3 O| MCASP_PIN_ACLKX$ m+ ~, v1 b6 H. W( n$ F- v9 R
| MCASP_PIN_AHCLKX% n+ ]9 n3 X' v% z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' o# q. V: ]( E; Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# B; Y0 J1 K3 W| MCASP_TX_CLKFAIL 6 q8 A$ R- C8 E# R
| MCASP_TX_SYNCERROR; L1 }! C1 q9 z" m- I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 Q! f5 {# W6 X/ W8 ~, V: H) a| MCASP_RX_CLKFAIL* {1 z$ q* E, b+ T* h
| MCASP_RX_SYNCERROR # d. ^9 r# C8 C) P- u
| MCASP_RX_OVERRUN);
: v4 p+ d7 q. v! \: W$ Z} static void I2SDataTxRxActivate(void)4 k% { Q1 e6 d
{
) j& b( r- B) E% R; C/ t/* Start the clocks */8 M! b. N! X* K' t& O* z9 n, j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* [3 p# t" @' Q1 q4 P. W! l8 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
e; e7 p7 @2 t- R5 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ w( O0 J: { q, X
EDMA3_TRIG_MODE_EVENT);$ t( J& {# l Q! j9 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " s8 [- Y2 k0 W% S, ?& F: q0 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 u3 f: a: @- D: o, w% o5 r/ tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" j! `# H# v$ u% I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! G x/ U- N4 X, ]. }5 A Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- P# d5 k1 h' }1 }2 F r& e- V5 eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; M! _4 C/ L6 V) t RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 Z* w2 n% x( V2 i
}
, E, N) w E- s; @6 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , O- G4 e/ C8 p
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