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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ A3 \6 a1 |! C1 n! I P; d% cinput mcasp_ahclkx,7 h5 A t) V. y; _/ Q/ F( l7 {
input mcasp_aclkx,
2 m' w$ {4 @4 J. ]! yinput axr0,
6 J. T* ]8 T0 O4 U0 P) R
, ^) g& h3 P( E# \3 qoutput mcasp_afsr,
' A Q% w8 \$ c+ Z" f& ^' w3 t+ I: e5 Uoutput mcasp_ahclkr,
' |9 i: I1 X* ?, woutput mcasp_aclkr,1 x3 ?7 c' m1 ]7 J/ c K# h
output axr1,
- F3 N. B5 o. M/ Y; b$ L' A" o assign mcasp_afsr = mcasp_afsx;
: k0 z7 v$ j' q S) k1 Z8 w, _9 yassign mcasp_aclkr = mcasp_aclkx;
" H( R) Y3 ~2 Massign mcasp_ahclkr = mcasp_ahclkx;
2 }: @9 R/ a$ [7 x n8 g. |assign axr1 = axr0; ! ^1 K' r6 v6 U5 s$ {
+ l: t* z/ @" X+ L) M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 f% o3 U/ v$ R7 O: p% b: S9 p
static void McASPI2SConfigure(void)
9 l6 L0 T' {; W# H{/ Z( ^4 k/ F% t0 p( {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( x0 w2 j) s" y' n+ o0 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& U/ E$ s M7 H* u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! C2 m) Z3 L; T' Y" QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 [# o) y5 \) C, Z. ]# Y+ j, U5 S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 b# z6 o4 x$ C5 \* ?( l/ e+ ^/ b
MCASP_RX_MODE_DMA);
2 e! ^9 h+ z" V7 m* b) B8 GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 U& J$ i# |4 U& \. D2 I: AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; w/ _; A1 e, S' T' [4 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& d z% _& @8 e, i& A5 k" W' n. ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ c2 K6 ]2 B4 L' A5 x; k0 g; gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* G3 R6 a$ v, ]$ o( iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ U) c, x; {, PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 r# l* s; Y0 k: a) D, X EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' x2 K. }, w1 P% l$ n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. m4 W0 \, E8 F* O% M. R
0x00, 0xFF); /* configure the clock for transmitter */7 v( x. a6 r1 U* S Q- N& W: i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 J" z2 C" {. ~) i: K7 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 X+ Q: y2 b. O; f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 z+ k* p3 X8 Z2 [2 A0x00, 0xFF);
$ i+ H' {9 _$ Q, N
7 g" R( e( t: I! d0 n9 K; ~/* Enable synchronization of RX and TX sections */ ' L! U* X' c: ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" }9 [* S" ]0 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 k: t- H8 \9 s o$ k5 V0 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, c" j& r) X4 I( y0 u* I** Set the serializers, Currently only one serializer is set as4 b5 G& u) s! \2 H+ |; [1 B
** transmitter and one serializer as receiver. u4 p; ? [8 P y {
*/7 P: |' @* W( c8 f: d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; R9 [* E- P& o- [: n$ q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 e4 |% k6 d" s+ f! |6 @
** Configure the McASP pins 4 [; Z2 R+ l; V5 g( n, H9 A" W5 f
** Input - Frame Sync, Clock and Serializer Rx
. j l, K. `( k% p+ |! N** Output - Serializer Tx is connected to the input of the codec
) f8 d i9 @7 z2 ~ Q*/
# {: e- J# b0 Z! E7 `/ QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 Z: m/ a/ ]7 u4 E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ R' m$ x( E! OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ p- x E& ~; ~4 n( v
| MCASP_PIN_ACLKX
' \- O% j$ X, g3 c| MCASP_PIN_AHCLKX2 k% d1 Q6 l" _# }2 F) ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ v" d1 ?) e6 K; d7 s* {; z6 T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, E# s p+ m2 T/ r1 || MCASP_TX_CLKFAIL + a; i8 o8 m1 b. z/ q7 c7 e
| MCASP_TX_SYNCERROR
' @( [' U, E- P/ A( ]9 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " h t2 x1 p4 u
| MCASP_RX_CLKFAIL
- M( d9 X- Z. C| MCASP_RX_SYNCERROR
5 _* F: ] Z, e8 I8 g2 I| MCASP_RX_OVERRUN);
6 S& a7 ~8 w4 Q0 b1 m. K2 S$ T/ S# Z} static void I2SDataTxRxActivate(void)1 p9 r( V( n: q/ [
{
: H! ]# S0 Y# E; F4 S+ p7 _/* Start the clocks */
T4 Q# b6 v* b2 {( w: t2 q2 P6 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
F- e8 K h+ w2 m$ T5 VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& @+ q7 B5 ^( b7 {/ oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, q e) T1 u( ]+ V5 XEDMA3_TRIG_MODE_EVENT);1 [/ x% B; W, ?% u# l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ J" U/ ~' m% BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ T. l; h- j ^+ L+ WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* n. f q1 r/ t/ Z! x, n; R/ s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 ?4 a1 L$ r5 O5 i( o$ Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ z. D$ J. W* |+ HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) T: @) j% r7 H0 W( A; z# t' A b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& V9 l$ A1 j$ \0 t, F
} # m# b" v- u% @6 o6 {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " Z8 f5 F3 o5 |; I: |8 P# v. }1 `# @) y
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