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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 g9 J. ]/ _& l) F
input mcasp_ahclkx,. G) W3 A$ z9 m3 ^& Q" K
input mcasp_aclkx,
$ L$ S6 p% g [% zinput axr0,$ g* s! I ?# C" @3 v
6 A; T8 x' f1 m$ I
output mcasp_afsr,
3 Z" J+ P! i. C& v" koutput mcasp_ahclkr,0 h; G# n/ K3 C7 U
output mcasp_aclkr,, T* y+ c9 a0 p3 ~9 _
output axr1,0 H6 V @1 W5 t2 v1 A
assign mcasp_afsr = mcasp_afsx;
4 @6 e) B" L# H1 @assign mcasp_aclkr = mcasp_aclkx;! \8 q, s! {9 B1 p+ `
assign mcasp_ahclkr = mcasp_ahclkx;" M' |" x; W% J" v9 M% `
assign axr1 = axr0; 3 M7 A+ }/ o& \0 \" N3 h/ C
: s. n8 C7 F& y3 k1 k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 C) A% S' u/ m! C5 Bstatic void McASPI2SConfigure(void)
# ]. K8 ~# n+ s' G. S! j" x% R{
2 h; r# e( I* [' R' r) X' z9 l5 `7 eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 g+ z7 j% q$ V* J4 p& i' lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 V3 @. ]' ^# @% m* Q8 \! f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: U; M9 _8 C: Z1 T+ u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 y& \% a4 d5 T; q' TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) \" I$ d: u5 k" B9 J- H1 M( t
MCASP_RX_MODE_DMA);' l) D( O9 T7 P& M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 e1 k" s* x& t8 ~" D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! U9 Z1 g) O3 h# v6 n+ z; H5 j( C( OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ s6 N% F. B9 T/ {: h( X7 i. WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); O# d% u" u0 T- U- p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 q( |) I7 G+ V* v& dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: ~! w1 i7 _, N0 D4 o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! o7 U2 h% |+ o( `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) K! F. b- y# ]' W* q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! W( q+ P, |, W
0x00, 0xFF); /* configure the clock for transmitter */; R8 w4 q1 G( X: d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 A; V0 x6 t, R/ x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 R% @) n% A& o5 h, @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 @/ S5 d- i& U7 y5 h2 l, w0x00, 0xFF);. S4 r# t% T! l+ i# u
, e+ O' s% n+ J2 }* N
/* Enable synchronization of RX and TX sections */ $ G: z1 z. p# g2 A+ G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, R; Z6 ]: E2 X/ W: |* J/ ^+ I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" x, p( j' ~& [8 d& d1 g. h/ ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) z z1 ~/ t+ `: j" i J4 k; C** Set the serializers, Currently only one serializer is set as) s. ?- j7 G4 @- L! {
** transmitter and one serializer as receiver.
( U) N4 f) F# X3 M/ {! q*/
4 d, ^ L8 s; s. `. |! ^; v' ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 H' j$ d: P, L- U5 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 c* `3 ]# |/ k$ s5 Y3 L
** Configure the McASP pins
. m6 d. S) A* M** Input - Frame Sync, Clock and Serializer Rx" C. j$ }) f& [7 y$ g
** Output - Serializer Tx is connected to the input of the codec ! N2 `8 E% B1 O. K2 ^0 z
*/+ _* @) l+ o) K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 ?) n) [6 t/ ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ B9 Y, I/ G T: N" D+ ^3 R3 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, j! t. m1 _* Y! ]8 A4 w| MCASP_PIN_ACLKX
% I& C, q7 ^* |3 W! \$ k| MCASP_PIN_AHCLKX
, V; o0 ]; F% H; M* _ s* f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% _ E" C) G8 a+ ^' ], X- _" i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& C2 F+ T8 z: `' I. Q" G| MCASP_TX_CLKFAIL 4 ~2 d6 o4 A8 k2 Q4 T* i3 O
| MCASP_TX_SYNCERROR/ F; ~7 w: h, Q8 i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . [% ?* q [9 R* I1 a
| MCASP_RX_CLKFAIL ~ j& y' R4 J- Q- ^0 R, J
| MCASP_RX_SYNCERROR
) A9 N0 o e8 a( J% A: h; _/ ^* R| MCASP_RX_OVERRUN);
0 D6 Y7 B+ s; H( J} static void I2SDataTxRxActivate(void)# U' F) O8 x+ F3 a4 y' \* j: W r
{
% f. a9 t/ X1 d, t4 e( f* ]/* Start the clocks */2 X" K- U( J! y, c$ M" ?6 w6 T$ w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# h! F4 F7 ~0 ~+ y( _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% J1 k$ s9 Z9 m$ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," p( s# S/ B# a6 t/ ~5 K) t
EDMA3_TRIG_MODE_EVENT);
! p* k# N% v2 M; N6 P/ N# `- SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 [' p6 s0 ]' w) B0 s( W. B5 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# p4 ^; r" N7 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 L7 |1 o) \7 b- E# V9 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ [. ^7 n7 l# S( ]- Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 p u% y( f ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 g9 A1 S2 e$ M% {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' e6 g) Z4 ^$ x; C% A8 J" p
} ! M5 S3 R# l0 a3 n6 V6 `7 M4 e% e% @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 T, f6 \8 i8 ~8 ?0 l- j5 r
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