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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* n7 k6 N8 V! r' Winput mcasp_ahclkx,
* u( @0 m/ p1 X$ U! ?input mcasp_aclkx,
9 Y7 E; ~0 J3 w* N8 x8 Oinput axr0,
% ^6 g* \9 ]) G. u: e- ]
: c W- y b ?4 {1 boutput mcasp_afsr,0 k5 t$ V, W9 p3 i( [0 C
output mcasp_ahclkr,
5 } @# K' ` L2 e1 c8 f coutput mcasp_aclkr,
/ ?: o! B+ m" _' O: c0 h1 H* Doutput axr1,
: L1 y# C( W" ]# {) t+ P assign mcasp_afsr = mcasp_afsx;! d( ^4 |7 `; S
assign mcasp_aclkr = mcasp_aclkx;4 {4 T4 \0 B1 s- G, M; C
assign mcasp_ahclkr = mcasp_ahclkx;/ F) v: T6 N0 F* m8 @
assign axr1 = axr0; 5 V' S# `" ^4 N7 b& s3 g/ v2 d- x
. w3 S4 ]4 l. B% y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 m% T4 q% X% ^- u; F
static void McASPI2SConfigure(void)0 W2 h5 E1 `, k/ \
{9 \7 y+ {. r B0 ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 \4 t7 H) s# N# O8 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 Z7 M' C* p: l( e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& t0 s9 F6 {9 [* a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 n' {! r) k. k# N; }+ hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 l b, Q) t, u8 s! IMCASP_RX_MODE_DMA);
( D$ {# }2 e/ ~8 R7 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," q# T E8 {6 C8 K' V" S8 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ U8 S# g& [& l, e. V$ b! QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: J* Q7 Y! r# l& O: M. BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
r3 P$ K* r0 Q* ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; E& r6 G9 \9 ^$ y& c: N. M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" T; ]# f+ H( s/ _% j" k. qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- \' D+ L: i" s( tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % J7 W; J$ s1 @/ e/ F# k" G0 a( l; q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ h/ k5 r0 g$ p# n0 Q2 e9 g
0x00, 0xFF); /* configure the clock for transmitter */
* K" [9 M0 K# B; }- K& D, W0 {/ ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& i( u1 e3 D" ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) W. \5 [5 C0 T+ L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( t0 ^7 t6 `7 S' ?( c
0x00, 0xFF);
1 ^' g$ J, R% @7 r+ D
0 o. W) O: g/ c! x2 z& l, j/* Enable synchronization of RX and TX sections */ ' `: H! L* u6 I" Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ ^6 K$ F; I) G5 `% q+ ]5 s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# k: O" s/ U. H, E: g) x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, Z. n$ T. S. Y6 q+ C! Z
** Set the serializers, Currently only one serializer is set as
) V/ Z' d( K! b% P' |( h** transmitter and one serializer as receiver.
2 t3 r- [- `8 K*/; G1 U6 t$ [& H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. x& K8 a, H4 o, P$ b, d5 r7 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" U* k. z( X5 i, k6 i1 ?/ P** Configure the McASP pins ( I+ B3 Z$ |* }( R* l, {& O
** Input - Frame Sync, Clock and Serializer Rx
! Z- u9 c9 ]3 [* M$ t/ Y, D** Output - Serializer Tx is connected to the input of the codec
! \" B: o8 z4 m+ b7 A- r*/# D. J7 T) M" w1 { }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 t2 h2 `/ |* d8 w8 ?) P4 a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- ?1 r7 X- Z0 h: @" K1 t3 J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. ^/ e0 ?5 T) \3 m
| MCASP_PIN_ACLKX- H1 r P; b, F+ N- e Q
| MCASP_PIN_AHCLKX
8 ] m7 l1 j. P9 y& h6 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& e9 r' _7 r7 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , U: m: T/ _6 e `
| MCASP_TX_CLKFAIL ; t7 A8 w8 x# {0 u7 R
| MCASP_TX_SYNCERROR
5 }7 m1 P1 Q' b" v$ || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" t2 y( `0 @; W6 h| MCASP_RX_CLKFAIL
" V. i# d9 R; g2 H2 G9 `% M+ O6 o$ x| MCASP_RX_SYNCERROR
2 E I" M7 g( Y* Y) f% I. j| MCASP_RX_OVERRUN);4 k3 y# A$ u* U E
} static void I2SDataTxRxActivate(void)( I8 J0 r, N8 h
{
/ u; G0 F: S: S* P- l) |, q/* Start the clocks */
- I7 U; c) T8 A: z) O. d0 @& BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, N r6 i" q5 c2 t4 f4 p9 Y. r, FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 u2 j) V* \" Z {/ `' F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; ` X3 Y7 S5 w2 q6 W. BEDMA3_TRIG_MODE_EVENT);
; U/ w; F" ]5 F& s0 h7 i) o5 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 p. {' R' P6 P4 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- a: r @1 E( ^0 L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ X; G! P7 w7 |' uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# ^- Y+ V# t& a7 v& U! @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- L( t) m, o, o7 g* CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* I* W% V7 `$ n% UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ p* X+ n4 y) M: A) I5 w} / Z% q J* A. H1 @) `/ z4 n; {* R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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