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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 y" j. e& _+ c( ]6 }/ m
input mcasp_ahclkx,; U/ s- k# h2 W) c
input mcasp_aclkx,
8 a: u. v# y) @1 d6 Zinput axr0,
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output mcasp_afsr,
& ]" J$ v% l3 W4 ?# ?; koutput mcasp_ahclkr,
* F2 ?' b2 ~% }) `( }; |- `9 ^% ]output mcasp_aclkr,% C" E6 a5 q( w1 R
output axr1,
0 r. C8 H ~8 X* [ assign mcasp_afsr = mcasp_afsx;; ]1 W5 R! C* W) A+ i
assign mcasp_aclkr = mcasp_aclkx;6 K0 S# u9 V% f" l' R
assign mcasp_ahclkr = mcasp_ahclkx;9 a! O! M, R- Q0 N
assign axr1 = axr0; ; I- w9 }# S9 F' U& R5 e S* Y
9 W6 z w' N: X+ u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& L5 } R% O; Y+ ?- Ystatic void McASPI2SConfigure(void)
! U- g/ j. u% K* G{ x4 y1 E/ ^- a* o) X9 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 d7 @) v. H; l1 l% P) B. L: v" XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ Q; y% _4 N, }: u( k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 w" \, M5 G% x: o& vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// w& ~3 ^: x$ M" C3 y- y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- _: c$ S4 g q) m8 YMCASP_RX_MODE_DMA);# H$ M1 L: `: X( U" {& ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ U/ } j6 [$ M* Q- f# L, ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 D) H. n B% B8 ]1 E( T9 b6 _$ GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* @# v" l5 f0 M+ i* h; sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! D( ~; c. v7 D) o) k# n9 h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 a6 }! v' p$ Y% J, \9 [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 j: A% ?7 S/ X4 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* V ~. s& |1 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 q4 c) _& I( X; D4 C# \1 j3 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 a0 y& b* E$ F/ e& k
0x00, 0xFF); /* configure the clock for transmitter */
8 I$ s2 Y0 Y! |* R0 V A: i7 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 n9 ~ C* z- C% X7 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 |5 \$ K- e7 A. i5 z6 l! hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 u6 c$ G& Z3 M
0x00, 0xFF);
$ V9 g3 e. P; x1 \. O4 ]$ h
$ ~5 s1 d: v m5 E) U5 F7 f/* Enable synchronization of RX and TX sections */
9 } e& A" S/ m' F9 fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: |% a( f$ e+ y$ ]( } @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 E3 Q6 A2 D$ b3 KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: V3 I4 L0 F( Q) E& D3 y** Set the serializers, Currently only one serializer is set as2 N+ J. {* R2 Y5 n7 l8 |
** transmitter and one serializer as receiver.( T5 e+ |7 e$ x7 H% {( o9 i' m$ b
*/4 A6 v; `; o1 {8 k) X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" l W, Z9 H; _8 @% g0 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 E; E1 ]5 A' E/ w* P [+ N7 T
** Configure the McASP pins $ b: w z4 I u
** Input - Frame Sync, Clock and Serializer Rx
5 p6 N& R* n& W. d** Output - Serializer Tx is connected to the input of the codec
- [6 @( T b% K$ R- J*/
. D$ g/ S+ F, Q0 |/ \" @+ A' FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& j `/ ?& V& B9 H! E7 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ _' p9 ^( I$ G; U. S I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ C) o, s! r6 J& p6 _& W! n* n| MCASP_PIN_ACLKX
4 U' }& O/ @' }2 _' C, [; P| MCASP_PIN_AHCLKX4 ^" `( |2 r. U- N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ N$ j) Y% I; Z! B$ H% ]$ eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% X# M: e7 r [5 P6 k k3 w/ m| MCASP_TX_CLKFAIL * _; j' _2 l7 V5 }6 W. N5 e
| MCASP_TX_SYNCERROR
) f d, u! d9 _" K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " f; d% d! m! K' _$ X( t$ v
| MCASP_RX_CLKFAIL+ ?) G" U' \7 e* I6 J
| MCASP_RX_SYNCERROR 8 k: B t7 a4 D% l% T. s
| MCASP_RX_OVERRUN);& _- G% x$ G. \& _2 I
} static void I2SDataTxRxActivate(void)
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/* Start the clocks *// i" [" q: z5 A- e8 r5 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& i2 X3 \# A4 @ ?, \2 z' i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: _/ _1 J+ R* N( {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 \% c! q# I8 \( D5 pEDMA3_TRIG_MODE_EVENT);7 e" S" F' s/ J( \1 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + t5 }/ y" P0 `; f9 h! n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# ^6 ?7 e3 ~' \2 F) Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# [ s0 e" {* N0 \, A- D( p6 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 a+ c# J0 y7 Z. c5 N5 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 U/ M p% _: ?5 h5 V" l- \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
F5 W1 U& W/ q% EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ j# {* d2 |; A" R- l1 d
} 0 x, [% ~0 N: c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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