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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( m$ A" N! i, \4 f6 [: kinput mcasp_ahclkx,8 l3 r% B8 P0 _2 |* |
input mcasp_aclkx,
" C# I8 p' X# [0 `input axr0,
@3 o0 I' M7 _- V, W5 p7 n8 M I: n/ o8 w2 n, w8 `) v
output mcasp_afsr,2 X3 x. v6 {! K* F1 d, t' h; B" ?/ w
output mcasp_ahclkr,* G$ [% X+ Z+ G+ D9 @
output mcasp_aclkr,7 B G# x. ]* s0 ?8 d
output axr1,2 ^6 m& B' m0 `
assign mcasp_afsr = mcasp_afsx;
- b- k8 x% ~; s4 a0 L: R6 |assign mcasp_aclkr = mcasp_aclkx;
- A- V/ o% n6 K' `assign mcasp_ahclkr = mcasp_ahclkx;
7 m6 e& }( Q- ]+ m' M" b1 _( t/ S- u% Qassign axr1 = axr0; 8 p$ m8 o; ~. n( V2 R
& o& n6 r! ^% Y: |- B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 l9 e2 w$ G; B0 }. }$ l- s0 k
static void McASPI2SConfigure(void)
$ _; t- B; H7 Z" y; Q5 u5 M{7 u, s) V" u+ ~9 F, |0 A/ K" G+ h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ E& \- G* i) K4 g: N8 |" ?# G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 R+ F- \$ g4 A+ p5 ]* MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- k6 Y) ^* P7 L6 } y# X& g t* TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ m( V% v/ `: ]. e1 V# c" @! nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 |2 Q g/ f& V9 N" N$ m4 NMCASP_RX_MODE_DMA);
; u1 c" I4 Z' e* ^( ~$ `& O9 \7 F8 c0 `* VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 k* f/ x, Z* X X) l/ M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 g7 p6 J: d5 f; e1 \& mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" X1 D4 |* A; T) t. I+ M0 XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' [' b% y$ D7 S, Y/ BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 d* n+ \& M4 s" \; `% v- p4 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& c7 f5 f1 \ t: o% h3 U8 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& x5 F c' U2 o8 ^% _6 g# f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ y% P' _# G% j$ iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 L! R5 g) f6 F }" o0x00, 0xFF); /* configure the clock for transmitter */
, d/ E* @& S/ V2 E$ dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ e' F; S! p, w9 M6 aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 ^( c- ^5 S( e% P2 t& Q0 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' P6 _1 S* ^' T1 O7 R9 r& E" T, Y
0x00, 0xFF);8 t+ ]6 Y* r# h& [ e# ^) R1 B
{ V1 {; f" z9 m/* Enable synchronization of RX and TX sections */
: f. k% t m2 o$ DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 g' ^& p" j3 M) ^! N! x; QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 }: l+ Y0 `# X! Z# [+ s5 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: Q; z' i9 A! d9 q+ V+ ^** Set the serializers, Currently only one serializer is set as
, M5 c" v, K% s9 Q. W1 C** transmitter and one serializer as receiver.! w* e- I" u& p3 I# F! U2 I2 r: R
*/
- t6 o) Q/ k; O$ a' Q5 J8 \3 K2 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 B' Q# D+ w; O; J! v% z) z7 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 A8 V+ b; Z% N9 s, r2 \4 k3 y** Configure the McASP pins
$ B1 u) {: q7 a2 e2 U** Input - Frame Sync, Clock and Serializer Rx
) z& B3 k9 Z0 g% x** Output - Serializer Tx is connected to the input of the codec
/ ?- ~) ^/ _$ w( H9 U2 b*/
- }' \4 R. S, DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" @; \# F& e3 k4 E/ D6 QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( i0 n0 T. Z+ E5 {2 E4 }$ rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" k/ _0 x. x8 _1 Q. z| MCASP_PIN_ACLKX8 S/ Y. H. b7 F9 ^' f% {
| MCASP_PIN_AHCLKX3 R+ D6 e1 n) J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# j1 |7 t( i6 ^& {; q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 A1 t( l; o3 ~
| MCASP_TX_CLKFAIL
2 |3 {5 j8 `- S| MCASP_TX_SYNCERROR, _" s$ f" w: K4 R3 E, m5 X' J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , ]( z& w8 Q4 s/ I# [$ P$ y
| MCASP_RX_CLKFAIL
* I% _9 C8 O' m% n& h& X1 l' b; i| MCASP_RX_SYNCERROR # L0 t6 p* y* F
| MCASP_RX_OVERRUN);
7 V7 A6 S7 u% `} static void I2SDataTxRxActivate(void) J2 w) D. b# H& q$ Q
{% w: ~+ L1 _! `7 }, M- {
/* Start the clocks */
0 K/ R) y1 u& z; F, ~9 ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! {7 b6 Z6 p, k( B0 C! O% g% W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 y/ v4 w' K6 H- W' e0 [& }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% v$ g& V; O) ]7 j
EDMA3_TRIG_MODE_EVENT);& d1 W! ~8 n4 m8 v$ Z' n6 S8 V( M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 W6 }! ]" ~3 B2 F( w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 H& @3 f2 I2 I4 p! oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# G9 g1 `. s+ Q s( Z9 j) o& ^" _& x' Z J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ [- c) g" x% ]+ Z( v; x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! i2 c$ W% p1 q9 b3 h: [: d+ d( F4 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 ~" j: P! Z* R% a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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