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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 B/ J/ F0 q @ J J
input mcasp_ahclkx,
. U$ K; p# r( @ Q& C8 M, b" S Einput mcasp_aclkx,
; i. T$ W% W# f8 T; _9 X/ ^& Y( Ainput axr0,) Y' ?7 T3 o! A5 G, T" H
# V0 i2 A% z# b( I i! P
output mcasp_afsr,8 y2 d" Y8 L2 d! S W4 d7 i
output mcasp_ahclkr,; L7 i; w( t. @# |- B
output mcasp_aclkr,
, O/ ^- o! y" H; |7 Ioutput axr1,5 I V( i1 m; O- U' z$ Q
assign mcasp_afsr = mcasp_afsx;
, o6 l, d1 A4 A, aassign mcasp_aclkr = mcasp_aclkx;
2 ]9 c N/ W4 ?/ j, Y) Lassign mcasp_ahclkr = mcasp_ahclkx;' q. p7 \) i- y
assign axr1 = axr0; * n# N. }$ y _" O: y
6 _& y. U3 p6 g6 T- N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 `, O k Y! K$ `static void McASPI2SConfigure(void)
6 |; j) |4 k) W- L( d2 Z+ d# ]# b{; u" Y& w+ o: r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 k" b& q) b+ E9 F1 {+ U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 u d R. C9 u5 |! j! ^8 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' ?- d' U8 F: ?% [$ h- QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 w7 B( `! n3 j0 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: N' n; h# z! @) tMCASP_RX_MODE_DMA);
/ w& s$ E9 w. z! f- gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, Q( X3 k0 M3 r6 @9 P+ uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
p1 x3 Y$ p. O5 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 @% k5 O! ?3 b1 s4 N; G( uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. o! U3 F* U( X. D+ ~$ F0 E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 q4 Y R7 E) B h; y1 `9 F# iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 A- \- Z P e( zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( C- D M7 q6 d R8 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! E& p& f$ B& J3 m) r, Y* d! W; ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( D5 S" S- l1 j
0x00, 0xFF); /* configure the clock for transmitter */) R6 ^. k( J0 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; i4 C! V) W0 U1 U( _. |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) w+ G/ d9 j4 ]+ W1 ]" N3 qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ j! x' O7 }7 O: y" ~! Z0x00, 0xFF);. K1 t. ]; I$ M& ]
# U1 K1 O. e7 T* l5 [3 {% \0 n( l- e
/* Enable synchronization of RX and TX sections */ 6 s" c1 L, w' {* c2 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 M3 H0 L; w8 U- yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: y0 a3 x5 `0 v7 H9 P% p; q2 w: yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 v# `3 e; `# l# Y4 a, l+ y
** Set the serializers, Currently only one serializer is set as8 m( J* ?5 r' M0 R5 R
** transmitter and one serializer as receiver.
( C$ M2 k( M8 m; B+ g1 V6 M( J*/& [" e9 Q4 @3 T( J+ p4 e0 L- m, E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% @9 w: O$ m; }5 ~9 n5 E% g, YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' f' L- V* t# N+ u, _
** Configure the McASP pins , S! b6 G8 c K) _
** Input - Frame Sync, Clock and Serializer Rx- J7 ]4 l* D3 x6 w/ \( u( |4 K
** Output - Serializer Tx is connected to the input of the codec % h2 P6 s& g+ G' v
*/1 `$ a. i; s3 \$ ~) r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ B6 ^; \% H1 {, o- w. NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 g& ^' ?- A! L$ TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 O0 v2 ~# _/ |9 s5 d
| MCASP_PIN_ACLKX
) R# J: G( d$ W# w/ Y( n, }| MCASP_PIN_AHCLKX; k7 u% L9 d: n/ b; h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: f6 }, u0 O6 Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % J% {4 M" N( D' V& E
| MCASP_TX_CLKFAIL
2 K% w1 c0 s3 ` L- {| MCASP_TX_SYNCERROR, x" `* k9 s. N' G/ v/ ?: V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ U2 e; f+ v- \& F* Z. S| MCASP_RX_CLKFAIL
2 m- s" B: q9 H( U4 s| MCASP_RX_SYNCERROR
: n7 e) N/ l% d| MCASP_RX_OVERRUN); l8 b( g, b& ^! ]
} static void I2SDataTxRxActivate(void)) l4 u3 ^) w. i; F* k$ |
{! I* Z* ?7 V8 Q" l4 Q$ n
/* Start the clocks */
$ W2 [ g- o; T% k# NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 r; w3 Y0 ?. d" C7 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, o# K1 @1 f9 t8 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& x. i' {0 f Y$ z
EDMA3_TRIG_MODE_EVENT);
+ W" J) z4 }8 A% i2 k$ v& aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- M8 U4 n( M0 |, oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 [. ]% j L7 N# v: w8 wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 O& V" i" ~3 j5 F0 Q9 s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
?. v/ G. v4 E P8 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) u V+ F ^) U2 kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# i9 n, P4 w. f9 l0 y9 mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 |9 J. L! s- r
} / _6 o' Y0 a* h5 Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' x' Y: ]/ q$ `+ l+ n! @9 H" c
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