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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. `9 r4 d" Z8 v9 C
input mcasp_ahclkx,
/ q7 w5 L7 S* J! p6 U5 iinput mcasp_aclkx,4 R3 A' L6 D" m/ a. J
input axr0,# a! G2 u( q% p" r$ a, ]
9 O) x; |2 x4 _output mcasp_afsr,: z4 }' r; Q) h6 {6 E1 |
output mcasp_ahclkr,; @8 ?5 T' n' m) x! h8 O5 \9 S H4 K
output mcasp_aclkr,- O) `; k/ D# Y: c
output axr1,9 ?. ]( f' Y6 f$ z
assign mcasp_afsr = mcasp_afsx;
' _; B$ c8 m. ^5 Iassign mcasp_aclkr = mcasp_aclkx;" b% l+ q3 W; R, f% ~1 X
assign mcasp_ahclkr = mcasp_ahclkx;" b5 V" `0 P/ j5 S0 P) K; I* J, _0 X5 C
assign axr1 = axr0;
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6 b! c. T ?* h9 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( Y7 y3 H0 }0 Y& L ^ c6 y/ ostatic void McASPI2SConfigure(void); |2 Z8 b; q& f4 ]. `) n; B
{7 J! g: s2 t3 e/ ~0 Y* ~* d; L" Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: b/ C: J5 z& ]0 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, c, z. _ H! S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ F) O9 ?5 y u; Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ O+ r7 S% a# FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 T; b5 L4 X+ E" X a
MCASP_RX_MODE_DMA);9 J+ `) C$ _" O3 g. M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* ^1 {( H: o3 g9 z7 ]' h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: c2 L# P$ k% S% D2 U7 D4 I& Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 o/ F/ Z0 y, T& q, V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ k9 I3 Y3 N4 ^5 b( F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # A6 {* g, e4 c, g3 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- r* r' q1 _% {5 P9 v# P( M# d0 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 ]/ B5 k4 ]# V; [8 A, z1 YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % X0 @+ B6 d' c7 P! B; y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; L" I5 F; V! l+ f; y7 F3 q
0x00, 0xFF); /* configure the clock for transmitter */
O, E: j" N7 F/ k4 [$ n6 uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 `. D3 r$ I" J9 S/ cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 P" z5 N _: ]3 c) @9 VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) Q& G: x2 O* M: U$ K. g& _0x00, 0xFF);7 S0 ~8 _ |# V' p9 K% v
5 ]( S) I* N1 C3 _4 a# z
/* Enable synchronization of RX and TX sections */
7 J3 V1 z) c/ h" V3 R( W' ?$ n& p- W. YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* \4 n& J6 [) l! q, t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# b. x/ e% U- u G! q; k8 b, u c* tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) s9 a. M- N: G7 ^
** Set the serializers, Currently only one serializer is set as* l5 ~; U% w$ \0 Y$ o
** transmitter and one serializer as receiver.
. ^9 |, U7 r; O+ F Z/ _5 }*/% s. O* o) `/ ]! y( o* s' @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% p7 e, [' i4 y" F& a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% S5 V9 E5 j$ b% r' w" y** Configure the McASP pins ' g' i" M0 H8 i/ [; G5 ? M; \
** Input - Frame Sync, Clock and Serializer Rx* ]1 v% h0 i4 n
** Output - Serializer Tx is connected to the input of the codec 2 y A6 A6 G! t6 j7 N
*/9 W/ A* {$ _) P; \( K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 V9 ]+ \% r3 q' K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 Y+ u) _' l5 x5 g3 ]8 Z7 O ~( v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; e+ Y" z6 d' Z( ~4 }
| MCASP_PIN_ACLKX# w1 R+ s1 N+ j2 @ q* ~
| MCASP_PIN_AHCLKX
9 ^2 u- P Q8 X1 M7 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 `$ R# ?4 v' ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 J$ g6 ?, z2 r% R" l
| MCASP_TX_CLKFAIL
1 R2 r2 Y0 l7 K$ L8 P& M" p3 D9 m| MCASP_TX_SYNCERROR3 i' d1 ?* j8 ?! s$ J! K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. L h5 {0 X" X8 V8 J! z& i| MCASP_RX_CLKFAIL. o2 {5 c2 `, a9 v7 ?
| MCASP_RX_SYNCERROR % R F \ l8 L* P
| MCASP_RX_OVERRUN);
) \, G8 v Y1 I4 o0 Q2 j) W9 _6 ?} static void I2SDataTxRxActivate(void)4 o+ y% x2 M( W6 g! r
{# ^# m( N! k7 { `8 m
/* Start the clocks */
% q0 v6 K1 V5 ~( @- wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# K( }4 x- C$ r& |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! f0 X/ S3 C0 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- f9 m$ {( [! o: ]+ L d, ~
EDMA3_TRIG_MODE_EVENT);
3 _$ U/ o8 Z7 k! uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( B2 n6 z9 Q2 `6 ?" Y$ R! Q% O: BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ O: z- ]0 m& t9 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. H! P$ M1 V' y2 M9 aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 Y2 t! ] e. i( O/ K' _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 y5 d' m% Z, I9 UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( v) n, j( V- i5 \6 G5 yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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