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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% k3 P6 q" G" sinput mcasp_ahclkx,1 p; M( a8 X3 `) D7 T# o7 r
input mcasp_aclkx,$ Y6 E" Z7 q# N6 D# n3 z
input axr0,
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5 J* |2 {& G8 E' N0 Xoutput mcasp_afsr,
8 c7 W3 J: l" a9 N. I2 ^6 ?output mcasp_ahclkr,. g, ?1 j- s* O+ K( |7 c0 ?
output mcasp_aclkr,( M, m1 k1 ? u U4 `3 s3 M" Q
output axr1,
! \. t. H' r. o {) _# g assign mcasp_afsr = mcasp_afsx;
! Y x7 |/ A8 R0 e9 A/ r o0 Sassign mcasp_aclkr = mcasp_aclkx;
" F' K' @8 W% ~- [' Jassign mcasp_ahclkr = mcasp_ahclkx;/ `2 ?( x' Y4 U+ ^9 G# s
assign axr1 = axr0;
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* m( B* X' z" _' e9 G+ z& ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 o4 B8 L/ j( R7 a$ A
static void McASPI2SConfigure(void)
) W1 W4 c' F: X+ {, B{
- U+ C; z {! I1 _1 K/ _McASPRxReset(SOC_MCASP_0_CTRL_REGS);, E. C2 E6 ^, N# q: u9 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 M" u) W X8 @8 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! [9 q9 o6 R! q' j% [: S. qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" {( L. \; @" U" D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 c E, J1 J; K$ e @* t
MCASP_RX_MODE_DMA);
/ q5 Z: H" h, QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 D4 j% S$ P2 O9 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# u, m9 q1 d9 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 `- S) y" Y& |- l' [" h( D% w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" G2 v1 [& z* E% {2 b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 p1 T, r: i* r# t" G. p/ DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' [0 [, `: w! Z8 RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- ^/ P, @% ~5 ^3 k- U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% u @* f" c% ~- U+ AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. p3 J' ?" }' @# G, X) x) k% R
0x00, 0xFF); /* configure the clock for transmitter */
$ r N" v$ J, P0 U7 |+ f8 MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' p+ `5 A- J q* [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , e2 t( G7 z2 j1 `! w' P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, f4 ?3 ?6 W* k- P, X, ^: @
0x00, 0xFF);: a+ H; F/ ~ O- s6 Z
1 x( p5 }2 e$ i1 a4 I: L/* Enable synchronization of RX and TX sections */ 2 ^, l. |) o: V* d/ d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! v. F& j0 B: J2 O: S/ t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 J4 @4 ?/ X( o9 [) kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** L5 Q4 F4 r! c$ G0 b7 H) j! i1 ~9 F
** Set the serializers, Currently only one serializer is set as, }9 @0 ]9 u4 ~! _/ D& c$ t
** transmitter and one serializer as receiver.9 g9 @- `7 [1 a+ J
*/, P% E6 |- g! w9 W( l- K% c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- |1 T1 k3 X. D7 {! F* U# ?: hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) E/ s H; ]2 D; \** Configure the McASP pins
: R, X& n* V/ b7 y7 S6 V** Input - Frame Sync, Clock and Serializer Rx
: L8 ^3 _ f- H: {% v `% O** Output - Serializer Tx is connected to the input of the codec
( H5 e5 R/ V# k( w! }! w8 x*/5 @9 Z O* y4 g( b# m! q4 ]* U6 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 i1 |( Y; s- \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. ~; A, Y# e+ K8 d( X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 l# I$ Z1 X8 \& p% p Y1 j4 w
| MCASP_PIN_ACLKX
4 ?( D6 S/ N# q* i| MCASP_PIN_AHCLKX& d/ x' o" l# e8 b8 T+ D0 l4 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ A( j! t5 j' o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% S* s& @1 `, g' y' `' }) ^| MCASP_TX_CLKFAIL
4 M2 E5 V, y5 D% C/ P) q| MCASP_TX_SYNCERROR0 n) V1 e r3 Q1 Q: n1 K- |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ o: k# a n$ J* ?! o
| MCASP_RX_CLKFAIL m! p+ j2 P( S! y; i/ F3 Z1 Y
| MCASP_RX_SYNCERROR
- I, H' x6 n9 T: ~, S/ \| MCASP_RX_OVERRUN);
: x! x+ v' d2 H} static void I2SDataTxRxActivate(void)
/ i+ s1 }7 B" m7 p4 z{! F8 [: V) J4 Y
/* Start the clocks */% f- _) m6 `5 S6 W& K" f! y* v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! x1 l( v" a; r" T# G, S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- N6 F+ b7 l/ AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# d8 ~3 E# k: g" o8 h; M/ @EDMA3_TRIG_MODE_EVENT);2 I: b; }. e# f3 s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; F/ E1 \6 i1 O+ B, r( }+ Q# h7 T9 P0 g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 g. p+ t$ s4 | S: Q0 l$ u: y! ~% @" a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: n& \& J) I: V) R% x" WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( U! A \3 Z' n* f9 Q5 i- H5 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* o8 q5 \; f' T( w: H& l4 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: L2 P) S0 ]4 ~9 x. }" \ @' `) IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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