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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& D5 J. v6 o( k2 j% A1 k3 q4 Q% oinput mcasp_ahclkx,1 J" I# a" u) l; D! M \3 u5 w C
input mcasp_aclkx,& h. s6 m. N" v$ N+ `8 x
input axr0,) b1 b* J6 N% p- e# ?
+ K) `7 m. @# D: F! u0 ?' }
output mcasp_afsr,6 I Q9 z; |1 [& H1 V
output mcasp_ahclkr,0 ^' y# m8 M0 v# ^
output mcasp_aclkr,% X4 U" q' r' V: S9 b* k
output axr1,# X$ K. ^) c+ E' G- X
assign mcasp_afsr = mcasp_afsx;
2 G- w5 y# {! |6 ~6 H7 sassign mcasp_aclkr = mcasp_aclkx;
$ {" D4 y4 w1 z/ qassign mcasp_ahclkr = mcasp_ahclkx;! f/ m* @6 T- }9 s
assign axr1 = axr0; . u/ w3 R6 \1 W3 s7 l3 H! z
: `# D5 W" |+ f7 n' i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
F' Q" Z0 M* Ustatic void McASPI2SConfigure(void)
; X0 c; ?- M/ k- t# _5 [{% d) ^8 B" m* ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( d s3 J: g! C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: w2 T4 G3 n" p/ BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 L% o" J. P% x F+ S2 BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ s) j3 Q: F% G: i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; [: M7 p; ?3 ?+ a3 N: a( q
MCASP_RX_MODE_DMA);. C8 C0 w: J, W' D9 u; ^, I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) M) K) M# l1 Q" [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 {; N* a& z4 M. N" e3 [1 Y3 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # s t5 M; M" G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 o9 U( E3 l6 J# h0 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ Y5 B4 M, _3 W5 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; W7 \( W5 \! y5 F `( c( QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; y+ H- B" K( B1 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; p8 u+ e. c+ U* i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& w0 L3 f1 o( g+ P- G: _) Q
0x00, 0xFF); /* configure the clock for transmitter */7 t5 l, U; ^: J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- d: Q# s6 \& VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* g& [ ]' d" c8 w# V) sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& a3 Q4 N/ c; z! n. K9 V0x00, 0xFF);
# t$ z( V: e2 k! M ? M
: }7 T" m4 c& j/* Enable synchronization of RX and TX sections */
0 D% V' c1 n! v% q2 mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 j4 [, k7 b; s' n: ?8 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, B5 R) n, z0 {, ^# T; w0 L1 A) _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) N/ D% S& W; ^% E
** Set the serializers, Currently only one serializer is set as" g: K7 P$ U% d5 b
** transmitter and one serializer as receiver.9 U2 a* }6 n/ H' p# z3 H) i0 |
*/% f, v/ B6 K+ a8 e' U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) C- }/ p! e) l- G. Y* r" }9 D. FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 D7 t8 C2 k3 R ~' \** Configure the McASP pins
. Q7 s- X, V5 A9 d B6 G2 I# P** Input - Frame Sync, Clock and Serializer Rx
4 M5 a) x5 k. L$ w** Output - Serializer Tx is connected to the input of the codec 9 x7 a' d( L3 w* x* [; x
*/
7 n1 I7 Y$ | Z: m1 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 R0 C6 ?* y% u; X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" Q6 | N5 e) S# Z7 U# A" m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX w) ^* Y. b* K: q' k* q
| MCASP_PIN_ACLKX3 j' G+ Y& `- A4 |& {( P+ [
| MCASP_PIN_AHCLKX/ y) h0 }5 V1 i* n7 A& A) t3 i5 a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% F" S$ ^- e' }$ A* \ f# |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! W( w( F- `9 Z* h L' c7 u
| MCASP_TX_CLKFAIL
! N4 O8 s8 \9 k| MCASP_TX_SYNCERROR3 L6 x- y/ y" j- _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 r$ ~2 r/ R! ~: h, P7 t G- c( w1 V
| MCASP_RX_CLKFAIL
1 U: i9 @4 D0 o" V5 e! f% a5 e2 G| MCASP_RX_SYNCERROR
3 j! E% r! A, U9 P| MCASP_RX_OVERRUN);
6 y! n/ a1 b% W: N3 `} static void I2SDataTxRxActivate(void); O, Y/ Q9 `% y' d( o) H; Y
{
, a/ a! l$ u' M- Y4 J3 c: S/* Start the clocks */
; E5 n% H( n2 i( l8 v, L* ~& xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ v7 _2 T8 l- n/ T# ~" q+ f/ FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" d) B# ?0 b# |7 U9 l: N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. S3 ~% `) [" J4 g6 }/ n3 kEDMA3_TRIG_MODE_EVENT);
. e; i) p5 v' f2 w7 x; gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & n7 G1 `; ]$ e m: R" j8 g: R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ @- v' _& O/ o& qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 e' z. i# |6 D# a% s6 x& c1 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& w' d! B& @! U! u' \; P4 j" H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% P' ~/ v$ T( j3 V* \% o& n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 T9 |' T8 \ uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* z5 E; w" p' v) I} 9 i/ F; b a) u* T. ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , @1 {2 ^' C; x1 A: r; b& G! w
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