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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 V. I, ]8 I, e- l1 ]% r# @3 Ginput mcasp_ahclkx,
+ R5 o5 X- s! einput mcasp_aclkx,
b* r# q9 W6 ?- l3 ~1 P; V+ N, p6 Winput axr0,7 q! i% E" `4 l& \3 p1 P$ n
7 p8 ]4 b: w9 x( H% ^
output mcasp_afsr,+ t4 ^# y* i( `4 |- t& P9 x
output mcasp_ahclkr,* T; c0 Z2 V; C/ V4 N- D8 ~
output mcasp_aclkr,
; r% S$ l& _0 C% Z- j0 U0 j$ routput axr1,
- z* k, v& z2 o' m# i8 j assign mcasp_afsr = mcasp_afsx;
0 t% ?7 {, p2 G% r' M& F cassign mcasp_aclkr = mcasp_aclkx;
9 ~" l z; t9 r. n! H1 C# V6 q3 Gassign mcasp_ahclkr = mcasp_ahclkx;
! `: ~. ~& b7 D: d9 n0 xassign axr1 = axr0;
; g5 i* U. }$ C4 f9 h$ j; ^, e, z: {7 m, ]( X+ D- X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / |( Q* m0 F1 u- a
static void McASPI2SConfigure(void)9 Y- I" y1 I: p' y; Y j
{+ g2 \4 Z& F& N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 g( h5 S+ _' r+ R3 H1 v8 V7 OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& U6 N- k2 e6 G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; k- ]- V/ q$ E ]( ~! k* c2 z7 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 s$ D7 j( [4 s9 B7 t& Q' a( G% XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 M- i4 X, z2 s. T! _) X# X
MCASP_RX_MODE_DMA);
. t& {. y( |1 z8 f/ B- \' Y0 V5 L' BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" J5 ^* |+ S2 s& E# lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 R$ K: x! `) _8 b( t+ N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! |# c+ z2 n; W) q) O' x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ d# x1 h3 }" X$ H3 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) k+ l' w- W7 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) `% q. |- F( V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" p$ q; `" `: s7 ~% hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 k% X8 i& @) _2 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 c3 w. w; { N. d, Y7 ~. J
0x00, 0xFF); /* configure the clock for transmitter */
' V0 C1 M9 u' D8 A$ NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 K F7 B/ z, ^4 T0 k- ]8 c) _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 u% e' p+ g7 A5 Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! ?3 A7 ?- C. V y" `* |
0x00, 0xFF);& A" B: }$ b, ~1 Y' z- h+ _
0 M+ J' W9 C8 O; z/* Enable synchronization of RX and TX sections */ C/ B: J4 i* i7 s1 G8 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, v s1 v6 e/ B# _) H [( y# v/ A, Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) M! ]7 ~8 J2 ~; f4 D; u: QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" G* \9 m" j/ |1 p** Set the serializers, Currently only one serializer is set as0 c- H4 P9 e2 v! u. h
** transmitter and one serializer as receiver.
% W1 f: U( W# D# N6 [% u1 r( D4 w*/
( r5 k* [& a p/ _ {6 u. [; Q' NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# j6 j: H9 p+ `: p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 n5 w+ k$ |4 n1 Q4 |$ m1 ^** Configure the McASP pins
8 Y; \5 J& F6 U7 p2 C** Input - Frame Sync, Clock and Serializer Rx: _/ Y$ o2 g3 u9 z' R' Z2 A, c
** Output - Serializer Tx is connected to the input of the codec 3 B8 d6 b. ~* i) R( u
*/
7 `/ G$ d6 C1 {* {8 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 X/ u9 R; M" w. I3 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# U4 L' N$ I& |1 i9 i4 d- j7 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 @1 `- p$ M+ F+ t- H3 w
| MCASP_PIN_ACLKX D+ f9 m; F3 ^
| MCASP_PIN_AHCLKX
4 N$ F# {" q. {3 W9 O9 W {# I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ h0 l3 ~3 L, M# n7 h. I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ D9 ]0 T3 P, _1 r6 h| MCASP_TX_CLKFAIL R P$ g' v0 M
| MCASP_TX_SYNCERROR
$ [! h. ]1 K* F/ P. _4 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' D; Q# G* t8 F+ M: t* ?9 `6 M| MCASP_RX_CLKFAIL" H) j9 ^1 s4 Z( M* T* H$ H0 W" _4 L
| MCASP_RX_SYNCERROR
7 U- e8 w4 W7 j9 {& Y4 i: E. \| MCASP_RX_OVERRUN);; p# a, S( h6 t6 S! z3 p
} static void I2SDataTxRxActivate(void)
$ a1 u* v8 w8 F+ E8 A! d' O* n{0 u. t+ k5 v& Q/ Z1 g# N9 f# d% u$ `
/* Start the clocks */
5 k7 l: q2 K1 a: G9 fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
~7 l0 {: @) p' u' f/ j9 i- \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ c" e# q( M9 x) R5 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! @8 o6 W6 a9 {' K, ^
EDMA3_TRIG_MODE_EVENT);" J3 F* B* A5 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & Q- `) K' e" t+ p, u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 I+ I$ {2 _( w) `/ p3 q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 [! Z0 J" W8 N2 z0 ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 a) s+ l: I! `3 _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 i; Z- f' Y4 R0 Z& f: C* R. j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 F. H/ Q$ i. d6 x# Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ p; H9 V% E& J) h} # m( a. z5 d6 ?3 h1 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) R/ J9 I: e. C2 j0 q
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