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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. E+ C* ?9 K4 `% O
input mcasp_ahclkx,
! {, [4 O$ s% {% X! n6 Uinput mcasp_aclkx,; T0 Y% H7 q6 W, k% S
input axr0,
/ x8 S+ Y- n; y2 k+ }. H; i; l8 y; k, H
output mcasp_afsr,
2 P/ H" o+ x6 Y/ `, E; c8 o1 ~: q; s1 Youtput mcasp_ahclkr,& ?: j- ^) N, \2 ~- h, g/ m1 J
output mcasp_aclkr,8 C. E# b* b4 P0 p
output axr1,
# M& d3 ?4 p3 K1 `3 l assign mcasp_afsr = mcasp_afsx;
5 @9 x) \* W8 X7 j5 D- U9 f) tassign mcasp_aclkr = mcasp_aclkx;
: P) U) Z- I, \) R. M5 G t( xassign mcasp_ahclkr = mcasp_ahclkx;
7 l5 G7 f$ W- Z0 k7 Z' E0 {/ N& Jassign axr1 = axr0;
$ f5 ^" q& C1 d: T. j! W- L) Q- q: Y, `. L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 V+ `1 N( o0 Z# b# ]0 v* astatic void McASPI2SConfigure(void)
) H# e' ~3 ?- m1 s# [{2 j; f8 |; w" C, k. S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# o, C+ H# f4 e# iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& b, H8 s* a3 N; W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# n* o+ R8 c$ T) ^& W9 {3 D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- h9 N( V- b6 \5 n5 w/ s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 y$ R( l8 u( r ~
MCASP_RX_MODE_DMA);
- y- L0 g; V. C! f3 @1 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 E ?; W8 A! \3 O, P+ D! u6 ^0 ?+ MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) L: m8 R6 k; U# fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & O* f1 P& w% w# |2 T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ d1 A; g, ?* N2 y9 y# d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 T1 H* V) w6 C$ p# W8 z' h! PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// N# k$ P q: k% ^/ K J4 N+ x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 p/ L9 ]3 C! B& j- }( _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( v8 u! C( ~4 P9 `0 O$ `; MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," ^2 t) x2 {7 F* i! S* k M/ z
0x00, 0xFF); /* configure the clock for transmitter */
) T9 ~$ ?& F8 k, f: o6 @& E9 m% S" BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 X0 m) d3 A) nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. A0 y- c! n* C( YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ R2 K0 o" y/ K/ o
0x00, 0xFF);- T9 }3 M2 s3 q& `) M! K/ O8 t. I! U
0 T( a& l5 g5 V6 K7 B
/* Enable synchronization of RX and TX sections */
9 V, {* Z+ p; Q+ qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 Y- S! H' ^4 L) o6 \& MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. K& P3 Q8 Y6 T: C9 M3 A0 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' B5 ~: g) e5 ?: Z6 H0 z" o
** Set the serializers, Currently only one serializer is set as( [/ k5 a0 @, `, }% v. Z; a
** transmitter and one serializer as receiver.3 Q2 S. ^, @6 q4 ]+ M& @
*/
0 K, ~% d& n1 p+ Y# r0 a [' }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: q: p9 I6 D9 ?( d. U1 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 p1 g( ^4 ~% p' m
** Configure the McASP pins 3 l4 q$ s6 z6 {4 ?* o
** Input - Frame Sync, Clock and Serializer Rx" S2 j6 q3 o0 g- w2 u' \+ l# U
** Output - Serializer Tx is connected to the input of the codec . Q. [8 }% }$ W' P
*/. d. b0 ~" m4 u: p8 `4 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 U5 v. W# \0 L& x& t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 l$ P* M: y- i' e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 L( \( N. f5 o4 @. d1 s| MCASP_PIN_ACLKX
, |) w8 q$ [( F/ j. `& \| MCASP_PIN_AHCLKX3 i. U' |; Z9 c- \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 d, ^0 t; S, S/ LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 U5 T$ D, N+ W$ }7 Q3 P( P9 U
| MCASP_TX_CLKFAIL
E$ v& w) k1 @; Z8 [: U v4 k| MCASP_TX_SYNCERROR! f% h# t3 L+ l+ z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 p! I3 J) K3 V8 i/ L| MCASP_RX_CLKFAIL9 P4 X1 V a, F% p3 P
| MCASP_RX_SYNCERROR
* T! w) E: N2 B" n# T6 m| MCASP_RX_OVERRUN);: n' y# L' U9 T0 N6 R/ V$ J
} static void I2SDataTxRxActivate(void)5 h6 U& S' a4 J' G
{
, L9 k* s! L, ^* P/* Start the clocks */
* n% a) H, `( g3 ]& V5 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% h; k/ _$ C2 W, z* N0 T+ e) }# z, O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: e( Q" b1 R% _4 N3 L# bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' }# a# l: F2 x% h4 w
EDMA3_TRIG_MODE_EVENT);. w, X E* h9 g6 I A1 {& I; X/ E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , F, ^0 R, j6 K" R! t$ \ m2 G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 e1 g" O8 r. X% ~' |* z; mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! n3 ^5 F: j$ }% n* U; |5 E1 p( ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" O% Y8 d3 C4 j& b ? E5 P5 g$ rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 {( j/ `3 \. |9 c0 S+ ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ ]; {: d# \4 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" _" _- }8 m. |! v, d
} ; Q' K: N1 h E" d9 \; I$ _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( y& ^: {8 {1 C0 L7 k3 m8 i- M
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