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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 m. c/ v! x& a2 r+ b: u7 r% B/ ^input mcasp_ahclkx,( }, y/ k5 \7 z3 b6 S! Y1 z
input mcasp_aclkx,
! A, h" x0 N5 U! A7 a6 c/ Cinput axr0,. e) h) x$ {; U
. ?& U5 b7 `$ Z
output mcasp_afsr,! E' g5 C' P) H! C% T
output mcasp_ahclkr,
+ R# J( e. D- Q( ?output mcasp_aclkr,
9 [1 r% u0 r& g0 r( a/ j8 I ^' ?output axr1,
- }6 M Z* [. ~# M3 I3 l assign mcasp_afsr = mcasp_afsx;
; F4 a& A7 j" m4 g: }; tassign mcasp_aclkr = mcasp_aclkx;
# \0 y% ?: f7 ~4 gassign mcasp_ahclkr = mcasp_ahclkx;! c% m+ m$ F) j; K9 J
assign axr1 = axr0; & ?6 h0 P( F. C- Q
* ?3 p1 B+ `: s4 ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 Z* f$ {/ j& ?& zstatic void McASPI2SConfigure(void), b2 e4 A& B6 g& y: Z
{
, a; j5 |8 ]9 o4 c0 gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 b. {2 Y; _* \6 k- ?' @8 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 [" u' L0 [4 h4 W# U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# C* x* |+ n5 U$ J5 _6 u6 e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; \7 y1 n0 v( i& A. q7 ]" D d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 }5 f9 L G) K5 ]2 R) {6 H
MCASP_RX_MODE_DMA);
. T% H( C! s' r5 oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 j$ e X$ a0 L& V D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ ]5 B) P/ _( y8 o% ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- g* _ {% W" N( u4 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; A/ J, C& z" O; Y/ |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& o9 i; M# _3 x4 xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 Z4 i |" U2 u# g0 a$ p. S6 D6 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, l( v5 @8 ^2 Q8 Q6 H# b, v( |+ ~' X- ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ f, k' N4 @: g/ X: x, tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( K; `/ y6 h; d4 z% m0x00, 0xFF); /* configure the clock for transmitter */
& X- q1 f. [3 s }! _- ~8 E0 bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 r. H2 v( p( }, o, EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); r, V+ a3 M. J5 m" R* |! t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 u- t/ [$ u( w3 V0 Q9 D0x00, 0xFF);" b( q/ z" o3 I3 J% X1 p- n
& U/ B* [# s- Y" X/* Enable synchronization of RX and TX sections */ ' f/ h2 c+ B- _: X: m) p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. K4 l( Y1 m; z: J& u* V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. u( ]0 ?4 v1 F5 F8 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! m+ J* T3 V0 g2 j! X$ ^** Set the serializers, Currently only one serializer is set as) X* f8 Z; }: o; ]
** transmitter and one serializer as receiver.
5 U8 J2 O$ ^* F, o/ K& |. R, e*/; k6 N9 U% m2 f7 L; l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! X9 x7 O" Y* U' @ Z; s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ _, U" j: B" i
** Configure the McASP pins + q" {! B" O$ S E8 c& b+ s
** Input - Frame Sync, Clock and Serializer Rx F. Q$ y/ ]. M
** Output - Serializer Tx is connected to the input of the codec : H" ~- q! }. `4 D ]) `0 n
*/; e" T& E ?, v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 h" r1 w( o8 }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( V/ B2 A8 ^0 m3 Q! ~! W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 u. Z+ ^$ ?+ Y& q& |: w: J- Y6 v5 V
| MCASP_PIN_ACLKX; s( u" f4 J0 f6 [0 h! E
| MCASP_PIN_AHCLKX
3 T( } V+ ^, p/ v) R1 i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% R: g) u% I- [3 U! O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 c# ^5 r' u8 I# D9 k) i
| MCASP_TX_CLKFAIL 0 H7 m; x6 g3 L+ J
| MCASP_TX_SYNCERROR; D8 ^" g& n: g5 X. R8 E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + V" K4 Y4 ]' ^* V2 ]
| MCASP_RX_CLKFAIL
4 s0 M4 b0 T" Y6 W/ w| MCASP_RX_SYNCERROR " B- A" v) m7 u" e7 |+ m0 X% H: k) H
| MCASP_RX_OVERRUN);
; o- h0 v- h# p, n6 I7 C% d e} static void I2SDataTxRxActivate(void)
" |9 L( z# o5 Y" ^4 f9 p{ k+ c V5 I8 f+ _) i1 i2 {- z
/* Start the clocks */
4 z, j( j0 ?2 S8 vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* ]! J2 o- X& x2 ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' x( u8 z. p" e; o( @6 ^' p% BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 m+ u1 z* B$ E* x" i. r
EDMA3_TRIG_MODE_EVENT);5 ^6 d$ L$ Y+ O! S' V; E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 [# C, P/ o' A" v% N0 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, H1 B% _6 i# U. ~: HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: w" x+ h" G, T; T0 m* S* N: e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: c& q& @# Y, b2 g% Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 C" e3 W5 b. k, _) }) d" }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 c! r6 c5 _& J1 @, _# xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ ]& {: L0 w1 ^( S4 x L}
4 l8 a4 X( `& @* t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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