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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 |3 X) q4 [( w7 r" Y3 a
input mcasp_ahclkx,: m3 z& X! u- `. K0 P" X' \; K
input mcasp_aclkx,9 y) ^+ j5 [5 @# x& D3 k7 v
input axr0,
# s- [9 L" e; a7 m6 i1 R3 @! q- ]
output mcasp_afsr,
" `! G$ e$ Y$ o& |output mcasp_ahclkr,1 U: V& r6 c, M" x1 V" o6 G
output mcasp_aclkr,
8 x0 z' X3 G2 U1 routput axr1,
( R b$ `7 F- ~. Z7 J% p assign mcasp_afsr = mcasp_afsx;
# ~0 U0 z4 z7 c2 |5 p; gassign mcasp_aclkr = mcasp_aclkx;
: r2 k& J' R6 F9 D% [7 nassign mcasp_ahclkr = mcasp_ahclkx; i1 m( U" v$ O* c/ t+ ]
assign axr1 = axr0; ; k) c6 ~. B% v- w. H; k
' u. w' c2 U: B* J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 T6 D4 K* @$ a# W$ l, }
static void McASPI2SConfigure(void)8 f. j; ~% V+ t r9 c! d0 f
{# t- S& \5 K* N& o; u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) S5 \, ^; }' w# H, A. X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 f( n; T. O. D) z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 z/ ^$ o q# M6 W8 V7 XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# x. h# M5 j0 j$ @6 J& \% n# r4 Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ l/ w8 {' ~7 j0 s
MCASP_RX_MODE_DMA);
% z" q) Z8 J. B$ qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," M( M0 e. [6 W) J+ h" j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: f* l8 U' F" L+ T/ MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) ]+ Z* E; B2 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 H0 l) I. I9 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' e4 w6 E1 l/ ~/ q! l B* t$ zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 C3 q3 @' ?' a0 R: kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) @4 u z7 l8 A1 r4 e. ]1 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ ~6 c) J6 w: }8 YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# ^4 X* D7 h( |$ U0 o
0x00, 0xFF); /* configure the clock for transmitter */
; t3 A; O# D" LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& ] d' c: u' C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ j a) p! r3 |: N" ]4 S8 X5 s; FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" M8 O2 w! `4 c. U( e) z0x00, 0xFF);8 V& B: J3 Z( ]4 K- o8 Z! x
" d8 V. ^- t2 @ s4 l) A# _: E/* Enable synchronization of RX and TX sections */
9 w! e0 ~ z7 C7 j, ?% DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# `+ O5 y7 h4 Q% f" R+ uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! I3 \4 h8 W% }7 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 R" C% U! R6 M& [% x- q
** Set the serializers, Currently only one serializer is set as1 U6 B+ f& V9 Q4 C+ b D8 S
** transmitter and one serializer as receiver.
) h, {0 f/ {/ Z*/
4 s/ D0 ~3 H! K( }" qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 M3 H* V }+ c$ b2 o* b& T# D. HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) I9 w Q8 I1 @
** Configure the McASP pins + z. t, @3 M3 d
** Input - Frame Sync, Clock and Serializer Rx
( u1 @" z8 T( u& M** Output - Serializer Tx is connected to the input of the codec
. p9 ^/ Q `% B*/$ Q' s; j8 S2 Q% P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. Q" u6 u; [- S1 o) h# i4 R; eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 y1 X" b* S9 A8 J; P6 Q8 PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- Z1 h: X% ~, G ]
| MCASP_PIN_ACLKX
: c. k/ k( x# R) O. M, x$ a# p5 C| MCASP_PIN_AHCLKX
% k$ l2 q3 Z, }: i4 _0 f/ o: Q5 N6 m- w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; ^" q# q3 K' {$ G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) Q8 A" I. g% W. T) G| MCASP_TX_CLKFAIL
7 u0 ~! w" k/ w) [( P& _! W0 Y$ W| MCASP_TX_SYNCERROR
* I7 x' S, X- I+ o* ?7 y$ U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & r5 {' j6 z, }) F
| MCASP_RX_CLKFAIL
+ n+ r4 |! ~% L/ Q2 s| MCASP_RX_SYNCERROR ' x9 k& |: V/ ?" r D
| MCASP_RX_OVERRUN);
3 V8 C/ _. K! \; a} static void I2SDataTxRxActivate(void): m- R0 F1 k6 {+ _2 M) H! j
{, b! T0 k5 H5 D, w ]0 b7 m1 A
/* Start the clocks */% y$ D2 r+ J8 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ ^' L3 X' l+ ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% T* g4 q$ R8 Z0 {1 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; ?4 y1 v) C% ]7 i8 E' [EDMA3_TRIG_MODE_EVENT);3 }- L( L/ n- o+ _" H0 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& K0 M) M" i4 ?; O( S; ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) x9 v6 k" |9 m- F! o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 X6 Y% W0 S! B( r" B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, r7 R& `% }3 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, c5 X1 l O, \8 a' f* V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 c# ?3 R& U' ~, W) P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& A) p2 z& [- ^ p; Z3 N: u) C}
6 z, I' K d# n/ s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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