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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 B0 `7 _& Q7 L$ I$ j% p; Y# C
input mcasp_ahclkx,1 x, B. P. D: X# @
input mcasp_aclkx,
# m5 X$ @' {7 { p+ v% O* dinput axr0,
! l; K* A& i* O# r, e
/ j) l% K, y O, z8 p6 q8 M* S6 Ioutput mcasp_afsr,( B5 @6 @/ P6 D! v% i) j
output mcasp_ahclkr,
. t2 @; F* p1 |8 X+ |output mcasp_aclkr,) Q7 v6 @+ V9 `3 g# e0 k
output axr1,$ P) `. m5 ^* Z) b: P
assign mcasp_afsr = mcasp_afsx;
* U" c. V& w+ K8 fassign mcasp_aclkr = mcasp_aclkx; ]4 a. G5 I' l4 F) q n
assign mcasp_ahclkr = mcasp_ahclkx;
% a' S5 X8 v5 Massign axr1 = axr0;
& n( s5 @# R8 _0 _6 b; E- V* T: b
' n8 g" n9 v, v" w9 Z/ b( f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 b: l# Z/ I* ^. Jstatic void McASPI2SConfigure(void)
4 @5 L7 u) S: X0 t{* q7 d" ~8 ~: g. l7 S5 g/ N' \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ W) o D- o3 ^; n( S& T3 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 o. t5 P" s7 N( D+ ^: JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 w+ g& A* r5 F7 X( ]$ _$ I3 s* ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ G2 ^' d# J. I* TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. c2 h+ `3 r/ ?& x5 p0 F8 d/ q& OMCASP_RX_MODE_DMA);
9 ] [+ S7 G' O! `! DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; g( g/ S+ }$ k; N4 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 P, C7 W9 t0 _, m8 wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( t0 M7 L$ c; @* E' v7 {9 aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) a7 J1 p9 f0 ^- S4 _4 t/ a: ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 E/ i& M+ n y7 uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 `% [! D$ [: \$ Q& pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! h. W. a) B: q$ H# }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& I/ d2 @* Z' Z. {4 Z# n2 ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; `9 ]" d- f6 m6 A* G# @0 w& C- R+ R
0x00, 0xFF); /* configure the clock for transmitter */1 y$ ]' g" l W) g2 U1 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 d+ @; \- {9 l0 W; E' R- H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( {* W8 \. B: l8 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* Y2 [( f( @1 Z3 p ]; a0x00, 0xFF);+ E) Q1 t. x2 C% X
# N$ j l( l; l% l' r4 Q; b/ T/* Enable synchronization of RX and TX sections */
% w6 s5 p; z- n* O- mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ h; i: `. W5 \$ a. T# w% S2 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 ~1 i' X( z% F% s7 K; g3 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% T3 H1 R& F Z/ \# ]$ l( t E( \7 ]** Set the serializers, Currently only one serializer is set as4 \( K) q4 b( `% |
** transmitter and one serializer as receiver.% U1 M7 ]0 N) H; H* k3 k7 J3 j
*/! k6 m0 R" p) H, j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- [1 s' T* _$ c0 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ q% A9 d1 C: H! m6 S** Configure the McASP pins : Z8 H5 v% |3 I9 P, ?
** Input - Frame Sync, Clock and Serializer Rx8 u; v6 B, W4 G( Z
** Output - Serializer Tx is connected to the input of the codec
6 a) Z! m5 N( e1 T3 k# R. V. P# ~*/& `% X' V: V0 {3 j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' `# }8 ]$ _8 B( pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( t& M' Y4 _" s3 p# L4 c1 Z6 @, `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 V- v7 j0 b" C: c% J$ ?| MCASP_PIN_ACLKX2 h. A b9 h: l4 _9 w
| MCASP_PIN_AHCLKX" [0 g2 T1 f- x' I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% w9 k- n2 y& zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# p: P1 ^9 ?3 G| MCASP_TX_CLKFAIL
- v" ?+ i# ?6 J& ~. C| MCASP_TX_SYNCERROR
A0 E5 W1 F ]8 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) W6 a) w) M4 ~3 l/ S; K
| MCASP_RX_CLKFAIL
( E' b# @0 Q! j; W| MCASP_RX_SYNCERROR % v1 O/ k3 E' R, g* ?
| MCASP_RX_OVERRUN);9 y4 o( I+ N* _
} static void I2SDataTxRxActivate(void)$ I) {: ^ x/ z3 _
{
$ g5 l0 O& P9 Y$ ?/* Start the clocks */
- t9 i2 K7 T4 ~+ XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 e* ?3 M* A: J6 K0 w/ w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* u% k& U8 u& L" V' jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 }+ B/ U: Z$ \# G: W% x! c0 dEDMA3_TRIG_MODE_EVENT);* G! g/ j) L8 Z' e; F3 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 o) b- [4 J7 KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* g. W# k- C8 F5 a6 F. }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( M# L) j2 S& Y/ i2 d6 U; r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. u3 J2 n3 W+ g) P+ o* ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( M4 G$ S. g7 h; K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 J8 I% [/ X* i. J. SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ i- G$ z* T0 v' m0 |9 y
}
# S! w. }( n2 [+ Z4 @8 Q: c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " [" ?/ c8 v" X* r* H/ a* }
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