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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% v. R1 l5 m0 J1 j2 e! W% jinput mcasp_ahclkx,
* m2 e1 n* \2 Uinput mcasp_aclkx,5 W U. ^( P& G$ ?6 S
input axr0,
6 i, S) U# Z3 w U
1 {# T8 I# M( h1 L; Soutput mcasp_afsr,
+ _: U4 ^5 u( v, Eoutput mcasp_ahclkr,9 R1 [: v, u }9 r( P6 j/ ]) G! T/ _
output mcasp_aclkr,' e+ T3 _$ H! ?$ Z0 }! q
output axr1,
3 M% B7 z" ]0 C assign mcasp_afsr = mcasp_afsx;
# F& u( S7 L8 K! E$ t* Z ~assign mcasp_aclkr = mcasp_aclkx;; _- @" ^# B+ f; f) N3 Q
assign mcasp_ahclkr = mcasp_ahclkx;; }$ i8 h( N* s, [
assign axr1 = axr0;
% @4 L. X: P: Z9 J! P z5 j( w: V- X! G% ?* M( f- e% v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 h' z9 C( V- h
static void McASPI2SConfigure(void)$ w: l' ]' t& w1 c: H
{
1 B8 S! v( a# V- cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 b: _: l3 O& u. W. VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( h# z9 y9 b6 K3 u. {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" R+ Y$ F! P& Y- H: g* r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 z0 {7 _+ M3 u( X2 Q- cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; K6 W" E6 J- {
MCASP_RX_MODE_DMA);
8 m- P' Y6 i z8 Q, BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
W. p+ Z9 [7 u$ Q, H* ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# U0 l( d( ^$ _ }# d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, P6 f& w5 i% M7 }+ X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* V( @2 w# Z1 l2 m, ], k; P( RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! p& I' c6 W/ O: l( {& WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% J, P. X1 T& ~0 X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% g- p# i3 ~9 ^: Z# n+ m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& _( D q9 p f9 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 `2 O4 z& _: z! R* L* m0x00, 0xFF); /* configure the clock for transmitter */
4 f2 V6 e0 C* R7 F5 T1 q7 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ u) p+ ]6 ~. i2 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 u6 o9 v/ S9 }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- {! f1 u. Z: m% z R0x00, 0xFF);8 _" K/ N5 A1 i' k1 z
" N0 z% ^, P" k) y/* Enable synchronization of RX and TX sections */ L, l# P+ D% V' K/ `# m& W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- T$ U. Z' o8 K* IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 Q- k3 }! Y2 j( h( S4 B0 v* }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* m: q$ j* E, R( @& J, j% x, Y** Set the serializers, Currently only one serializer is set as
4 A' X% }% g) Y, F/ \0 D" s" @** transmitter and one serializer as receiver.
7 V3 [2 c( x( U1 j8 H |' ^5 G8 L+ _*/
* E R! Q1 L$ J1 j7 K$ q6 TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- c! i; l% H t: U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# S% B& J4 [( B" }
** Configure the McASP pins
/ R6 G- }7 M! a( m; v** Input - Frame Sync, Clock and Serializer Rx
2 i: e- [3 H% r% C4 x** Output - Serializer Tx is connected to the input of the codec . X. ~. L; S6 n6 R r0 @) d6 u' S
*/% R; k3 g f X3 r. F. W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 z& V7 k- G4 P; h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% g0 U! w4 W' ]' hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) a4 |1 V) ]4 v) N+ Q w, q# }" W
| MCASP_PIN_ACLKX
. N* O8 A: y& F1 ~. U| MCASP_PIN_AHCLKX7 I- l" `8 C; _4 H' e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% H8 j, A5 j; J% r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) _# f Z4 {6 |) K H- y4 W4 {
| MCASP_TX_CLKFAIL 9 L7 U/ K2 K: j6 R9 [) Z& ~- X. A: a
| MCASP_TX_SYNCERROR: I+ b( |/ v9 z8 E5 E! q2 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % c; [- D: i7 }8 r$ o
| MCASP_RX_CLKFAIL# z0 c$ g$ N" X
| MCASP_RX_SYNCERROR
2 A2 O# Q, E5 Q- k| MCASP_RX_OVERRUN);
( ~3 M1 a- V: Y- e% r9 F* R$ U} static void I2SDataTxRxActivate(void)
- f8 U! K* {) w0 p* y# h3 H- u, }{
; [7 [/ U: w* w2 m: _. z9 l/* Start the clocks */
1 W# s( `( X! `/ n& CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' b3 ~! d' E1 P& n* b# j: iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: Y$ L4 [- \( \7 R+ v0 F7 U8 ~/ P9 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 u' E" v1 P; PEDMA3_TRIG_MODE_EVENT);! s5 Q% g$ w# |( p. Q% |1 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ P+ c9 b3 D& P6 [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( N: c+ [8 P6 w" wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 Q/ s: G, Y% ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 ]8 r& ?1 `( K& q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& D* p+ o: M8 h" o% `0 S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 J8 y2 p3 M) ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) {8 K8 ?# }% s [: e0 H* l j! a/ E
}
% g% h/ u/ Z9 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . @4 P# C! A: A" D
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