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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 h; P# Y0 O/ s O3 N
input mcasp_ahclkx,- l, L3 o* T* G! x( q
input mcasp_aclkx,7 @0 b" X" u. T9 j& J
input axr0,
5 I- L" w; ^$ k& O
7 X" u1 j0 z2 E: {output mcasp_afsr,: X5 B. h# y: n
output mcasp_ahclkr,
; F/ h, e* I6 Xoutput mcasp_aclkr,
7 H& y; Q0 |2 y; Q( V, ]( M% t- ~- v$ Woutput axr1,, l4 @; s" W6 [) V$ _3 m' O* f
assign mcasp_afsr = mcasp_afsx;4 _7 _* y* ~8 w
assign mcasp_aclkr = mcasp_aclkx;! P+ R/ e- J, E; c4 \* K1 N
assign mcasp_ahclkr = mcasp_ahclkx; I. G+ f4 P) d3 ^: t/ i6 @8 [+ |
assign axr1 = axr0;
4 r2 [" o# J' p* d% G5 I! Q g* K& J1 J: e) y' B5 |/ a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : o: n! [( }9 R+ B' R/ o& v; d
static void McASPI2SConfigure(void)! N6 x& H0 ?3 n/ N( M6 E; ^# M
{
& y; x1 G# d, A" \- T3 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 c" A8 P% C" X& l' M% dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, f# R' P4 ]. ~" c& C! k1 u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 N3 D8 t* ~1 s8 v9 Y: P* c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 R: q0 x/ N0 s4 ]6 ?3 h, l4 P; z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 P7 w3 ]8 T# S8 HMCASP_RX_MODE_DMA);1 \1 A6 X/ l9 }- g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, e% `1 {. O8 N3 Q4 @, o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; Y! A; H% U8 `9 u N& k' m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 q8 U9 M, V4 y% e* F0 ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% p3 N8 E' F! T& d$ f& P$ `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( w. ^+ W& d0 X1 M* b/ Z/ |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 E: y, C6 G# ^# i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- }6 F2 [+ M, E$ d, A" t7 ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 E6 _6 B' n" k7 W- C' Y i' O& UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% L: R- \; V0 ^( d$ n$ B, G0 [0x00, 0xFF); /* configure the clock for transmitter */
, U1 z. c0 V1 L8 L. U7 j' z. e2 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 }6 K8 `& p( m/ u4 }7 S/ `1 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - O, X g3 g" f' ]! a+ _) C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& T8 j/ X, j! n, b0 _* `& Z- v, L0x00, 0xFF);
3 q7 T/ ]$ D" K2 [+ u& h- ~- [* j/ v) w! u0 i" Y' W; e, _+ O+ y' Z& @
/* Enable synchronization of RX and TX sections */
9 K7 Q, \' y. O1 g. fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ l. j1 P4 V: i5 l# q5 }1 I2 b3 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 d6 f) |( X* h. s) p' r: l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! y( w& R/ I0 o( u
** Set the serializers, Currently only one serializer is set as
: t: C- o& B; }& T R** transmitter and one serializer as receiver.
% G6 ~$ m2 P1 q*/) o& Q4 i0 a; m3 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' `* e0 p$ z$ l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 e4 J' v" `; C0 a+ N3 g8 [
** Configure the McASP pins
1 B- W, G! N. L8 n* Q v** Input - Frame Sync, Clock and Serializer Rx3 M( x5 j. Z Z2 Y2 p
** Output - Serializer Tx is connected to the input of the codec ) `" w( j+ a8 J6 X( f
*/
# ~% I' D, D/ K, pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% {3 m: Z7 N3 S; c9 n/ O. d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, d2 j- @& z2 \( A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; Z u; \4 _& n
| MCASP_PIN_ACLKX
0 n/ S# f# {+ L. `9 i# || MCASP_PIN_AHCLKX
! p: H7 N1 \6 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 ~) s. f1 O0 }2 d; ]5 m) q. p/ c' JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & Y$ G6 M* o t! g$ t1 N
| MCASP_TX_CLKFAIL
/ R: Z! M( O. l- d" ]| MCASP_TX_SYNCERROR! U W) s/ w( a% V, Q0 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * C5 o& _8 o- f4 Z8 V" X
| MCASP_RX_CLKFAIL
6 H0 b+ y- {. o, B! T; {1 ?" A8 g| MCASP_RX_SYNCERROR
4 ^( z( x* I" q* [| MCASP_RX_OVERRUN);/ e! D& E- I2 @. T8 K" P
} static void I2SDataTxRxActivate(void)
9 A* R9 g: x9 v" K{
0 S5 F! S4 P2 v! O! c9 w/* Start the clocks */
1 g0 d: L/ V9 L6 t# BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) J2 d- |- O4 w. v/ j) q2 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 } E4 {, V/ @ D5 {3 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 i2 X' B6 Q/ ~- g% X8 gEDMA3_TRIG_MODE_EVENT);% s; F) K- E1 |/ D5 h$ G/ _7 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 W, ]& Q8 |: J& j( \9 B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 X. T% q8 {4 `4 K/ H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 ]9 t& |5 Q0 I% s9 F6 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ k, Z4 `+ J7 H1 P) Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) A0 @) n: e- o! `8 W0 L, o N9 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, u) D0 j+ g6 Q( W) @" w/ vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! P$ m O5 k1 S* z: k; u
}
; c# O5 V7 ^' w4 I. L, c7 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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