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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 l5 r# U# l, V& \
input mcasp_ahclkx,
% X# B0 W5 N( P" F2 A( Minput mcasp_aclkx,3 c. P) o/ n9 v5 @; n5 H- W$ |+ H6 a8 k; c
input axr0,
& M. h6 c: G1 A2 J* i. N3 w! s2 p1 g+ B3 z; m: Q2 U2 k) o
output mcasp_afsr,6 ~% g/ }- r) F
output mcasp_ahclkr,
& ^) S$ N Q4 Boutput mcasp_aclkr,
9 v8 H) _, w! Q/ n4 Y) }output axr1,
! Y' }) H, T5 I0 j& O& t assign mcasp_afsr = mcasp_afsx;; N6 @1 l! z( w- q
assign mcasp_aclkr = mcasp_aclkx;9 u. x( F& X$ A- l
assign mcasp_ahclkr = mcasp_ahclkx;
# E& x4 Z) W6 W9 D' Y6 Fassign axr1 = axr0; 7 X: D1 b( h& ]* G
. D# ?0 S- U1 E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( V0 U( O( ~, E* |- {2 E6 x
static void McASPI2SConfigure(void)5 f. f" W+ K/ w5 s, a# C5 ]
{
. p8 f" G/ x: d/ }/ H3 @8 AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 A! }! w" n o$ _. @7 ?$ S: I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ |8 K. [( g# H) ]/ p8 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) K, b& v; D, \1 jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' N" ?1 A8 F, Z5 [. X" O% G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 {# D1 V, o0 b% H9 ^! `" n+ X, k) J
MCASP_RX_MODE_DMA);- Q* H. v b. h2 E' X& ~' i: B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* O( o, {; @" D$ M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% v. ?& m6 g' q3 a$ ^( U7 y4 N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 g' o/ U m& o8 }$ J% v; A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* L2 N A8 \9 S7 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ k) K! B! W- ?5 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 I7 Z- m. c6 L! I: i6 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 q) y0 Y0 z# L. ~/ N- `" P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* a6 ]! i! o% c8 E) A/ J5 cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 L- s1 u) j Y' f) ]8 G6 o
0x00, 0xFF); /* configure the clock for transmitter */
5 \! F$ r& A9 S; K* N2 J. GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- k/ q! z6 J/ y! f7 w' c- G: Q7 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * {2 J& o3 G7 J" c/ h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& L5 H+ o' G0 u* e
0x00, 0xFF);+ u( Z- \, j7 a8 U
" o6 B( J$ ?& x+ |0 u4 g" t4 ?
/* Enable synchronization of RX and TX sections */ 3 C9 w# C. t& P, Z0 x! f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- B1 ?. E# ? A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# x1 B; y# o9 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ L4 W/ z& f, @! T- t1 s** Set the serializers, Currently only one serializer is set as/ ^" K5 e3 G3 w/ L( M$ r
** transmitter and one serializer as receiver.
7 L1 Q$ H" Z5 T/ ]*/
# u5 l8 j8 R* r: `; ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: A: ^: l8 c* DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" g9 g# R" Z6 s( o' ^6 i( A
** Configure the McASP pins 7 B) G9 U8 X! U7 l E$ k0 A
** Input - Frame Sync, Clock and Serializer Rx$ k9 P) K8 y- d" d
** Output - Serializer Tx is connected to the input of the codec 4 ]; f; A6 H9 T" [3 Q# T
*/
+ y) c' x- @3 ~$ ^; `! |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- @4 \ [% K* V6 ~+ U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: c: R! R4 ]; a' ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# {1 i- a1 [: X, {* | @| MCASP_PIN_ACLKX
* Z: n) [. z% ^3 R$ _ f| MCASP_PIN_AHCLKX
: l6 p: l k/ t/ L: F) || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 _! |+ n$ R0 d# T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) L* U0 f# l& |; ?2 n. G+ L| MCASP_TX_CLKFAIL
9 w. O% [7 _- s9 C: @5 f0 C( [| MCASP_TX_SYNCERROR
4 W7 Y1 z$ I, z2 u- o0 D+ s) I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ g/ F! Y& p/ k' z! s| MCASP_RX_CLKFAIL' z% C* R8 w( s" O3 f- l; C {
| MCASP_RX_SYNCERROR * q$ D \* d8 G9 c, f
| MCASP_RX_OVERRUN);
: z, D. \' \% T- a} static void I2SDataTxRxActivate(void)! w9 Q3 {6 ]+ K+ }# |: p3 G' p
{
$ \+ c6 |! o; B1 [, G$ m% ?+ ?( B/* Start the clocks */
$ t0 J$ I4 I8 R; O nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- x6 ^6 B; j' U# D0 L9 yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 q+ F$ a$ r: @* g. T0 u6 ]6 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 u9 c7 M0 e3 U& i0 E
EDMA3_TRIG_MODE_EVENT);( p- p: d& s3 v# b; A6 M, H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 e2 |7 [9 H+ M+ Z2 z& @3 r1 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) Q3 n: p1 I. t: s' EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; } u9 p0 H- g# g( j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% G9 b# l: t3 q, {% |6 ?+ I0 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& S4 T! G2 b! q: D8 h* F7 kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 a* \+ |" B; d* F. zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 \% Q3 Y* k) g0 J
}
' U( y" J9 `, Y. @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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