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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& T6 x7 w" C9 B1 F7 |# s- Hinput mcasp_ahclkx,$ m* v6 t3 G. R
input mcasp_aclkx,
* W8 w0 i k0 }0 J. F% y+ g4 }input axr0,6 d4 ^4 f& j F% F4 p
1 Y l" ]' P! h: p: q2 m
output mcasp_afsr," X+ k( _3 g0 D8 G
output mcasp_ahclkr,7 W0 N8 Y6 W( K7 {# Q* k, g
output mcasp_aclkr,8 J, W9 t8 z: f* z& o
output axr1,
+ z: q8 ^ a/ v assign mcasp_afsr = mcasp_afsx;$ c" d( Q: C" H! D! d" X
assign mcasp_aclkr = mcasp_aclkx;5 T X! U# T% o. V8 V7 X
assign mcasp_ahclkr = mcasp_ahclkx;! F2 N" }0 c' c' c5 w: t* G* ^
assign axr1 = axr0;
8 M' r5 x$ T& @
) ~4 C4 N) \/ |( ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: ]1 ^! @4 \4 v/ a% c# mstatic void McASPI2SConfigure(void)' N7 X- j. Z4 t2 P
{
6 N; e+ z, H' a: iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" ^, a8 y- o, Q! l2 k& P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- L- m: |' z! q6 P4 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 @1 N; a; w# [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 Y. R. s3 f6 ?8 R! |2 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 L4 Q" E' T* F
MCASP_RX_MODE_DMA);: n2 n( J5 p! K r1 X+ \* K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& c% y9 r! q/ N6 v* E& [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# V0 R7 s; Y2 Q( ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 X9 P( I# v% O! |; `7 T7 [8 [) gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' N9 N- c" \# q; Y; N* ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! I2 D# K0 _& n$ E. TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ q" c# F4 K& M3 i, mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" i& {9 a3 t. t0 k# jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 ^: _: A4 G! K g8 i( J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! d% F0 F) u L- o" L
0x00, 0xFF); /* configure the clock for transmitter */
: J L, v3 q7 U. _! J: _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 u+ J; B8 T2 d" H. m$ I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 N5 F& [ d3 T$ Q! T# i* Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
~& L1 E) p: Y0x00, 0xFF);6 [! _0 N1 X `% t: G2 |
1 c% u; Q o2 A7 N3 i/* Enable synchronization of RX and TX sections */
0 v8 Y E7 y2 s( e1 T) J) ?0 |' AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& f8 {- A' I/ `- ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% @" m, D& H* U/ b' IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 a4 ]$ O. ]4 e- j6 W
** Set the serializers, Currently only one serializer is set as# b/ R9 m+ z2 m' ]+ b
** transmitter and one serializer as receiver.; s4 I* M" q# _
*/
6 \4 S& h% N4 U8 ]- P6 l& CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& A" u: j/ u& j8 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, K: `0 P( P, V" [5 m+ d) X
** Configure the McASP pins % P8 ]0 n b. V; Z/ A
** Input - Frame Sync, Clock and Serializer Rx: k f8 V+ e7 u7 n! ]/ i1 f
** Output - Serializer Tx is connected to the input of the codec z) |- t' O- R" X3 p/ x
*/
3 I9 I, s" z$ |' R+ [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( t. k1 r1 V2 {! K1 ]) f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 b: w p5 j l' L- v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. F$ Q$ @! P. v# c6 n% z
| MCASP_PIN_ACLKX
) `+ K! `+ Q6 D% W; W| MCASP_PIN_AHCLKX. p- {% S9 I; I; _+ a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! C& t. `7 T" W- }* ^& b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 x( h! q( _8 \1 a& p) e2 f$ M( i| MCASP_TX_CLKFAIL 3 f, N: I- v- s# i3 W, q) x
| MCASP_TX_SYNCERROR8 |- j, K+ M# p3 H$ Q G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) e4 I' o0 _- t
| MCASP_RX_CLKFAIL
" ~. h3 s8 T6 r# V| MCASP_RX_SYNCERROR 5 T, |/ i/ Z4 l* h A# |2 j! j
| MCASP_RX_OVERRUN);5 V' R. R3 \ l5 X+ I" N# H/ u
} static void I2SDataTxRxActivate(void)( r( g5 l8 N4 f) b2 G7 ?
{
+ ]# k5 E% H0 W a7 h- h/* Start the clocks */
1 ]( Q2 P7 `7 Y+ n, L5 ?+ ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& V- P( i8 X& Q" n6 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 y: g3 Y& j& K( I) ~2 M& X3 c/ @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 r- y3 B' c" T: q* h
EDMA3_TRIG_MODE_EVENT); c( _" l! `5 c* s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% x2 \7 S: P0 _( O* X( A' mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 o9 _; A- g' N5 H2 @- oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% w8 J5 ]: Y i3 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 t# i. q# v* [& L5 j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 T" G" `- u+ |4 IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 r, W# H6 j- r& y- u+ S2 Z2 W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' m% R& j( S7 J' V8 Q}
' h$ F, j9 b6 y9 K* J9 g% r! B7 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) Z+ e) c/ t8 f0 w( U. \& H6 q
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