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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* R2 R2 @" b! \/ M5 r2 ~' j, ~
input mcasp_ahclkx, r$ a: {$ g1 s; R% h
input mcasp_aclkx,
" A( K+ I+ b( v. a; c: z/ \4 F5 Vinput axr0,
& H0 X2 S6 d' W
* {& w4 A7 @0 F2 v* ]3 z/ P2 h+ \. O. ]output mcasp_afsr,2 K h& r$ c: n1 P. z
output mcasp_ahclkr,4 z4 v% N# G( g2 K- C5 D2 B
output mcasp_aclkr,) F9 n' {& j2 b/ e5 R/ y
output axr1,+ u& t3 ~, m, _# b) ^
assign mcasp_afsr = mcasp_afsx;9 a1 v' b6 {3 ~- N
assign mcasp_aclkr = mcasp_aclkx;* N8 c5 s& @0 x( I9 @' C6 ~) S
assign mcasp_ahclkr = mcasp_ahclkx;
! v0 z+ @1 k8 K( p9 F3 T: V% D# ^assign axr1 = axr0; + n/ l' ^' l3 y; g4 t
4 D" T7 K, p& Y7 r" j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , c% [0 v# V$ ?2 ], q( z/ s
static void McASPI2SConfigure(void)
4 D4 l; j" P5 x/ b6 `{6 J. j i; ?! ]& z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ j+ _, K& G$ ~1 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 s+ S/ { c1 ]6 f: h' E* D. jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 e' V, v, ]; N6 n- ^- M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ ], x$ p" P: W6 m; N1 Z) Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& H% B; p' t& [0 _, ^MCASP_RX_MODE_DMA);# k0 ] e) v. ~1 N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% F) P, Y0 }8 a! e3 Y4 R* z! p( H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 ~! V( {( T4 c( m @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % o+ B/ N3 l# Q6 A6 P6 d; }: P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 t' h6 s, G( \3 [ b- k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 v; k- o. g* Y- h. MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 h' x6 d# [& G7 j, l0 O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); l ~. O& F) i( H& _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / W- K& i) s7 q. s1 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: [- B( L' d, m
0x00, 0xFF); /* configure the clock for transmitter */" W# [1 A( q! e$ o" i" @! i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, ~, {& _8 ~' N7 z1 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- e9 t6 G6 y8 F0 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( f) t J! m6 ~: `9 U
0x00, 0xFF);0 e: Z' S7 `) V/ K
: |0 _1 k7 ` `1 v0 j. s8 b
/* Enable synchronization of RX and TX sections */ * r3 R" u# ]" k, h) h$ o3 s& s4 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ |# h l& @7 P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ~* V1 o- y$ c: ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. p, N7 _3 F( [ }7 S' |! l% M** Set the serializers, Currently only one serializer is set as
* W& B8 x, v3 }8 R. w1 v$ y+ y5 Y** transmitter and one serializer as receiver., b9 F3 o, P) G/ C4 C
*/$ p& y% Y3 i @# ]- |* W+ }" q' ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" z# r* q* k8 x6 g: f( Q* I! F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' w, E. q4 K' P- g/ ^$ O& v5 w
** Configure the McASP pins
& U+ j y# M5 G/ H; V** Input - Frame Sync, Clock and Serializer Rx
/ x9 u* D+ W( {9 t( s2 w** Output - Serializer Tx is connected to the input of the codec
# W% J! S' Y1 I7 v*/
: H% {: h, N7 T' I1 E6 j. d2 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% j3 p. `. V9 ?7 z: V3 M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( X1 s# Y/ ^7 A K/ b0 C* k5 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ h1 H( ^ W+ @% a) q- e| MCASP_PIN_ACLKX
. f$ H) |! t. a0 m+ `" z2 f| MCASP_PIN_AHCLKX
9 W- j' q w1 z% s# a1 |! P1 m; T4 G1 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: B4 i. H6 L* r/ r0 r" P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( X" Y6 z2 {1 Z' c( N
| MCASP_TX_CLKFAIL
1 k s- i2 Q5 S* Q4 K) E/ [. m A| MCASP_TX_SYNCERROR$ M5 }* Z! t9 Y8 q/ [! A3 u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; t- o! t; t( x8 z| MCASP_RX_CLKFAIL
8 l4 r& d+ `! W || MCASP_RX_SYNCERROR
/ o5 D$ ~ w! f" T6 z| MCASP_RX_OVERRUN);! p" N" \$ ?; H3 n& [4 e, g
} static void I2SDataTxRxActivate(void)
?3 G }# ^1 D( A{0 ?) m( n) t& m9 P' |
/* Start the clocks */
& M$ Y# n8 m! H. x7 Y3 T* MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
F) ~4 B- T' a" U9 @( M9 ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' K2 {4 ?$ N Z9 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) F) K% p' \0 S+ _. F' W2 B2 x
EDMA3_TRIG_MODE_EVENT);
% D6 p" a( M- i- ^5 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' ]! l1 w3 W5 x5 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 E) Q$ h# u* M8 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 L& e% r/ F! E7 w- Q. uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% |7 M8 X: @5 p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 k: \' K# P+ _6 q1 }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 \# `3 V$ d, ?. q: ?, O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& ^% ?* Q4 @+ s3 Z5 J3 |
}
* [* u5 T+ M7 O/ F" e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 _0 ^5 j2 i# H. l2 R. L* v" H" f: t
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