MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
! z7 d( p2 U3 T1 t/ Minput mcasp_ahclkx,
7 D) A" `% X% ]- u) dinput mcasp_aclkx,
- y& ]9 P5 O8 Qinput axr0,
; Q& X' N* n8 {1 o' O$ q
, v( N" ~" p8 u4 uoutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
) K7 g3 ]2 R* Q; c: b

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
1 q1 n1 {/ v; C% ~" P5 A- M! Bassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
6 E. G9 [# [8 A1 n# m{
) X4 ~# Y7 A$ f3 g# H# w9 g( b+ t9 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 X/ D0 Z; \, b2 O& H, j9 ]McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
4 Q. m7 ], R+ }& ~0 g& x7 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
( d1 |* _$ m$ f% j1 z$ a  PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
1 C8 r: j5 @9 l! g+ W0 [4 EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* n, S+ _5 @% n+ R4 s% mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! m2 E8 Q9 P0 H9 h8 z' TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ S) Y( E3 A! m* E4 Q1 j- cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 J* D, D5 B* t, a$ t  cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 T& K8 _( f. s0 Q; [0x00, 0xFF);

/* configure the clock for transmitter */
5 d1 k# c$ m& `7 K) l. [: C9 L: hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 i0 S; @, x& h9 g% D+ K2 Q& c6 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 Z1 I2 c. U$ Q7 e0x00, 0xFF);
, E6 M# s( q- v$ s9 A( |8 b$ ^
1 O; C9 _( D1 N: u/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
: _: J9 O7 A, x/ r0 _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% Z! |  s) ~- }# v# h% t& l4 v1 xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
) ?# I0 C/ ~5 Z9 O4 V% u8 O2 g** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
* l/ E9 B5 h$ P* qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& l+ }# n4 E% M5 O5 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
$ D; a/ c, ]6 T; c** Output - Serializer Tx is connected to the input of the codec
*/
& ~- O( |7 r: ^6 e7 A( TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
3 d+ r$ g+ y4 F: d" k| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 x9 {6 W9 h- o* Q6 b$ b* P( F| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
& S* H- E% l. n& a) N- || MCASP_RX_SYNCERROR
4 V  }8 q- Z  b| MCASP_RX_OVERRUN);
3 T1 A) R/ C% h  e# c}

static void I2SDataTxRxActivate(void)
7 F) k* n: f* R4 B( R- ~{
. }4 n. N2 `, f0 v2 e8 `1 u/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
9 _3 a: [+ K% X6 e1 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; V  ~. A  b; Q4 d. Q* U1 H# ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
: _" w+ Z: ?" k7 W4 p0 Y+ |/ uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
$ O+ K6 |/ S/ o& H/ |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 M* r  `% J' A1 H3 rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; q0 v& w" {+ ^7 |/ r, A0 w* {" j}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.