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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" }$ }+ m2 }# s( ?' Pinput mcasp_ahclkx,
9 P+ x# Y2 Q0 p2 D8 \* V! y4 ninput mcasp_aclkx,, ~. p* P5 i& R0 @
input axr0,
! T/ v' _; N+ A# H# J- V/ P/ c5 G" N7 x
output mcasp_afsr,
5 J, h8 Z5 O# doutput mcasp_ahclkr,
5 j! c6 l# L% J, X# koutput mcasp_aclkr,
5 W9 H4 I3 M& `; houtput axr1,1 k8 c! m: p5 e) D
assign mcasp_afsr = mcasp_afsx;/ m8 E% Y5 \( S# w
assign mcasp_aclkr = mcasp_aclkx;- K- a3 Q/ V& \& m0 O7 W$ j9 j
assign mcasp_ahclkr = mcasp_ahclkx;
. b1 n# @: l, P9 Qassign axr1 = axr0; 9 \* c/ T0 ^$ y9 i
1 i( N0 f8 j4 F' O3 n* j J5 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* C4 _ f+ y! ~1 Z/ tstatic void McASPI2SConfigure(void)1 f; a. T8 J1 }9 N
{
) u$ V% G: ^; I2 m( ]+ X8 m3 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: Q/ }6 r [3 _+ c { Z' q5 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 L0 a$ x7 L% H# L: |- \/ C; z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" [( R/ t/ p! xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# S% ^$ a/ R5 z0 g3 v+ k6 Z5 c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 S7 O0 T- E+ v( o9 ~7 l" B3 k& VMCASP_RX_MODE_DMA);: a) A8 o6 Q, p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! X. ^) |" p4 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# c1 P( t l3 I5 m: v. x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 ]( F: }3 G! R/ r8 b2 X: l6 [( {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 z2 i; B8 e( W0 [% B: T- _& W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. a6 r- A! t! d/ v( QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 E( v4 ]' R/ W7 s. xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! c% R- ]) Y0 _6 A; @3 O6 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 T' b x3 y- I) k4 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ u" |$ R5 M5 X3 b2 b) g
0x00, 0xFF); /* configure the clock for transmitter */
# E2 u! [0 b9 A: E3 r. ?8 MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- U: Z2 F0 A7 q3 j& a- {) e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , ~, n& t: e8 E# [9 g7 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% g: }; L2 ^9 i. F3 |, C6 o" V7 {
0x00, 0xFF);7 t+ _: b0 c+ Y4 f
# X$ x' G7 V* P4 i/* Enable synchronization of RX and TX sections */
- C9 [0 ?2 {$ {: g2 N6 v1 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 z! W# N, F* V( Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ f+ `7 c# i6 W" k) V) D, BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 |5 A, n: c/ x3 c
** Set the serializers, Currently only one serializer is set as4 t7 K" G2 V$ C: [! F
** transmitter and one serializer as receiver.5 {6 V3 ~" I1 S$ G: b* j& R
*/: a1 Q( M8 h/ X: } I( N+ s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' U! a$ F4 i5 K# IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 E. k3 X) m |$ F% k** Configure the McASP pins
! E& b: \/ l \ @4 n** Input - Frame Sync, Clock and Serializer Rx
+ e3 T8 n# O- g** Output - Serializer Tx is connected to the input of the codec , t8 N9 \! Y2 Y+ }8 g+ C$ R9 ]; n
*/0 E9 U' ~; h9 {8 T" ^7 ` u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ @9 w4 f* M! H$ J6 e2 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: u" @9 I$ \" D3 Y* {8 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ N h/ T. f4 W% [| MCASP_PIN_ACLKX0 a) E1 j3 U6 g, c$ c. X9 ]
| MCASP_PIN_AHCLKX$ L7 f. \) ?# [& P: A* G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 V1 L& y9 L2 J# C3 ^. }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 q2 w u( w# f| MCASP_TX_CLKFAIL
" G( }; F( x; s4 o| MCASP_TX_SYNCERROR* G2 ]: g; p4 q0 L% m$ f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; s, k5 o5 P5 j' H3 N| MCASP_RX_CLKFAIL
9 s! y7 W" V0 |: {6 Q' c' Q| MCASP_RX_SYNCERROR
; k1 d% b$ |& K0 Z' l' d| MCASP_RX_OVERRUN);
& ]# m. \% L9 p" Q} static void I2SDataTxRxActivate(void)% K$ d% Y& u Q
{. X, z$ k" s& x' _$ H7 n
/* Start the clocks */
) N& X" i- i* ?4 m8 c7 T* e+ oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" G1 p$ g1 F, h2 {# e$ oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: @" m% d1 ?& x- S4 J! p4 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ S) }' k4 D$ H( i; P6 L
EDMA3_TRIG_MODE_EVENT);2 w2 n) y# E' c1 u2 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 U; W: p1 b' Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 p; U. B- U! C4 K1 WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# f! q8 K+ P( {+ R9 B( r, V% R. MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. y7 b6 g" k" C, a( d+ X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 a; t) B( d" \) r# bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 P2 d3 Y$ D/ Z5 j. eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: O1 v, T2 F1 _
} 3 Y6 [7 B8 E" A+ c5 l5 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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