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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, t/ }- `- n8 _; p) g$ |* a |input mcasp_ahclkx,
& p5 O: Z& |, O1 j# l* }) d" oinput mcasp_aclkx,3 T1 t/ E) {7 b5 z! T
input axr0,9 V5 I; a( d. X
3 \* _8 z( \: z; z% R/ D' U& [, v/ x
output mcasp_afsr,) o, g0 ?+ V! u$ | M5 h0 E# [* v
output mcasp_ahclkr,0 p' `( r3 L9 k7 V0 d! x
output mcasp_aclkr,
$ \, z) j7 \# ^# j9 Routput axr1,
- s7 d4 ]; g: d$ l assign mcasp_afsr = mcasp_afsx;2 y+ E; Q/ x0 D; \# D' \
assign mcasp_aclkr = mcasp_aclkx;
6 ^2 H) U% S0 @' |9 o% ?1 Hassign mcasp_ahclkr = mcasp_ahclkx;
$ @( n0 D) x1 s0 x- z" xassign axr1 = axr0;
6 r, u! K* |' k \# @2 [( j( [+ W1 Z. p8 Z+ |6 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ ]' u3 z' v9 j/ C8 Zstatic void McASPI2SConfigure(void)
. c, t3 J1 M! z; a{
1 a9 j( T/ X% B+ i! E& U _7 V3 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& A" Y4 G v# g0 }9 L& KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// _" U! Z. |) w2 r% k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 x* W6 j) L& f7 S- |/ T7 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ P" F3 v7 I/ S' h7 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 M+ u* u8 E6 f" eMCASP_RX_MODE_DMA);& u& ~1 |" n r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. n- A* e" R. @! r5 O0 {9 e/ r9 O4 xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ p0 M/ a0 g: z$ IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 a+ _. ]. n/ D) H- e2 k2 S' H! tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); b( {& l/ k7 u, ? A: A: A1 A# Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& V1 s) V# G9 F) zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 }! u% o: j e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; Q% Y7 {2 M$ ?: {5 j1 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 R3 m7 P' D$ d% w. W; j, c q" v0 t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) G% k! L. }: H7 {
0x00, 0xFF); /* configure the clock for transmitter */
1 f: Y7 z+ q8 _# WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 E2 `% t+ E$ r( z5 t1 L% J" {; T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 h$ m$ J" ]. w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( y9 c8 @" r) x' n( ?+ r, i3 i2 Y0x00, 0xFF);0 ?) u1 }7 q6 [% R. U6 M0 V7 z
9 \$ {7 h7 P1 W) c! w- P
/* Enable synchronization of RX and TX sections */
7 I& Q" o% L. Y2 n! u1 M( G8 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 \3 F+ c4 U1 A& T' {- R r$ h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 n9 s- j: P) r- [5 Q+ D$ `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
C: t* J+ Z8 T- l. S** Set the serializers, Currently only one serializer is set as) u% d0 M( c9 ?# d+ v: v
** transmitter and one serializer as receiver.! }' {6 J; a( j- A
*/
! H- N6 l9 P3 q) g. y( U$ yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; X" Q" V, M( o( Y; kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' C/ d/ x& J7 v- F9 H** Configure the McASP pins
) d: }! v4 A$ C" Z' B+ ]5 L** Input - Frame Sync, Clock and Serializer Rx
1 L3 [3 N$ H4 O& K$ [- c** Output - Serializer Tx is connected to the input of the codec
3 d0 m$ L+ B2 n: L*/
4 `" r q* T3 }0 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 s1 u; @( O: d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* l- N, l; p, E/ kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: S) A+ t) x: ~0 D
| MCASP_PIN_ACLKX+ Q! }$ x: U6 r# D" T' \
| MCASP_PIN_AHCLKX1 C, z( |( i' x' w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' x+ T5 g6 L: f4 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& X; O8 C' n. R* T [9 H) r| MCASP_TX_CLKFAIL : V0 [2 F* Q1 L/ f
| MCASP_TX_SYNCERROR
* x, c! H- j, x+ z; h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. L4 ^# g8 b5 |3 S9 U| MCASP_RX_CLKFAIL
8 ?. s/ j1 ~4 n# w| MCASP_RX_SYNCERROR 9 Z2 D" A) T4 `2 l
| MCASP_RX_OVERRUN);4 x2 ]6 @ y' \/ A3 N$ t
} static void I2SDataTxRxActivate(void)
. e# C+ p8 T# C$ s2 h7 Q{
$ l) A+ I$ Q) E8 t) _/* Start the clocks */
5 ` y z: b: p/ @. A$ C! L! {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 F3 t/ Y9 D7 d, e- O5 C( G6 o4 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 L! T' l2 M. N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 t0 D! o+ T1 a+ g: l
EDMA3_TRIG_MODE_EVENT);& k7 M; a. D. c; a/ g6 t2 I+ |9 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, d4 U' B9 i0 f7 P) sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ b/ _- |' s3 A- `! n QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) Y; o8 n) e9 h. H; i2 g! UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: q+ F2 u) d/ d1 D6 u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: e6 C5 r& {, d% {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 s: x! d# r6 w2 _8 g+ xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 b5 t3 P! p" M} , _! V: ?) A+ X' U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; p5 ?& s0 F0 {5 h/ V
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