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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 T J! l8 i) [7 T! G V) m* r
input mcasp_ahclkx,
; B- B1 e* T- u' w2 r- z7 r. n9 |input mcasp_aclkx,
# U8 r1 n3 C! Tinput axr0,
) n% W+ F1 X3 v' g- ~+ f6 H
6 V) A) w0 V9 w; u% n2 G& ioutput mcasp_afsr,, p$ Y/ s0 l( U( |' [* i+ m8 ^: ^
output mcasp_ahclkr,
/ ]' m: k3 \5 Q2 j& x" I* ]output mcasp_aclkr,$ w. w. k1 J( o; D$ v
output axr1,
7 w! h7 {3 t: J7 b' x% N assign mcasp_afsr = mcasp_afsx; P4 s# C* Q+ I
assign mcasp_aclkr = mcasp_aclkx;4 [2 C& h% j, m+ `' q2 x
assign mcasp_ahclkr = mcasp_ahclkx;/ }! t7 r+ l& F; I' A. v
assign axr1 = axr0; 5 A* j+ U+ c7 f& s0 V' A, R0 n6 D: H1 M
- H- f" r6 S9 o0 C2 o: b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : [7 T0 _8 C u
static void McASPI2SConfigure(void): [& X: [4 f6 Y0 |& R, i
{
8 c t) z3 {% W( wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( H/ {$ j' o, e( Z+ QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ q8 k% c7 I1 g) h. `2 I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 M; D/ l. _7 y4 ]. S1 j: X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ a2 s F5 x9 q: |7 v; a6 B: q G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ D; P9 B3 p3 QMCASP_RX_MODE_DMA);
2 @2 N9 T; @7 r3 e0 R5 gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# M2 s9 q' C/ P3 [4 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 V& Z7 |1 `: \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! ]1 L" L: c+ IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, K+ I3 h; T& l* uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 {; g. ^( o3 v# LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 o- M: f7 P U7 B. F$ D9 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. b2 n6 Z S' T3 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( U/ m. ]$ B, k- ]$ t' i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' w+ q. ~$ F! h f
0x00, 0xFF); /* configure the clock for transmitter */
, e1 \% s! D; }; F9 X6 ~) u* M% rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* X) v8 @& ~, A. O2 i p: Y- NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " }- W( A0 |0 ?: z- Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- S9 D) `" z ^: [* g8 f. o4 y0x00, 0xFF);
' ?% k, J9 q1 b: T5 E m1 K8 @7 u b9 a( {) h$ L2 p5 n/ p
/* Enable synchronization of RX and TX sections */
1 @4 ^/ ]9 k5 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ T$ E6 Z% ~& LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( W% ?- s" s0 q6 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, A# J- J! W8 k+ R- `& i' l3 M$ f** Set the serializers, Currently only one serializer is set as
2 J* V' C8 z- O/ [; @/ Z** transmitter and one serializer as receiver.0 J( `% W2 K# i3 }% @5 l" o0 U# C
*/
2 f3 D; L0 Q! F b8 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. W7 C! j0 X7 q; ^. {+ B1 m7 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** S2 s) Q5 j$ d% S
** Configure the McASP pins
9 v- r5 c9 E3 x** Input - Frame Sync, Clock and Serializer Rx3 ?2 A/ y1 k- W; d& N3 k
** Output - Serializer Tx is connected to the input of the codec ; _; ?+ ?! N# x, M: D2 K& N
*/" l+ m) T, H# U1 c2 q5 x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# z1 e4 K; C- Z" \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 \1 {. M. Y4 R# o& @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# p7 R4 M+ o% c; M| MCASP_PIN_ACLKX* l" ?* i8 I1 _3 g: F2 w2 r% H5 A
| MCASP_PIN_AHCLKX4 ]1 C/ G# ]- o! P, Q$ i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 |& _8 G8 u. w. }2 q$ AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % E$ Y1 ], s7 e a+ E
| MCASP_TX_CLKFAIL " }8 j; B2 I3 a9 d" E2 V
| MCASP_TX_SYNCERROR: L/ W- f3 P! p7 S5 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) ^5 n- A! e K5 J
| MCASP_RX_CLKFAIL
_& g b7 K4 x# {+ f+ r6 P| MCASP_RX_SYNCERROR % e* p9 |# l3 { K( a
| MCASP_RX_OVERRUN);/ ?' G# J6 [" h/ U# Z
} static void I2SDataTxRxActivate(void)/ [1 S- ]: p$ A6 d+ a1 B2 ]
{% E$ L7 B7 {- ]3 U1 I, K4 j; h
/* Start the clocks *// `$ Q3 l- }) O$ a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) r Q8 v/ e* F5 H# E9 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// Z$ G! f4 l" f, U6 Q! f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% ^2 o3 \! {" L2 y! M* T- r8 V
EDMA3_TRIG_MODE_EVENT);& ^' q* K; f1 X% L$ b2 K3 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 ~4 G0 ]9 f3 @* ?; p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 E4 \1 }* Q9 H8 `* g- |, mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! E+ _6 G4 {% G" h8 H$ q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 b. n9 H4 C' R. r* G" O- T+ J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. n, y5 h& |( c6 o! aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; H/ H( F4 L, s: OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 E3 X: [0 g# m6 L- ^
}
1 |; X& e2 d" p) [3 \* m6 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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