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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ Y8 w3 l0 A2 x' j" _input mcasp_ahclkx,: t2 G5 u) z* `7 C u. q$ a
input mcasp_aclkx,
& _3 v# Y' w" U5 Z; b* v$ ~input axr0,
p% x4 J, k! n( v% s: g& b+ m0 V- i9 v9 n" }
output mcasp_afsr,
# p* ^$ D5 H1 W# h) q# uoutput mcasp_ahclkr,* v7 v3 ]8 W: y) k& D
output mcasp_aclkr,: r6 ?$ ]1 ]: B$ R; |
output axr1,2 V8 Y* } P* c/ t/ v- C
assign mcasp_afsr = mcasp_afsx;6 K$ _1 w3 ?" T5 G; L+ S
assign mcasp_aclkr = mcasp_aclkx;% i% }4 r K" q, B4 L! f9 S
assign mcasp_ahclkr = mcasp_ahclkx;
, Y; e0 T2 V( n; Y1 F) aassign axr1 = axr0; ! g! l# m- y7 t' E- m* T2 y
5 [8 A0 V+ p. t8 v* c7 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; Z" [) i8 D* Z; M, q2 Wstatic void McASPI2SConfigure(void)8 w4 j8 k, O% d1 ~! M4 K
{1 h: X8 p2 G' J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 K0 I5 S, C$ g; O- G' o: s: ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; T! X% A, g6 H3 T7 H% nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* k; }8 R7 i0 @8 Y: B' [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' |; E2 Q8 S3 mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- b6 w0 J# y: ]+ KMCASP_RX_MODE_DMA);
+ H) B3 x, F' O `+ HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& `' F9 K# R& Y0 h; B3 G0 i) zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# ]: E; {( d) _& _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 Y/ H4 S* w! x$ Z. Y: G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 y- r, k/ z! ?, b. a/ w: WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( [& v$ e! c7 c* n$ w) g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ H4 L: f4 Y# N! A6 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) B8 `1 e, l5 z# P- X6 d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * B1 E* j; d( c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# P$ W0 b3 W0 F& c
0x00, 0xFF); /* configure the clock for transmitter */( ^8 F" q1 V, m( a" W% F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 w q/ ?/ n+ |; |4 m5 i' DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, Z3 D q v8 o* s3 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; g6 e, Z9 a" T/ k' P8 c0x00, 0xFF);
1 j; |- {5 N- X% V& d! E+ I! t6 w) n. w* {( `7 p' v
/* Enable synchronization of RX and TX sections */
' H# } n9 G9 sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, l9 @" v1 z1 r, e2 K4 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ M# L) Q3 W" d0 [ f( o2 N' g# ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( F( {1 D* ~- K+ r/ t; E+ J7 Q
** Set the serializers, Currently only one serializer is set as$ U3 G( B, J( S6 y
** transmitter and one serializer as receiver./ r6 D( ^# j" n8 ^& c" H
*/
1 {/ h+ x3 H- s; I; ~# U2 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% ~4 x8 C: g$ C6 R! n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 }% s* M4 W1 \. o
** Configure the McASP pins
+ x: ?/ `; A! [% p* M** Input - Frame Sync, Clock and Serializer Rx" _& m) Q* ]! \) }# |! y B' `/ S
** Output - Serializer Tx is connected to the input of the codec
7 d' [9 T( \2 J+ `' H5 h*/6 J; r U |$ \: V/ r" }# Z/ ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 l; i8 h) C2 D% O. u# PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% v- f' d6 a* \) S0 B. l2 YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* x/ d& i( C% C# k* R# _
| MCASP_PIN_ACLKX
: i) i+ v2 s4 k& Y3 }0 {| MCASP_PIN_AHCLKX
8 x4 I/ j4 `2 k* S- n9 @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% i" d/ d3 i0 f8 d) A4 CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* F4 `% |+ @* ]3 M7 O| MCASP_TX_CLKFAIL
' m/ i$ v+ E+ z% f' j| MCASP_TX_SYNCERROR) j7 @& j$ P4 D* m2 C ^1 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 g6 }" [# o2 c0 @| MCASP_RX_CLKFAIL
0 N; w. W) w6 v| MCASP_RX_SYNCERROR
- A; a, z* b7 c; B| MCASP_RX_OVERRUN);( f( |/ G9 S0 ]% W: r; h
} static void I2SDataTxRxActivate(void) m) ?. \- U/ ?( ^! ]
{% c; u5 c: A8 @% P7 d, W
/* Start the clocks */
% A6 Q2 Q+ [' vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% W# z# |! O) f; @. ]: R' e8 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 Q" c3 o8 K7 t1 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 C- I- x' [1 t! v lEDMA3_TRIG_MODE_EVENT);# s, h9 y, K* }) f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! F" H' s/ G2 x) m% iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 G2 E* a' f. x: hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ I; I2 z( B& J* i* p0 [' X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, x! o: W1 S7 nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 Z1 O, K, [7 X. ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* ^2 M. `* c* d- g7 f- fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 m( I) _8 K& F! d) ]
} # L0 R" \5 U0 [0 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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