|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 ^% _/ ~/ l9 m( |2 A* ~input mcasp_ahclkx,. ~1 o6 B3 w K' n+ Y! m0 U
input mcasp_aclkx,
! _6 H* y1 Y! w5 T. d' x; `input axr0,
6 s' m/ q+ F. M. k4 ^+ B- l, i) O+ k
output mcasp_afsr,
2 ~6 b! u$ n# W, n% D3 m, youtput mcasp_ahclkr,& D5 q; O9 |# e. ^0 _: j
output mcasp_aclkr,! \2 g1 y7 L& {3 r: Q" | y
output axr1,1 a% Z/ O* { @+ m: L6 |
assign mcasp_afsr = mcasp_afsx;
$ n6 H# X; C7 ?% W' ~assign mcasp_aclkr = mcasp_aclkx;
2 j2 v3 Z- Z. F3 xassign mcasp_ahclkr = mcasp_ahclkx;
9 W3 e( _$ x# f) u" passign axr1 = axr0; 0 L2 u5 Z5 B. n! e8 k' V8 _
7 T b' f$ O- M( @, r+ x. u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # r/ ?+ p" E" w5 O
static void McASPI2SConfigure(void)# Y' F5 g1 S# K" E# ^
{* }( u5 e. |/ Z% j0 U3 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ o2 T' P, R" Y/ s3 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; w/ K, h( t6 S5 ~3 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 S4 a. ~" j7 P% Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* r: ~2 A" g' ]& lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& r3 U5 X: z& h1 M
MCASP_RX_MODE_DMA);
# P: n1 |* F. ~9 U2 }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' f: x' R' a4 Y0 W# G8 yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. u' n4 `& S8 g' ^* e2 N3 [ GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 i6 d' G4 j0 p4 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 j' ~$ z; P% O2 P5 F! yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 M0 @" P4 Q8 U. D& W8 f, LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 K- X; `. W8 [- y. o3 C' j" [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 Q7 K' G& Y9 _* t) e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( C# P' f* l( e( c/ H8 z7 B7 t+ k3 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! _4 M0 u0 `& D/ y- v
0x00, 0xFF); /* configure the clock for transmitter */
: Z7 E$ S! ?1 z. e5 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( D1 F- Q- ]5 w! G4 g8 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % K2 r9 Y$ l6 R" Q- x A6 C4 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," S( z1 k) I- O: j
0x00, 0xFF);
2 o4 E6 y I% z" m5 ~+ i
, B; t; K7 |* M1 f2 H/* Enable synchronization of RX and TX sections */ 9 Z! a$ \# q( \9 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( j4 H8 @2 g8 N) _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& ], L: O! O2 J" L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 U {7 |/ f+ S* Z3 D. `9 X3 ~8 z
** Set the serializers, Currently only one serializer is set as
& z; h9 i5 [. E- g! B** transmitter and one serializer as receiver.
/ _( ^6 s$ {7 o# Q: y8 @2 m& b*/
8 S2 e8 O+ [0 G. p B( H! v' WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# @7 G7 d0 D x+ k1 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* u( W, Q; o6 L0 q
** Configure the McASP pins + B; \7 `' z+ f, c4 Y; ], e( p
** Input - Frame Sync, Clock and Serializer Rx
! g6 `& s4 I. Z9 a% J% E3 [** Output - Serializer Tx is connected to the input of the codec
* `1 l' d) |; x2 Z, C- R# `*/, E* t; f) s7 i3 Y- W( Z; J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 J% m8 x7 \% s3 T {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" E. [2 G6 c8 q) b% ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 C' p1 K3 o$ a9 L| MCASP_PIN_ACLKX
% _2 M8 W" t0 z- L( s' ^9 G9 P G| MCASP_PIN_AHCLKX
2 ^3 @- w6 `: A# S8 b7 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" ~5 D: A1 G1 H! _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 T/ q1 x+ O( F$ F1 Q+ K; T' a* S| MCASP_TX_CLKFAIL + v, @) ~9 W* s8 A
| MCASP_TX_SYNCERROR! g! u& Q- G9 Y$ V( {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : D& A$ @5 [. f8 |" f5 J. I4 ^5 E
| MCASP_RX_CLKFAIL
& v( g1 O; ?7 Q- J2 b `5 D| MCASP_RX_SYNCERROR
: }7 m; ?5 Q' K5 F: v8 U| MCASP_RX_OVERRUN);/ w4 r- P z: y" d9 d4 ~1 k$ {9 j
} static void I2SDataTxRxActivate(void)
7 o7 z, K" `1 q! _/ V8 m- o0 T{
$ L8 c1 q( b) E" a; ~- D/* Start the clocks */5 a- \. P& e$ }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
P7 n1 u% _+ p" N3 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 p4 B) i* K; s9 k. ]- @2 Y8 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 e, y6 J& q( n" d% s6 c
EDMA3_TRIG_MODE_EVENT);, F9 ?) t7 t$ E( ]/ y4 h Y- W5 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 C; u. K! O5 t+ n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) `. ]: f6 l9 F3 HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- {4 y; Y8 b, P9 s% b: |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& W0 G2 Q2 Z: r; r( y1 J: \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# z V- M# g8 B/ h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, m% W, i# Y( |7 K! B, @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" P: @3 _: O, E+ o/ d% M @} * H. q" Q& @3 s. g/ j F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
2 X+ F3 A" t/ M% ^4 _" k0 { |