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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ Q8 ]5 U+ b: \2 Q7 I8 X
input mcasp_ahclkx,
) W+ H1 a0 s' ^4 }/ |$ a4 N3 Hinput mcasp_aclkx, c/ ?1 ^7 v) ?. E4 {: m
input axr0,, h" r7 @# M( l1 z5 b5 j( K
; w" k6 e" g/ k9 o: \output mcasp_afsr,
% Y- V; ` r l! ooutput mcasp_ahclkr,
% C7 k/ B7 @! t5 }0 N1 x3 Y8 Houtput mcasp_aclkr,
$ p- Y- D. l4 u3 o0 ?5 i9 A: _" boutput axr1,
8 l# V" U m8 t' s1 |1 o& u5 W: a! d assign mcasp_afsr = mcasp_afsx;
$ s0 ^- u- ~- E$ C- N* cassign mcasp_aclkr = mcasp_aclkx;
- u! t8 e0 P4 j$ T9 Q* L4 Passign mcasp_ahclkr = mcasp_ahclkx;) C0 a9 f; o. p5 h! G, D
assign axr1 = axr0;
" u/ I: V7 Y; U2 Z. s; b5 F$ [/ X% O/ \/ U& F% R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 n8 T& a: Y" S* X mstatic void McASPI2SConfigure(void)) ? v7 a- S6 R4 f6 b* J
{' l/ m5 w6 t) K- X' G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- ]/ R- o6 [2 p9 A ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 O& n- T8 `# A+ n: Y9 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& q7 z8 N7 A* ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# A* \5 F. b; l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& f- J( d% T+ b( Y: |% M- gMCASP_RX_MODE_DMA);8 t% X# k0 P% u! m* z4 |7 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% l0 R: x; B: T7 M+ \) X5 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' R) x, ^1 v& y& b4 P4 f* U( z( }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 b5 q0 p& v) {3 W+ {3 b6 k& ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 c6 Z+ d; Q* {. C4 G' r# C+ L* o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 P# S7 \% y1 Z$ }' m. |% H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; ^8 e; \2 D2 [ g6 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! G. u: a8 k9 K4 M, S3 x( m* r' P4 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; z0 W2 _$ a, t7 V* m+ o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ S3 }- T$ W+ A; F7 p% N0 q' W% b0x00, 0xFF); /* configure the clock for transmitter */& n$ K+ g9 m- Z: F7 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' f) s9 E0 b$ p* ~0 G8 s8 n. eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! A2 O! @$ x9 F: |6 g: _9 _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 h, b2 R$ b) H7 V; K4 Z0x00, 0xFF);. D+ M% n; h) U2 s
5 Q% n( Q& W* A2 T# r& c( ]) L
/* Enable synchronization of RX and TX sections */ 0 H) h: S1 @1 H# ~( D' L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' E$ r, ?" j! M& U) qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 S8 V& J9 N* y6 [8 d- _* G. mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- u/ D+ P/ P+ [% O- P' J
** Set the serializers, Currently only one serializer is set as @9 w, b6 N+ |. f+ Q3 H
** transmitter and one serializer as receiver.
# }! c' g9 I( ~+ k |( P9 e*/7 Q# S% s1 h( d) f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 k% u g# J1 p" TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 U/ T/ n X3 I6 o' S# G3 s
** Configure the McASP pins 9 y. j0 Y0 L$ b
** Input - Frame Sync, Clock and Serializer Rx: Q; r. }0 X( q0 P" u
** Output - Serializer Tx is connected to the input of the codec ) j! v9 A+ G- v
*/
3 _; L* C- X: t. a7 z0 }) K& g6 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 \6 v& d5 Y! ^. P: ?- s9 }9 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 G; {4 n9 l8 Y) u/ y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 D7 K* B. {6 G% [0 |7 l| MCASP_PIN_ACLKX( b7 d7 o- c. F5 \
| MCASP_PIN_AHCLKX$ u" \" @/ g0 I! Y. g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 q3 H! `+ O) @5 p* |8 V7 R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : d0 c& G1 C& B% b+ S
| MCASP_TX_CLKFAIL " B, G( c1 M4 G1 Y- @& F
| MCASP_TX_SYNCERROR
4 t7 X' q) A/ a) e7 D( A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " J0 J9 n C' y. \. O# U
| MCASP_RX_CLKFAIL
/ `0 i7 Z- p$ F3 X# O8 O| MCASP_RX_SYNCERROR
! n) a8 G/ S7 ?6 T$ j| MCASP_RX_OVERRUN);
/ {. Y* {4 ^* R+ J} static void I2SDataTxRxActivate(void)5 l3 Z7 @$ U+ V7 g& e5 j( Q1 z
{* v- d p# i6 ?7 \- e/ a
/* Start the clocks */; U- G: i0 ~. X ^# F: o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& u, H1 J o5 hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- n. B% S9 x" u3 o- o' \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' g6 v6 U# |9 h, [0 W, \/ \& b+ c/ DEDMA3_TRIG_MODE_EVENT);+ W7 C- C0 C' m K2 M% I8 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 c% H) _2 M* z* ]( k& r T+ S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
K. t* ? R# |. S; d9 Z6 P+ P" JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 t" Y2 p v" q! cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- u7 e0 Y! n2 Y2 R+ T/ mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) Z4 H/ W' q1 D( g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, e6 l: {. u# T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 f, X: o6 B5 F6 Q6 L
}
" T% D1 F& F9 s) B( O7 L9 w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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