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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- ?/ `% g$ S' w: o# u7 C6 cinput mcasp_ahclkx,
4 z8 B1 \# L8 P9 `! m# ~; ]6 ^; Linput mcasp_aclkx, k+ [+ u" @# M7 Y
input axr0,
( O7 v& d4 w M# x9 o p! ~" ~% [3 l5 C' d1 K
output mcasp_afsr,8 N& H9 x S9 ~8 A- t: M5 l
output mcasp_ahclkr,
2 N* K+ Z) _# c( S( k' s3 Coutput mcasp_aclkr,
) O7 P3 G7 D' R# u' \8 E, ?2 V1 woutput axr1,
/ X5 d: k9 X5 c: N assign mcasp_afsr = mcasp_afsx;
: c+ c! y* C4 Nassign mcasp_aclkr = mcasp_aclkx;0 P+ [5 o2 \0 y( d. P2 k4 W# q6 _, Y
assign mcasp_ahclkr = mcasp_ahclkx;
8 P3 Z* O9 _& O" Rassign axr1 = axr0; : t% j# O7 o* F! I" k) B
5 Q; L8 B6 M1 ]2 z6 s- i# l; ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 u3 u1 i; W0 r: t: p# o
static void McASPI2SConfigure(void)
0 L( m- K `2 l, A( b2 B{
* S% [$ r6 {; S% N/ t2 @9 k; Y2 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- I7 f) r6 e9 J9 U" h6 _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 Y* E) u: v7 k8 ~( D/ c/ K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 y3 }, V0 P$ D" \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; [) A9 U4 o0 a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) K; I5 M# w( B& n/ W6 ` W
MCASP_RX_MODE_DMA);/ G6 s0 H; p6 \ M V4 [1 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ l& c B* p& e% r5 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ R' B: i( F* }- w% z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 e9 y x7 x8 B4 l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. }3 t0 c u5 O TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! ]; ]+ C" f$ p$ t0 Z5 x5 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 Z) n+ X7 [2 s4 U& k" t& a* ^* HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 V2 ]+ i' d* [2 y+ r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 U* b5 M, Z! t! X* zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 @* G" g: D _. Q) ^0x00, 0xFF); /* configure the clock for transmitter */& F' G8 A) p" h. {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# }! Q+ k) P$ q2 o: LMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 R4 O- t6 P; ^5 x6 w1 H; PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 U1 t( m, O4 D) }6 I0x00, 0xFF);/ `8 n7 c' ^: F# n$ f, y
7 w# u, n7 X3 y0 @/* Enable synchronization of RX and TX sections */
- z6 a w/ j h& rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* G' O; C2 A8 R9 W, P7 w4 I( |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: d3 a, @7 @% e% b U! `( U' A) ?& }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 s: [" D) i: g% X& [; j** Set the serializers, Currently only one serializer is set as
, z9 Y' H$ O) i9 O3 S** transmitter and one serializer as receiver.8 C! u6 v% E0 Z( s+ \8 ~, i% l, Z$ o
*/# t' N/ T$ F2 M5 d" R% \; c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 ]# X+ H% K" ]5 z1 aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 y/ D+ T9 Z5 q
** Configure the McASP pins
$ U C% Q5 c/ ]! C** Input - Frame Sync, Clock and Serializer Rx
- M% |' Q! p! @0 l9 D** Output - Serializer Tx is connected to the input of the codec
: F3 k0 x( _5 Q0 `*/
! X0 h! u8 T3 A. fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ O- d* p# A+ C4 b: J' k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' [3 b* c& Q- ~: mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 a- E( a' x1 V. \' v5 m, g| MCASP_PIN_ACLKX
$ y* q2 c. ~4 j i& C' T1 E/ K| MCASP_PIN_AHCLKX% L' }; A9 J, L6 q' ]* m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 ~! v& M6 ?% h& r3 m# t# B( g5 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; b( P& Z; k t( M6 \
| MCASP_TX_CLKFAIL " C* `6 `: B6 W+ R) h% S
| MCASP_TX_SYNCERROR& _( \/ W& P: E9 u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 i% ~, N% `# T% [1 G$ |/ P2 l& U
| MCASP_RX_CLKFAIL
' [1 m( \# r1 L. Q% L3 Q| MCASP_RX_SYNCERROR
$ Q. C6 d1 j7 i) A5 A6 t s2 Y| MCASP_RX_OVERRUN);
3 Q2 D9 k0 m& q- ]2 _} static void I2SDataTxRxActivate(void): A3 t b3 y3 _# F
{
9 ]( `* H- L G& Y6 g) d3 s6 U/* Start the clocks */ W- f2 F2 U& P1 r0 O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 C; o/ H7 J, y% b5 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 V9 M2 X/ y' p5 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% E5 O& Q2 c8 V- s$ ]7 o
EDMA3_TRIG_MODE_EVENT);9 l) R' X1 G7 K: o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 x' Z6 J) r( w; K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& H& j2 n j# }6 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! V' Y! ^ Y5 S3 e7 D; T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 u+ m) ~' c' V. i8 X1 hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 d h$ G; I$ H5 x' k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 v! Y% a- l5 Q# c0 x; hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. q! v* e' B a* G' ]0 d- v
}
; F( I' P! t$ y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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