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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( b/ T1 n* U* \! Kinput mcasp_ahclkx,
5 f" P/ `5 {8 D! ^, {9 Yinput mcasp_aclkx,
9 J8 m' t. [3 g# Z$ o0 B; Dinput axr0,
( T! |6 [( K5 {) T. r1 g
% G2 e2 d" ^4 K% ~9 W: ~output mcasp_afsr,
6 U2 C$ ^; \/ S. voutput mcasp_ahclkr,
1 s* b, A. J( Joutput mcasp_aclkr,) i' F$ z+ J* D& m. c# M
output axr1,* |5 @, J! v$ {/ I
assign mcasp_afsr = mcasp_afsx;
" C* D* ^1 ]( i* B6 D, \assign mcasp_aclkr = mcasp_aclkx;
( j/ Z" O, z6 F8 D) o$ q8 w+ w" Hassign mcasp_ahclkr = mcasp_ahclkx;; R+ d- `: g7 I, L6 G
assign axr1 = axr0;
( w, H# m6 U' j2 O( s
0 m9 ?# b; N9 s$ y. X2 ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 E' j( r1 i! m, K
static void McASPI2SConfigure(void)$ z$ P3 ?8 b2 P) f
{% K" K& I" W% o; I9 V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 }/ S& ] Q4 z3 \/ G, `# ~6 [+ aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) ^% J: }: ]& T8 {( |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 a# q- a$ O% V5 \, bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! ]. o% \( \: b2 ~3 c+ ]) n( o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- n% L& v1 [" f( fMCASP_RX_MODE_DMA);% H4 p! n5 S4 z+ Z5 J; k* w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 H8 H& @5 G; W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 v$ w3 k9 C, S N/ e% E' I3 f/ m7 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 E! F" A4 c% rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 @$ _7 Q& V6 r F5 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 `8 T: ]9 v! B1 H6 v# VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# n% T1 _ s5 Y- j( \5 W: o* n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 E+ V C; b' A h$ [6 @* v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 l& W+ K! n; M& HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 g1 G* @5 q9 o! U; W* }
0x00, 0xFF); /* configure the clock for transmitter */4 @1 l4 R" q2 B% b" w6 a ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& N: w: c+ d; BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , H7 |) b6 q" r# L0 R0 {6 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& {, S8 F, U' b# O6 O2 {0x00, 0xFF);
0 R0 m" Q8 @8 b) a( }2 a! [* H2 c1 h% Z: o5 x4 \! N( N
/* Enable synchronization of RX and TX sections */
. ^8 X& \9 N# H3 ~+ `8 e4 E8 ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* z9 x P9 J7 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 l: n- ~# s4 l: ]* fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' i$ Z6 u8 ^9 b" ?4 y
** Set the serializers, Currently only one serializer is set as
$ \0 S8 C+ b8 V5 D" c** transmitter and one serializer as receiver.
9 ?# a' B4 S8 P*/
! L5 r4 W$ z/ U; J7 G( H3 i- ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 L& t/ U- v2 F' p- u1 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ A; ~8 q+ @4 a- A2 G
** Configure the McASP pins
1 ~2 @- V# _+ V2 ]' e! t; J6 B$ B7 @** Input - Frame Sync, Clock and Serializer Rx' E5 J1 u: k# R4 @/ Y
** Output - Serializer Tx is connected to the input of the codec
1 f% W4 }% @) c% X$ I*/
( s0 R$ T K( \5 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" r. P0 @8 W- h; C _" |! U+ ]3 J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* o" K8 b" j" G5 s) ]1 D$ JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 H- q" ~, F1 s+ p" i
| MCASP_PIN_ACLKX
# u; Q/ V1 W7 I. S; n/ W| MCASP_PIN_AHCLKX
2 r' L2 J$ m% g2 y" b; e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 e& Y" q) y& I6 |" g$ k7 VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 i1 @: K( c$ L| MCASP_TX_CLKFAIL
* D' i9 x) L0 P- ?! A, S! K7 n| MCASP_TX_SYNCERROR
. e8 P4 x/ P+ y, N: T) D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ ~" A7 _6 G5 H) E' r| MCASP_RX_CLKFAIL
% D; M& k9 l& ^9 K, f| MCASP_RX_SYNCERROR 9 O; R! x: W5 W1 r% ]% H! ?3 p- J
| MCASP_RX_OVERRUN);( ]+ c& o2 B. p
} static void I2SDataTxRxActivate(void)
7 q% T" i7 z% X' |{
& g6 L0 e# F: {/* Start the clocks */
?# s& e* [8 ?3 K) Y! I; A6 tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 h: J @$ v) T F% `9 N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# k6 I) Y. X1 t6 `1 t4 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 i( r# o$ Q4 H; O/ q$ o) \( K: GEDMA3_TRIG_MODE_EVENT);8 b5 n* Z, X2 L& y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 R: v V {3 Z5 c8 X0 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! c3 h, T8 G) A: K; l, f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
d8 x1 L/ A X1 A+ nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 U. q% R, e+ d9 t1 O$ q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; f% i# w# ~$ w. i% mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 K" a2 Y; \( X; z# ~4 o, b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 o* x9 \8 Y) V. M}
$ Y3 m2 O$ p2 @ v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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