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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. o5 g4 h ^- Q$ g5 ?" X
input mcasp_ahclkx,* R: k+ \$ r! S1 Q; |3 R
input mcasp_aclkx,
0 j# }1 g5 p1 B( qinput axr0,3 e3 \9 J: ~8 x$ j8 U/ m
) E8 P1 ~( Q0 r( m# Z- Boutput mcasp_afsr,' O" x7 s' h) P' p P( ?) h
output mcasp_ahclkr," U% ?. N6 P9 s
output mcasp_aclkr,2 b$ |7 I* j& B5 D1 y
output axr1,1 E5 g1 P, C8 ?7 m! b6 X
assign mcasp_afsr = mcasp_afsx;
' v& X/ \- }! Hassign mcasp_aclkr = mcasp_aclkx;
6 c' ^0 T5 a; g( ~assign mcasp_ahclkr = mcasp_ahclkx;6 G' |' x# q2 h) W
assign axr1 = axr0; 5 D) k& M3 K# B$ J$ A
( a6 }" t/ L, i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! g6 P" k6 M( m% O
static void McASPI2SConfigure(void)0 V" Q; g; Q4 l8 \. R# k5 T4 B8 U
{4 v9 o, _! D; Q- ^4 D; Z& K( b$ V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 J: C3 A, i3 }: |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% T- ^9 |2 b; a8 g9 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 w1 e% J8 {! E2 mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ h- E! Q' ~+ I: T. m: {3 Q/ pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; x3 R% ` y# m/ m: N% H- }9 j; f# |
MCASP_RX_MODE_DMA);
) X( s9 R D* V4 _/ EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: [+ K5 m/ ]0 m( G7 g- Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 N. Y* ]. \6 b% d3 _/ IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + p* n- z& n# f# M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% _2 j1 N+ V! a# p: a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + A" _" x9 L/ U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ q9 a5 A7 P- R# \* p8 a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- T$ z# G/ V9 W3 N% S& D$ j, JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 ~* G+ j. N, n) [0 y1 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 y3 c1 z1 t4 L
0x00, 0xFF); /* configure the clock for transmitter */: o9 k, s' a% y( n6 S1 p- E0 A& q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: p$ A- k+ K: x+ s9 j% ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / m+ B' R7 ^, u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 s" [2 F3 L5 C2 _( _" l& |# z0x00, 0xFF);
- l+ [& @3 ~! K3 o
2 k) j3 p( G- Q1 S! C+ R/* Enable synchronization of RX and TX sections */
+ S4 H" \, L. e, ^8 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' X; M$ [" H* I7 ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, Y4 s2 l# m" SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 v" L3 ~; F/ Y' O0 E
** Set the serializers, Currently only one serializer is set as
5 _# r1 T5 M+ A% d0 ^** transmitter and one serializer as receiver.7 s) h( W" i1 p; ]7 V
*/
5 }+ P) b+ g- `" [3 DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% Y' T2 t' u$ K( P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** R+ C" N4 }( M; d
** Configure the McASP pins ! {7 b2 h4 G/ S, {2 u% D* q4 w. Y [
** Input - Frame Sync, Clock and Serializer Rx) \5 L6 E5 t; |0 s$ u5 }
** Output - Serializer Tx is connected to the input of the codec
, H+ n5 q& V4 o! |! i; i*/3 d2 q. [5 q' n8 e! {; ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 J* b7 Y$ w: P. y3 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
o2 V, N" _; d, D" N* a) jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( d/ D* D4 t5 `; V+ F2 R% P* J
| MCASP_PIN_ACLKX
/ {) Q, q1 I1 g% M| MCASP_PIN_AHCLKX
5 b2 |0 o+ M9 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 `" C$ N7 z. n9 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 W- k/ `+ m2 I7 E' F4 L, E" J _
| MCASP_TX_CLKFAIL 5 A' b3 V# b6 S
| MCASP_TX_SYNCERROR& U u0 S) \3 c, ~6 S0 |% w9 ^$ k' q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR J, p7 f+ _0 `2 J# i- n
| MCASP_RX_CLKFAIL
/ W1 g/ d4 ~7 [9 Q2 P| MCASP_RX_SYNCERROR 5 [" G0 K: g8 C3 p$ J0 }' k, e
| MCASP_RX_OVERRUN);! p I# }" Z+ @& B
} static void I2SDataTxRxActivate(void) Q q& O1 K7 t2 B; y
{
0 ~. }# `5 h9 O' K0 ]8 f/* Start the clocks */
/ a- ?8 I" O# fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 T3 B0 g! J2 j; v5 M# a4 C' p. _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' n2 y# `' Q' @- ?9 O/ T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' b$ G4 p* Z/ W& H, b! Z% d, ~
EDMA3_TRIG_MODE_EVENT);" b2 Q# n/ {( W. \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 z+ \) T* M! E- L" ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 o7 U z: g( I% h# _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 e! X9 V7 O5 e4 w! i" l h' x. Q( J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 c& ~ G! d1 t& t, J [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ Q7 j4 |; r: {- x0 V3 T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ u# @3 \" N+ XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; h1 d: F! Y- Z! C% F* E+ w} ! a3 w+ }& l |. }% S' p, U. E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 w; K: y& e* x$ g# p
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