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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 s: x7 u9 [* I" L+ d0 @" {input mcasp_ahclkx,
! u& h' b6 b9 n$ G2 N# sinput mcasp_aclkx,& l6 W$ ^; G+ d7 ?& Q9 M J
input axr0,
4 H9 ^( k' R7 n8 d9 G; N( `* f0 s9 Y7 I$ l6 `4 M) h" Q
output mcasp_afsr,6 o! J2 o7 w, w' }4 c- n8 M
output mcasp_ahclkr,
7 y6 a9 e$ y2 P. H, W7 Ioutput mcasp_aclkr,4 r3 I9 Z" e0 _, D8 R; ]% x/ Y% y. K
output axr1,/ @2 a2 }5 N4 O% N
assign mcasp_afsr = mcasp_afsx;; C' Q! T# m) H& |4 I7 H
assign mcasp_aclkr = mcasp_aclkx;
) |9 u7 y7 F8 ^assign mcasp_ahclkr = mcasp_ahclkx;5 i4 R+ j+ |% E. [/ A( `0 T
assign axr1 = axr0; . f, k8 I: c7 C
! r9 a0 L' R$ ?$ t' T7 r* H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 F) l$ H0 p. Q" E% z8 t6 ?
static void McASPI2SConfigure(void)
+ Y$ x0 ?0 O p5 b; C( ~{
$ m4 D* m4 j# W. n+ k f9 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 M" f6 o( v2 p) _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: `; a8 \) I7 A1 KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 O2 s5 ^ v6 x: i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& n6 h4 {, p2 l& }0 k" @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 Q& ?3 C- t! W$ g: v
MCASP_RX_MODE_DMA);
# ?9 {2 f, t9 E- lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: c/ S. R* Z/ NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. b( Z5 g( U# F* s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
M) q2 U- t8 ~1 z" {; T+ ~3 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( a% o) f0 a. I2 ~- F" x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# O) Z: P/ t3 I% QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
C$ Z) Y/ _2 s7 e; [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 }1 e. w; \9 b0 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); L# }2 l' X- q. F* b8 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# T7 s, b% h& F) `7 p1 \
0x00, 0xFF); /* configure the clock for transmitter */
; F; w0 k$ C8 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& r5 f- F+ m! f' {6 A7 _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' q3 o) ?1 f: u' F! _ v2 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& p; f% K3 K0 K0 D4 f6 ?- h
0x00, 0xFF);/ R5 }5 h! x. G& V6 c6 j& L" A
- \' R! U4 g: D9 y: E/* Enable synchronization of RX and TX sections */
7 H7 p9 k0 i) `2 ^3 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! ]+ F) O* y2 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 V+ p2 H- w5 G; O% ~, v z6 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" o. l, D" _$ ~; ?, J
** Set the serializers, Currently only one serializer is set as
9 a& L$ b8 Y9 q- P. ^3 q) v. f** transmitter and one serializer as receiver.+ p$ @! x: e% a" k2 x& c5 Q6 H, L# K
*/
: m# `; c0 q! x- l# p0 W, fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
U8 ? P l& w/ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( ]5 {9 n% A v* ?: z& G** Configure the McASP pins k) Q% u7 R) A2 u& n: K: g' {3 @
** Input - Frame Sync, Clock and Serializer Rx
$ b; j: X2 t! m' [** Output - Serializer Tx is connected to the input of the codec
7 t7 J1 u. ~& Z$ M2 t; y*/
% T& J8 s& f) l1 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, R! k: ?- s' C9 g1 B, G/ ^1 {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; O' W7 k( |+ ~; R( V4 ~: lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 `% C- ]7 e( v- Q& n( w| MCASP_PIN_ACLKX) u3 h# u9 m. D6 M1 F
| MCASP_PIN_AHCLKX. k& n& S0 o$ b% \ O {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ _+ q r$ z- [1 H! Z# eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( H# D& l. Q6 c. @| MCASP_TX_CLKFAIL
" j% }4 D5 j6 x: K! ^| MCASP_TX_SYNCERROR7 G& W/ I4 z2 Z" e5 L. @( M N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ i+ [9 x9 Y* r( a0 u! {| MCASP_RX_CLKFAIL
& R9 I' ?/ @) b| MCASP_RX_SYNCERROR 9 h5 w' E& L( E+ x9 m( g
| MCASP_RX_OVERRUN);
+ `" k% G7 `( [} static void I2SDataTxRxActivate(void)
5 _" @' Q9 h, t9 K/ }, H4 ?" {{
0 ]/ Q1 p5 x9 m, i8 D0 M& h/* Start the clocks */
+ ?/ y. k3 s* r3 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ n7 F. C, m9 ?8 R4 f. XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// F n& R8 J. I# k/ O( R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 _% b" p3 I! l& I1 Z( `" K: V2 AEDMA3_TRIG_MODE_EVENT);
' j! Z4 S/ f, `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% G- Q! a. T! cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 x; D) ^9 v, i0 W/ q; n& O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); f9 ?3 p p( w. ~; f$ Z- o0 o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# g; K8 Q3 Q0 q8 |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ X/ c4 Z' Y# V% ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 L& [6 F2 U( O. F I# @* X' EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( ?# f% M+ L0 l) _$ d" x) V} & V' v* T+ J/ y$ p5 `6 e$ H+ N4 y& V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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