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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 x1 P+ u8 O; X4 f& r& N8 N
input mcasp_ahclkx,
+ k! k) U. p) O \0 tinput mcasp_aclkx,
$ g1 W7 E4 p/ M2 \. ?! vinput axr0," X+ v7 W4 c, T
+ B) u: {% v" w4 G
output mcasp_afsr,
# O( G7 M% U2 z( ~6 ioutput mcasp_ahclkr,. P& O/ Z: `8 @/ H' O
output mcasp_aclkr,6 \% m6 g/ W+ a I' @& g
output axr1,# p# q* ^& M5 t G+ }
assign mcasp_afsr = mcasp_afsx;
+ p2 B. a' z3 m6 r' k$ Cassign mcasp_aclkr = mcasp_aclkx;
% V1 r* b( g; A8 h+ B" Kassign mcasp_ahclkr = mcasp_ahclkx;
0 R' ]' [( n+ g6 x% N3 gassign axr1 = axr0; , t, r" c8 @+ s/ A
% `$ [0 U- Q# V" t g8 c' D' Z- C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
q; C: J" @7 Y, r; a6 t- a6 D: Astatic void McASPI2SConfigure(void)
- u! I$ j: w$ A7 }" o& A/ u* x- [{; N; y* V4 f( \0 O9 `! Z/ g8 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; G$ |' ~% k' B3 V% SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' a, M1 w1 B/ _- X1 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% w8 j% R' F" Z+ j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ q" k" C9 U. v" R! M) [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% y+ e" ^9 G+ [/ e/ o! _6 q$ lMCASP_RX_MODE_DMA);) H0 ~4 |3 R J- G. W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ C5 W7 I. F7 v& yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 y' X8 Z9 s9 @! \2 {9 S" n+ EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * v& F0 L7 Z: B3 x# ~; Z8 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( I% O3 o3 |' x. ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% X, k4 Z, T% X7 ^. hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* w4 P, q3 D( f6 F7 P$ [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, d' V n u; `) y: m! j( g0 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 w8 e$ }9 `3 D' w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: I1 d+ P3 a. g! `% j2 ?: _4 h, _$ y0x00, 0xFF); /* configure the clock for transmitter */5 G/ J$ g$ ~4 l# J3 S2 R. D$ E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% A% S, ?/ y' ^! R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); x" q& Y2 K% L5 {9 G. L& v7 q0 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- j: w# l# j6 f) F
0x00, 0xFF);
( l7 u; K/ A) y- F* L" v. I1 [: m% _9 i, L- ^9 K
/* Enable synchronization of RX and TX sections */ ' c& K% E9 k$ N! F. S$ a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, M0 \; ^9 P) O* n4 y% [0 sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* t( t& S2 m/ j! m- S" x+ g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** p. z4 b" x- d
** Set the serializers, Currently only one serializer is set as
/ @- q+ _: D9 U/ q** transmitter and one serializer as receiver.# o1 J5 o! ]1 B) [) @) w
*/8 X# ~ r) K O$ d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ L+ w" m4 g5 f& S( q8 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" S; g, s `! e* B3 @! v2 {
** Configure the McASP pins
- \" `9 }/ v8 o# @) ^, N** Input - Frame Sync, Clock and Serializer Rx0 f* | v, u( @$ h; Q
** Output - Serializer Tx is connected to the input of the codec
# ^3 L+ x0 p0 G$ v" S*/" @( i) O' R: i% t1 P! ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 A+ [& f5 j7 E; H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 Q6 Y0 `) @! m) c3 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& w( c2 n2 W" P7 N4 K2 d/ y" d* D| MCASP_PIN_ACLKX
' F4 A0 n @8 g- S6 R2 x| MCASP_PIN_AHCLKX* f! }3 z( V T) o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 A2 z5 f B7 N9 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( Z' W# @; h W3 D: \9 u: w7 x* X| MCASP_TX_CLKFAIL ! |( B$ G6 K4 q( \! J
| MCASP_TX_SYNCERROR
% a' B, F" J. {' t7 w; ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) q, w* A) Q6 }" I9 j+ z$ j; Q| MCASP_RX_CLKFAIL; b* }) e4 T- s I' O5 w9 J
| MCASP_RX_SYNCERROR
$ d7 W# p' x5 m. e4 M| MCASP_RX_OVERRUN);
' R; K. H1 g; c' e5 U} static void I2SDataTxRxActivate(void)0 x" }% j2 ~+ `9 Y F4 q8 T/ {
{
/ o1 p( R3 m* v, I/ }/* Start the clocks */
4 V1 T2 ~% z# Q2 m9 O: DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# R2 y" h J/ G1 X; ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& M; u) \) C+ a! c# T) Y1 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- b* v& c2 ~1 AEDMA3_TRIG_MODE_EVENT);6 ^8 d# q( s- G# U ^5 u- z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" ?4 c/ o6 c% S1 | m1 w" M X; ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 E) L' B# K. ?: PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# i% [3 h& x% `* j. x, v( D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. V6 }/ f. b. {5 Z' i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! f/ l8 N! s/ @3 ]8 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( q4 H- z+ I7 [+ k3 i9 P+ rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( o! ]2 U7 w$ E}
, Y7 D; w% Q, p+ Z8 J3 ]& z- u; q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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