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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ D) }+ U9 ~0 K! v. T$ U9 {input mcasp_ahclkx,
7 m' c0 P& y: o7 Finput mcasp_aclkx,: }% S0 ]( E) z `4 U
input axr0," q; }( k9 B8 ?2 {) W
. N% x5 ?4 f' A/ ?3 Voutput mcasp_afsr,2 { A3 N2 ~4 w1 ?
output mcasp_ahclkr,$ K/ Q, b8 h6 O9 s( V0 u" l+ l
output mcasp_aclkr,, Y7 i+ ^ z3 U+ n
output axr1,( p* ~) p- I m; O
assign mcasp_afsr = mcasp_afsx;
' `# |- T" @ Y! [assign mcasp_aclkr = mcasp_aclkx;1 ^+ E! W* k# O( c( ^
assign mcasp_ahclkr = mcasp_ahclkx;" ^/ T$ {1 ?- a' r
assign axr1 = axr0; % _) y& K# d& O( L
% q p0 v+ j, _- ]3 ]7 C! E9 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ W; O: j$ K& l4 Z& jstatic void McASPI2SConfigure(void)
3 \- u! D# \( ]; R/ r1 y* Z{ \( R& G0 v! p! q: P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: d3 p5 T, I% m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. M4 u& j8 t% A" l o' s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, D0 d/ |0 s: r) y0 H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# Q5 S7 n2 R! }# |+ s: \ XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 C# |7 f3 a, Q3 u4 t3 rMCASP_RX_MODE_DMA);( e# c% J2 W. x; ~6 Q$ S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ o, J% w* A% s. d/ c* jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( Z+ d2 y! u, E# E8 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . M1 c& F+ X* _% ]8 Q/ r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' w4 L3 v) U* F5 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# G5 A/ @2 D# c+ f$ I; WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 s& S! u: v( S' ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: |5 ]" s4 u R% A+ f2 b* I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # o8 ~: U; y# E* x. D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' ]4 m. U# e4 ?! E0x00, 0xFF); /* configure the clock for transmitter */
% I k! H# G- w! YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- C0 }1 e. p' R6 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* o7 ^4 A) e: J+ G8 L a" p: Q3 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% A3 W I& j( |! o0x00, 0xFF);8 e% T+ q% k9 O8 _$ F }
+ I) U1 D2 ]6 F9 g% Y: l/* Enable synchronization of RX and TX sections */ 6 Y$ z5 [1 q2 b0 `' X6 W! ^) X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 }6 d5 H8 O* hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- A" l7 l H5 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! v8 T1 d6 x3 V( ]** Set the serializers, Currently only one serializer is set as
! S: f. ~# c3 e& B! a# U& v& ?** transmitter and one serializer as receiver.
V/ P: @. k' U# C# Y1 \! Z, i*/
% t' f# R8 L9 ?- D# U" b8 M0 n, AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 G0 a0 g6 s ]5 z$ `5 ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& n: y1 C( W# u( m' K** Configure the McASP pins
7 H* i/ r0 K5 s7 E- D; U: x** Input - Frame Sync, Clock and Serializer Rx
6 S6 [0 |8 q" W( |. a! X** Output - Serializer Tx is connected to the input of the codec . y" J/ `& v8 U7 }: a' b5 n
*/( {/ {" d& A6 J( k. }& R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; L5 S* `6 @- [5 x- ^8 ?9 L- rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. N/ E' M% Z' N/ h# s ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" J. N6 B; D% b; e6 y1 k| MCASP_PIN_ACLKX
1 D" c+ G2 O- @0 V" t' ~; F" z0 u$ M| MCASP_PIN_AHCLKX
, H# m: h4 Q9 O7 {# d7 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. K1 H: [# u( X/ y' mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - h9 b1 X/ o# e
| MCASP_TX_CLKFAIL
& X: ]* s0 U2 f7 G3 j| MCASP_TX_SYNCERROR
3 u6 ~9 w s+ d. F- [# J. B) F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' ?4 {, Q! T- j. D
| MCASP_RX_CLKFAIL
* b* _% }. J# U, K- l! Y2 Y1 P| MCASP_RX_SYNCERROR
, X& n! l f+ Y1 a; \" @/ @| MCASP_RX_OVERRUN);
: B' p5 o4 G9 j! b/ q} static void I2SDataTxRxActivate(void)
" Q7 ^* ^* N* g- T0 P{
3 _# ?) q; y8 ]% Y/* Start the clocks */
( d+ k. z: z+ x" zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 q0 v7 L3 |. m# q- A1 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; w$ P/ O, E/ R% y- I! x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% ~4 A3 g, P9 P1 NEDMA3_TRIG_MODE_EVENT);* u: L0 j% q4 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" ?9 t+ W* E4 W- U+ S HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ z7 u( Q; o) M5 K4 W' e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 ?& C( d& j& ]7 w% t7 c4 S$ I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 G' |, @) d) J! d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 g6 u2 d) T# H& o$ v" n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& H- L/ n' \3 s1 P7 v: M' t: ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 L6 H- I) T2 F
}
! t8 h* y. k3 \' l6 E P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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