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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! X# O) d/ X8 l1 r2 ^* M! a2 t' r- Winput mcasp_ahclkx,
5 @* S2 P8 b6 T8 |& Y2 h0 e ninput mcasp_aclkx,2 `% P& t' ]) X8 z
input axr0,5 v' C1 S$ @$ ?" x* e
! x) j( ]# ?" A1 i, Joutput mcasp_afsr,
0 ?! d: A! g/ Q' Z8 F7 K/ j& soutput mcasp_ahclkr,/ x, P. W& U! p5 m6 f- ]; u
output mcasp_aclkr,! V( D' f b0 R. x% k' b4 _& u
output axr1,6 l! h; X! ~6 w% q* I5 s. O
assign mcasp_afsr = mcasp_afsx;
7 M/ Y# d4 `, hassign mcasp_aclkr = mcasp_aclkx;
% n6 ^& `7 v/ B" G! A& uassign mcasp_ahclkr = mcasp_ahclkx;
, f' p" J6 [$ P* |( L+ ]4 \assign axr1 = axr0; + x# q" t8 j2 L
# D' s+ x' C: Q6 \* S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" f8 p }% | J4 A7 q6 Cstatic void McASPI2SConfigure(void)
0 g9 U7 J9 o+ ]% D6 K{
/ V* [ U+ ?; `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" ?) I" R8 @* P: y% m: IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ B) v n) B* v$ @; S+ l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, `9 p# ?6 R6 N5 k" ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 f& N4 E. g4 g. S0 U ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' v2 E- f+ G- g) T, [1 c& S& IMCASP_RX_MODE_DMA);
/ p _+ `$ R2 g/ }" uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 e) b0 X9 Y7 b5 ~ t K. j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) t" ] l) [( z+ u" i- y8 h; P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 M0 f" X% b$ V* T7 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% T- {% C/ K( l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 ?, N' b" V6 P" ~5 @. q1 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ |: c) @9 y) [3 D! ?; h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, ^5 h+ Q x( x0 j1 B: Q: o9 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" z0 {# |1 W0 b$ X b/ [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( o: b. g1 K# ?, h {! o, a, }0x00, 0xFF); /* configure the clock for transmitter */8 D# h' u* v# h3 i, h n7 L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- t& f, s" o8 r! s: u5 {! x5 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% _% K: q" X# Z. v: ^; Z& GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! a% z! q2 s! `% ` N& S2 P0x00, 0xFF);. y9 L, Y h: H' W/ h+ ^
. R) y& [! B* b0 u0 R
/* Enable synchronization of RX and TX sections */ 0 ]9 k! x- g+ \" f2 ?5 G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* O1 X2 s3 e1 \ \9 ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 _& O6 J" R FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: q$ l6 V+ q8 ~4 ]** Set the serializers, Currently only one serializer is set as
" R' U9 a+ W, J* G' H** transmitter and one serializer as receiver.! D [" n: s4 a) B6 f9 d
*/
! Z9 y/ s+ w$ [* DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
z/ ?+ R, D, B; `$ JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: d7 B h) t5 Q) L" \ r** Configure the McASP pins $ b/ O4 w5 j: n: ^- u4 Q- f
** Input - Frame Sync, Clock and Serializer Rx
" f( _& L" y9 v** Output - Serializer Tx is connected to the input of the codec ) G8 ~3 j1 M' c7 {# f. n
*/
$ B* H! w& ^' q+ `$ g+ D% QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# n) E# `! B, L* ^3 d2 T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& O/ ?0 B( {1 ]6 AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; }# w% ]+ |! b# u" _7 z7 z7 t| MCASP_PIN_ACLKX: B( `+ B/ N9 C) b4 C& P
| MCASP_PIN_AHCLKX
7 p \4 I5 v. l9 K+ j1 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ S8 \* X3 W/ F& I/ q( a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
b& n* f, D: ~2 `$ a| MCASP_TX_CLKFAIL ; \: r" p+ M! c/ c9 a
| MCASP_TX_SYNCERROR3 \2 T4 a0 ^4 g$ F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . Q2 [/ m, b0 o4 h' m h* N
| MCASP_RX_CLKFAIL7 V) F& f8 m* a6 m; E
| MCASP_RX_SYNCERROR , u; }+ \+ E# Q7 D9 E
| MCASP_RX_OVERRUN);
2 D5 ^6 X* T8 i} static void I2SDataTxRxActivate(void)! L! X ~$ \) B0 d1 I! u
{) L5 Y" V% Q# x9 n1 X2 l% x+ A
/* Start the clocks */$ P2 D5 t# F, L% T: F& h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 R: j' v& @7 w sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 }/ }" v7 c5 }. P, N: ~- v( B! V. EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! s$ P9 j- |. L4 z& jEDMA3_TRIG_MODE_EVENT);6 j- n+ F5 O% @6 G `0 ~$ p7 R4 U# @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- W; ?( D1 E9 s, a7 P& |3 ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: f3 t5 _/ y! b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 ^ b$ B& L- k0 k- f/ @2 U( U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 M+ ~! z% W7 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# M6 g; x; p) e+ Y/ o8 A u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" D. f+ X1 H; b5 w+ aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ C( `; y# R+ c, I: Z* a4 @
} 6 t: G) Y y% ^9 a8 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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