|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 ~ s. T# i& S F/ `* M/ O
input mcasp_ahclkx,- y0 u! v+ U, j5 p4 r5 O- ]# O
input mcasp_aclkx,/ e& F6 h8 y: R, S+ ]4 X$ K$ G- }
input axr0,
6 Y, F" o* m) O, T
- n3 K0 T% }% L& k1 k6 Goutput mcasp_afsr,
& J% R8 r6 P4 n% d, g) t- ]output mcasp_ahclkr,
' P1 |" i. W q: e% [; O! A, @+ houtput mcasp_aclkr,
" Q( [: _* r+ B3 P* routput axr1,
5 P3 @; \$ w) w! b$ g h+ X assign mcasp_afsr = mcasp_afsx;
4 z# Y" O; }( @: o9 A+ V$ D2 E' u" ]assign mcasp_aclkr = mcasp_aclkx;' k4 V% b. m$ ~+ E, V. |7 X4 o; k
assign mcasp_ahclkr = mcasp_ahclkx;
; z. ]4 U# Y3 h. p/ C, ^assign axr1 = axr0; * e4 h' D' V c: A" ~, \
! Q# S9 R) K7 u5 N5 M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 }0 @' C/ e6 p- I
static void McASPI2SConfigure(void)5 O! H$ b4 a5 P$ a" [( H# H
{
) X3 `/ J9 a" W, TMcASPRxReset(SOC_MCASP_0_CTRL_REGS); t0 g, \' n) l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: w$ {4 ^6 s M2 t! c; b+ b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 q) R6 D: i/ @- |; N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* v K, Y( k& W8 C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 b0 w/ }4 K" }) }6 C: @9 w! s: u* g+ S7 xMCASP_RX_MODE_DMA);* U8 @$ A5 h1 h Y* n. q8 n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 e5 X) S+ W, q. o2 d7 U ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, `0 i7 p' E2 @# y `6 A4 x; ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 r8 @9 G7 F5 ~6 u% z- P* \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 P4 ~4 V0 T: B L" O( u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 _- J7 X: ]( }( k! M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) g$ h3 U5 a; J% q) L( b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 w5 s# l! V6 C0 S) @4 C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 @! ~) j' P! X7 NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 }0 d- N c7 o' A5 X: x/ o0x00, 0xFF); /* configure the clock for transmitter */8 u8 @" u# f$ B2 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( I4 W& a* s+ R6 U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : M( {6 k) a( B% P5 T+ a1 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( w6 `( V5 Y, h) B& w. J; Q0x00, 0xFF);
5 [7 E( V2 }6 L, k6 ~1 N& g- p5 {$ N/ ^% g# R6 M- M$ h$ F
/* Enable synchronization of RX and TX sections */ : i& R, x/ w, K& i/ J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 N- p$ w, z3 NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); S5 J8 ^- J8 D# [: C8 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 L3 e+ O" u/ ~5 j** Set the serializers, Currently only one serializer is set as
& ]4 ~6 l/ W5 _0 `" P** transmitter and one serializer as receiver.1 ~! F9 e. ~) C) Y8 o1 ~" J! a+ A
*/0 u- j( R L& p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
u8 P& D6 {9 x' q9 nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* J% O- E4 Y9 k
** Configure the McASP pins
" ?9 D4 W$ |' v1 ]& }. I** Input - Frame Sync, Clock and Serializer Rx
3 t& J; j4 d0 f+ l* D** Output - Serializer Tx is connected to the input of the codec " }: q* u/ n% _& E( O7 i
*/
* C- P+ f0 {, K UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 ]6 N, y* ]. F- x& q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" J9 p% w! e; q/ z% F) |4 |8 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 s5 s5 A" U* |5 R- T5 s/ F1 o ?
| MCASP_PIN_ACLKX
- k M5 C6 u2 {& v| MCASP_PIN_AHCLKX
3 }8 }$ C. v$ T! p9 M# ]( A: F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' \5 b* p. u1 ]7 T' z. `, dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR }; t2 W* C( ^ W. M7 l7 @. N
| MCASP_TX_CLKFAIL
: J" D! F* {( \| MCASP_TX_SYNCERROR: b1 e1 ?( |1 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! u5 r" @; D8 M- d4 \& @
| MCASP_RX_CLKFAIL
4 _# W/ y6 t0 k| MCASP_RX_SYNCERROR 1 p, M0 A" r/ l% ~3 H
| MCASP_RX_OVERRUN);2 `1 _, g6 ?% k& h6 E
} static void I2SDataTxRxActivate(void)
8 H3 ^) z: u6 G3 j, e{
/ ?1 Y/ A/ M- E' v, g/* Start the clocks */% G, h% f" C$ Z c4 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- Z$ R0 ? |4 _* e. s. v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# \/ w* N2 o% d7 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ c; Y; q4 N8 [9 H; d) k. hEDMA3_TRIG_MODE_EVENT);
# W" N1 x2 ?8 _$ d$ c! N" |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* w6 z+ E$ s7 c1 O; `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. h! U. J3 _7 ?0 k' `: y0 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 v" P4 c0 A4 ?3 _) p4 q( `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) ?, a9 E& X$ Y$ ~3 E9 z4 w+ ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 c5 E+ N5 U. J9 _6 b& {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ g, E" A+ \% z/ s" rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 |6 T. I5 T% } Y" V/ P4 ^
} , n- p$ ?! A2 O4 e2 B9 C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 Y. t# o [; `* R- M& ~& z* C
|