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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# P& ~. b! v6 W" p: sinput mcasp_ahclkx,
/ _8 Z: v2 F2 finput mcasp_aclkx,6 J1 o; \1 [. {/ @" i9 y2 c3 ]
input axr0,
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output mcasp_afsr,* Q8 q l1 R. q& C$ T0 J
output mcasp_ahclkr,
' J+ x1 \8 q/ P% f/ Z$ Qoutput mcasp_aclkr,# W' _5 l* W. a q I
output axr1,
+ \; L% ~0 A4 j% c; Y- }, y ~ G assign mcasp_afsr = mcasp_afsx;
A* o9 I. ?& H7 T" Q% bassign mcasp_aclkr = mcasp_aclkx;/ u }3 H, y, c/ T
assign mcasp_ahclkr = mcasp_ahclkx;$ Q* F. e# @" E5 Z$ x
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 c8 t/ r2 r, k1 S- M9 r3 W. U
static void McASPI2SConfigure(void)
% g3 z! F( Q8 J( q% [! ]# p9 J% J{# B, i. _& p v# k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 F# d' Y R& P& F; t W P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& O7 Q3 t2 q3 o' B3 b( ~/ j1 L l! b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& a( w: ^! ]- y% @0 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# |5 T9 I! Y" t, v, W/ N. D; x, |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
h I$ M0 { T7 V6 c5 M! nMCASP_RX_MODE_DMA);3 I0 Y% B1 b7 _, k5 v0 S6 A* Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 D- k1 E: }" NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// ~0 _% m k }! y- R) I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ V R8 G9 t0 i& w! E" OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* j, i5 E: c, J6 e" A0 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 v) k r+ ~, |. W5 [0 t( y4 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% v1 n) M$ t& H: VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! t9 C* I8 {3 J/ D0 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! ~0 Y8 o* B7 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, l7 M/ G5 e# z1 \8 a
0x00, 0xFF); /* configure the clock for transmitter */ o: C# p' a2 r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 B3 _& J& `3 o8 R6 g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); o) I: S4 V# h: y& h8 i2 j* K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! o% u2 T) Y* C! f: ^0x00, 0xFF);. j* X8 E% Q/ p' g
3 {* X8 }( A, x6 b/* Enable synchronization of RX and TX sections */
' Z7 J, L* ]; e" [( rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 @3 F. _5 ]! T0 h$ G5 G5 l8 X7 `( N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ P- O; _* ^% |% I# j/ V( n7 N$ }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, D( B" z4 K" V- w/ i% s
** Set the serializers, Currently only one serializer is set as
1 x/ m$ M# u& F: g** transmitter and one serializer as receiver.
+ \+ S. M, l0 h S, j& ]0 x*/
, v- C* G k# uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 @+ k+ m6 m9 l7 K5 t& ~4 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# [+ U* a3 B7 e' V
** Configure the McASP pins
' s( I3 s. B$ c$ S5 g" R** Input - Frame Sync, Clock and Serializer Rx
+ m7 ?, l& h0 Q/ F( [& X }0 t** Output - Serializer Tx is connected to the input of the codec
7 a' ]0 h! ]. b \) z9 R*/
2 J9 A$ z9 R3 x- S( |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) B* W9 ?$ n, {; E: m& Z7 OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' z$ h! g$ V4 B' G* W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; c& Q" d9 }; e) c& y( T8 @, L; _1 \
| MCASP_PIN_ACLKX
" F- O# M3 p, J' B; G, G$ i! ?| MCASP_PIN_AHCLKX
2 X/ h/ P( c, @& E# @6 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- _# W4 P$ E5 W# d, }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: N( o0 O5 O4 x7 Z& ~( T3 _| MCASP_TX_CLKFAIL ( c5 F+ A: s) M5 Y1 }6 L
| MCASP_TX_SYNCERROR$ j/ C' n3 |- b) H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ o& N" c. g) v/ O e3 O| MCASP_RX_CLKFAIL" D6 {: \/ \9 `4 l
| MCASP_RX_SYNCERROR 4 z' ~$ |. l! k( H8 U
| MCASP_RX_OVERRUN);+ M! z- Z- _. b. m$ o
} static void I2SDataTxRxActivate(void). X$ q2 h+ u& e" Q- J
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/* Start the clocks */
; [( ^5 X# i; v9 D5 F4 Z% qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% o C7 V) w- c. }- u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 {) U- [, j2 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. y! n+ B5 b# w" `& r6 XEDMA3_TRIG_MODE_EVENT);$ h( T/ D# q. a1 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! Y$ l+ j, m$ z v h1 p5 C( g0 t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 ^1 P W/ I. }3 h5 e6 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 K- y' @1 L. D, ^( J: b# |* X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; |% N( P8 S- ?- w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( `7 h! U. V7 |) ~; c' i- U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 k2 C5 U0 Z4 R% m/ p& ^" X! C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 x8 }+ ~. j2 I; J2 ^- Z( L
} % ^" D7 z" C9 m. M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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