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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( }. D) d( `' w8 Q. r1 Uinput mcasp_ahclkx,
# u+ F( X/ j6 M4 h/ \. e6 _! X& Z- _input mcasp_aclkx,
6 ~/ X. t$ R% p; P' winput axr0,
, T' T$ `) K( }" n* p" ~
+ M8 P9 c. }: D) g6 o* x G4 {* {5 N' goutput mcasp_afsr,
# U- i& j( A8 Zoutput mcasp_ahclkr," ~3 t7 ]! r- P& C" `! W4 Y4 D
output mcasp_aclkr,
% Y I2 @& I. f& A' q& Q% Qoutput axr1, x/ N+ d* G- Y, X6 u
assign mcasp_afsr = mcasp_afsx;8 u! F$ g( x5 K# z/ y/ d1 e
assign mcasp_aclkr = mcasp_aclkx;
8 N) L' V! O* g \! b' N5 Gassign mcasp_ahclkr = mcasp_ahclkx;7 q2 Q4 o Y4 G% L* K( R
assign axr1 = axr0; 9 q1 ~+ R2 ]3 d% r8 [
- ~* c5 O5 g L, f4 o8 w! U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # q! j5 O; z; X/ J7 D' O
static void McASPI2SConfigure(void)! X# f+ A0 D2 x, P# J k4 S: c& z$ o, M
{
% N5 r+ ?2 {$ k& ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, C, M: @6 f6 v1 k7 ^; |% C7 fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( X$ g- Z$ i- W( t9 HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 { F- T1 k6 @2 @1 b# WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* s/ k8 |& s$ k3 ^ T7 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! ]" s" M& m8 @8 q
MCASP_RX_MODE_DMA);" p# V( ]3 K( g8 x3 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 |' [7 P4 I4 M8 l+ G% G& u0 a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 b2 s2 g/ F9 W/ q6 W9 sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! _, k0 p! j8 {2 r9 `+ ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 p( O1 ~# U7 I" S- w1 AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) t1 x8 O* B/ R& B& oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 R) a5 ~. Q$ @7 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: l% a' D2 o5 B! \ {7 ~5 I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . U2 G, Y7 b0 @! P' t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 Y* Y5 k8 o& I/ X2 w2 Y0x00, 0xFF); /* configure the clock for transmitter */
1 T: c+ U3 X# }5 N, A/ ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
~; w; o; K% k! v% gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " x" V% w9 s/ S* m6 F/ b2 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! o% @! k% O. R
0x00, 0xFF); c, [% K0 X$ c6 Q2 x
) ^( P# y! `3 K- c/* Enable synchronization of RX and TX sections */ a+ V u- w: [. p1 U1 X7 c' Y% L) k/ B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ P: q7 q, R# r }; h; NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' W$ B% ]. |, u# d% G" z" b' \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ E8 n0 ^7 r# m; F% a** Set the serializers, Currently only one serializer is set as
. r/ g7 h9 J8 x W* Y; ]7 P** transmitter and one serializer as receiver., G% C% g+ S) r6 d
*/
3 g! B' X R' z L0 m! _; rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- }) s! r; g2 J* W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( [ X6 A$ d2 l; Q' _0 `3 |9 R
** Configure the McASP pins
( ?% P5 k0 C, }** Input - Frame Sync, Clock and Serializer Rx) R- N9 ^: y# a
** Output - Serializer Tx is connected to the input of the codec
3 \4 n0 R6 X$ H; x- e3 E& B( g*/
. Z. Q* q1 ?) }, w7 FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
_8 o2 I9 `4 N8 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. y6 M* b8 l8 [# k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# G# d% R( h3 x3 h9 r, V
| MCASP_PIN_ACLKX" O' Z9 B x* |* G4 e
| MCASP_PIN_AHCLKX
3 o! I. W. S' t. O+ Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 b4 M R0 A" X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 P* s5 \( I# m6 f8 W( P| MCASP_TX_CLKFAIL
' y" {7 g( t0 n- J( ]+ a| MCASP_TX_SYNCERROR
$ G% r0 w! g. x) d' X a& J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! K' ]. g& |! s H8 f# x1 k0 P| MCASP_RX_CLKFAIL7 D6 ^ t h% g/ l
| MCASP_RX_SYNCERROR
5 b3 S2 L; t: C4 A0 X$ {| MCASP_RX_OVERRUN);- v a) H7 ^6 y, u! M! D( O4 E
} static void I2SDataTxRxActivate(void)' ^# T) x' z/ \ n, s$ U
{
3 W, O7 _5 S. k/* Start the clocks */( G5 t' [3 G0 J" y4 l8 n1 h; S% Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 m' K6 k! @7 |7 i* N+ m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; `* ^' d$ t6 l+ z$ S2 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( c4 k' G5 N' D C8 X
EDMA3_TRIG_MODE_EVENT);: i0 c$ K% d$ H! A( N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
M O% J, E- }* |( ~( ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: K; Y5 w# W8 u. c7 M; kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% U4 j( K0 W7 h" e# Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 i4 I2 H0 a$ x. Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 z+ F9 k& x% H5 s/ o0 _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! w; p9 h2 J: G" f5 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! ?# s2 V- U p/ i N+ B0 _1 p}
! r8 R+ P4 ^+ {* ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + ?* s( D0 H5 y4 k
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