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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" P; W# R! K" e" Vinput mcasp_ahclkx," X& @; f* d, L5 K5 o0 ]
input mcasp_aclkx,0 g1 {8 Z4 U" \- Y+ m
input axr0,
~1 Y, ` [' ?9 o4 H$ U
* r4 p4 l$ ~4 n* xoutput mcasp_afsr,2 w& a/ u& z; @# r p
output mcasp_ahclkr,3 W4 Z7 a4 E& d' V: _ O) O
output mcasp_aclkr,
* P- r% p9 L+ Z4 D1 Houtput axr1,, P8 H7 f/ o* B4 J- |4 \7 @
assign mcasp_afsr = mcasp_afsx;
$ H' ?% x1 j# ] s) Tassign mcasp_aclkr = mcasp_aclkx;
- Z9 ?& X. @ p9 D* bassign mcasp_ahclkr = mcasp_ahclkx;! L7 ?0 V3 k: J9 x: I" b8 n
assign axr1 = axr0;
2 E! M7 L( {1 G- @* M' h% ~: \
, o0 D: Q4 u, W+ _7 J; |' ~" L5 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 i4 x, E% Q; Z' B4 x" ~ N8 w! lstatic void McASPI2SConfigure(void)
+ e7 B8 F( A( R* `& L{; B/ w* Y* y3 v, u# ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) w- `$ J, a4 O0 k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! J, r5 e( N" R! |3 F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) _" W" z, V. \( ~# @; P7 N5 Q: iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ x1 }5 u+ u" ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ l/ i; y8 u- H2 i( j0 v/ w
MCASP_RX_MODE_DMA);' a4 O* ~1 T) I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! T3 K+ q) d' L3 W3 F3 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 ?. Y @& y6 T) \- p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' h, Q( Y- H& C+ w8 |4 v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 S4 u$ j7 g) L3 }9 H/ l" J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . G4 S" `1 i- y. i N( G! v. m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ ], I4 y: w) m- |% B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- p3 o3 W; F$ I$ q1 \8 y: PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* Y0 i9 G, Y2 C# ]- }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ m1 X& o4 f. B, I& Q0x00, 0xFF); /* configure the clock for transmitter */& C2 g' f6 ?; a7 [% v6 y6 L$ @6 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- P( N `6 Y) a. z! J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % r+ R" l M1 @ I" ]% D; l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; ?, O0 V3 ?4 `6 V
0x00, 0xFF);
5 [. p2 y1 T1 P/ A9 X4 I* X# }1 b& ~4 b
/* Enable synchronization of RX and TX sections */ 3 h( p2 I0 D) r! y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% X4 [: S+ G8 O8 \& Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' Z" ~& g& R' n/ ]0 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" H1 t. a! Q. R- n3 x. A" t** Set the serializers, Currently only one serializer is set as9 \" f3 b6 |" c) O
** transmitter and one serializer as receiver.
; J2 ~: Q7 \: N9 e" j/ p" Q& Z/ u6 J- M*/4 u3 U c; T' B9 p' h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# `5 g" O4 r. x8 G, f5 dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ O" W+ i$ [3 N. K& Q+ w
** Configure the McASP pins
! P4 {) E& U- v, h** Input - Frame Sync, Clock and Serializer Rx
" l: w2 B0 D1 X0 J" S- m; C** Output - Serializer Tx is connected to the input of the codec
1 l: L: U& [- Q/ j6 g*/$ m3 J: t/ S1 l0 K& ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ u# g" t: U6 c) l& b; A5 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 D4 l; r' o- |+ P6 h5 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ ]( v1 ~* {9 z9 W
| MCASP_PIN_ACLKX( S" ?5 u8 k* d4 l7 p6 H5 t
| MCASP_PIN_AHCLKX' _% T2 @/ C8 `4 K9 S2 Q3 d' }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% _$ J3 j, p+ Y" i$ J+ o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ {( {- u; s2 f5 ]' p) y) `+ h| MCASP_TX_CLKFAIL
1 @' q4 v' T, h: O| MCASP_TX_SYNCERROR
: t. n, w/ q! e; ~) t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* t3 A" Z# o% H$ J5 }| MCASP_RX_CLKFAIL
0 n- o7 E' I3 K7 N- |7 Q8 t| MCASP_RX_SYNCERROR
! c: B+ ^; o a1 Q" M# ~& k! o| MCASP_RX_OVERRUN);
$ j% i0 t/ h: Q) @7 N} static void I2SDataTxRxActivate(void)' Y" x" _+ [4 c) O' W& S7 `2 m) |
{4 }& Y1 Q9 R0 T* M6 t9 [4 k
/* Start the clocks */
7 |* ]2 V+ I( \& j5 {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 C1 l0 A) s( h" ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 M) x$ d5 Y' C! l' P8 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 Y# h4 l* q# Q: _EDMA3_TRIG_MODE_EVENT);% C. X8 m1 i G4 U. @1 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 W" l! x5 o! u$ ]0 d# C8 }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" }5 \4 |/ @3 p2 p/ A/ FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, b# D" {, c: W- Z, V0 c$ _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 r M' y& {1 C( Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! L7 }, R7 f/ ?7 m" d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# F% H/ a& O9 N* i. k! ?0 N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ W$ @3 R+ S7 c& V/ _* n n$ H
}
) g" V7 L" }5 [* L# y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : f, w$ L( r5 H. `7 I
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