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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, ?1 z9 {0 Q' q! I5 y Y9 }0 xinput mcasp_ahclkx,# `2 Z0 p2 \. f* U9 s
input mcasp_aclkx,
9 J) `" }' @- G1 oinput axr0,
) j( d6 _* L- I. A1 A& |/ W3 o, B% W4 @' s( K; a/ ~
output mcasp_afsr,3 _6 K6 V: y0 n- U e7 \9 a: v. [
output mcasp_ahclkr,
& d- A2 C \: w' j. d5 C: o5 Y) q6 qoutput mcasp_aclkr,
* u5 V- M4 q% w5 ~9 voutput axr1,! C3 }" y4 D; i& h: E
assign mcasp_afsr = mcasp_afsx;
" x6 Q) O" g k! k$ i% Jassign mcasp_aclkr = mcasp_aclkx;( m+ u* E7 ]5 Z1 v) B) s
assign mcasp_ahclkr = mcasp_ahclkx;; v0 @+ g2 R; N( c
assign axr1 = axr0;
1 [9 ~+ r8 b6 I2 u9 o& F6 _( X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& l: E; l# j- Z& \) _7 c2 jstatic void McASPI2SConfigure(void); u& E/ d, S$ Q+ g0 x
{
# s; V5 |/ M7 S8 E3 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( ?. B" _3 H9 M5 K- \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ r" }8 v' b7 |, f' d3 m% oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* C' p- A6 N; p& f6 [+ cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 W2 F8 ?$ p, ]9 I2 b8 y) B% h1 A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! X2 f2 n9 c8 A
MCASP_RX_MODE_DMA);
1 y5 y: i! P. H6 W) S" hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& b9 `7 T9 y/ w, qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* E, K5 b8 s. W A' XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 v, ?0 y7 I+ w( jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 M0 Q& S' W, k5 e+ o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 L% G0 k2 |7 H6 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" c4 R# r1 n& l- iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% N, P! u" | q5 D& r8 {: Z6 j/ QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" K+ U' w" Q$ {, NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, m& J3 F3 v G3 q8 E* h
0x00, 0xFF); /* configure the clock for transmitter */0 J& o; i7 q. h; y" I" D. d4 q. _7 ?% }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. k: R- l& A- j6 x) M7 o% n, DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 G7 O/ M/ l9 l5 b# I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) K4 _4 j+ j" b. k: L1 F8 o0x00, 0xFF);
+ R7 D; Z8 X: r0 r+ l% S2 _* Z+ u: n7 q& X* c* p4 B# C: a0 ?
/* Enable synchronization of RX and TX sections */
9 Q' k; d1 z5 s/ p; DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 i! |% f. o) wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) z3 l$ t. S+ w( w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* ~( o3 v4 |* u" A0 x8 ^** Set the serializers, Currently only one serializer is set as
( \1 Q% @) L! v# G0 h9 ]; D** transmitter and one serializer as receiver./ ?8 d* t w4 A( G: G% U# ^* h2 U/ B( Y
*/$ R y( A7 y5 Q$ z& {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 I1 S; `9 I) @# X3 u1 |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* Q% t( ~2 S' ^6 F** Configure the McASP pins
2 k- Y; b2 y( n** Input - Frame Sync, Clock and Serializer Rx
+ M2 d$ ]9 W1 A. E! K( ^! w** Output - Serializer Tx is connected to the input of the codec 0 m# |9 D H0 ?' B+ u" Y! c9 q
*/" x3 q5 U$ F' K6 O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 L$ `- U9 [% N/ K4 R% y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- _" H" O% X) I7 }$ b# CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 ~( `+ a% o4 @
| MCASP_PIN_ACLKX% |5 R6 v) h6 c9 s
| MCASP_PIN_AHCLKX4 Y- h0 S, Z" X' T, U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; _6 b9 S q, z& b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! [- T1 r- P0 j| MCASP_TX_CLKFAIL 5 v! e+ i7 v5 H! c' g
| MCASP_TX_SYNCERROR
# ~2 q' r) L+ k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. N* w/ y/ W( E9 h- R$ X+ k| MCASP_RX_CLKFAIL8 W7 ]* G- L7 _" r' e1 _6 F
| MCASP_RX_SYNCERROR
5 {, o0 z5 r7 ^! c/ u8 S' p' D| MCASP_RX_OVERRUN);& r' j) A( x3 e8 f: j5 |0 O
} static void I2SDataTxRxActivate(void)# _. l, ~2 f9 M! m
{ E; c; {5 N' X+ Z$ S' a& u. r
/* Start the clocks */; X s& I2 O6 m% |* Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 S- F2 m6 M+ O& O2 w1 Y+ F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 j. Q4 r; O9 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, C/ z8 _5 p7 p2 l
EDMA3_TRIG_MODE_EVENT);1 C, W7 N* ?. P% x, w2 x2 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 Q+ m/ x5 E5 x% W' wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; a9 X) Y, Z) ?! h6 WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: t% B$ x" i- a5 c! V5 O, {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 E% g9 R8 a) W+ l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 O( L4 P2 v2 k* H/ S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 {. x. p/ M% I& fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 z3 m2 R- z/ ^* ]" O1 ?}
* y* I$ _6 Z9 W$ L# @- g, k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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