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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 }% h! c. p- a4 f/ R/ Qinput mcasp_ahclkx,& A7 e% \ T J
input mcasp_aclkx,1 z3 u* s) b. Q! [
input axr0,2 {) A+ Z! }* i' n' n
7 D# ?$ c. N3 {. D7 g! r
output mcasp_afsr,8 b" ^3 B- c d
output mcasp_ahclkr,8 }& n2 U& c+ \1 J& z
output mcasp_aclkr,
4 F5 O5 A6 A7 p) `. h: ^# ooutput axr1,7 e5 `, j4 V3 ]- q; S6 {: {
assign mcasp_afsr = mcasp_afsx;& q, D9 v8 F: l. Y# q7 ^
assign mcasp_aclkr = mcasp_aclkx;, c- Q* q7 R5 X7 Q
assign mcasp_ahclkr = mcasp_ahclkx;* Y+ ^2 d5 M$ ]
assign axr1 = axr0;
3 u; D s; h2 g# Y. B! H7 _$ i) o/ X1 a$ J2 J& f. j4 x: I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ P/ W: t5 }- x# F$ \& ~: m/ e q0 Y; Vstatic void McASPI2SConfigure(void)* H3 k# m, B( c+ O, p! o
{
/ Z( m8 [: w5 T$ F( IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( q; _, c8 @5 y# |5 h3 h4 I$ p6 a. Y" _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! O& f# n) f! C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ d* c- q9 E! M7 U% N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& Q. m# F; [8 f) J' w/ R) w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: O6 W" C% Z5 r1 _& hMCASP_RX_MODE_DMA);
+ s6 H9 C1 D4 j7 A bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 X7 v5 N) p5 T9 M) i4 ?9 F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) W' }7 n% S+ z) pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + k# y& {- l* h8 o* E% q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! d8 ~' y" u0 T% C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + N1 d2 r' j9 g2 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( U T h. x$ u- N# K# ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) @3 [6 Z+ P5 D RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 @7 p% }# u# K: yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 y* ]9 s* `6 L/ Y W0 H
0x00, 0xFF); /* configure the clock for transmitter */( v& C" q: l9 r* z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( n# x6 p4 J) N. G1 \. `8 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 T8 E. f; u$ G& {4 `, ^5 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 [6 C3 A4 ]( x( K% _4 B2 ^: Q0x00, 0xFF);5 G$ [4 l/ Y5 ^2 u. I
: l( n7 N4 L5 u, V0 O: l
/* Enable synchronization of RX and TX sections */
$ ~; }7 x9 [% I% `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ g4 `( X% M( c* K2 j- Q1 q. D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ u _5 n g' x( g3 J1 [( L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& B+ w% u, e' r e
** Set the serializers, Currently only one serializer is set as/ p4 P8 Y; o$ \; j
** transmitter and one serializer as receiver.8 w/ Z2 T$ V; m
*/' d7 \/ _4 g8 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- {2 M8 E a7 N& I$ Q; _% ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' y8 Y+ f4 v4 E. n3 ]** Configure the McASP pins & k2 O3 W+ m7 G9 \: C5 _2 A
** Input - Frame Sync, Clock and Serializer Rx
) Y: y' E( R. z4 v- t** Output - Serializer Tx is connected to the input of the codec
# b- T) k/ q3 t*/2 `( x4 ^: j/ t* p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 X& a8 B8 L7 ^5 w6 G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); ?3 p5 A% Y" e1 ~0 A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) Y) t5 X6 m0 S| MCASP_PIN_ACLKX% B% @; W8 `8 ?) N3 @
| MCASP_PIN_AHCLKX
% @8 K; U0 {- \9 B$ E# e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 x( g5 \* m; @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 h' `; ?. \9 H N7 h- E# ~) @& r: G| MCASP_TX_CLKFAIL
0 H* K& d3 p3 {' D0 \! || MCASP_TX_SYNCERROR
0 Q# F1 o2 s4 q9 n( R8 g: l' [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 T7 | Q0 y0 I, _2 O| MCASP_RX_CLKFAIL- h0 u5 q7 R( U0 l( I1 F# Y
| MCASP_RX_SYNCERROR
A) W; T& ~9 B* m| MCASP_RX_OVERRUN);7 Z6 S! k' H4 {1 H) s
} static void I2SDataTxRxActivate(void)4 M$ g; f# n- F1 }7 `
{
6 O3 Y7 d7 P5 ?1 D' ]8 w) v# ?! E/* Start the clocks */$ g9 w& W" K2 e% x1 v# A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: j: W* J* S% I: |9 X% }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 T+ N8 d% L: |9 R7 f" [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) U. m* s/ \+ P# z* s
EDMA3_TRIG_MODE_EVENT);
/ _9 x9 Y# Q( v7 Y! ?* ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. S+ l9 c2 z% d* t) Q; xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 R6 ^ y, v, uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 Z* g) Z* Q3 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 }8 t9 ~" L& \" t V( l5 Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 E/ t6 D+ }5 r( Z2 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* h, u, H6 P5 k: BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& ]1 Z( t+ l4 T" C, U4 [ R, R0 `" d
}
( J) u7 `# H& P, h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 a* y6 _* {6 W2 n5 D' P: M% O! w
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