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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. ]5 o+ n, i1 X1 P; S, ]
input mcasp_ahclkx,
4 [, j& f8 F1 [: `0 hinput mcasp_aclkx,. M) Z. x6 U- n* g8 V7 p% r$ t
input axr0,
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& @8 L3 c( U$ J; houtput mcasp_afsr,
: ?+ _( V' ~+ j7 \output mcasp_ahclkr," K7 w, h f; E( O
output mcasp_aclkr,/ d& f" M" G! T! H5 [/ k2 I. |
output axr1,4 X( @1 p/ m3 n% d4 p
assign mcasp_afsr = mcasp_afsx;1 M) i2 R3 d2 K2 w
assign mcasp_aclkr = mcasp_aclkx;9 V, {# j3 ^1 w% v) b
assign mcasp_ahclkr = mcasp_ahclkx;
w5 A6 Q" e* Y5 X. b: cassign axr1 = axr0;
9 M/ w- r! x. G" A% e
( O0 B3 A% B% J# a% D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# [; R9 N) ]+ \7 S# L* H6 b B3 ^static void McASPI2SConfigure(void), S: J7 H; P% @
{
, L& z. R2 Z* @) w5 r3 q1 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 G. |0 [# e& T& y2 W8 u# kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- S& _6 @8 a; @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ @/ B7 I2 `! ~3 o+ v. X& d/ JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# O" \2 X2 Z. qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
`: r& I2 |0 h6 wMCASP_RX_MODE_DMA);' r! e( m# H% U- Q, ^1 a% U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 |, G' w% J( E6 @5 m/ g3 A4 S* _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% Q+ B, H; X6 n) j' w+ gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 R4 |. ^: R. aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* F7 w* M J' b; X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 x* [( p. w: r7 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; V% `1 Y6 X, a. |$ R; SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& j7 P8 c" H7 r6 Y# n5 vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! n, I; l! t0 V5 B9 b0 NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 K! |1 G- ]% W3 d2 l; c4 }0x00, 0xFF); /* configure the clock for transmitter */
; V5 W, t5 [3 n6 E: dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 h; P1 _( S- F& YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & L) e# S/ r+ [( d P7 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ t8 }4 @" l; G2 I0x00, 0xFF); w& p( W$ T1 M0 }2 ]( a# H. F
3 ~/ K0 b8 O$ l1 {
/* Enable synchronization of RX and TX sections */
4 u/ I9 P. c3 E/ q0 G5 n2 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 r6 l0 J; m* M; CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, o+ a6 a# s0 D! G& q: m$ y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ ]& Y& [/ T" _) t** Set the serializers, Currently only one serializer is set as
9 R4 E0 X* B9 ]$ U' i; ~ C7 {9 x** transmitter and one serializer as receiver.
- D A( W2 k3 ~3 s*/$ ^; }/ H3 b/ t. x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# C/ V* {, S6 D, u2 f5 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ N1 c; M3 X8 U. a) e( ?: V
** Configure the McASP pins ) e/ u( X, O7 E- P* f
** Input - Frame Sync, Clock and Serializer Rx
* L: L, D* C+ ~" a5 M j4 |** Output - Serializer Tx is connected to the input of the codec ; ]/ k) c5 V% [ g n& U y0 i
*/
3 S" n3 T7 K# U4 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# g0 P: W- S% S. k, l [; O% u2 E9 S# ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; x5 E5 ^! ]4 d( W0 }! w5 T( f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; J& r% }9 J+ {. h8 Q- h: E& D
| MCASP_PIN_ACLKX
8 z% f V- |6 d2 u| MCASP_PIN_AHCLKX+ P5 p$ m9 J; v: X: d, y/ O- b7 J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& H% v" `9 i8 o- H$ o& n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! d: e2 n1 u1 b- f( u/ g7 w# K C
| MCASP_TX_CLKFAIL
, q4 ]6 }+ ~) r9 F/ k| MCASP_TX_SYNCERROR
, B6 f6 k" ?. }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& g! @7 B2 {' C M- _' v: Q+ M| MCASP_RX_CLKFAIL: ]$ H$ Q9 t, y y# j
| MCASP_RX_SYNCERROR
/ P$ s9 l0 \; _# |$ W2 f/ w| MCASP_RX_OVERRUN);2 b. s7 v$ T& A% J8 ?0 t
} static void I2SDataTxRxActivate(void)
$ B4 J2 \2 T; w- m8 X6 b3 U6 n{- ^+ S: T( B$ b9 O
/* Start the clocks */
9 @) j9 a4 [) I- m! I& dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# [ m% F% s* r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 o( y( n/ U. n) W8 N; ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 s- y! n& }, M" Q5 f
EDMA3_TRIG_MODE_EVENT);; B$ x2 U& S1 }' R4 J% i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) e: ~7 X9 ~0 Z9 ?# a0 m% P( XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: l+ g3 K$ c; m( ` Y! gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 l0 P+ C9 i. x3 A* |9 s" c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. Z) x4 H$ M' ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* _+ d( b! {1 ^5 _' iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* h, }0 a) k8 \6 _7 |! t9 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ N" \+ }) R* Z( d} ' D# i( b" A- v3 F$ Q8 F" h/ t4 k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 \8 \9 z# ~" g3 G' w8 C* Y
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