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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 F- m% _ d% B# r \9 A1 {: @; cinput mcasp_ahclkx,( O: s' @" f I4 ?0 L4 j( a5 \; ]
input mcasp_aclkx,' v( _3 l: s3 E5 w' R
input axr0,
1 o1 K8 z' i( t! {# ?# y5 J# h. b2 v2 ~7 K9 x
output mcasp_afsr,$ E1 H3 d& Z5 g' V1 ]
output mcasp_ahclkr,
( d$ O; g. C* M+ j: j- N0 {8 houtput mcasp_aclkr,; X1 D% p- S* X0 _8 W/ Q3 v
output axr1,$ h8 A2 W' C5 H! {0 X8 f
assign mcasp_afsr = mcasp_afsx;0 z& P) v! V, U: |8 e7 H( |
assign mcasp_aclkr = mcasp_aclkx;
9 ~$ X$ N0 g: c3 |' z) kassign mcasp_ahclkr = mcasp_ahclkx;
$ ]2 g# g2 ~0 w3 E' c, qassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + E7 e8 i% C7 j) S* n/ ^7 T
static void McASPI2SConfigure(void)8 D9 i9 K8 D3 v3 n
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);& T; |4 W: _" p: x8 ]" Q, v! k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 X0 B9 r Y6 i& J1 C& a8 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ o2 R5 p3 F( ^& E C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: j. O. Z" g$ V/ F' V ?, M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ @0 }0 a$ r, T- ~' u# nMCASP_RX_MODE_DMA);
/ Y3 J* N) e7 ~4 I3 @; WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" v' d6 e& b, C, Z/ x# ?4 \( `/ cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 ?; H d5 y" y- G& t4 W6 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 g, z, t) P2 Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# F8 P' ?. Y( x% H& `: ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
{, H: v9 I9 |) ~% v5 n' Z1 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- @% a) u( f9 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 a) I) e5 B$ R- u" H \. C; `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ^ `& ~1 g8 F- G5 ~$ \" {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- V* K7 D8 v, H
0x00, 0xFF); /* configure the clock for transmitter */
0 d; c* W- z+ Q5 u+ nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ J2 Y; _& q4 U2 n# T. C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 B( P& @0 W. cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: P. l& g% \ N3 w x& E/ \: Y0x00, 0xFF);0 j7 n' g4 C" T- q+ P
. q# Y0 o2 { K( a5 y! I4 k
/* Enable synchronization of RX and TX sections */ * Z |& Y. f7 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 E& W$ \: g1 D6 J- `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, L" S. y/ Y* G; {. o! H1 E" B2 `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 O9 Q( j3 B$ k; V, R! \: p. P** Set the serializers, Currently only one serializer is set as
/ V) y- W$ L" ~** transmitter and one serializer as receiver.
( B, U0 t; h+ f*/" c Z$ T" {; J8 @' l: _ t7 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ R2 a" G! F( [. @7 F& T, B! P7 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 V2 _0 Y4 \* M# |5 F** Configure the McASP pins " N, N+ ~" E, F+ d
** Input - Frame Sync, Clock and Serializer Rx
$ L6 f$ R+ |) }+ V7 G3 D) @. v** Output - Serializer Tx is connected to the input of the codec $ z8 h. W$ O. e( J- h7 T
*/* w6 ], n+ o! I% A& y9 X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. \8 h4 P" O3 c: z5 d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, C k8 e# p, e5 G, {9 Y: cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% ^' P" _" {. m4 }
| MCASP_PIN_ACLKX. y8 j/ F; f( e4 g, u, j' z
| MCASP_PIN_AHCLKX
) B9 I1 |0 N/ ^9 T: A \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& Q# g8 I+ n" }# m8 ~) CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. r4 c9 r& q9 H" ~| MCASP_TX_CLKFAIL 5 \0 Y, @% f& @6 R& V& P9 f7 M" F
| MCASP_TX_SYNCERROR6 \- w3 C+ N, H0 c0 y) y8 M/ P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 q4 ?3 A+ K& Y# L* I/ f
| MCASP_RX_CLKFAIL
. j; {) T# H1 f; R9 @9 b| MCASP_RX_SYNCERROR
7 g5 J( @% L' h# N4 [3 U| MCASP_RX_OVERRUN);
$ v0 O# u8 T/ J1 Y1 B9 ^1 T2 z( N/ J} static void I2SDataTxRxActivate(void)
7 M* J2 [; O0 y3 m{
& Y! B" ]! U0 b( |/* Start the clocks */
: ]: |; F3 E, X2 Q( W2 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ c' k3 b3 L) G' o x2 Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ F! a; e1 Q/ |" U3 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 f* m" j9 E, m) j) wEDMA3_TRIG_MODE_EVENT);, A* `2 F d. T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. B6 Q7 n& X! h+ M/ E' I- Q- J8 p( ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" d' G0 S0 Q9 U- P7 u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 E/ g6 U R5 G2 [! IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ Q, n2 h2 T6 W+ D0 n' _: B4 Z' E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 W5 @- z2 z5 w& F1 m8 L; e7 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 T! b& v, L' X8 S% y8 Q; ]0 |( d( i3 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 h/ i+ n7 ]: y) A5 S# @5 j
}
" } Z/ V% W% o4 }) T& _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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