|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& k* o+ a7 y( \$ A$ U3 S! k
input mcasp_ahclkx,
9 J( r5 h$ J1 u2 a: Z* R1 [input mcasp_aclkx,2 a% d; ]9 |) a% |' o q+ ~4 W
input axr0,! t7 ~& ~8 J/ a% S' E0 q9 U
2 U$ a! f; I& S: w3 u4 j0 Joutput mcasp_afsr,8 w, O: y% X9 ~$ j1 e) N0 w
output mcasp_ahclkr,
4 s7 r- s1 Q5 n+ w; Loutput mcasp_aclkr,- I& h$ J' {: C2 b: c, e
output axr1,# g! k e& ?& {% j$ b- o
assign mcasp_afsr = mcasp_afsx;% n6 M) z" ~+ L/ r
assign mcasp_aclkr = mcasp_aclkx;
k" S# P& }: c2 e% Yassign mcasp_ahclkr = mcasp_ahclkx;
2 O4 `( _" n/ q6 eassign axr1 = axr0;
5 J) Y& @$ E% a: | T& z1 U) p- {! k. v U" D! Q0 t. M- J7 k! }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ X% f# ], M4 B$ w7 r+ S% K6 H6 B8 Ustatic void McASPI2SConfigure(void)
% H* }/ f0 t: N- o2 N# S{8 }6 H" W4 P# x7 x/ {: G' B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 X7 f7 H3 r1 I, C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 Q" n, C, u& v; | e. v% n- vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 W: @' ]. q& ^0 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) r9 e/ f" K3 e3 G. H- }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ z" D" L- S; h& v' w, ^' Q
MCASP_RX_MODE_DMA);
& V( [& k- G; X. c9 ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: v% W$ z/ l' ^ PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. U x$ a) `. GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 c. v$ k3 w+ w* }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) C3 J) |) M1 r' @* y+ v# L! ~3 n) t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 Y# ~7 D1 W) f4 t& H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 v5 l7 R: b* n5 R9 }& |! Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ Z, c8 z, C. n9 X4 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; ^# g2 N) Z. i; A! c% ]6 cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 M, X& D8 e1 F+ [0x00, 0xFF); /* configure the clock for transmitter */
* t+ i6 \4 t+ h& c4 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 m+ H8 U! O0 `" x( _) O! P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 V* V& W" b& }* G# P7 \3 N. w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" X# S% U+ s& I0x00, 0xFF);
B- w4 P- }( S" s/ A3 C
7 ^" H- W* y3 C/* Enable synchronization of RX and TX sections */
9 ]" s5 f4 k* I$ O, N* w2 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 J+ \8 |# T I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! q( r% O+ R8 G! l9 ?% F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 ]* X1 t8 e) `/ |** Set the serializers, Currently only one serializer is set as
$ n f* S4 H; I! o" h2 X** transmitter and one serializer as receiver.
9 k8 s) @( ~( @8 y9 Y*/
8 h0 F) T, `. m* S2 _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 S; M* x" P& k# o0 U, {' V7 {8 {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ f1 o% | V R** Configure the McASP pins
% U7 C- m; S1 U7 Y* L** Input - Frame Sync, Clock and Serializer Rx
9 C% M% v# i8 b** Output - Serializer Tx is connected to the input of the codec
9 e* e' _" z7 D9 P1 X+ z5 V*/
/ l1 [2 c/ i' P+ ?" kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ b2 |! w D& B3 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) T) L7 q2 \- b+ o# y8 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" I9 C, k$ e1 \3 f
| MCASP_PIN_ACLKX
5 R+ B/ f! H' e| MCASP_PIN_AHCLKX
! s; P7 r& v- e3 d' k. w+ o8 d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, n( N+ i* _% h- h% `' m( K2 IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 S; a5 ^+ K$ x' ]0 p| MCASP_TX_CLKFAIL & m! a. r1 b2 x7 ]& ^
| MCASP_TX_SYNCERROR4 ?% C( w6 r: H( L: j! [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - w6 \5 ^- O; @! s
| MCASP_RX_CLKFAIL% }9 J: T) l, Z2 Q
| MCASP_RX_SYNCERROR 7 P6 e# j1 G( _$ t
| MCASP_RX_OVERRUN);7 n' x' e: \7 Q4 `7 ^& z
} static void I2SDataTxRxActivate(void)
& y2 E8 G6 O8 @; ^" J( E{% k7 }3 m! [5 w- ~
/* Start the clocks */9 b E# t" m: _/ f: n4 |) o" L; t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ p; g' T0 Q7 L6 v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 w/ r4 L! o/ U' m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 C' o, U" Q( g7 kEDMA3_TRIG_MODE_EVENT);
. b* m1 H' U4 n- [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * C- y( u$ R8 f" \9 \: ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) m* F4 r u% ]5 k- \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, k; |! h& W$ a" C$ y7 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* U! o8 Y0 m. B- _' d, K2 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' f) c& U g, b, U2 A4 n) v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; c- @4 b2 @# l5 [2 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ a1 X. Y) _2 c& R( Z7 S}
( p* R1 ~! G$ `, y6 {2 @* A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 B4 O6 |8 b0 A, j: f1 y
|