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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 U' ^0 G b8 A9 J0 I
input mcasp_ahclkx,! d% E, M; u; p& c/ Z
input mcasp_aclkx,' F$ F. n3 Q. p: k
input axr0,
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( Q7 \* a3 _* ]& E! y6 ]$ joutput mcasp_afsr,+ {& \; j# n" H
output mcasp_ahclkr,3 A# W) d6 Y9 _, E* E
output mcasp_aclkr,
8 x# r2 c1 `- c' t7 V. Q5 z* e. Qoutput axr1,
! b: @+ G6 _7 G assign mcasp_afsr = mcasp_afsx;% x) g) w* |4 @1 [$ M& }3 T4 U R
assign mcasp_aclkr = mcasp_aclkx;
; r% F8 m$ y2 o5 N4 x/ zassign mcasp_ahclkr = mcasp_ahclkx;
8 n9 |2 T3 v0 O& q+ U5 v3 T9 Z* Gassign axr1 = axr0; : k$ U. ]6 I5 w' e% {
/ r: D" c/ `* j7 z1 V. @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 c! |0 ~5 b {$ l! q5 `static void McASPI2SConfigure(void)" R" `8 x9 q: N) a. U* K6 F
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 T+ I" \- E( H' }# XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- `: n. u+ K7 Z9 B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 v* o% l! a ^7 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 ^. ^+ t5 y. D- v3 c! j- }7 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' g( o* D0 K* [6 O6 k
MCASP_RX_MODE_DMA);
( X) @2 ^3 c2 M. }8 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 I; ?' {+ R" }9 W+ w! h" L, H" aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" l* V% S; ]2 K6 N" [* [) _: m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ e0 p. B5 F' {% X' M1 O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ H8 ]* T) e( V( l: OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 V" I: y/ m" W3 ?# tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 R* a* ~# ]7 S/ H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 O* k3 c2 N/ l/ [; T" s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' j5 Z0 c/ J7 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& L0 n' |+ G1 p+ F, `1 I
0x00, 0xFF); /* configure the clock for transmitter */* |% a" ^# T: e n$ t/ g5 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 l, u7 \% X' i; [7 G; SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / s) o4 h2 p8 Y0 d0 V" x: g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- j$ [$ x/ c1 X3 Z1 B9 K
0x00, 0xFF);( A0 k+ O. F7 X+ w7 l0 u
% U5 K& S& [5 o/* Enable synchronization of RX and TX sections */
1 ]0 V9 T) q: l5 tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 ?( d5 P* z: p7 @9 J* o" `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 d& @; O- J1 c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 @# n+ E0 [3 C
** Set the serializers, Currently only one serializer is set as" m, A: j* o& C1 _5 G
** transmitter and one serializer as receiver.
9 t7 m! `2 t3 u( b*/
; y) E* o: R- @0 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' ^7 M& {7 f, g9 {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" S* j D9 K+ P% ]5 Q0 [
** Configure the McASP pins
! z6 |3 H* U. ` v; q& K** Input - Frame Sync, Clock and Serializer Rx
6 e9 O+ P; K/ h, s& z** Output - Serializer Tx is connected to the input of the codec
! B: }4 L5 G0 e( K4 W! u*/
* Z4 S4 X; g) q+ a; S8 JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 }! q) q. C% z5 B- _2 z( bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ } V3 h' `4 K: ~4 h0 q- v s* y4 z& iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 B. L' S) v* t5 l2 K" U
| MCASP_PIN_ACLKX @$ w, x; {; ^& N+ e! l6 D0 p$ E9 X
| MCASP_PIN_AHCLKX
9 d" n- J0 h- z8 u! p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* j9 N' U3 k8 x8 | G- u* ?$ c, YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , B! q( T4 i2 U4 [# n: D7 |% l
| MCASP_TX_CLKFAIL + I9 h/ F2 o9 I7 B9 [/ v" ^- x
| MCASP_TX_SYNCERROR& y9 j3 u8 K! y0 S+ X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' C# j/ F3 w1 Y& h: l| MCASP_RX_CLKFAIL
2 I. c: I) E/ K| MCASP_RX_SYNCERROR . ~6 v8 d4 F4 @4 J0 m( J
| MCASP_RX_OVERRUN);5 F q6 n3 T/ ^2 g& _' t
} static void I2SDataTxRxActivate(void)2 H4 G) }$ j9 y2 `+ m7 B
{
" a- W% [$ C4 e, z/* Start the clocks *// V6 n, d" T: R, |# ]* N7 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 A! { H1 s+ y' \6 u( P; V1 }* KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 m F0 S9 l% K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," ^. G( m- X; _6 J
EDMA3_TRIG_MODE_EVENT);
7 {- Q6 ^4 J( |% t2 b. k3 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + d' @; q u3 o3 M$ n4 }; G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& E. S/ I1 ?) H4 q8 Z5 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! C8 P' F; B/ Z7 M# t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. w, H9 ^) ?" e: T# t: [( T' m' A$ kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& h# X* m# y8 x2 Y9 IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* _$ ^7 E1 @2 x# uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 ~1 R: l/ k- G
}
- t+ f. `8 ?8 ~6 z& Y% c2 k# F( _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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