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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 \% c( s# P3 k) c1 h" ^input mcasp_ahclkx,& D' W2 K$ X) z- Q% D
input mcasp_aclkx,
6 d5 O# D' P, P# Minput axr0,
- {8 Q+ c M$ G7 ~" N
5 E: g: T" b. Ooutput mcasp_afsr,
" P, e7 Q k, L( l5 F1 Z0 Houtput mcasp_ahclkr,4 _" X/ x4 q6 O' w% ?- ?' U) g
output mcasp_aclkr,4 [0 Z' f3 p; }& z4 S8 O
output axr1,6 I$ l) T' h! O/ j
assign mcasp_afsr = mcasp_afsx;
' b: Y% m: _. _assign mcasp_aclkr = mcasp_aclkx;0 ~) w. K# ^- \7 J% Q9 N% I' b
assign mcasp_ahclkr = mcasp_ahclkx;8 D6 R0 @3 g/ }0 S/ P/ W
assign axr1 = axr0; ( `% {0 ]1 }; J; C1 o. \7 n v
- c7 L5 M% l* r7 G" q5 `, r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
H3 Y0 ?; P$ ~static void McASPI2SConfigure(void)
% ~! |5 K/ x1 U{
/ E+ `& x; T b' K% ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);# a& Y4 `5 E( x2 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 p( f+ _! w/ @4 \5 b6 v1 R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; p2 p( M2 \8 F8 D6 SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% O) \0 o4 A s9 \! f. y r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; O) p% |" P) y# u+ |$ T5 @
MCASP_RX_MODE_DMA);& v8 I+ o' [- ~% R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, m2 e% g _ M' ^% ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' h6 G O5 d# _* [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " O" Q1 W6 k- K, N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ `$ |' U/ C. B& w6 K( _: {% L* `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 M7 s$ A* \$ D- j' f2 A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- Z0 ~+ B/ [% c/ I7 d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 f# L5 f/ N8 l; O% q3 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 s0 J) |, p( J% k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 e4 i r$ Y1 S1 B$ `$ w* W0x00, 0xFF); /* configure the clock for transmitter */
7 J& R X& j* A! N) X2 Y% V, uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ H+ d2 o x6 K0 v5 }5 \* [8 D0 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % i! s7 A# d8 P8 H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ H" I5 ^( J" W' j1 @0x00, 0xFF);
# c6 d; `+ r4 B* T: |# S1 I
% H. v2 x# J# i/* Enable synchronization of RX and TX sections */
5 ^; ^5 W' N. r5 o& K3 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" ]4 ]* q; i& _5 g7 H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& p$ w0 z" d4 ? pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 }0 @4 N, H2 M4 ^* H
** Set the serializers, Currently only one serializer is set as5 Y5 |/ f' I# x1 G' h7 I: ]9 d
** transmitter and one serializer as receiver.
4 w% s! o) j0 l; Z# E4 W( v*// v3 p" U+ R9 P& S1 d% j7 R }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' ?' k" ]3 W F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- l( z2 E I# I/ q8 c9 z3 r
** Configure the McASP pins * c; I F4 y2 P+ O2 [, R: E% @
** Input - Frame Sync, Clock and Serializer Rx
+ L* m8 j- l8 @8 ^) F2 @** Output - Serializer Tx is connected to the input of the codec 9 L- [4 W o/ y: z; g0 k
*/$ e' P9 p) K* ^1 F/ R; v' Q4 |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 s6 U w Y, w4 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* c, o! |7 R3 } x4 J. V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& b: R! \8 E ~1 f* S: x
| MCASP_PIN_ACLKX
5 I$ J& V+ R3 I( h| MCASP_PIN_AHCLKX- Y% P9 `9 w3 h1 k; w1 Y! P# C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, K$ X1 t1 m ~7 m A7 p6 J0 KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 \9 }* p( X9 W- [3 d
| MCASP_TX_CLKFAIL + P* e; E' x( F. n0 ~
| MCASP_TX_SYNCERROR
; M6 B7 Z# n5 s. D% k1 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: n+ F8 X3 \9 f3 g; `1 M/ c| MCASP_RX_CLKFAIL$ B. \- x% X: y) E8 J6 C. U# u
| MCASP_RX_SYNCERROR
% O$ y5 L5 f. k! ~3 @| MCASP_RX_OVERRUN);5 M/ t6 N7 ]. |3 P% l
} static void I2SDataTxRxActivate(void): b% e8 P; I/ p
{; Y9 c7 u f6 _8 \
/* Start the clocks */
* N; @) D9 a5 t0 c7 S, y9 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 u1 \4 [: Y7 {5 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. S8 T. x. y+ e. q) \, B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ o% C" d) m: x! ?; GEDMA3_TRIG_MODE_EVENT);
8 |& D/ f" D7 {0 A, a! l4 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 d% q' t$ k1 D7 o7 QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 t2 e. W( E+ c' |9 Q6 G' U3 M+ M2 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 [ ~; g' v s- w2 x* ~% i, U; tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" n/ q5 T0 ^4 Q4 V3 S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# |, H' X& S9 ]; k, }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" S1 e# d1 f& d% n j4 a0 v# eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) g0 B) F7 B5 P* P# Y8 w}
# O; D, H: C4 f8 K6 [5 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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