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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ \! O" ]1 R1 H$ s- B1 finput mcasp_ahclkx,0 V C5 n- q# e6 J. t
input mcasp_aclkx,
" w- P# N5 s. l1 x7 i- oinput axr0," p9 m* l& P& @ @$ J
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output mcasp_afsr,# L. D5 l/ E5 v1 x
output mcasp_ahclkr,6 Q, A+ U# T8 V9 e7 U
output mcasp_aclkr,! L" O- Q, O. n f/ }1 s
output axr1,
) h- c# L! {* \) q" o/ t1 Y1 M assign mcasp_afsr = mcasp_afsx;4 W! N% a M: T! H
assign mcasp_aclkr = mcasp_aclkx;9 n' {2 m2 q, Y, F5 B
assign mcasp_ahclkr = mcasp_ahclkx;
' s- L1 C/ A- [# kassign axr1 = axr0; " E: n8 ?$ @- \$ f* Z4 A$ Y
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * ~2 T* X7 e% f0 \: @) P ?" ^5 c
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 @* k! q) e8 ^$ X$ v9 [* O7 kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" _, h& h0 ~ J' W* p3 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" n! [. l; w: G2 c4 U/ ?3 |; E4 WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 X2 c: T" o! F9 P$ ]7 }* Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, J' q( V/ w0 w; m* T4 ~/ qMCASP_RX_MODE_DMA);1 u8 f4 u' H! s1 O3 L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" a1 q' M9 g& z) JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; U/ z$ G! Y( H3 c" EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 p6 r+ X6 V, G* P4 t% KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) U7 I: m, L7 lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( L, }6 _0 h: s$ c! tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* k/ h7 Q8 U e* d! r% |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. ^4 B {) ]7 b) R2 c' I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 T4 u' s0 D1 K7 P1 H" F& YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- w j& f$ c% J$ N0x00, 0xFF); /* configure the clock for transmitter */' G! [9 z7 f$ ^7 ~3 s5 T$ Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# Q1 Q% f' S2 f& a% k0 U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
}6 p4 \8 v+ ^- a3 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 {0 R# z5 Q E0x00, 0xFF);- A: s- u2 z C( K
" |$ t( {, f n9 f0 P, r/* Enable synchronization of RX and TX sections */
b9 a2 Y3 ]# |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ [* N5 v1 L2 L; L' O. i) ]2 d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 R& B9 t: T( D2 eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) G* r M: K1 j$ Q8 e0 `% A** Set the serializers, Currently only one serializer is set as
6 ?+ B% K9 Q, @. ? v0 l) e# ?9 p** transmitter and one serializer as receiver., T! H; K3 n$ m' J$ |" ]( [
*/
r7 v1 h# h) M9 M! CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) \; W5 h% ~5 ]2 a* s5 c' n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 C0 [1 ^8 A- S1 Y** Configure the McASP pins ) C& }2 l) X# d( y: [' C' W. y
** Input - Frame Sync, Clock and Serializer Rx4 B( J7 K: b" s9 f/ y7 `
** Output - Serializer Tx is connected to the input of the codec 0 f/ X$ ] r q5 Z# K
*/: H; o8 n7 o) v* B$ q+ t: L% x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: j4 p7 \8 P# `$ y* H# Q& gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); x1 c% _* Y3 o$ u e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 F2 S' S" G* R| MCASP_PIN_ACLKX
- i! V; {2 V. c# \" x q| MCASP_PIN_AHCLKX
5 K& ?3 [2 U3 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* U B0 J& O& `. G6 x. L' X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . o2 m2 g% R( Z) R3 `* r
| MCASP_TX_CLKFAIL
2 F. R: B; G7 | x# K" S4 k| MCASP_TX_SYNCERROR
F0 O! K9 [. E8 R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * ~ `, l7 P7 e( c6 h
| MCASP_RX_CLKFAIL2 M- Y: y2 { v" G9 K! P" C
| MCASP_RX_SYNCERROR
7 K, J; V1 \9 N| MCASP_RX_OVERRUN);
6 Z/ b$ ~2 f2 k- `0 _; |} static void I2SDataTxRxActivate(void)
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% J4 M! x- {' C2 y4 }/* Start the clocks */
% U) o' M: j- ~, e' _ sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ M7 M h$ g. E* Q: ], g) e( [( m7 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# N- H( h1 G3 t2 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) |9 F& y( ?* c% w5 }2 U$ y* u/ L
EDMA3_TRIG_MODE_EVENT); {& ^7 }6 [, C. t) H- B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + M& r4 h$ o* `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; P. C/ \ r" `4 s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 a/ \4 w0 c1 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" ~. B( I/ P' z- h o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 _" x! v5 z# f: [$ O6 O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) P( @+ G. m; H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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