MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
6 M1 ?/ ?4 i  V- b! C* y: Uinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
/ {1 \3 X6 N) ~# H7 koutput mcasp_aclkr,
& I0 W$ }7 j1 d6 _- z1 houtput axr1,
% Y# I, K/ T' @7 I

assign mcasp_afsr = mcasp_afsx;
8 R8 u8 w# K2 H2 V& uassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
, D6 W, a, Z+ x: n1 o  Nassign axr1 = axr0;

& V: R+ K) Z  Y& r. W3 v

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

) H# |2 _+ N& K5 _! B

static void McASPI2SConfigure(void)
8 W7 x* |  }+ a4 E3 W{
5 |) f! l+ J( _& HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 ^0 d5 E0 S2 n9 e* ]! a3 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
0 J9 _- X3 c: A1 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- j- H  D1 f" B7 b6 g( OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, B  E2 ]: R# @# P+ L4 xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- L* Y9 _' i$ {) O+ e) MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 }& F1 `  \, }& {% }# j0x00, 0xFF);

/* configure the clock for transmitter */
  G' U4 `1 Z" B$ X; GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# L' C$ W+ m6 L6 S+ C, n. FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 N( ?/ ]( e* T; n6 gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 `* s! Z3 D: ^+ P0 n3 ~0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
" J# V. E& W, N. A** transmitter and one serializer as receiver.
: w& c! ~4 ?: g8 e- S: ?*/
' x; H0 _  t  H. ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
" m: P' K1 o* U/ R1 W3 i" h" m# U( C  [** Configure the McASP pins
) v# `+ V+ h; f  K1 n* x** Input - Frame Sync, Clock and Serializer Rx
" q. b- j$ F1 t- H1 f5 q& L** Output - Serializer Tx is connected to the input of the codec
! d, s; q* o9 V7 ~  n) d3 R! F*/
' n* m+ A3 i- P& m4 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 ~) _" x; ~  a/ X: U& _5 i6 f6 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
7 f$ j$ Z3 V# k9 [$ G| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
0 @% G1 o* h9 t7 l. |) DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
/ a0 f7 T, G7 z1 I| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
1 j9 `  I% ~; M* [) b0 }| MCASP_RX_SYNCERROR
# v# e" i5 k5 @3 A  `: w| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 W; H" c# g$ LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 ^& i. M7 ~( ]1 E! \; KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% i& @8 w% B* y& l6 l* EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
7 c" m1 S( H$ G$ t4 ~+ ~! H: Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
2 |6 j* s4 y7 b7 t  Q& V1 j3 sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# M# E( n- m' \  aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.