MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
% e% l" Q! x' V5 R4 y% y/ Cinput mcasp_aclkx,
) H8 c1 z% D: s" F+ pinput axr0,
% e/ L# Y  Y' y/ t- }
; }! c+ K7 F: C4 Zoutput mcasp_afsr,
) U' j/ `% i  T4 j2 V7 ^output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
8 h5 ^5 h7 v/ G+ }assign mcasp_ahclkr = mcasp_ahclkx;
- b* Y! O+ P) {# W& ]assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

; j' I1 M4 z1 Q. l. l& U; a  x

static void McASPI2SConfigure(void)
  Q+ ^2 B/ k1 T1 A{
3 U7 @) ~0 M! w4 i/ p. fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
2 w: X" c1 R6 r* lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& Y+ s0 A+ u" y/ h5 R7 K4 k4 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ k  i$ ~* A3 s1 UMCASP_RX_MODE_DMA);
) {, o- F) O/ h2 V6 J$ c. a6 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
  B7 W) u% y& ^- j. v0 h9 Q: e' `MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ |' L$ S: P& O% b0 v1 d# B4 {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 [' |) i1 M: a/ h) e* C7 F5 N. U% QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
( s0 D5 Y5 p- h) |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ n+ b% W! {; Y7 S! X$ g! F& N4 DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 s7 n. B5 a! n+ v3 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( P! n6 e$ _- E! e) \1 ^# t/ c2 l7 [0x00, 0xFF);
+ H! Q- w& g: b& c1 S! x, j2 P
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
* f  _# p9 H$ f+ ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ W+ v- d9 q) A/ pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
0 H0 K+ q7 j5 ~5 S. |+ z4 [** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
. j) p" `" O: j4 O0 ]" R2 X2 @*/
; y0 ]7 h  V- TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& L: h' h% Z5 S! L- i  |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
- t& [1 A" e7 f5 R** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
2 [, ?# ~, k, ~** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 F0 O" d' B  {# F* lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
& y( ?; Y: I1 {; l/ x' r| MCASP_PIN_AHCLKX
3 j& {7 y9 g0 A# Z8 R' g- W| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
7 e* r; B# \4 Q9 f. Z; p& q| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
& e  W8 k& z& w2 [- y| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
3 p9 z# ?/ w0 e. q4 l+ m) z/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 N) Y- Q/ M" n: z# V9 bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
% W6 j* L  G; z/ X" jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ r$ \4 M, R# v0 F( i& H8 B1 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
6 s, ?$ r" N7 i/ @7 U0 Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& W$ R0 p& ~% ?' ]; _+ x+ O1 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: D/ O& q, `; m  @8 E}

* N/ K$ K. n3 W$ y5 z

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.