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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 U8 F- V2 D) U$ v& u$ `input mcasp_ahclkx,
+ y9 ~& O, ~' n9 a' m2 h6 |4 j5 winput mcasp_aclkx,
1 v8 ?7 g2 I4 _6 F+ S, Dinput axr0, s0 u: y5 t7 W/ J7 e- z! I/ D
! s2 Q0 j$ C) `
output mcasp_afsr,
, z$ i$ `5 Z' a! ]% Y) g3 e$ Uoutput mcasp_ahclkr,
+ k$ Y' Z* i2 Xoutput mcasp_aclkr,! Q; T0 ^+ m/ \0 o1 M
output axr1,
9 u, Z, Y1 E# X9 k2 L' }; C assign mcasp_afsr = mcasp_afsx;3 V$ x7 L4 i( k3 k
assign mcasp_aclkr = mcasp_aclkx;
, [" U- ~1 w y$ dassign mcasp_ahclkr = mcasp_ahclkx;1 \% T, Q* q0 e# C! w
assign axr1 = axr0; 7 D5 i! U0 D3 S5 ]: B
) C" D$ b# q# ^# W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' B0 y! q6 C$ S: U: C3 C, Z
static void McASPI2SConfigure(void)
2 P" d# M- v: L7 E$ j{
5 m8 s; [9 z$ R5 Q- {9 H% n" gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* g- ~% U- V0 v4 G5 l8 W' f, B' eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- k4 A/ e2 b3 U/ _9 G* w2 ^8 C. AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); F6 E/ t+ Z L F" Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( a% y$ F, h; T0 ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ B3 G) T( G3 n( H j7 s) H
MCASP_RX_MODE_DMA);
, N4 X+ E) ~; n4 ^8 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ L2 U- a* d. MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 C5 I: l% d' k9 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - Z0 E" W( w* |: C7 I& r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% U n) A$ \9 j1 w* v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - j, y; O3 j8 ?' D7 b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 z! `# w2 H, S* a4 W9 }8 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
R$ w' V# l* r; A iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! ]* N \$ w* qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 Q* T3 { ]' y2 w! h+ `0x00, 0xFF); /* configure the clock for transmitter */. ?1 U7 E4 Y$ f. d" m4 @+ {) f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; L! W% X. E; R0 a6 ]1 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ i) D* D$ R3 H* k' Y) oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; ~" n( ~* _8 F) B$ S0x00, 0xFF);3 f# v. z. t5 ~8 M g, L* e
: u( ^7 ] e( }5 x$ r0 |* }! T
/* Enable synchronization of RX and TX sections */ 9 a. s% t) p3 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// ~: X7 w, ^9 d3 W* P7 G4 ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# l1 R* @0 `) P3 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 D9 M4 Y& F" @* E
** Set the serializers, Currently only one serializer is set as
) i0 C" b1 J% t** transmitter and one serializer as receiver.
8 @7 K8 L y# [9 `1 G*/7 o; L" k/ w) L1 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ ]. d' r- N$ ~3 s4 o- `+ z; U4 b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* q3 E' z1 J/ m
** Configure the McASP pins
1 o& r: v8 k6 f3 ~2 p( y** Input - Frame Sync, Clock and Serializer Rx
) M6 N! A" Y. z1 g. p7 H** Output - Serializer Tx is connected to the input of the codec
" {2 Q. B, r: f4 r2 X" e4 F*/
3 G4 o& j9 i/ H0 ^; dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 K/ M& i: o5 a& R/ t( D2 r! B5 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* n6 l( u0 d* E, H. h- p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! l7 [9 [9 l3 S1 x; D5 I$ Y| MCASP_PIN_ACLKX
S% j) c" J; i$ i7 H8 m| MCASP_PIN_AHCLKX$ K. z3 l; K: ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* d/ W; |0 f4 {& `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " p' P) v6 }' J" x# \* n
| MCASP_TX_CLKFAIL " q) e8 r) s; G# {
| MCASP_TX_SYNCERROR0 D2 q; t0 U- }' A9 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 E& A# h" F9 f. y% a/ R| MCASP_RX_CLKFAIL1 o- { s) M; A3 D$ ]; \
| MCASP_RX_SYNCERROR
& n( S5 x0 d% S Y| MCASP_RX_OVERRUN);+ i0 s# c( C6 o: x/ t( V0 l! o
} static void I2SDataTxRxActivate(void)
5 a1 F. V" G$ c. [" }{" K) e8 r7 B; x2 o+ A8 H
/* Start the clocks */
' ]) u; O! H: mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, p' Y4 a- ?6 o. ?8 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
w) K9 l6 F+ D( x7 T6 T# V0 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* v: _6 n& z' l. k0 _EDMA3_TRIG_MODE_EVENT);
, b) q9 J4 l- O5 t- d: lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 n3 a) V+ e) c* J, MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ x5 j2 M( E' dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 `2 [# c1 U; m* E" j. [( _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ z4 D( E+ _- W; g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 b: R p7 o5 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) C9 }/ b. m+ h: n. n( Y. `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% m- W& D$ E8 K2 k9 _
} ' r1 V* \6 w8 r, w! c' ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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