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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ n* t9 x, i5 G, o' H9 W1 Hinput mcasp_ahclkx,
0 x& ~* ~; _. g% j Oinput mcasp_aclkx,
- [+ u. z$ R J P" n/ linput axr0,
4 P: T! o9 \! \& a& U4 u y; D9 I5 ^- W* ^ \& N4 y: |
output mcasp_afsr,6 y. Z3 `: q& \6 n
output mcasp_ahclkr,
; d5 J1 Y/ E& j2 _( moutput mcasp_aclkr,
1 E# w# |6 y+ [* Foutput axr1,
5 R4 o8 j0 h# m( a5 y assign mcasp_afsr = mcasp_afsx;- E. i+ C& Q4 Q% L
assign mcasp_aclkr = mcasp_aclkx;
/ n, K" o6 b0 L7 J" ^assign mcasp_ahclkr = mcasp_ahclkx;/ R% A# c6 s2 B( \
assign axr1 = axr0;
& {- {. m9 ?; y6 e$ e% D6 Q
( o6 e: j# i# `# N- F0 L- g# \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! S7 M6 h+ `+ {& _4 z9 |
static void McASPI2SConfigure(void)
/ {9 v2 H8 N! W* }) z# S3 A{4 d' k5 W! V( P; K2 f1 l, a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: C( I1 Z" m0 |2 jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 i& ]7 r2 G+ K- s) ~- u% ^) D6 S; I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& Y1 {% l. D6 D3 P8 nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* f" y8 t! ?6 \. f/ T1 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ I; D# z9 P% N" g9 x7 |6 t
MCASP_RX_MODE_DMA);
0 u8 Z8 I9 g8 n; z) DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: i" s9 o& f/ i0 D5 YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) U1 X! i: j" WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! {4 o& e, c/ z- A0 fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' }3 {1 |2 e3 X6 Y3 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# H" j4 }' I% s2 J) z4 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 [% Y" e! \6 C( S( S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 }5 f; i9 _9 x$ q: W6 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " {, G6 f' Z! V3 [' g( x# l) n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ a2 c D a" Z) n% r+ w
0x00, 0xFF); /* configure the clock for transmitter */7 |* K: p9 U1 S5 L; g9 w {! W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% J& C1 h5 ~: y6 n* k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ K5 n0 V! M O( d4 \5 AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 [7 C2 I; _! Z3 |! S; ?0x00, 0xFF);
* m6 _0 D' A6 l" y
/ o3 e& Q2 y2 A! J# d. B' A0 M/* Enable synchronization of RX and TX sections */ 1 ~" W' s0 O: b3 @2 _, l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& E! h7 \! g6 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 x" D8 T9 K3 Q; \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 s" G# Z, O. T, @1 \- I* h
** Set the serializers, Currently only one serializer is set as: s4 A- }, E( r+ |# M, N
** transmitter and one serializer as receiver.
& W( N. u4 l* w# W& C8 r*/& @7 q* k9 S- O! G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 b W; I1 a, e! \) K. T8 JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 J8 P5 o7 z4 j# N( O** Configure the McASP pins
. R! Z8 K/ e( h7 Q2 l** Input - Frame Sync, Clock and Serializer Rx
9 Q; t$ r' N) {8 Y' Q** Output - Serializer Tx is connected to the input of the codec
: W( d$ N, t& v7 D0 r: x*/" v; o' o! g N. w: K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& g( P4 q* j/ ~* G& dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* g2 F2 V; [& s- B5 y1 HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" r* W4 n! p3 x% H) Q
| MCASP_PIN_ACLKX5 q: _/ L3 K; c* g
| MCASP_PIN_AHCLKX
- r4 v. |; U, v P, i% Q/ ^4 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 v8 @2 @1 o& m6 D6 R7 B) M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ f. {1 Y) U' l; i| MCASP_TX_CLKFAIL , b: J3 f% U& G: b8 B8 @6 j, f, T
| MCASP_TX_SYNCERROR
8 E$ V" X' d, `9 V$ M' ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - f7 G I) Q w, a
| MCASP_RX_CLKFAIL8 S2 m2 C; k% Z7 i$ ]: j' V
| MCASP_RX_SYNCERROR 1 p3 z0 p6 k) b' _
| MCASP_RX_OVERRUN);
: o Y& J* I. W} static void I2SDataTxRxActivate(void)
, d% X+ ?* K9 f2 y$ Y1 v{& m( |1 x% t4 [2 A0 S0 C: @ z* c
/* Start the clocks */
: W) E4 F. T+ D' P7 q0 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. `- V( Y6 C! a1 R$ Z+ [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 \0 _) U# N/ W) A. g* @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# Z* I9 M+ \+ ~& O7 D5 Z% TEDMA3_TRIG_MODE_EVENT);, a0 \0 N+ ~: Q$ X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* W) q3 q: U$ Y+ F# P1 r5 o* |" YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 q3 |4 J' c2 V. o! ^& a* D5 l! a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 Q+ [$ y( b2 T, H4 v) uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 j0 {: W0 Z+ ]! e/ m5 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: e) _$ _9 z. Y! o9 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 W8 p! C4 R3 x; F3 e% v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: @4 i$ u" n# [0 w% q% y& u& v
}
$ q9 p& I4 c+ I! k& L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' |. f9 t, ~6 k6 |# _: P# l) v" b' [
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