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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 o: @: B4 o- D, }: p Xinput mcasp_ahclkx,
) P8 Q; H3 s/ u) X }% linput mcasp_aclkx,
) r6 W7 h4 s: l3 b5 kinput axr0,
! n+ v- \, ]% o5 s- z c1 c0 L" Z) B# Z/ G! R
output mcasp_afsr,* |- `9 N' f4 {) D# Y; Z7 M
output mcasp_ahclkr,6 g {% I7 X9 R8 Z5 q, ~2 k
output mcasp_aclkr,
6 z" s6 N i) N/ a7 K! ]output axr1,
3 Q; w M h6 R assign mcasp_afsr = mcasp_afsx;5 C1 t$ [! {, N" }
assign mcasp_aclkr = mcasp_aclkx;2 J7 [- t" h- k( w8 f# e9 m
assign mcasp_ahclkr = mcasp_ahclkx;, c5 ?9 W6 q( E
assign axr1 = axr0; ( p" |& u& m; c" c9 h. ^! K, N
4 G( D: _8 y2 a# c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & ^5 ^- B' u; @ P" x5 q
static void McASPI2SConfigure(void)
! C( k9 p* ]3 u+ N, R2 x; @{; x8 x2 [! W. e# F5 W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 g3 Z& A2 a: h% t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 F# g. h8 E1 R, O4 Q8 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ E5 V3 d1 E( {" h# g# x, qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 h" s! u2 _4 W$ j9 X/ NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 x, s4 s1 Y+ v) t. `MCASP_RX_MODE_DMA); D x$ F# y4 M+ w; m) C' S+ W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," p1 t3 _% d) d$ y, g, @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ y1 V- J8 l4 V0 o' X" }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 V: u! u d4 K( a$ b. pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 m; i2 u# d$ T. u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 S# b* r4 T9 s: ^# J- ]$ Y) dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- J$ ?- x( Y8 V% cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 n# C2 C0 @( e& PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" H; S& v1 A: c4 I! p6 TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 U, ?0 z( Q n" V: a s
0x00, 0xFF); /* configure the clock for transmitter */
' B5 ^1 P8 m/ m. V& d! ^& iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ G, A4 N1 b/ g$ L* t7 [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! q M4 C6 x+ B' N2 eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( |4 G" w+ n. [% M- J2 f% O
0x00, 0xFF);
( d9 O2 [5 ~, K' P' x l+ k2 V' W: r" v7 f |/ P
/* Enable synchronization of RX and TX sections */
4 ~3 x7 z5 f# Z* y3 H1 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 b2 [) `- U$ ]: o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" ?! o2 s: a8 R) _3 X" k2 |) Q3 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- }- R1 v4 Q. E# o/ B+ Y** Set the serializers, Currently only one serializer is set as; g5 m+ s1 r+ |; v
** transmitter and one serializer as receiver.+ Z$ G0 S, m% n
*/
3 \- X' @8 E. D cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 l3 C# ]) I! n8 a* P% d: d5 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& V; B( k- D! `0 z9 G& ~6 m& F
** Configure the McASP pins
8 z3 ^% |# X) t9 B- |& V U [, ]** Input - Frame Sync, Clock and Serializer Rx
`$ f2 [. Z! [+ ]** Output - Serializer Tx is connected to the input of the codec
6 W. C" T0 w4 K0 H1 e# }*// k$ g% q. i% F# ?. l u; p9 {5 S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# l% A# y# g/ r6 x+ b% w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- y2 w: u: u5 I( n6 o1 l$ PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 w1 E4 d6 R* S' L# g2 L: n7 v
| MCASP_PIN_ACLKX3 o& X% _. ?1 @( Y. J
| MCASP_PIN_AHCLKX2 f$ ]/ S8 z y" l: R# s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 i5 W. M) z" R. s* _4 ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 b5 r0 S1 M6 X% a- v' Y| MCASP_TX_CLKFAIL % j$ t- h2 X- w
| MCASP_TX_SYNCERROR
$ I5 Q" ~5 r6 I8 y2 h& \2 z$ k/ @( L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! `2 n0 k7 I. r0 B8 d3 i& H
| MCASP_RX_CLKFAIL
; I8 S4 [( P5 Z( Z3 f4 A% `| MCASP_RX_SYNCERROR
2 J$ f3 g* b+ g3 Y. S, \( j| MCASP_RX_OVERRUN);
6 w: E. C9 Y" X _} static void I2SDataTxRxActivate(void)
; p" j/ l6 P4 Z9 g: O{
2 Q/ D* z# D/ ?2 @; Q! c: T( `/* Start the clocks */ `. o! i! o& U; e- r' Z6 @' g* a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- V4 V' {. l2 MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 l& Q" e3 q2 H$ T ~# T) C6 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 m; v b* ^5 z% C+ K! ^
EDMA3_TRIG_MODE_EVENT);# o6 L1 c: S5 d. J/ C2 F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % P( ]1 d/ m) x( s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 I2 i1 y# _+ C5 v+ {8 e* V) l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! \" [7 {0 b j3 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 O" k. P5 a; P0 n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- V, z8 b1 Q4 k3 x4 JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 S; J$ r% [5 O+ f3 Z% o! X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. v3 q3 J. Q' e1 z2 f, p& {}
. v) }5 a8 s0 l0 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 {- k, L) L8 T2 l' P
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