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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& f7 L3 W, |" M( v4 U, Zinput mcasp_ahclkx,
2 L( D# q0 P( C6 b9 hinput mcasp_aclkx,
3 P* D9 x9 z, `; Binput axr0,
6 l1 L1 D) [* B* @) ]& C' v# q+ Y* Q' Q4 A m& ?
output mcasp_afsr,
# |" ^$ p& H i3 koutput mcasp_ahclkr,
6 i1 X& G3 e: e% ~output mcasp_aclkr,
5 P2 b# F& `" }" g. woutput axr1,
* v; _0 Y5 M) L6 _! z assign mcasp_afsr = mcasp_afsx;
9 w" }# p" C; r$ `8 lassign mcasp_aclkr = mcasp_aclkx;# @) @) y# I$ E" w6 ]+ u
assign mcasp_ahclkr = mcasp_ahclkx;
3 L% V5 h) `2 t7 ^: H: A' _assign axr1 = axr0;
- y5 H3 F' c" P$ _" |" @/ v& H& g, [0 ~! `9 J# H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % O2 x1 E5 Z4 g& S, n3 z1 z
static void McASPI2SConfigure(void)
7 h% m2 C6 o- W" E, p5 n{1 L5 g8 h |7 _
McASPRxReset(SOC_MCASP_0_CTRL_REGS); g, F$ P9 @9 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 a2 Y4 ?5 G0 w9 O' U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( I+ {- l) j6 B% Z, u. I# oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* c. O/ {. G! }1 x$ {0 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 u! _6 G9 x6 r7 O2 O9 FMCASP_RX_MODE_DMA);
- {0 m' F& d) MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
K) K$ q/ \( N( EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" C, R& ^5 ] ]" I7 H" w. rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, y7 O: @& `2 Y3 ~: s( @' a' OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- d. x5 `8 A8 s) `3 H( D9 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' s+ `; z \, W+ U1 ]/ MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 O' o. H) n$ H1 O' T" G3 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, W1 Z" S+ _ ?6 W- DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) A, {# c4 h I; f! F2 y0 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# E/ w! K4 _" p% t0x00, 0xFF); /* configure the clock for transmitter */
; Y( t! a+ I* i+ O& A- C& aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 Z- P9 w/ A6 T( v7 J6 f, W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 m4 A9 ?2 g5 }' S- u6 j/ uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 I) l) g4 o0 I3 a/ P' b
0x00, 0xFF); D( e' h/ E% G) U( k
4 F9 B' T5 d0 E% D, [$ b1 _/* Enable synchronization of RX and TX sections */ 4 Y9 }0 J- r3 u \5 H4 ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 r1 A+ }. a4 ]( V. W" P" w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 W( A v: S# ]2 [' X4 QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 A& s+ v, b% `9 O' L0 R. ^
** Set the serializers, Currently only one serializer is set as+ B' Y: g9 q0 i; P% m
** transmitter and one serializer as receiver.
/ q0 F- B5 q) m( _*/
7 d& F W7 g! t* J. ~6 l R' }1 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% s$ p( \) S* Z5 q! F: B6 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 y! ?+ E9 _1 D+ z. y** Configure the McASP pins 3 i2 k! d3 [+ v: H k% J
** Input - Frame Sync, Clock and Serializer Rx8 I @$ m8 l( k5 s, P# t
** Output - Serializer Tx is connected to the input of the codec ; b1 E* ]9 |( T3 Z: r( U' p. L+ g
*/( s* d u, F$ g" v0 b* Y8 c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. ^1 A" v/ I U3 _% I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* a# u) B# A* O0 z% G' Y+ A( {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; {5 L ?5 x6 Z
| MCASP_PIN_ACLKX
! N$ ]! l9 ^% E/ ]2 C| MCASP_PIN_AHCLKX
# C6 ]" @2 U9 c R2 C0 W6 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, x! |* F( d) ]- G5 Z) Q2 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! T4 v6 I* y5 `' H% {
| MCASP_TX_CLKFAIL # O2 M4 B; M: ^" j9 S y7 q5 ^* P
| MCASP_TX_SYNCERROR* Q! `4 V6 I& N* N2 ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ f, \9 {! I& `% ]/ A7 L
| MCASP_RX_CLKFAIL
7 D6 D% r& X8 t4 S m6 @9 y| MCASP_RX_SYNCERROR
% R$ r/ j, O5 w$ M' G| MCASP_RX_OVERRUN);: F5 `' n7 ^8 _7 O/ Q# a* ^& d
} static void I2SDataTxRxActivate(void), u3 s/ c b* J& x% m
{4 u; {% y3 M- ~7 T. q
/* Start the clocks */
6 s# Z# E! \& r0 G7 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ y' u5 K A# l% o% |1 K+ aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 A; a% @- P* G! e( ]4 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* p& N) v4 x# [+ sEDMA3_TRIG_MODE_EVENT);& b0 D* Q5 ` `) _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 `3 k0 ^, u3 n5 R6 W8 s6 g$ l8 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% D8 ^6 e1 h% @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 g8 j3 S" _) Y: T3 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 N4 i( W4 b3 v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* \4 J: s: x6 y6 p- s9 V6 b: ]4 s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); L& Z+ d! u4 {' w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' [6 `/ n0 j* Z/ ?} 5 C5 }" }9 W7 i9 t5 r0 ]: {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( }) R( n! O* Q+ R/ L1 X1 F
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