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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; z* X3 W8 [- X1 x5 E! H
input mcasp_ahclkx,
/ p" G& q. X6 }3 H9 @# t: f* Pinput mcasp_aclkx,) p, {7 \8 @' M- o) `
input axr0,
G$ Q- y9 ^+ T5 n0 w( G* ]: }2 I. y. D* r
output mcasp_afsr,' a+ |* D$ b9 f3 J! s+ X3 w* [7 b
output mcasp_ahclkr,
: l s/ q$ h$ x) U/ p1 p- o+ Boutput mcasp_aclkr,+ s. d: o# E) n7 U# o5 c, P1 P. h
output axr1,
+ M; Y) `5 k4 ^4 ?, a assign mcasp_afsr = mcasp_afsx;. p6 ^0 [' h' O) b9 g
assign mcasp_aclkr = mcasp_aclkx;
- ~2 x) b- f$ | j$ t9 Gassign mcasp_ahclkr = mcasp_ahclkx;
1 c- |" E1 Q7 g* y/ rassign axr1 = axr0;
* v6 w" _8 h0 n5 L; M3 c" c0 S( y# ]& d- @+ ?. w, O+ Y1 H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 Z5 L, \2 c }% ]static void McASPI2SConfigure(void)0 g) c( E3 j& b* H( } [$ U
{! u, G6 E, A/ p5 l- a3 T& T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# _1 A9 z( L. c7 r; vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 M1 f! w: u# s/ Z2 ]2 n) l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 m8 w% D1 L7 y+ ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ @# T- L, [* n; qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( U& G8 S2 C0 H& l- Y0 s
MCASP_RX_MODE_DMA);
+ K$ X8 P) h. mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 V& v2 K( Z8 t" A( y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 P* H$ o2 U8 E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' q" ^' S4 g5 [" k5 X& K y% {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 w/ s1 ^1 Q5 m- F" F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- }( x: i( W: K! d/ ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; W3 `! O/ B: H4 W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ I0 m/ x6 v* _ s" {/ EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + U5 a, w9 J! R4 k" f8 e! S6 \/ d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; F$ x N8 @# z* T/ ^ z; L
0x00, 0xFF); /* configure the clock for transmitter */3 v8 z6 F: i0 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! C3 x; o( F* P* v4 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 F* q4 j. j( ], @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! P4 y6 y; b! d, _. |$ P
0x00, 0xFF);' t d3 Z; B6 e# d) D
, R- E# f5 z, U) V9 g1 d% q8 |/* Enable synchronization of RX and TX sections */
) w9 l8 v7 m" c; ~: X1 hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; h! M" w y+ n7 o" }4 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 T3 f: I/ Y8 b5 ~9 i- y+ z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 B6 v" M, f( |2 |3 _! O
** Set the serializers, Currently only one serializer is set as
0 x7 l/ s* n/ \3 ]** transmitter and one serializer as receiver.
" i; q- d" x% Y) @$ P* x C3 L*/
5 r! \9 e" |4 @+ J$ \, lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 F. g# |4 T8 ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 y! u N$ t3 P- {; f2 q7 u** Configure the McASP pins : r u7 I8 [( `
** Input - Frame Sync, Clock and Serializer Rx) V( `7 a8 K" P# K
** Output - Serializer Tx is connected to the input of the codec
7 u4 b) m v# T' M*/
5 A5 N% L( s: r2 T _/ b) GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ N2 ?( z3 R0 G9 h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. A( ^2 s# E* }* NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# F0 {' {6 n/ N0 j* w| MCASP_PIN_ACLKX1 N' {" j4 c" M% Q
| MCASP_PIN_AHCLKX8 _ \/ s$ ]2 v0 y4 G4 B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 ~1 @! N; f( h- P, M1 W* s: y, J( N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# f7 a1 I7 S; c7 R9 Y% {| MCASP_TX_CLKFAIL
( ?& k% w% i# n4 F3 _4 w6 f$ n1 t, e/ S| MCASP_TX_SYNCERROR
6 ~! B4 t) N# j0 f9 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - e& D: P: G$ d6 U
| MCASP_RX_CLKFAIL+ {- a( Z9 m% T1 B# N8 s
| MCASP_RX_SYNCERROR
4 }, R4 R. S! E| MCASP_RX_OVERRUN);# C. W5 _) I4 `) U
} static void I2SDataTxRxActivate(void)6 M% N+ [* h; k) t6 J
{$ P. A0 J& N- s. D
/* Start the clocks */
* {7 V8 N H8 J2 P3 z' eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) K) ~# _& `$ i4 eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 i& }! E' b8 W3 b- W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! p3 f8 J2 ^) C5 b8 C1 M* i
EDMA3_TRIG_MODE_EVENT);! R5 T. E: U9 P! b N9 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / n% k( k, ]; {9 b% G. K& t5 v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 B1 C$ G( \4 l) `, }* U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% ?; Q* I; T. ]4 b) R1 @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( x* D& Y4 r9 K; E5 G* _7 Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! M, \# E) o9 P7 p5 [7 r1 U( sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* k' F' m- G. C2 a. L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ `4 Z( a3 D. G% ^* K+ O}
# d; m6 {' C' V2 K, x: l4 |. i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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