MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
. H& |& O& Z& u1 G  G8 jinput mcasp_ahclkx,
, e  l5 a0 a. T% ^; n/ s, F. X3 o$ linput mcasp_aclkx,
$ k3 l- ~) }% F# Q, X$ [( t1 U0 X" zinput axr0,

: |/ s, o0 F6 o1 routput mcasp_afsr,
$ e" {8 C9 G6 F( uoutput mcasp_ahclkr,
output mcasp_aclkr,
! y9 I+ g  H; G% Routput axr1,
% r* R  h; S+ U: w

assign mcasp_afsr = mcasp_afsx;
" K$ u* ~2 S9 q5 W3 c- vassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

  D8 ~9 I9 A; W6 n5 E

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

/ L# ^2 W- v/ `" f

static void McASPI2SConfigure(void)
0 E) M8 D" Z9 k- D% }6 x{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. R0 p( X2 Y* C  p7 c" T: RMCASP_RX_MODE_DMA);
. ~6 [* q: K8 d/ l8 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( s) o* Z3 g' e3 _- p; j# H% WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ T$ Z, \( l6 I- _; P1 R# {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
  Y2 F8 z/ X) x: \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& V: z; `$ g$ `- AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 H5 V. m2 ?6 L  q8 q' oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' ?  [0 p4 Y7 v, v/ i& h8 }) L7 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, K! \9 r0 B" ^0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
" e$ o8 i/ |% e5 \. V, tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
. r1 g2 e- ^: t- X; [1 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 V, o/ i  q/ p( Q2 R4 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
9 a! H" X6 p/ V, _" R$ c' ?- [** Set the serializers, Currently only one serializer is set as
2 a  [3 r: M1 F+ [3 K6 L0 `: Y** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
6 Z3 q7 M3 D/ z1 }! c9 i9 H& bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
8 ^1 K' S' }  _" g! x# c: \& l, S* ]& G| MCASP_PIN_AHCLKX
! \" F8 j. M1 T) Y4 W| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) D  Q# k% s" n6 U+ I- CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; v, p5 M9 a4 ?& k! u- T| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
  ]# N+ H% S/ }+ x4 P| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 A& g% N: L* a1 F8 _1 l* k| MCASP_RX_CLKFAIL
0 r. `$ ]* i$ }+ P+ ~6 k" N, p| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
9 g$ }  P: c$ [+ R! ]# [}

static void I2SDataTxRxActivate(void)
& f$ n, Q) T& K5 J& }- w+ v{
/* Start the clocks */
# X8 @% L! z* d9 }, s" }4 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 y; w( {: b1 ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
5 \9 @& X( s0 L! [: h/ G1 e% h9 h: |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 Y% P0 \" C: }3 I; MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
9 c& u6 C2 s3 m9 x" hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 _: t+ _! q5 I& c$ CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: g: e+ M& j0 e& A6 u( R/ R}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

* V% g& z0 Z; u; _# k0 a