MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
6 u: p$ f/ N+ `$ i" G! L7 P6 q; H, Oinput mcasp_ahclkx,
6 b/ p: Q4 M+ y7 N& L& o' p6 Minput mcasp_aclkx,
2 z8 ], w5 f6 n+ ?$ ninput axr0,

( z, g8 q  ~2 ?4 |output mcasp_afsr,
output mcasp_ahclkr,
& ]# V: Q, Q2 g" a/ S: z6 Zoutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
& d+ A5 P. B9 \assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

# g6 f( s4 G8 [! G
: c, |3 ]9 Q  n$ J$ v2 C+ }

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
( X1 y- e6 Y7 B  W7 L$ T- dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
) T2 M2 }, _* U3 l* k; p+ Y4 HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 F. b9 v3 i; n; _; fMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ a5 [% j- `; SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: v+ F2 F! T( Y3 k: @3 yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. z' n: r, U0 U! G$ y& m' GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" n( u+ E% v+ k2 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 @5 r1 h( U9 ~0x00, 0xFF);

/* configure the clock for transmitter */
/ \. z! x8 R2 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' ?: b& j- h& F; e3 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

, F3 d* l4 K3 F) Q2 }# q/* Enable synchronization of RX and TX sections */
& n3 R2 |; q; |/ H* @$ f, v9 d9 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 a2 B; R0 S) V4 \0 C" M2 z0 Q$ }: K9 e' wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
7 G& Z* g$ J6 M$ Q7 P7 i3 c& z5 C1 B** Set the serializers, Currently only one serializer is set as
7 i! |2 t: x5 u- ?8 D/ Y: V** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, B" t! e: B7 s7 J; ]2 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
8 K% y7 w3 e; \8 j0 L** Output - Serializer Tx is connected to the input of the codec
*/
8 Z6 a* s5 C  k8 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
9 T, }4 f: E! _0 J0 M| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
1 f; S( f3 `. t; H  e+ dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) T3 o" G$ U% H# }& }1 ?| MCASP_RX_CLKFAIL
, F: H+ I1 L8 k1 F4 V3 R| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
6 w6 I4 |" D5 y% M! B" R}

static void I2SDataTxRxActivate(void)
7 F2 m) I) e7 l9 G$ s. A! ]{
! d( N  Y4 N( p3 H7 x, ?6 d/* Start the clocks */
9 Z0 d0 o( x7 z: gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
  G. H  X8 `! j6 o' U. W9 W7 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% q9 Q3 f& n5 ^% fEDMA3_TRIG_MODE_EVENT);
5 K: e9 Z; T+ {2 c7 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- d6 I6 c7 U+ n  r2 z9 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
- s) J1 W6 e2 k) Y& E8 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
4 ?, n5 g1 j7 n4 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 d& @) G$ t/ Z}

/ g/ w5 B  i, ~" z  h

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

6 S% ?! k* r+ u; b  f" k