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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ i3 D4 v2 ]9 U' o$ Linput mcasp_ahclkx,
$ \1 G0 Z. K$ Y/ x8 Dinput mcasp_aclkx,& b* y! f1 o# Z7 o8 {0 f
input axr0,
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output mcasp_afsr,
% g" i; f# N- x3 Youtput mcasp_ahclkr,; i% a3 q1 } i7 r1 ?0 b
output mcasp_aclkr,' w( M: j& R. ~1 i; v' U0 @8 R8 T/ K: x
output axr1,# R3 r( S* E W% M
assign mcasp_afsr = mcasp_afsx;% }# |) D, Q9 N& t
assign mcasp_aclkr = mcasp_aclkx;- Y4 t- _ C5 `" k2 ^" z' Y s! n
assign mcasp_ahclkr = mcasp_ahclkx;/ O) S; F( }; g; I' q* `2 ?. e: k8 [! R
assign axr1 = axr0; a& i! k" X2 }; Z$ N
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( @+ ~7 z: c' U$ N$ U3 F# M! J7 ~
static void McASPI2SConfigure(void)
9 e/ r" P1 b0 w% ]8 e" ~{$ m' ], B' H6 G* H* }. {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 r0 J/ t# \) @/ |: _2 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 X3 E% Y ]- z) B- e$ l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 t+ z; m& Y' J1 F8 vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) x# e* m) \' @, t( I* z DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. x7 V+ h4 T$ ]% J+ h% {6 U6 k* UMCASP_RX_MODE_DMA);" \7 h. x2 j0 o+ [' ] k; {: [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; g! |9 ?+ {5 ~$ C* \' z8 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: w! M. L" {1 T7 e4 |2 Q+ x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 @; s6 Q3 {; X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: U7 n8 C- @0 P8 [: J) @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 X9 W" D. Y8 | w ?0 v, a' C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: X% y! ~/ v s) b% `: M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 y: e) d$ _3 J4 T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 q$ v# k1 D% B7 |( B0 i5 ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( J- l5 V; S) s. }( {/ ?
0x00, 0xFF); /* configure the clock for transmitter */
7 G* ` y& j3 j( CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ R4 w4 T( X# J1 e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 B4 p" {3 {" G; R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 V. a! \) `6 b/ t2 \. W
0x00, 0xFF);4 R4 u( A1 G q2 I7 t- `
; B7 v" b! j' z) r/* Enable synchronization of RX and TX sections */
( {0 Y; B) U; t b3 m, I, V2 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) r0 ^4 ~7 o. O, N. {# u7 Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( B& Z$ ~; N7 W9 cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 @% r% W. @) ]6 ?8 E* ?** Set the serializers, Currently only one serializer is set as
, v( N8 X5 L6 G y( a** transmitter and one serializer as receiver.# w( P" `, X7 }5 ? W
*/
! G$ a3 R$ d4 D+ {! |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 T' Y* v0 u8 l3 s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 T- ]( ^! Y% h" }/ d
** Configure the McASP pins E6 [" E+ r3 ]+ `& H F& [
** Input - Frame Sync, Clock and Serializer Rx
* O& x) T* c, O" L K** Output - Serializer Tx is connected to the input of the codec
2 d& t) {6 j# ^5 S3 }*/
) N& i2 l; v# I& ?/ u" HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); |& J7 x) v) l% q! W% c' x- k" M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 L% i) U' ` F- }' \& b/ A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! D# i* E7 ^9 T5 ~| MCASP_PIN_ACLKX, U% n9 m/ y( K, R3 K5 ~8 Q. r
| MCASP_PIN_AHCLKX1 |, k5 r& `3 p/ v3 D u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 h$ l* E' `0 n' q: z! |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ x+ r; ?) d0 P) H| MCASP_TX_CLKFAIL 2 G$ g" ^- [# E7 H. ^3 ~
| MCASP_TX_SYNCERROR
. b) K1 ^) ?0 N) o+ I5 M* P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. C! B: D/ a) c! p5 Q# x7 h$ Q| MCASP_RX_CLKFAIL' @8 n5 [. A' M; c+ m
| MCASP_RX_SYNCERROR
5 z/ i6 X& G f2 q* j* X| MCASP_RX_OVERRUN);
4 A. o$ k( y6 L} static void I2SDataTxRxActivate(void)9 X# y; u8 [2 m; l3 a
{" d, P, z8 C$ o! x3 e
/* Start the clocks */
; T& v6 i9 d7 O9 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. M7 U, k( E8 m0 t$ qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 J- |; ] `7 K2 a0 m# I; n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 @1 j" Q, ^* U( G% M3 }EDMA3_TRIG_MODE_EVENT);
" }2 _# R+ v, q I3 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% @: |9 z) h; T- p; A8 A# @/ ]/ ~; L+ tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; T+ {# C+ t( J1 jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! H& g6 ?, O4 P2 MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- B$ x) A. K& {: l6 O, M$ m, Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 I2 z% J7 K$ J+ h, C. j/ z0 K% V, DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; h5 ]: u, x- A$ i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ a4 Y# I) [' R8 c* P: l( z
}
1 [: J5 I& |0 \' V8 [& p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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