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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ Z- E; J9 U8 T
input mcasp_ahclkx,! B$ w, P( T, p4 D& I- Z8 o0 z
input mcasp_aclkx,7 F2 Q4 S& j7 ]4 \( o" L0 C- @# _- ~# J0 `
input axr0,* n* `# g5 K; Z
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output mcasp_afsr,6 z) u! v# Y! N x- l# O$ o- q- d
output mcasp_ahclkr,
0 Z. r& ^2 P/ H# f/ @8 soutput mcasp_aclkr,
. A8 F3 W3 `+ f: i/ {1 K' ?output axr1,, `7 S z* r# f3 {1 f& h K
assign mcasp_afsr = mcasp_afsx;: W9 W v: d5 o8 r6 @4 u5 f4 a
assign mcasp_aclkr = mcasp_aclkx;
9 z6 a) U* C. g. bassign mcasp_ahclkr = mcasp_ahclkx;
+ G! M% C7 @1 m4 Iassign axr1 = axr0;
& m. p. P2 x, L: h1 W7 Y7 v/ L2 Z4 ~. y0 }/ |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 m4 W' Q- {9 S" T" O( y2 c# _
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 R w9 Q+ ~* O! QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 K5 j* n0 R+ Q% sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ Z0 {: ?0 V% `0 V! O3 d9 T, i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& A b* V8 c* d9 H+ G _+ t- NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 p. Z1 Z3 k: }MCASP_RX_MODE_DMA);9 ]) A# [& u/ P% h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) x/ c) U4 s' D4 ~1 N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( S0 d$ }/ B1 D" I+ b/ LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / P( F. {9 d- v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ n4 V' w! n8 p" ]/ v' M$ D' p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 R8 }, _0 F6 z& RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- |) W) C+ ]/ e! Y4 C( t) n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 ]: k. k! M1 k* x6 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 m4 o: Q6 b4 B( B( u, s& cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; ~" h4 f8 J" h: f7 Q9 X0x00, 0xFF); /* configure the clock for transmitter */- o! w# p( j/ F* P3 y+ x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 O. ?* i/ {8 t3 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + l6 f* I; ?' R* k& ~$ {7 {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 s5 S: M& C, _4 i' T2 c$ r
0x00, 0xFF);- F, v! i% k! C- f! W: q- h% N
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/* Enable synchronization of RX and TX sections */
! e! g. x' g) NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: @9 E+ `: N# B/ i o: T1 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" u+ S/ M1 a5 u0 E$ a0 n$ K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' S" M5 J& W T' n3 i** Set the serializers, Currently only one serializer is set as
7 e3 E' [* X5 O/ b0 A& i7 O. L** transmitter and one serializer as receiver.2 D Z" c6 q1 E- ]/ l! \
*/, ~/ o h/ ^, p+ K8 A. f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; @1 b" I+ t( ^# Z) e7 P/ d# a! yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& s* _9 s; j8 u: _6 d+ v/ s6 {% S** Configure the McASP pins
+ Y) L% s, B7 f. K+ ^! p+ B8 g** Input - Frame Sync, Clock and Serializer Rx
, i; a) t; A* {' i: r( x E' c6 W* s& g** Output - Serializer Tx is connected to the input of the codec ) s/ U, e" j3 n
*/6 t( w( ?$ l! Q2 C$ I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% _4 N, x! _( C6 L; @* x4 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% Q% k0 z7 R/ d! P6 A) h C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 j3 A, E- M7 Z }+ ^; |3 ^
| MCASP_PIN_ACLKX6 a7 o) F. _- \- s" |" Q
| MCASP_PIN_AHCLKX
6 Q& i# F' x6 d8 \% {6 l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 }( z# A8 x* ], OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - ]& w6 z9 h* ~2 V- A2 u) w
| MCASP_TX_CLKFAIL ; V" ~0 U. Y2 j" p
| MCASP_TX_SYNCERROR
! q) p- L# d$ A) d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- h/ q) I* V( x W| MCASP_RX_CLKFAIL
9 {) @; ?# i+ I| MCASP_RX_SYNCERROR
7 Q( g9 g7 d, ~1 @# h! \1 p| MCASP_RX_OVERRUN);
7 Z# `2 p) H2 h$ z3 [7 V} static void I2SDataTxRxActivate(void)$ C5 W+ R$ A2 Z! o) k6 O; R0 `
{
+ f4 H5 W! K9 a$ ]- B7 |/* Start the clocks */
! c1 i: S0 u5 y5 GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ @" E3 U5 }' `1 p1 s8 p! q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 O4 H6 V. }) O( B/ E2 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 Y' J: Y( e. d" U# r/ o; ]: ]
EDMA3_TRIG_MODE_EVENT);' g/ z. i1 d& I& B7 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 r+ Q" L3 C! vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 H. y* G" T2 A$ _1 t1 h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' o5 o# C3 d" z/ |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ ` Z, C& T3 ]8 _# t6 n% s1 ?6 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! t" B5 f- ^( {; U: aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 w' f2 s) s$ Q8 h0 w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) C) y" v; X5 y( _
}
: U, V9 @4 x( g! N$ k0 b2 c6 R$ P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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