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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: _7 }7 F2 u' r L: vinput mcasp_ahclkx,
: t/ D4 A5 k7 ^* |input mcasp_aclkx,
9 z3 z8 {" L% F D6 Xinput axr0,. D+ c8 g4 L7 I$ j$ ~/ B% z
6 [, Y* F7 G$ g9 I* L" E4 t
output mcasp_afsr,4 P, J3 y A. T
output mcasp_ahclkr,
2 J' X' k, N% X l9 n: xoutput mcasp_aclkr,) E9 p* c8 }+ Z
output axr1,
+ s% P& |" s p$ J& s6 Z assign mcasp_afsr = mcasp_afsx;
8 q0 N; E. M5 Nassign mcasp_aclkr = mcasp_aclkx;
' V' X. [& \: y5 f( ?0 Q2 Nassign mcasp_ahclkr = mcasp_ahclkx;/ x. C; n, m7 J3 v) P5 I, a
assign axr1 = axr0; 9 \3 ~* t- n. m/ S+ w
/ ^ X6 w$ m1 W2 G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 F6 \ B4 \$ j8 j! gstatic void McASPI2SConfigure(void)# y T4 v* S/ U2 v+ ?
{5 o" V- E: [2 i8 C Q) ~& H' H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" m* s. ?% Q+ iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// N t6 U- k4 w5 A! Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 s* m( |# P8 T: x/ {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, |5 v7 g l- ?9 Y% a- N6 Q/ k$ L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. s; E) h/ M: [! C2 r1 _9 J( y: [( v( I
MCASP_RX_MODE_DMA);/ G T+ S" m4 x& w6 R4 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 n7 M6 a4 L7 TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 s$ g6 c7 m, b: x) b! Z- B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' `- t. q' p) ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ d" \7 \0 ]$ V* aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % U s7 G0 U% Y, v/ y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* |* g: n8 W+ O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 D* [2 _& i* S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ~: ?; L* h2 D3 g: ^0 t: EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 k: A3 u3 j# P5 \3 y& M' ]+ M; r
0x00, 0xFF); /* configure the clock for transmitter */0 t1 ^/ `* y! q- C8 C7 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- [9 J. O6 a7 f+ C) P- X* GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , P( O2 X1 v8 ?, ]8 `" T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 s& M" e$ t% B5 K" k
0x00, 0xFF);
0 M( R V: M% L. T/ Z
- j R9 X3 U. C1 i$ j6 V, C# }9 x( C/* Enable synchronization of RX and TX sections */ " F3 n& y4 ?1 l& {, ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* X* j3 x( a5 D9 i# HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 h: ~3 V9 j; h6 @, S: g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( y, c6 g; d! v/ Y% X5 O** Set the serializers, Currently only one serializer is set as
) t/ |! p7 E6 ] P1 ^** transmitter and one serializer as receiver.& _2 Z6 A X0 X: z' g
*/
1 u# o& i6 z! Y8 y- l/ \6 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 a/ P: x; ~% C' a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 O, p& m* N$ i) o' |9 p% T* k, \** Configure the McASP pins ( L; p' [+ p( S2 S7 a; m- h
** Input - Frame Sync, Clock and Serializer Rx6 E2 Q! l: _ t2 F& P3 |4 R+ Z2 D
** Output - Serializer Tx is connected to the input of the codec
+ |9 N- H( E: l( q+ k9 J*/
+ i+ d, y# ^- E! C9 V3 ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 A: G, |) \; A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' U" J# u7 v' ~; n. h, `, JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! q- F- p5 F6 M' l' u| MCASP_PIN_ACLKX
8 ^! M3 b* a! ^+ S( {| MCASP_PIN_AHCLKX( h2 T/ Z" k. U" L9 H7 Y9 ^( K i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% N2 L! G1 ~! J$ |. xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 r8 B8 ~* f6 l1 N) z8 T1 k2 U| MCASP_TX_CLKFAIL , z0 C% V2 N, s
| MCASP_TX_SYNCERROR
% y( a$ X" \( v% T' ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 l% C. H. ]" ?5 Q
| MCASP_RX_CLKFAIL" Q: ^/ r1 a9 Y0 Q. M
| MCASP_RX_SYNCERROR / }" b* I* l4 A( L' _
| MCASP_RX_OVERRUN);
& R* e/ {. z2 u1 Y5 h. m2 I2 t} static void I2SDataTxRxActivate(void)
: R/ g w' d2 z9 N, Z4 y4 q, l{
# x( a% F6 U& {- e5 a. K( \/* Start the clocks */
" z/ I( T- F- _* \" {/ j4 J5 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" h3 }. y5 p' F# a7 Z- L9 b/ C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 R6 q5 q3 {: ^: P8 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. g" [/ v( `3 S) |* Y% C+ p' J
EDMA3_TRIG_MODE_EVENT);
- L* V6 h d( k+ U" k& dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 I$ ^6 f9 Y+ `- a1 p4 V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- h7 A7 @, c; v! sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 V! D$ ]$ `5 n1 h! V7 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% f' d% l( v. L; ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# L/ }% f4 X( g# K: N0 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* k1 u: [2 @6 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ }, T4 N& ]* u9 ?' { t
}
% F/ j7 \) ^& ~* Z0 E# B- e0 a4 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 ]/ l0 e; ^9 n+ C& X. ]
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