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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) K$ U, E4 g. T6 d. c
input mcasp_ahclkx,# F3 v K) M" y( L
input mcasp_aclkx,
+ k8 i" |; G( v! O; K4 Dinput axr0,
+ Z6 {1 [5 A6 ^4 W6 a: b. ?
6 q- D) ^- ]8 A$ {+ ]: Z" Woutput mcasp_afsr,
) O3 I# D& |4 C! R+ _- o2 foutput mcasp_ahclkr,- @' i) l. x& z3 `: r5 Z1 u
output mcasp_aclkr,
5 S- ]. Y' {. u; ^) o7 h7 m$ ]output axr1,
) h: A1 Q& ^% |! g) C* @( W; G; e assign mcasp_afsr = mcasp_afsx;
: k+ _& R6 W( V% q+ Xassign mcasp_aclkr = mcasp_aclkx;- L+ I* H% h j" ]
assign mcasp_ahclkr = mcasp_ahclkx;6 U0 Q& _5 u0 {& M. R) ?
assign axr1 = axr0; ; j( R6 H) W/ p1 F' F
4 m3 N* x$ o. s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, j" z* A. A" A4 bstatic void McASPI2SConfigure(void)- q. E+ H7 S& ?2 {
{
; [* C/ s4 f1 o" h9 E& _& ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# W" _; U4 f0 i* t" ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ F4 x0 N* @- C: H8 W% s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 _. b6 {2 J+ J8 @" GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% |4 R0 H" R# X! P# j/ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 D) I7 u2 q7 rMCASP_RX_MODE_DMA);
" V( v& Z3 F8 G) [# D) @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 b9 @( r0 q9 Y$ }4 c( T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% Q9 X$ V! k8 g. T* e4 B$ ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' d3 r3 ~( u/ J& v7 m8 DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: [1 i) L8 }* q! `, v! w! u3 d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! h- [( R( ~2 K: G9 @5 _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# v% {, v( K/ i0 S6 s3 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: R0 X; [5 p! ]1 F- T; }" Q: q$ i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . Q- F. C4 ~% m8 N9 t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: K$ a0 A7 t+ Q4 K$ [" n Y5 F0x00, 0xFF); /* configure the clock for transmitter */4 T% H8 D. h+ n! J q5 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 Q8 }8 u: d; P$ ?$ I2 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " ?* V8 k- ^- A" }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 [8 }0 `& m0 v& u& k
0x00, 0xFF);
2 z! z, [# R8 |7 @# R
) j8 c! z. p, u% M, m/* Enable synchronization of RX and TX sections */ ) j3 b3 k7 [+ i$ U2 F, l2 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 O8 L& ]) H( o. Z; _5 v# {! n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ }$ F! [( _- fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# |# T2 ~- ^5 [( g1 n ~( b** Set the serializers, Currently only one serializer is set as- I3 I2 p. Q$ J5 C% i
** transmitter and one serializer as receiver.
; G: _4 ~: V/ _# V0 u*/
2 w# t/ s" R9 U: \4 S8 }: S" KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* h" d$ `0 V8 }* c( G! ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! c, N. A1 \4 k
** Configure the McASP pins
% e8 l. E( c% T6 L6 Q# ?0 O. O** Input - Frame Sync, Clock and Serializer Rx
' J7 _# A7 |& N9 J** Output - Serializer Tx is connected to the input of the codec 7 m2 ~" c& q, J& N q- K, [
*/
$ a( P( j% c( Z# x1 ]/ l+ Q6 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& c& V' G# y J& n* U' }' PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 N, x p, I- c9 {& {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ A' w1 B( u. k; C7 L3 U7 e
| MCASP_PIN_ACLKX
' f7 x+ n5 l& ]& F: J| MCASP_PIN_AHCLKX
* @% t* p7 A" n2 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' ] m: f' ~* j( c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 `7 _2 R* B6 n8 N| MCASP_TX_CLKFAIL
) D Y8 k- \; C! i& w6 y: X- y| MCASP_TX_SYNCERROR% g+ K" i7 Y0 x! i9 P4 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* H3 D" M: m3 S: || MCASP_RX_CLKFAIL
/ v! n# P( ?2 ?$ H- _| MCASP_RX_SYNCERROR ! ?7 E2 B8 V* O9 m8 m5 ?% O& Q- v
| MCASP_RX_OVERRUN);
_: c) J+ K, g& O9 C$ C% h} static void I2SDataTxRxActivate(void)6 `. u- p4 b; \& z- m# G# T
{
1 @# H$ }; w5 n! i; ?. Q: u& F/ M# B/* Start the clocks */
2 i3 q' S% L- Y* P, d+ |4 w1 qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); j5 W4 E+ m \7 I l4 ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
c) [- L. a G" Y7 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- m% H& G* X6 N
EDMA3_TRIG_MODE_EVENT);
w% Z c9 f+ j' G- j9 N; sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 W. {* x5 n5 v& v5 w* qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 o( [% Q# M" Y6 R1 i& r% h0 P, |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! J' H9 o7 j, q8 |, J* P: t4 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& @2 A/ k2 }* U" [' U# J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" \9 t9 K# }) D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 t [/ Y( A2 l$ O8 b# fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 k' k; }9 @3 s0 i7 i5 ^+ A3 \( w
}
3 n/ b! F( M3 O# S' w" O' {) I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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