|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# E8 E! F+ e0 K1 p! A0 O1 I2 c- Winput mcasp_ahclkx,4 i2 m x5 N% c* Y$ E' o9 q* `
input mcasp_aclkx,
6 r) g z- q. D7 s* G7 A5 E* }input axr0,, t; c# y( I \4 C; _! R/ A7 J; x
: g: [' z- `5 A/ q0 b
output mcasp_afsr,( n1 ^0 x' }6 \, \
output mcasp_ahclkr,& X2 x2 D! U6 }1 j) \+ C% L1 {
output mcasp_aclkr,* p8 f6 p0 }) ]( o& K9 f
output axr1,
- N. H- c4 p( T Q5 x assign mcasp_afsr = mcasp_afsx;
% i' D4 H4 I; u, E' ?! B! p6 k3 Rassign mcasp_aclkr = mcasp_aclkx; e9 ~! B2 P7 _3 P: c3 R" h
assign mcasp_ahclkr = mcasp_ahclkx;
5 U" B' d$ l0 F7 h# G# G" a- X$ B) [assign axr1 = axr0; & p; N# m- l" Z. c8 _4 n, z. e
. ?+ R4 l/ _ I! S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) W' C6 P; }0 R/ D% F3 H1 [static void McASPI2SConfigure(void)
0 I2 e9 ]$ V, ] Q4 I& g{; o! Y2 r: w- b F( ?8 a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 b4 b2 V9 r. b. Q7 P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' o6 f5 Q% P F/ ^& X5 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 F f! U% b# {9 S% S* z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! m) w/ r* N- p7 G, P: c. VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; X+ `' x$ Z6 E$ j; Z
MCASP_RX_MODE_DMA);
- c1 h$ I. f% ?+ Y Y$ WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; |. [5 M# ~! E0 g9 fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! {1 H1 C6 T5 N z% l. vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 }+ C3 Y" K. A7 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: c1 k- u+ H+ J; f$ f" e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* [" S5 D5 d7 n$ F* _6 LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; M' O7 _# z9 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ V# V9 H7 E- E, {6 p9 ^% {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 W$ c( ?* j! w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 T+ h. V9 }! E, A+ |
0x00, 0xFF); /* configure the clock for transmitter */
5 L, F0 |1 y8 H' K2 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( P2 T) x: ]9 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( @9 h, R. r0 eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 z# i( c! l: m0x00, 0xFF);
2 J% b% \, w, f* ~! a k9 q6 V) B3 }; U. Y- _( j
/* Enable synchronization of RX and TX sections */
b6 G" X; ?; \" q! ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 H. j! a( t6 N8 ?4 u- NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ G) _: S7 ]- _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( z# J( W% ]: Y# C** Set the serializers, Currently only one serializer is set as
6 g: ]+ q- |, m" \2 F** transmitter and one serializer as receiver.9 v" h# T* x" K2 ? `: a
*// j$ l( W) z% i" @8 i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); v7 m* L6 w% C! \* z! u# ]* g! }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 ]; W! q+ b% b5 C% C** Configure the McASP pins
4 e; ^0 r' u3 [** Input - Frame Sync, Clock and Serializer Rx. I! Z F/ x4 l. k5 w2 j5 k
** Output - Serializer Tx is connected to the input of the codec # D# Q; {, T6 d3 r
*/
" K% S$ M2 [% Z8 x7 E' BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; t0 {3 C B; t1 I. |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' ]' _9 k8 H) d+ x/ I6 C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. X- u" s. e C% r
| MCASP_PIN_ACLKX; Z S" h3 S2 M' l3 @0 g1 \6 @; w8 W6 Q
| MCASP_PIN_AHCLKX
& A! Z8 d2 w. R# t# q* ^1 {: g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 N6 Q5 w; r4 J2 a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
o* W3 B' S+ S! [5 v0 A" _/ u| MCASP_TX_CLKFAIL
, D C: j p1 b4 w4 b. I* r| MCASP_TX_SYNCERROR
% ~& \, E% T9 P+ S) E; N1 e; `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " b; P" t! s8 M* J0 n: x+ ~
| MCASP_RX_CLKFAIL
2 ~) [& E- w1 v. @: O9 N| MCASP_RX_SYNCERROR
e$ r" S3 m V4 z, [| MCASP_RX_OVERRUN);
2 c# A- y) ?( m} static void I2SDataTxRxActivate(void)
) u" R; L8 d' u1 g{
, G; ^. E7 o6 }. O/* Start the clocks */& u9 M8 [4 l# |6 P: t; l) T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 Z% t: q; r- {% [8 T7 P, g8 X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# z; o: L- M* c1 e2 a7 Q0 x' XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" b1 O! Z" |# W- p8 E2 qEDMA3_TRIG_MODE_EVENT);5 m) r; {- z4 B4 N# U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 E7 J; Q, l5 l; A" ~4 I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# ?+ V& m ~/ h$ e/ SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. L" u/ r: f$ N) L7 L, f, j! tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- H* d5 c5 M8 R, l& y( y0 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 }* I# Q$ f2 [0 C; G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; S. c* N# m! |- ]( I3 m/ J/ KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( V$ _7 U4 B+ T; i& F: F' U
}
8 J) ]% N6 S1 j$ ]7 h7 y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% B% Y* Q% C9 | |