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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( J9 U3 C# R- o4 _$ ~, ginput mcasp_ahclkx,
+ y$ F' q- ]4 W) M% `# j1 pinput mcasp_aclkx,2 @/ O. @4 Z5 ^1 I3 k3 D
input axr0,
, X Y6 d: V& z7 r1 F. \/ n9 F1 n4 T R
output mcasp_afsr,: \3 t4 z* A2 [5 n: S! i% E2 U
output mcasp_ahclkr,: ^7 \1 o% Q1 E$ k/ {! z3 L
output mcasp_aclkr,0 N" \$ R; N- p l: T* Z
output axr1,
5 H2 F" {% F9 J$ G% q8 O2 M assign mcasp_afsr = mcasp_afsx;3 Q* }, @% I' D) n
assign mcasp_aclkr = mcasp_aclkx;1 Q/ `" s) f1 d3 {# ^# g
assign mcasp_ahclkr = mcasp_ahclkx;/ j- \* y: I0 a; [# q
assign axr1 = axr0; , M6 |3 t% @9 W6 C5 w; [. b
$ N3 Q: j& ?7 `8 n7 D' q7 j7 `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : \& f1 o9 n9 \
static void McASPI2SConfigure(void)( `" X1 z5 Q3 r- K, n; }
{( v! L6 h& Z6 e3 Y: C4 S' h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ v$ g0 y% b# H$ Z4 n, Z. `; Q8 W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; G. U4 U3 K% W. ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 h Y/ s4 O+ P( Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 B; _* a8 q+ d, m5 ~" rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& s4 \* Z& S p
MCASP_RX_MODE_DMA);
; ]& H! e: `2 I. w' [' l: a" ]8 q" KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& d/ L2 t' o; W# S; A4 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// Z4 h2 e/ b3 M0 h9 U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 X% Q5 J1 @$ [" M* S/ s& \" z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ Q# J8 L+ V/ H( Z* l9 @8 m4 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# K# e, E" M, g/ p+ f" t/ L+ uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) f7 B( `! f. D1 y# Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) x! }. v* D9 R) o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ J* l* h8 X3 k4 V: eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," c. X6 X" G1 N% L1 `
0x00, 0xFF); /* configure the clock for transmitter */
" a, u) m: p. d. d* |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; h5 ~6 j; I ~( |( a# tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . g; v+ @' B2 e$ J* ^$ Y$ g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) V5 p) ^/ Y: C* C5 Z9 w6 W0x00, 0xFF);* x: k- G! M3 i. f- n0 U2 t, ~
# }1 f6 L% z' \/* Enable synchronization of RX and TX sections */ 0 b3 m! u' @) I$ E. V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- m) V& \7 X7 x" wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& f* z F- x0 u! }( u) `' @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# T' j) S7 ?6 L! g6 |( A
** Set the serializers, Currently only one serializer is set as
! Y) u0 c* H4 @3 O1 _1 j** transmitter and one serializer as receiver.
- ]- J- \$ d' |& Z# S& Z a*/' X3 P7 ~/ N6 j4 m- Q& z7 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ a5 g$ K0 N. y: J4 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 y: e0 E# S2 d' O4 p5 [7 b
** Configure the McASP pins
* X, i; m! h( A8 U5 p/ |! n N9 _& f** Input - Frame Sync, Clock and Serializer Rx
# F" W& b! b; b: @3 L( _ O/ C3 s** Output - Serializer Tx is connected to the input of the codec 7 K4 ~* M, T3 W$ n% D4 o" Y
*/3 Z: j( s% d7 ]% n0 m* d! f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 A4 Y" x5 C; D7 s3 e. u; R' l. o! i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' c7 I% C" w: R. k7 }7 P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 c% _: p) }0 E2 h4 o- z, X) e
| MCASP_PIN_ACLKX
0 @1 C K9 i8 v9 s- f2 [6 U3 d| MCASP_PIN_AHCLKX" W/ c. }% `- Q4 B8 t* L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ D l4 ?% @/ R+ H7 O5 }" CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 C& Z5 F q, v# \) D
| MCASP_TX_CLKFAIL 3 N6 \9 j4 x4 D, W' J( G0 C
| MCASP_TX_SYNCERROR; O6 b/ G" z0 t" Z* T% Z) l M% {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! Z7 p& k& B( r' p% U+ m+ W( V
| MCASP_RX_CLKFAIL2 j5 l1 c8 q( E. u
| MCASP_RX_SYNCERROR 6 T5 ^$ P$ X" P" J( w& T
| MCASP_RX_OVERRUN);
: u+ @! Z' q( R" w9 v" Y5 H} static void I2SDataTxRxActivate(void)
* [$ O! _; O- U8 O" ^1 w2 M{! \9 ^& }( q& Q
/* Start the clocks */& e) M% O# ~% ]- b, D C% c2 R: k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 a2 ?" O% X+ |* z$ V) H$ d; \6 hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% K9 t9 f6 q! Z# f7 R8 O2 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 U3 C/ a: T' \) w) ^& V
EDMA3_TRIG_MODE_EVENT);
$ `! P9 k+ X4 r; V lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 V- D5 W# M9 e7 G/ M) U, qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, r& B: K# _/ HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 G( f9 [( ^& D9 ~ j- b6 ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: A) l2 B8 u3 e$ Z& K8 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 [# |9 B1 m$ S+ m2 B% oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. I9 h/ ~2 j: R3 i% b! ?' ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ I. W0 O7 g! i7 u* g: _& T& \
}
~" a! v: s* O7 E8 q9 L, \9 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . J1 L5 k6 F3 q4 D; _& p2 g
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