|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) `9 u& G8 q& F( M8 {% Y" u- ainput mcasp_ahclkx,
, v$ l- K" V1 z1 pinput mcasp_aclkx,; g$ B8 ?% {* h, c2 O$ [
input axr0,6 f% {7 g: K1 o) L& n
3 _" B, Z+ g/ b! V
output mcasp_afsr,
7 ~3 ^6 o4 f8 o: w7 }1 foutput mcasp_ahclkr,
( V! r$ F) h3 e( P# Houtput mcasp_aclkr,9 X5 K3 z- L& ~% }8 v! |: ~
output axr1,
4 h5 A* ^! b) Q3 I assign mcasp_afsr = mcasp_afsx;
8 @: a( C/ @. r, g, h. F3 Massign mcasp_aclkr = mcasp_aclkx;. t2 I& \, t% Y$ O2 R( |* f
assign mcasp_ahclkr = mcasp_ahclkx;* M6 g; n% k/ p2 T2 K! h
assign axr1 = axr0;
, `. M9 s$ v% n" g5 D+ U1 H4 w2 P0 v' S# U# T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 j5 L2 y3 W7 l9 S' f
static void McASPI2SConfigure(void)' m- |* Q: v/ R) p
{
( l4 ?/ D* O7 g# v6 ?* jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: D% ?, V4 Q/ G9 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: N; N# J+ E) K- Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, b% J& v' P: Y3 K7 F5 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- I6 M8 r" @/ O" }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ A: @% }( z+ i8 n6 L& N4 d8 P
MCASP_RX_MODE_DMA);+ u" m; r0 b& W7 `) |2 T; q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ i/ O4 \* ^! U1 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 o6 B) T( E6 a6 }8 i T8 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' f$ T7 M6 i( \: e5 A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& k- K. O, ]( nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" j# R0 B. \5 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 r' r' U4 E& H7 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 ?& e$ S- C% s% W! y8 C: [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & Y$ `* T4 V; B* X0 C/ ~7 B! Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 n' Z1 F# A# Z" U0 Y0 y! p! w8 _6 B0x00, 0xFF); /* configure the clock for transmitter */% u/ _' B8 X2 b" I. B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' a. k1 }' \& A$ A. e7 D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " I5 ~: F$ s& G0 l" \' `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# `8 T# P P; c/ J0x00, 0xFF);5 A0 Y" I: p: J* O# n8 g9 Q
: @' X0 ], m) O& L/ M
/* Enable synchronization of RX and TX sections */ 4 ~5 Y+ h, D2 b$ D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 n' F) [: b# g0 X4 s! VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 M5 a! a6 c' h8 z" }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ B. L" x: Z' `: W3 |$ A+ l2 U
** Set the serializers, Currently only one serializer is set as
2 O- n; _, E. Z" p' W+ O** transmitter and one serializer as receiver.5 e6 |9 i3 [1 j: @& N" h
*/! j! ]% \+ M& B4 ]" V8 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& g" K5 ^' Z) k$ d0 ~; IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 A: \1 r' b: F! s& J: w
** Configure the McASP pins ) B8 w5 | q) \; N) f. ?
** Input - Frame Sync, Clock and Serializer Rx+ M& h' Y7 N0 m. d! b6 O, C- u
** Output - Serializer Tx is connected to the input of the codec 3 T. H! A, K3 |- o, b+ F7 w$ u' `
*// m' Z& Y* X' d, Y: I( o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' ^ ?/ a7 m' Y& D2 Y/ HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; X1 @ z# d4 |! DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" k1 k! I( P% [
| MCASP_PIN_ACLKX
# A# h' ]* X9 S9 P" |2 r| MCASP_PIN_AHCLKX+ r" J; x5 q7 h& m# y* }0 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% O4 I: j3 W8 A9 w# J( j6 W$ p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 j% F/ D) O$ z; Y* o4 q| MCASP_TX_CLKFAIL
5 Y0 H9 ?; w0 ?| MCASP_TX_SYNCERROR
% y L- _$ j4 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % S7 u5 @: |% }* P d4 d( S3 K; l9 v
| MCASP_RX_CLKFAIL
1 V; F1 o8 ~ I/ M/ Z/ w. || MCASP_RX_SYNCERROR / i8 y' J. |' v3 _" y% D/ k: W
| MCASP_RX_OVERRUN);
2 f( c2 |1 Y0 B/ k} static void I2SDataTxRxActivate(void)
0 `, p8 W9 y4 `{6 G7 g3 _. t \, v; P9 a; f4 ~
/* Start the clocks */
. \1 X) p' ^% c; X5 Z+ fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 X) t1 {1 O( @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" w3 g5 \8 @4 [, Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( p8 d& ^' V1 f" G; H CEDMA3_TRIG_MODE_EVENT);- w7 ?5 X3 g$ J# x+ j+ w; e6 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! o( ^6 K" g* C. a: T7 N( ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! t+ [" o3 I; B" C0 f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 o+ n8 y, p, @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& j( R% m5 I) F8 Q' Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. m3 `/ U1 f, ~3 F) O, Q- X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 y# s, o; e3 z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 v" t) V0 Z7 z! P8 Z
} 4 V/ m! z# H f. l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 k! B3 T' d4 P# S% B0 f |