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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ D* I. G p2 W/ h# X0 yinput mcasp_ahclkx,2 y. C# f* \" g1 M. \* a
input mcasp_aclkx,& d9 e+ h. R/ u H
input axr0,
, D- m- ^ v/ e. [9 a% `# u) g" S9 O9 ^4 \
output mcasp_afsr,8 ]6 D- ?0 M* z5 c6 [: l- f
output mcasp_ahclkr,
e6 j1 U& y# k" m8 @output mcasp_aclkr,: K5 g; H, X9 H
output axr1,2 f; r$ \8 B8 S2 l8 e
assign mcasp_afsr = mcasp_afsx;
; e& s8 n% Y2 d [! Eassign mcasp_aclkr = mcasp_aclkx;
* p7 q$ d1 v+ A ?* P/ k: X1 {% @assign mcasp_ahclkr = mcasp_ahclkx;
! y% r3 x' Q0 \- d- k* x8 V passign axr1 = axr0;
- E, Y4 p2 F, x ~) ?3 P
1 X# b; {9 B$ U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! ~; O& |" d" @1 E- F& j# G
static void McASPI2SConfigure(void)% `( c8 }3 E& x
{* Z, A/ n3 I) y$ N- c! Y+ l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' g7 l4 o; x, s2 F* l j0 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* G; r3 _5 S( {/ @$ b* N) b9 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
l$ f' Y( `! D/ WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& ~0 K& x$ \! y; l7 O- A" G- N/ vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 }- x d* v! z3 _% eMCASP_RX_MODE_DMA);& S$ C9 V' o8 G& O5 o3 h/ U& D0 W& c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ b; ~: l' n: ^5 ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ X6 k% f( _9 S7 S6 _) a; AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 x7 U* D& @7 {) V r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! t/ F, T3 e* S6 p& a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* m J) R0 x" i" J- U5 z$ }, kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ C, u% c: n9 x7 M/ Z6 U1 DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, F; S+ }; n/ e4 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 ~* i7 X1 T, w0 D# P) m1 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 P! b+ o# ~- x( M5 v
0x00, 0xFF); /* configure the clock for transmitter *// u& J. t3 F1 {1 G) B* w8 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ e5 y) S) ] Y0 H% Q* ]- NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); L( J' v1 R. w: Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! p) n( \7 t3 z) U& o9 h0 ?
0x00, 0xFF);: h2 d- F4 |+ \0 v8 k
: ~! t" \ V7 G h
/* Enable synchronization of RX and TX sections */
: K. m! ^) R7 e* E" cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) A" O0 E6 t9 }4 o, f( m* `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) l" W8 ]# b- ?! _7 Y/ [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 S/ | c/ \% L2 H+ }# C
** Set the serializers, Currently only one serializer is set as
( A1 L2 a7 }7 Z** transmitter and one serializer as receiver., U' L: x8 i' y3 K
*/
1 S b u F4 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# q, Z4 E- V6 z& o$ N# Y" s! wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: _& e# S* H: G
** Configure the McASP pins
9 H6 }3 o6 _ B& ^" T** Input - Frame Sync, Clock and Serializer Rx
- l }) C! s4 U9 i** Output - Serializer Tx is connected to the input of the codec / ^' v- b" x6 \# U/ r6 a6 P
*/
. a, ]* {6 E1 s; S8 f/ n# uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, v2 i1 q% o7 Z) k" K. H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 v, K: J. C$ b- n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- X; A7 w& \8 T, Y( G" S& X| MCASP_PIN_ACLKX- L9 E) @% e# r5 c3 ~
| MCASP_PIN_AHCLKX
/ N# S# S" A4 _2 j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 w/ y2 _ f7 q4 P7 z3 A, ^3 `! S& [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " A: ~4 Y% k) H2 m- w, B
| MCASP_TX_CLKFAIL
3 ]+ q! B: Q# a) e4 t| MCASP_TX_SYNCERROR: ?3 t- v a6 t* h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * A4 _* B: d: ~- O
| MCASP_RX_CLKFAIL
' S% u. ]5 k/ o% s4 n| MCASP_RX_SYNCERROR 6 J$ d. x" c7 l0 S. ]7 d
| MCASP_RX_OVERRUN);
9 K3 E. |* v# c0 M q# Y} static void I2SDataTxRxActivate(void); q3 e2 g2 K" c! V, l# v
{
$ a6 M- K, G0 U |7 E/* Start the clocks */5 P7 c( k) g0 @ T7 ~" J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ ^9 i2 r# d: D: ?) X+ o2 ]9 cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' C# ~3 c# W/ T" h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 V5 ~- [% r5 t0 o( F" u- D
EDMA3_TRIG_MODE_EVENT);
" u! ?5 M! y( C$ J9 q! Z6 b& {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: H% W+ h+ s9 O, _) G4 ]) K. t; WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( n/ i9 |: e5 _3 x8 Y, r3 P4 O( q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- @: `2 A) j! U; _, o) o2 [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 Q2 [( t. h3 x4 j+ F, ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
X9 a9 |% ^8 M& S8 _+ |' E( VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. W ]& S" ~7 ?5 A' q6 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ n* n7 q# L$ F3 R}
( _( y2 d$ D+ k: ^+ F+ e0 g: `$ W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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