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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 T! `1 s" |" x$ j2 z5 Dinput mcasp_ahclkx,
0 N/ v, c% _. ainput mcasp_aclkx,0 b) {, ]7 z$ P0 W9 [# i* w
input axr0,
6 c v$ ^2 W6 S7 l
4 H3 ]# }* U# K, l& t" Q+ h1 \* `output mcasp_afsr,2 j$ t. i: z4 F9 y" S
output mcasp_ahclkr,
9 T$ _% j& S( goutput mcasp_aclkr,
5 `* J% m6 s. W% z+ Z4 coutput axr1,
0 \( y$ \: _5 W& v3 [# {) v$ E C assign mcasp_afsr = mcasp_afsx;) M5 K' M4 \1 n: h" S% M! n* ~# G
assign mcasp_aclkr = mcasp_aclkx;5 C2 x7 J, a' r0 H( X, @3 D
assign mcasp_ahclkr = mcasp_ahclkx;
, C4 e) d$ P( v! G; |* Xassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . O, n# R5 O7 K8 j. E
static void McASPI2SConfigure(void)- m& A( ]- {4 K6 x
{
. r/ n/ p& D6 ]! D1 N- M' h5 Z$ wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 I) N. e' A% x) C6 T9 u( cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 n* |& a$ }" I+ {5 l3 ^' w5 s- @7 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& x% P! G8 R- x9 } VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// \- d& r, ^1 W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 ~# }4 h* X) m& k2 b7 m" N
MCASP_RX_MODE_DMA);
% ?% q; r% @% ?7 W9 G0 V+ y. K/ J JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( j4 U) q- \* A' F. o! T* G- `/ NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 `1 _% N/ { J0 S% @# o8 Z' M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ]; ^3 j. M J! {1 E0 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! B' D: w9 x, b" {0 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% \1 }, T1 g: tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; W) Y: r$ K7 h3 u" HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 T- u5 v0 t+ W0 C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 E* }$ W! R: D, S( s% SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; L, [8 R- b% V7 }6 }3 J* h
0x00, 0xFF); /* configure the clock for transmitter */
5 ^4 e+ m9 C1 j6 J7 }4 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' o2 M0 W1 z4 I8 ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # A, C5 r% t! r/ J2 G8 ^" B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 U; X4 `6 n/ U& o; r" m! S6 a
0x00, 0xFF);% r. |5 _9 u, C/ g
7 U0 H* F2 a9 l' ]# [/* Enable synchronization of RX and TX sections */
/ R. E$ j4 J1 K0 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# t$ v. |& v7 ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 m+ C* J* i! l: Z( |" _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! K2 J6 x1 M0 J
** Set the serializers, Currently only one serializer is set as
; l+ n6 w3 S# j( c9 p2 ]! p** transmitter and one serializer as receiver.
9 c- v' X# A* }$ O*/ }8 E6 {( s: ?- ]8 ]/ D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) ~* v0 ?* f% g% e! V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 U; q+ r, Z7 b0 V4 {7 O** Configure the McASP pins
- S2 q' z8 ^4 o- @7 Q- U** Input - Frame Sync, Clock and Serializer Rx
! S; {3 Q( G( ^! F$ h$ {** Output - Serializer Tx is connected to the input of the codec
7 I) B1 Z2 w% h6 r*/7 \! r. Y0 `9 R7 B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& m+ h+ T4 o" ?/ `! b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. P# o. R8 {8 k4 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 F( z; a( b- H1 T2 w* D+ @
| MCASP_PIN_ACLKX
" z6 X8 C7 g/ ^, W9 v6 ?| MCASP_PIN_AHCLKX
( k5 t" \' x6 G8 S" M" }& T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 ?$ |( O% _" K! A1 c+ D' T$ c- U5 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , P9 @9 \. K6 U, z
| MCASP_TX_CLKFAIL
/ i. n0 l' l v5 V, y| MCASP_TX_SYNCERROR
8 p! v, N- W8 j- u+ f0 t6 j8 p ?/ Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 I2 D. y; w) r, f. K% f1 C| MCASP_RX_CLKFAIL" R! A/ q7 l, _7 r6 ~
| MCASP_RX_SYNCERROR # n" p# q# W$ N
| MCASP_RX_OVERRUN);
2 |+ P6 g/ r6 q" Y} static void I2SDataTxRxActivate(void)
7 l) Q# U) @( I$ W H4 W& l{2 b' u4 l2 R" v/ L
/* Start the clocks */; _+ }3 V" a- [& K1 R8 |) I# [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- k5 w: _" I* E+ Z J/ SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- R8 j* m1 p$ O& s/ w3 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 f$ H1 n& }- @# W R6 L6 DEDMA3_TRIG_MODE_EVENT);
# U) W' h5 f* @2 w- i+ ?' jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . c- ~5 M" c5 o! {8 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! s* @6 p9 V- j1 o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, p. h/ E( Z7 q1 Q6 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: ] `3 {8 l8 `# u4 J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ z% d0 Q( d% p/ J( B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& D& y5 L0 R: l) e' bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ z! c+ d+ n) U$ A; R0 k% O' G}
J. F0 ]; S; M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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