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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; H; u# T( I1 S1 m% M) B* Hinput mcasp_ahclkx,/ R5 X* L* m6 q2 q1 i1 n! R: w6 V
input mcasp_aclkx,
. d0 k+ ?" z' ? v' T5 Yinput axr0,' Y8 G6 r2 S Z. E
1 `, O8 x1 ~( J2 p, e. ?
output mcasp_afsr,
! j( g5 Q# G% U0 Z+ B- H8 i4 joutput mcasp_ahclkr,
( |* L/ f. \, c/ y& u+ D0 E) r& Routput mcasp_aclkr,. o* |) f# z1 M* m; h: A
output axr1,5 Y1 T( T& t- T( `# d
assign mcasp_afsr = mcasp_afsx;
0 ^$ j# O0 i: ]assign mcasp_aclkr = mcasp_aclkx;: H' e" W& [+ M
assign mcasp_ahclkr = mcasp_ahclkx;
! E$ a! T$ T: u. e, `& u2 F+ Yassign axr1 = axr0; V0 G( g ^) Q2 y- H/ G
% \9 S: b4 k1 d5 j$ W- P8 q0 F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 U, H- N% K* e y! k/ f" V
static void McASPI2SConfigure(void)
5 U" \; O) a" t, c( I{) i$ {! \. e" I4 m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' G) [5 k3 I7 N+ ] \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 C3 ^/ h4 X- X) A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); I7 N' s0 j( P) m; B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! @2 l0 _$ G* A" m6 }% k8 w# S3 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; b4 M W4 T6 m( t* P2 hMCASP_RX_MODE_DMA);
; z, p- O" K" S2 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; Y! U- n. {9 Y' n- o5 c+ E3 h$ ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 O6 z: S; a1 H1 z( g" s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' l# C6 |8 p0 `2 ~% |' c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 B& B, {* `. K% `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 [; D9 `" ]; a& D1 \8 Z3 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 C2 G0 f9 K, l1 g5 E& JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, L3 [: x2 O. q9 ?9 `) |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ J0 h$ Q; p- Q+ G. @! n$ ~( iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 b5 t2 i L4 _) u6 ~0x00, 0xFF); /* configure the clock for transmitter */
8 h* u- s, @* v, CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! I9 L: d7 S5 Q# f( y+ yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% y5 D# R( u, n' F: }& x) rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- I/ `# P" @7 P0 e& j- d
0x00, 0xFF);
+ c2 x( j' z8 K& w
8 w% P" {& J9 s9 x# c9 `/* Enable synchronization of RX and TX sections */ 7 t1 D$ l0 j' O0 e9 ^6 u. T+ K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# B9 M1 w5 B" B0 r g# [7 r( O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" e1 U( }# B, ^; h; {, O+ e' \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 o+ B) M4 K- v3 B3 U- D( Z** Set the serializers, Currently only one serializer is set as
; ]" o, k& S- c u/ B& W( B: q** transmitter and one serializer as receiver.: Q" Z6 c* F. a$ o
*/7 R! B+ {# B$ F" u2 `( _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( N% z* w* N% g/ gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, f" g6 j5 t- ]: q# r** Configure the McASP pins
! k2 \& e9 r7 }4 P: c, m** Input - Frame Sync, Clock and Serializer Rx
% M5 m% L- i7 ?$ {0 ?** Output - Serializer Tx is connected to the input of the codec |3 |7 A$ m3 s% j; b# m
*/2 J* \7 D6 `3 q$ `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: d y8 a8 c/ \& w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 _3 M9 S6 U% V8 X) f6 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- G$ s* w$ ?. w7 {6 Z" S Q5 A
| MCASP_PIN_ACLKX
8 l* e0 I i- n8 n2 O! [& \| MCASP_PIN_AHCLKX# r+ K% Z7 `, q3 Y, Z' Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& G! g, |4 g# B5 s; g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ W2 y1 p* k/ m# \4 g| MCASP_TX_CLKFAIL 0 W4 j2 b& S: q* L0 }1 K3 ]
| MCASP_TX_SYNCERROR
8 g: p; J+ f+ v. F$ M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 M: b, w/ |8 K. D0 i7 f- p| MCASP_RX_CLKFAIL& } N5 B9 l( G: `
| MCASP_RX_SYNCERROR
7 ?' z+ S0 D- r0 c, T% C& d F$ {' p| MCASP_RX_OVERRUN);4 a1 I- x; @8 |8 W
} static void I2SDataTxRxActivate(void)1 G6 Q2 n8 u2 ^. ^: ?
{
?* S" D( [* h2 w' Q( a/* Start the clocks */- r5 ^! a5 R/ @8 B1 r Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ L5 t6 |3 s& ] `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 t1 l! C( w, k6 l& y6 r% b% X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% \+ r1 c. k4 a- d1 sEDMA3_TRIG_MODE_EVENT);
0 p+ s! r& V ]. R! U: q( @- LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# D4 G4 u; q6 V' |* J0 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 P% V2 A9 y" m$ C: o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: Y6 ^( J# i! G# e( }6 i* FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 M6 [# Z/ K, R2 A1 ]; K C% w* }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& I7 S) R* N4 n6 J7 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; G0 n' j$ T& S: m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ X. z/ E+ p' N0 u. C, \} . y$ z- f# }6 ~9 K( \# @( E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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