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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, F3 e- ?$ J o+ G) h
input mcasp_ahclkx," W K1 X0 c: Y& c( f
input mcasp_aclkx,: s4 f( F2 _9 e( S+ ~% F4 N
input axr0, ?5 V4 ^# q# {+ ]% M( q& }; t5 J! E
1 r: Z$ N" Q2 Boutput mcasp_afsr,! J* {$ h9 o+ d8 T2 Q5 e e
output mcasp_ahclkr,6 M4 s* U" c$ ~( `; I; j. p& P2 E
output mcasp_aclkr,! f$ [. c$ j& s4 [. N8 x2 H6 I
output axr1,
+ B! y& X4 N. z2 ] t assign mcasp_afsr = mcasp_afsx;0 o( J! H& }1 @: c7 t
assign mcasp_aclkr = mcasp_aclkx;6 P" y8 `: \+ h* T3 _0 _5 x/ ]; v
assign mcasp_ahclkr = mcasp_ahclkx;
" H( f2 \* O9 k$ _assign axr1 = axr0; 7 b9 v" x' E3 G7 m
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * [- Q2 W- E' a6 Z2 P6 `! n8 v
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 v/ k/ w Z2 w4 T- I) j( ~$ CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 @7 c8 ~/ t+ p+ `% v& e- |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! i+ I7 u9 k# `* @" NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ [' c8 o7 T+ j, X$ W- t0 a6 w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ A+ |4 X8 ]6 E# o3 D, a
MCASP_RX_MODE_DMA);1 R+ D# Z0 p, s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 {( r; }, |; s. n6 e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' T% L6 o5 o" c& ^$ n' LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( v$ i6 T, e6 ^/ w$ [, E3 MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 _+ ]* C1 _ s$ e, U$ ~$ |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. l2 h* f7 ]& yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 I+ N8 U) F- N$ C* @( ^2 F# u4 ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- e4 K7 J, ?. T3 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 B2 ]8 ^6 x p* SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, U+ G, s j5 X( f. Z# _
0x00, 0xFF); /* configure the clock for transmitter */
7 G5 J. I# G' E0 l( d' EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! Z2 e! p% d7 e$ h8 |- k( k/ rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! \& y4 V+ X$ U8 z# N8 t+ {# w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 t8 Y! N' ^' F) E0 r
0x00, 0xFF);
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5 v; c0 i9 \+ K# B' K3 @6 M/* Enable synchronization of RX and TX sections */ ) E1 g4 X5 V# C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 i6 i d, D" s' u! SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# V. |. I7 H# K' w% o# l2 l4 |' K! kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% ]/ p- s6 a9 C** Set the serializers, Currently only one serializer is set as2 J5 h2 H9 u' R% C0 k4 u
** transmitter and one serializer as receiver.: u+ R. l7 s: j" p9 P- u
*/6 F- u& p0 Y' d' }' h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) o" |$ n' k! e1 G+ p, f, W* k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! o+ A, I1 j$ d- D. O; j** Configure the McASP pins
( g7 O% S" T. J' q4 e** Input - Frame Sync, Clock and Serializer Rx/ k- T* E% Y% I8 {1 z" F1 Z
** Output - Serializer Tx is connected to the input of the codec - M1 R, j; s0 B& K9 |
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 M- @2 x+ p3 U7 }" |- S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ \7 s% @. R- Z4 _9 N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* @9 `& B: [, @3 R3 Q) n; u2 q* D3 f4 f% m3 M| MCASP_PIN_ACLKX$ z% R' {4 q Y; f7 u& b# \2 z* d1 Q
| MCASP_PIN_AHCLKX+ V6 E* H0 F2 }8 v' V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 d$ Z6 T3 S0 z1 X* T) I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
x5 Y# U9 [6 ~7 f. A9 @, H$ P| MCASP_TX_CLKFAIL ; X. d% F" Y% r7 o
| MCASP_TX_SYNCERROR
, u& H7 u) Z: K! o% ^+ G" G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* @+ N: i W; U/ x| MCASP_RX_CLKFAIL
! c/ o2 p2 b8 M( |; O| MCASP_RX_SYNCERROR
5 _0 A6 }( G6 J6 Y, c| MCASP_RX_OVERRUN);
$ U% j+ x$ ]% |} static void I2SDataTxRxActivate(void)
/ P v! e `8 t4 {9 l7 `' z; }1 K8 \{
6 A' K. Y' b. @# H, q/* Start the clocks */2 y4 F, Y) Z' K/ ]& ?3 j( s; W; O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 j: O5 H* J: O) TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 w. A! s' L ` r' pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; B+ @2 e8 q" F* H9 g+ i% S
EDMA3_TRIG_MODE_EVENT);! n6 u- v0 r5 `# c9 d9 a% B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ e) _' r% D. _+ S( y$ }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) \5 ]4 D5 D2 `/ S$ Y9 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ G$ C' e/ Q1 U0 M( J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( v9 m8 ~- T9 q: xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% V) R9 I" c4 _6 c. L, W# cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( r5 }) N8 s. C) Q1 m# ~ C# nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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