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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ t; r7 O' ?7 P: yinput mcasp_ahclkx,
# E' p1 D' o" h# Binput mcasp_aclkx,
. ?- R# g& Z' @6 Rinput axr0,
: _! `4 M( V+ o6 c" ~ i. r+ S; _) | W# d0 ]3 `6 j. A
output mcasp_afsr,
" x/ e; P; B, _6 V, o0 moutput mcasp_ahclkr,! y9 S% @1 p. S( [7 k/ |
output mcasp_aclkr,! n. @5 Z% G L5 n: o
output axr1,
, r6 d3 m- b( s, h/ T$ Y0 [9 I- O assign mcasp_afsr = mcasp_afsx;
3 q7 w5 t- A9 a7 C# X% Bassign mcasp_aclkr = mcasp_aclkx;$ Q5 B' e L" {
assign mcasp_ahclkr = mcasp_ahclkx;
/ o7 |# A# j* W9 s) y) w0 ~; Wassign axr1 = axr0; " I; K6 F2 y7 H3 ^* d$ v& J. R8 e
8 D" k% ~% L% o+ H0 ^( ~0 C5 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & Y7 Z- M2 d o- Y
static void McASPI2SConfigure(void)4 h' F H7 j. D m; R! W( A
{% J* H& [( C- r4 X4 G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( s, F* D+ z( {" E; W. B' c) d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- {! ]/ b, [! U9 s4 g9 Y& p7 rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 X; B8 g, v( X) oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ h! T) Y+ u2 t6 iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 p; h, _) q" x, [& a" _" k9 p4 {& q' qMCASP_RX_MODE_DMA);# d+ T1 N( j& w; J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ C& r: v' }3 J9 U$ j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* x3 Y/ A* M$ O+ yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; t( I m& M; C& M* w6 b/ F9 d1 S! t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' F4 x& F( h* \# F D0 W q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# J5 {% H; @9 w c. s: D4 A! a$ }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 W9 T. Z% V: q: B: |- AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" f! z- r( `# x; \' UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 ?: A: t; c* u5 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 y1 s& ]) Q% \- {3 m- x0 E0x00, 0xFF); /* configure the clock for transmitter */
* I" }- \" I8 G, c/ dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 _2 i C: `5 }6 {8 j* d* K1 k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 Z9 P2 G# |4 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: c$ T, l/ w1 P' z R# s2 l6 k0x00, 0xFF);8 a7 X* _) D6 f; Z) N7 J* F
: {1 l4 G5 w8 }1 M6 T, i! \& T/* Enable synchronization of RX and TX sections */
7 b8 V2 Z1 |# X6 u% YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' J+ e0 i* ~% g' q) F1 OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 l9 a6 S2 @" u4 g4 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( z# k2 d, c+ q3 h2 S4 k8 D** Set the serializers, Currently only one serializer is set as+ q& {& u- `# f9 Z- d% P
** transmitter and one serializer as receiver.
/ Q# ?1 r6 U2 D d! }1 ^, |*/4 V3 t, ]* ]0 y8 p: z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 g: g# v+ l: ?6 V- j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) g! A/ T" h+ }# g$ R2 A4 O
** Configure the McASP pins
0 A/ }; A/ D. \$ W3 `5 A" X# I( q** Input - Frame Sync, Clock and Serializer Rx
1 x( M& u* D4 S }! @** Output - Serializer Tx is connected to the input of the codec 9 ^8 C0 Z" p, @2 R/ E
*/
0 R. q! i* ]( [1 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
i: H. h3 A- ?3 D- C% KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 ^/ U: G2 x D; w" X. H. n, H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) [0 P) q+ Q. A4 _4 R
| MCASP_PIN_ACLKX
7 r4 \& g, m: q: V9 b/ U| MCASP_PIN_AHCLKX
' {1 V8 p4 _; @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' D: r, X: ]$ v6 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- U j2 [/ B1 N9 F' Z5 w- z| MCASP_TX_CLKFAIL
0 m/ ?; {2 I2 h| MCASP_TX_SYNCERROR- ]6 _' q/ i2 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & O, g! U3 C1 L5 H. ]5 g6 L
| MCASP_RX_CLKFAIL3 D0 q3 y7 U3 A, W
| MCASP_RX_SYNCERROR 0 W# ^+ r; c# y: h, v$ Y
| MCASP_RX_OVERRUN);
5 @1 h* d& h! D# ?! H; z} static void I2SDataTxRxActivate(void)
( O2 i8 U6 V. B{7 B' V3 l- a/ B' @6 S( {
/* Start the clocks */# W4 z: W3 V; Y( e& Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! p7 T+ \2 i% ^2 O0 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 c3 n/ w* _5 @1 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 c9 I1 d# u4 }; m& h' A# P; ZEDMA3_TRIG_MODE_EVENT);+ J* a) f3 Q( u* g3 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ _* H& _9 O2 ?) L1 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
\- v, I& X, f- P: P- U: WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 g; @5 {! y! OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# I1 E8 t) t" b8 x5 H2 T- n1 X5 e& Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' n6 J3 s3 ?' h7 r Y, `* x! w& Z- c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 D- H Q% T9 b/ `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 [; e1 o2 E0 q# C$ K
}
! P4 L( G; p5 s# L+ U3 h) d, t. G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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