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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, J: S! g2 C/ D) ]$ ~, @6 Binput mcasp_ahclkx,
7 V- g" ` r# s+ @3 b# r) iinput mcasp_aclkx,
8 R4 ^, X. j0 C9 [% O4 X1 j" Oinput axr0,
$ `+ @( [( x% f0 ^9 P8 `& }
/ h) u. R* m- Q6 doutput mcasp_afsr,, f& {- H/ C: v4 z9 S
output mcasp_ahclkr,. H: d* \7 c1 d* L3 X0 T. m
output mcasp_aclkr,* O. ]2 n" u' k- f- O
output axr1,
7 D' a3 G4 K. C assign mcasp_afsr = mcasp_afsx; V3 M# q0 @. P
assign mcasp_aclkr = mcasp_aclkx;) K# s d# [9 R4 g. X! b, U
assign mcasp_ahclkr = mcasp_ahclkx;
3 c Y; s8 s1 ~- B6 G% Bassign axr1 = axr0;
! _; R; e. ]" B" ] F6 M+ f' [% v5 y: P2 r+ h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 d1 Q: j3 L! N6 y8 fstatic void McASPI2SConfigure(void)5 g2 J4 ^8 \0 I) B9 J7 O
{
7 B& _5 G7 g- s8 b7 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* v( G- z" n$ y4 Q' Y' ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 S, B9 V6 y6 Q- ~; p1 G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 o6 y2 G6 x. y4 Q2 Q- H1 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ `: f& d X1 G, {- ` {* ^; Q. o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 m5 b' A7 R$ qMCASP_RX_MODE_DMA);4 b/ _2 I; _& P6 b* D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' R, B, p$ C! x) ]9 w wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 `" l0 p( a% r7 V8 _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . q7 z [- B1 e T- E! r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% @4 ^( t! o! a0 B- z! L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 W m* s& k o. e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 v6 g: c, W9 C% OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 I! `7 {3 U3 c: }) }4 x& B1 |4 aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ v( U- }: _0 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 v: H# Q! M5 u+ }5 \; W! M0x00, 0xFF); /* configure the clock for transmitter */
" |( W# Y0 X, @6 E8 b* CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' X" a* [. S- pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# `: b5 Y! B% S# S, h5 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! n4 b+ h p# p$ P6 k. X, U0x00, 0xFF);5 n3 ]9 Y- L7 c
* R! u$ Z; R2 B: p
/* Enable synchronization of RX and TX sections */
; q- c; G, {, G3 L. qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 S9 v( L U9 P. V. z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" y0 e" q3 |9 P, [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; G. t4 N& Y" F* U' z( E) ]9 v** Set the serializers, Currently only one serializer is set as' L; W& t0 g! a$ a$ u8 t, a
** transmitter and one serializer as receiver.
3 H+ u6 E1 }9 n; T3 T0 Q*/) t; P/ R' g, J1 a8 d% U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' o3 ]$ \' M: L' H7 l# k3 y- d* kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 I$ [3 F* t4 A
** Configure the McASP pins
' J5 M) u- ]# ^* j/ Q0 v6 g, Z** Input - Frame Sync, Clock and Serializer Rx
- T6 ~, J) y/ L& G5 N( C** Output - Serializer Tx is connected to the input of the codec
4 [' K9 M# X$ n*/- b' ]: G0 ^% p- Z k% N3 n9 X. [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 e6 i( L8 d' Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, z( `0 C& u- w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) z/ A$ K: m9 H' L+ J% B% d: J' C6 b
| MCASP_PIN_ACLKX
+ v% s7 J3 \$ t8 x| MCASP_PIN_AHCLKX
3 E$ g" L9 u6 D7 W$ v; N$ [& W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 V }% c: S- @6 ~! lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. d { J' l2 b( c4 Q5 w% \- g| MCASP_TX_CLKFAIL
0 ^$ U! f7 m' G$ n| MCASP_TX_SYNCERROR$ P! p; q8 s4 z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! ]' K2 M/ S; c" ~" b| MCASP_RX_CLKFAIL
) o$ r Y% w, m' j| MCASP_RX_SYNCERROR
/ s( k, E5 l' I2 _6 x; P( }| MCASP_RX_OVERRUN);9 k) @8 ]+ z1 q- v# ]- [$ `( U
} static void I2SDataTxRxActivate(void)
, F- ~& ~6 s% `* \2 J; t{
6 C) U4 F, D. N0 ^+ f" x/* Start the clocks */
! [; \% V I7 h, V+ j8 \8 ]8 g9 u! b8 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 y" ~. D9 j* `2 a$ ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* }0 M! I& ^, e& G- n' I' s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ Z8 n& Y9 p# t# ~
EDMA3_TRIG_MODE_EVENT);) ^. W( ? f% C# D' B6 ?; f9 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 q. f% ], V: D* S4 F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 B2 O/ ^8 F3 ]" y4 LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! \ s! i! y* T4 q' |5 w1 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 h9 v$ x6 }4 v* @4 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 G+ K- p. A. M% l0 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ ~" @5 C1 _6 L# e% G$ N- m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# A/ c; M! a1 P0 k} * X' i6 k- b* ?- c: r$ i6 @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , m4 |% ~7 i$ v: j
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