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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ B1 R0 n' S2 W0 L
input mcasp_ahclkx,9 x a5 g3 W" m% F3 j3 Y: H
input mcasp_aclkx,- i6 c: ]1 R* F( b, Z
input axr0," ~9 t( B8 ^$ z) @7 U9 R
M( f% `+ X8 }! D- c& L! O4 h4 R
output mcasp_afsr,5 d( h5 ^. `; `( U) c) {
output mcasp_ahclkr,
" `. n. ]8 T2 Y) s" `- poutput mcasp_aclkr,
9 s: q# b1 ?, _5 q0 S1 uoutput axr1,
9 _) t- _# I B7 N4 j assign mcasp_afsr = mcasp_afsx;
/ r, X/ l# }: |% x+ Lassign mcasp_aclkr = mcasp_aclkx;8 Y# N4 o0 \4 X; x* }- J% M
assign mcasp_ahclkr = mcasp_ahclkx;1 ~- C: m6 G) J; g8 R# @5 j
assign axr1 = axr0; 2 {+ K, g( s: [1 |# T% s. r9 N
5 c5 c; b a: w( {# ?, e. q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' h! x) K6 k4 N9 }
static void McASPI2SConfigure(void)
9 V& ?; {0 [6 q2 Y: c1 Y; _{/ E( g3 K0 F/ K3 ^% ~/ X" h0 U, S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 ?2 N1 J4 c7 m; n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. K% z" N' O, C" o' f: [) \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& p# N2 G" Y" }) nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 U+ p R- h, o$ @# h! \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& Q' w: L6 M) n- I
MCASP_RX_MODE_DMA);4 {, P+ l7 ~, \2 }( `3 \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( I, \: ~* M: y0 u7 ?, CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! u6 m- d. b* b. N9 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' }4 n4 |% K6 D1 v7 r* L4 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ L: y% e o( G+ G% ~1 ]- {" M! q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) {9 F" A8 J& a7 |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* O; n: b& I% ]9 \. w4 O8 x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 @4 j L7 V2 j3 T2 i# f' gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " b, G& x! t5 W/ a5 t0 I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 K* _$ |' l; ]. `4 ~1 d- b$ F% [
0x00, 0xFF); /* configure the clock for transmitter */
# [6 ]! T) x2 _" C/ AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 f, B: U1 T1 p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! u4 Z! j# F! n' p* ^ `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: |- e5 G% O5 ^( g* R# r
0x00, 0xFF);2 S* {6 k. M8 z$ [8 |) ~8 k2 v& Q- E
g+ X; D0 P4 I) w0 M/* Enable synchronization of RX and TX sections */ : o: q, I) `) J% f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 F& O4 _! X5 M0 Q/ i* t) AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ \: e9 B9 n1 l4 @, j# x% ~' ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( R' g& X X$ g2 t3 l
** Set the serializers, Currently only one serializer is set as
7 J# u, ^8 L4 _# s** transmitter and one serializer as receiver.
" l% l9 j& w) i& l*/
. M- k7 _# H& w. o* i& fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 P9 w( C: [2 M. x7 I/ s2 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. i% R8 m9 q" m. k# J2 W& B** Configure the McASP pins ! R i% s" B) {% g0 [; `- D6 [
** Input - Frame Sync, Clock and Serializer Rx
/ T, `: y/ k, n' M: K# v# Z- ?** Output - Serializer Tx is connected to the input of the codec
6 l7 h9 ]- ~1 a+ W*/
6 b/ B. W/ C( j" [2 W6 ]$ ]- XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ~/ L2 D- v8 ~! }4 \- v- I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, a" \% e. A. c( t7 l. z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 c! g2 j$ X' @: F5 C& I. z
| MCASP_PIN_ACLKX
3 e: j" G" W1 U, z4 ^| MCASP_PIN_AHCLKX( |: e5 e4 p/ ?8 Y! y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- O% V6 D# \3 |* K- _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 n# g2 C2 Q P$ _0 W7 Q/ C| MCASP_TX_CLKFAIL * w3 x# w, H3 n5 X- G( t+ p) t
| MCASP_TX_SYNCERROR1 n* d3 U! R7 f# E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ h/ L' `; Q6 t: e* s! t( v3 ~| MCASP_RX_CLKFAIL
- b5 l+ c. C8 y2 G. r| MCASP_RX_SYNCERROR 4 T" W! {- K7 g4 C7 V1 C2 P( c
| MCASP_RX_OVERRUN);
5 i9 c! p c5 @6 K} static void I2SDataTxRxActivate(void)
; e3 C! e% U, }. F, F{
' H3 `& I* T d/* Start the clocks */
, t4 d3 Q+ K% `. K2 {* fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ Y, b: Q4 f. h0 V2 hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
c; A. L# ?4 ~; A2 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 Y3 A& S) x/ Y, M5 b
EDMA3_TRIG_MODE_EVENT);
$ t2 p3 H5 P) l5 B. ?! nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ g# I* l8 s( J6 t# V7 nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: @5 i* l' d- R2 {! _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 K0 z( G, W& Y$ c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ u8 ~+ K5 b/ k0 \( n$ x9 [0 F8 [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ q( i% F# x; z+ \, i/ nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# O4 [0 m# @0 J1 Q9 Q) u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" i/ V6 t: Y1 a: w% S+ j) q} + B- i9 e* O3 F0 x, E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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