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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," ~+ t5 ~ s/ u" L8 U
input mcasp_ahclkx,
/ z. x7 ~ X& \/ hinput mcasp_aclkx,
1 n1 F; w% j" B$ p q/ ginput axr0,- C) V3 G9 E; h% o* q
3 N8 X9 Y1 i$ N" C; M0 doutput mcasp_afsr, I; w7 n6 x+ P2 }
output mcasp_ahclkr,5 @2 L7 A* m# ~2 z. ?% D/ ?7 ]0 [
output mcasp_aclkr,+ ] B: S* i3 b3 t. T" F y# \$ m/ S
output axr1,
9 K& C, q, {# l$ [( N assign mcasp_afsr = mcasp_afsx;: c @6 O3 _+ C& [
assign mcasp_aclkr = mcasp_aclkx;% c, [6 r+ ^; Z4 v4 F% W
assign mcasp_ahclkr = mcasp_ahclkx;
$ T5 J7 k$ O/ ]' }" G8 zassign axr1 = axr0; 0 Q+ s$ ^. j2 y0 V; z5 X1 t
8 a/ n' L4 F$ ^9 _9 p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( `. v3 b* ?# t2 g* Sstatic void McASPI2SConfigure(void)
* z$ N7 b3 t9 V( K" \4 D* Y+ F{1 q5 ?& U$ c, g2 e# t1 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) }# d2 {+ r9 d. S% s- P6 ^% B% t* I |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- @+ }/ X) F% O% a/ i$ ^2 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 n; _9 O2 [* ~# b3 g! iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 O9 @' H3 |/ M) y# s* w& `+ B: [* ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, x0 {2 t/ A9 V& N( c9 L! S+ |
MCASP_RX_MODE_DMA);
! u) r0 k) Z/ D$ F5 t" oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 N- |3 c% O' }, e8 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" N! \: P) ], g% E* b( `$ |) {) b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 W7 E" f' R3 R( _8 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# e; y% H/ f+ I. S2 T' s2 i; ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 P) A* F8 F5 k4 K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 u* S: r8 W, P) N bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 D, o( ^. X+ Z E& R% JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: ~5 H: ?, n7 \- Z2 X1 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( P# m4 f: z9 k, C% S: V* G9 u; X
0x00, 0xFF); /* configure the clock for transmitter */
7 E+ D& d0 [. OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ V' F( W$ {9 {! n2 x, ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + @! W! W. d$ D$ _1 E( f+ p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( W5 m/ q7 x# n K0x00, 0xFF);
+ @* T6 ?& v' C% Z: C; g: s8 ~! c+ t! [$ n
/* Enable synchronization of RX and TX sections */ 4 Y7 f" C% _1 z9 g1 Q& Q0 g" j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ Z2 o6 P" F. P8 n) v6 y- X' t0 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& v1 i: m* s2 FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ K+ p8 a) a* M5 a$ o3 M
** Set the serializers, Currently only one serializer is set as8 [& g7 M7 P' X$ K) M3 n
** transmitter and one serializer as receiver.
- \" f& q4 q1 n& n2 O*/
: Z+ W+ M( [% q8 Z6 R' rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: E/ f9 s' c" ~" G9 j! m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ p% _1 l1 L4 J** Configure the McASP pins # s) _8 {: d, I. Q/ m
** Input - Frame Sync, Clock and Serializer Rx
1 V, x+ K+ t: p$ J- ]. a e2 x+ f: U** Output - Serializer Tx is connected to the input of the codec 7 Z% X* o1 y+ `! Z
*/
6 Z" ~# w3 o: Z0 Q2 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ }2 \: x; V' C& @$ r/ L3 y* `! tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) W( M, a3 Q2 ?, O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- X: `) l; X( } m' J( n, f/ H
| MCASP_PIN_ACLKX
1 h3 F! I0 M- _- Q# q$ m. a% s| MCASP_PIN_AHCLKX0 ~% M; H7 g% ~6 i1 e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ O4 X1 M# g4 X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' T& h! K2 D" s| MCASP_TX_CLKFAIL 1 U- R$ I5 t' q1 c7 L) O
| MCASP_TX_SYNCERROR
, I9 ]& k& {, p6 ?! X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: g0 a. k4 T8 j: G9 w2 Y8 _4 t# o# u| MCASP_RX_CLKFAIL0 J3 J) x& B2 }* |* H
| MCASP_RX_SYNCERROR 4 O6 i3 V7 ?" \
| MCASP_RX_OVERRUN);
0 B- @$ o" O. c9 A& a, Q} static void I2SDataTxRxActivate(void)
[/ ~4 u' c6 O; h* E3 j9 J{
, T; l# E! b! F1 O5 f/* Start the clocks */
- T9 Z. z4 o/ xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 k0 ^0 z' V6 E# a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) D% Z( I. F4 F2 Z' Y0 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 Z; W, ~/ _# U* Z, ~# m
EDMA3_TRIG_MODE_EVENT);
+ L' b7 J2 ]0 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* \; n: q! b7 j* L F7 f6 KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 e. ^9 ?6 e8 NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 f' ]9 V* s fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 n4 \7 p7 W9 I$ u. q! T# Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 ^& m; I* E- H3 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; g. u. D% J- A9 L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 @: |; q( z; M1 g} & q L" v* z% Z8 c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( \! L% P( V A! _- o {
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