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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ H' ], k% Q* N+ Minput mcasp_ahclkx,# |( C$ f2 ?& @2 V& R. t
input mcasp_aclkx,4 u; `8 D5 O% x1 s
input axr0,4 f; u- \3 Y6 t; E5 g5 x }; Q
' i( w' {: a! w! k8 |: ?% y1 A
output mcasp_afsr,
( f# o& ~( k( _" Eoutput mcasp_ahclkr,& R5 O+ ?* ]) H1 a7 K# J8 B
output mcasp_aclkr,
1 a) ?2 ?" u% Soutput axr1,
' _! y6 E+ C; i+ K assign mcasp_afsr = mcasp_afsx;# A& E- }, c# R
assign mcasp_aclkr = mcasp_aclkx;1 Q8 C% p4 P) u4 H) r+ A
assign mcasp_ahclkr = mcasp_ahclkx;" z) P/ W, M; D( c9 e
assign axr1 = axr0; 4 Y& L6 s$ c/ _- l
9 v* I0 ]$ p! G- u$ N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( D+ L' r& N( H7 f/ d9 Gstatic void McASPI2SConfigure(void)8 x* r8 w0 Z% I6 d5 f9 j
{
( W. s' w) o7 \. ?: h/ JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- S' x' z% A2 r2 Q2 W( @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 G* ^. b1 [& R0 Y0 H! K" h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ ^# y% `2 y6 r" r$ F% rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 ~( W" g$ X* |' D) Y" L( `2 @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 J/ t1 w1 V+ R7 ]
MCASP_RX_MODE_DMA);
! B+ s7 S% ~8 g6 M+ }% P hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 s8 |4 [ _& k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' D$ ?% S* j6 L" h' P6 C0 w# o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 W2 D7 a$ r9 a$ ~; I: YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& m/ u K" Z4 u# b7 K2 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 f; A3 r5 f% ^4 ~9 t9 W$ OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% c, T5 w4 T2 N8 i- fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* h$ a+ c$ P# N$ m4 o" ^4 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' N& h3 ]# m9 i1 l6 M0 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' D$ s' C: h/ f$ k$ r" K
0x00, 0xFF); /* configure the clock for transmitter */' I9 S6 p3 J: P; R' V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 ?2 j6 M3 ^+ m4 H1 Y% BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: C, s4 \$ ~% ]! MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ d, z. B2 B( ^* K N* D6 }) B1 } u' w
0x00, 0xFF);. I, p o' l. d4 u5 \
% q! c8 y" C7 A* z* M3 x/* Enable synchronization of RX and TX sections */ & N" k h& G3 o h' E1 D+ a5 e8 c0 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 h6 Z) L3 E/ ?9 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 R& W, N+ g+ _ e) DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# i- l: I' k- q# n6 s** Set the serializers, Currently only one serializer is set as' B, Z0 u$ C( [5 n3 f
** transmitter and one serializer as receiver.
" ^1 ]) U- u" j+ \*/
, F" R. l9 U% K/ z/ hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 {* X8 g3 @/ \( w$ V" I } q& t! B6 rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# J# t7 ?9 H% F( H# `# i! C( S
** Configure the McASP pins
$ x2 u" u& X# W% D" F! u. Y* O& z** Input - Frame Sync, Clock and Serializer Rx
' E( @2 J0 _1 h" f. F3 M( w** Output - Serializer Tx is connected to the input of the codec " D2 g3 l4 c- X. U9 w8 Q l) X8 ]
*/
7 H! f/ N* c2 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 w( J- \: S5 F; X: Y7 z4 s- i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. O7 J- l% x/ M- [2 |7 B: S& @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ A2 y q% t6 ]$ p2 m6 d| MCASP_PIN_ACLKX+ W$ }( ~+ C0 o
| MCASP_PIN_AHCLKX! F* V$ i+ H! P" T3 T1 z; u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' M8 S8 z- k0 V: j. S. xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* J* @ U: G* b# i: Q, f; m& @| MCASP_TX_CLKFAIL
" ^6 C( b/ Z$ L| MCASP_TX_SYNCERROR
0 M$ o: S$ _& W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' z- N! ?6 J" M3 |( U( P" |0 I' }| MCASP_RX_CLKFAIL
" K* O, a0 d2 c! X| MCASP_RX_SYNCERROR Q" W, B* R( q
| MCASP_RX_OVERRUN);
: P! t' l0 `) f( d& ]2 h: w: r} static void I2SDataTxRxActivate(void)
6 _' h5 t' l$ A9 V{
! G" X! _' k! x. L/* Start the clocks */
2 m! @) _4 M$ \- X. \. PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 V) I1 f" @% V8 H' A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 r+ {2 X$ v7 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 ^9 `) B7 g5 jEDMA3_TRIG_MODE_EVENT);$ k; a1 t( f. _' Y e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* r$ O8 k& U! M% T' `% h6 Y* N4 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) T# m- ^7 b) p" g& [2 }# HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: u- _6 D+ D7 |" H( M: i8 {3 xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 `- n, c5 }5 Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 v8 B' u: E: k* l% ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! _& w, Q; I& S; q. Y, LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( s6 A$ C! y/ _1 c}
5 u+ Y+ g" Q" R7 t* \5 X q0 y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; s. g( _5 }; o( g4 Y, n2 |
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