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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," j% f1 P6 ]; _" Z/ T! J
input mcasp_ahclkx,- b/ v6 o- b2 N7 [) }9 W
input mcasp_aclkx,
/ c7 d; k2 _' H+ W! e$ C# z. ]input axr0,
% C( e2 B2 N: ?3 M$ w1 c- }% ~9 O# y: {9 [
output mcasp_afsr,
6 O, z9 E7 h9 |9 E* ooutput mcasp_ahclkr,
' t! H3 S; v# q; ~9 z$ ^1 Xoutput mcasp_aclkr,. X0 N) ]6 m' f% h m# Z9 b
output axr1,, T5 J+ y0 T( Q$ f" C
assign mcasp_afsr = mcasp_afsx;
! O+ r1 I' m8 {* Y( a4 dassign mcasp_aclkr = mcasp_aclkx;
' W4 G7 ]( Y- U8 yassign mcasp_ahclkr = mcasp_ahclkx;
; M W: ~- P7 ~$ i' Sassign axr1 = axr0;
& g; O$ V9 P+ ~$ M3 X' T. Q, z* X$ [: P& `1 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' T/ r+ m( C9 @; R* C# k. D6 t6 U) t/ |( l
static void McASPI2SConfigure(void)3 u' @2 z! m9 n& t4 }9 m3 {
{" J9 |! H) e$ V; O3 ~% r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& U7 J5 T" A5 [# T* T: Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 C0 X8 Y; H/ B, ~( p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& s0 b, @# m* x" d9 \; VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 n! ?" ^3 Q2 h$ k2 s4 r3 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! v; d( a, ^8 s1 [1 n$ k0 }/ t- kMCASP_RX_MODE_DMA);
" A2 I) l, C3 G8 E# LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 a% j0 e u" V- c1 X: c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 `5 g$ V4 {! U \& J0 Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 W" e2 N* O% l5 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 E/ O3 {- v- _* F$ Z8 u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / X0 S* f6 ^( S' d' j3 ~1 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
o- y" X. @1 h! p8 Z6 _+ ^" mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% z7 q Z% q* mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 r: j3 z; @5 s6 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 {4 [0 j2 [% ~9 @+ m) F0x00, 0xFF); /* configure the clock for transmitter */
9 @0 c0 ]7 T& f+ j) J! [6 B# }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 b7 C% b3 t4 I% j& O2 SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 X! {2 n! _: Q' G9 xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ T* B8 `& z& B, i! |! ]0x00, 0xFF);
$ T6 ~. Z! }! l9 B5 C9 n
5 O- j# g" x* J/ Z9 P/* Enable synchronization of RX and TX sections */ $ c; h- N$ E2 P) O8 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 C& x( G1 F* C* G5 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 Y' R- Z! M; r) N$ w; p& NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ o$ r( c7 E2 C0 z/ V% x# E; a** Set the serializers, Currently only one serializer is set as
% A5 W, j$ ]/ g/ D: t** transmitter and one serializer as receiver.+ B4 c# P y9 e: R# G
*/
- ~: B9 H; W% ^9 hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ Q# @) ], c& p9 D- Z) H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 Z9 E4 o& D) X, m** Configure the McASP pins
1 H+ b! Q2 U/ D; j$ \5 D3 E: v. `** Input - Frame Sync, Clock and Serializer Rx' E) F' S& Q! W' `1 G! O: J
** Output - Serializer Tx is connected to the input of the codec # l# t8 p' {. n& Y
*/$ q& y+ U1 _5 W: ]* v9 s' z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" p' G$ v+ ^/ M; ~5 B1 \+ y, c# KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ _) a, ?5 u0 v' xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* `+ W2 ]3 ^9 H5 w% g t0 d3 i2 t| MCASP_PIN_ACLKX
" |' c5 `2 w. m# C| MCASP_PIN_AHCLKX
: v1 ]6 |: R( g- r; p+ W. ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- ?8 ^% N) @/ \8 ?: O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : s$ f% E9 P3 w
| MCASP_TX_CLKFAIL
) C% W" D% R# q1 q( t| MCASP_TX_SYNCERROR4 v% G% L) m& S! A; `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 u; y# O; z* m& Y| MCASP_RX_CLKFAIL& j9 k6 y8 T7 W# J
| MCASP_RX_SYNCERROR
! S. X2 _ t/ z3 Q5 Q| MCASP_RX_OVERRUN);( n, p7 q) W6 z/ Y! }
} static void I2SDataTxRxActivate(void)
- E* s( m8 w5 F+ q# R2 M- T{
- V4 u" L% L! i2 A& l% u9 g& A5 l7 t/* Start the clocks */
# d1 Z5 ?7 P7 A, p; l9 ?4 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: ]3 E' ]% M) C3 u% h! |+ f( H0 oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 G2 I9 V! R6 \# Y0 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, _, ^( X+ U. t' v+ x7 L8 A
EDMA3_TRIG_MODE_EVENT);) l& N$ X! Q6 a, c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 b0 C& G; L" i5 C' ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( r# U4 o7 u2 S1 u0 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 j" k) c% v: y# ^( E; ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% u' F: W+ Y6 _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, N) s$ F! G4 S, p/ ~7 u: ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS); I( I! R: o' ~1 ?5 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ [: N( x! ]% m* }" |}
( [5 j4 H* F3 H5 l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , F9 D$ c0 H- U* T* ^% U7 |
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