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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ {2 D9 J2 ]8 K% g5 h% |
input mcasp_ahclkx,
( T$ ~7 P/ x! ]" k9 x$ {input mcasp_aclkx,. t: V9 A I T( q3 z
input axr0,
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output mcasp_afsr,
$ i7 {3 `+ u m1 \% toutput mcasp_ahclkr,: P3 u1 E- m$ A+ w; q+ L! {3 Z
output mcasp_aclkr,6 `6 _) _$ k6 g
output axr1,
3 @2 q9 ^ p" d! a' L assign mcasp_afsr = mcasp_afsx;4 q& w; a7 Y, l3 a
assign mcasp_aclkr = mcasp_aclkx;; S2 [8 @/ m# U3 v
assign mcasp_ahclkr = mcasp_ahclkx;
5 r% I+ r6 p: O5 bassign axr1 = axr0;
) \8 j% I" S/ [6 u6 D; y( Q2 u9 i) J/ a+ J9 |1 e! t+ [/ H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; x- F5 L4 D; B0 l* b
static void McASPI2SConfigure(void)/ o$ W; K( c# i& `+ g6 D% z
{
. P/ u/ M. z: g4 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 w! f. r( a5 i/ A" \7 WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; v/ X( D1 T' }: U) ^6 E. J( H) }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" J: Z+ i6 {, |: cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% k5 u: o2 d. N% ~/ LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 J5 j- \- s7 z
MCASP_RX_MODE_DMA);
; B- ~# F6 B* {' m$ S; rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 @ J% H; V. l6 U) o" {5 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- d& F& X( W( ]& @- x4 X% ~, Q# nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / m6 a4 C9 {9 j9 `1 b: X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( F+ J8 n l& q' {# e) L8 N2 B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , w" H; t3 k3 @4 @' |# |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
p% E' l# t# n+ T; I% W7 JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. z y( e& |( z$ w" i7 a; dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 j" v* h% \' h1 F% R* `% P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 o8 j+ Y1 `; j1 O# N, [+ g$ F5 e0x00, 0xFF); /* configure the clock for transmitter */ I. D, w- P1 g5 o" {$ g J5 I2 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 E8 @6 a3 M* {3 B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # H, e! g& D0 `7 G. ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 p: O# y& k) Y- p, _4 |7 K) k
0x00, 0xFF);! p: f; S; Q6 I$ f
5 }0 N7 i4 D$ t$ Z5 r9 u5 o/* Enable synchronization of RX and TX sections */
( w. d( ^; Z" n( @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// e7 Y, j8 `0 r- B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' J! w8 M% C; C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) I e7 X {& \6 U
** Set the serializers, Currently only one serializer is set as3 S2 W& {9 h8 S7 l3 R5 S
** transmitter and one serializer as receiver.: m, u+ Z: r, I3 T9 `, c" |) W
*/7 D- J+ E. A! w( F! w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% t1 s; D0 I9 X: k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ \& d' b$ g9 v
** Configure the McASP pins
# `( x' B3 S. ~; H2 Z) {& R4 D** Input - Frame Sync, Clock and Serializer Rx
$ }1 C7 m8 B, X2 ]** Output - Serializer Tx is connected to the input of the codec 8 {# L# P0 D { v
*/1 ^. {1 I7 Q7 g$ U' ]; C0 Z/ J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 W4 E5 _' u6 L* Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. N# K2 t! r. J, L2 u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 f- K7 d5 y! E| MCASP_PIN_ACLKX, q, @9 g+ t* T1 Y0 g% h
| MCASP_PIN_AHCLKX) [! C4 a; Q1 D2 C$ f% m5 S$ ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* r; Q' q" ?$ A" `. oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 _9 R' g' V" |8 N$ \* n| MCASP_TX_CLKFAIL
9 v$ X2 A* Q% ` F) P* `$ k| MCASP_TX_SYNCERROR
2 ]& J+ Q2 Y- b+ N) {" [+ Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ `% x9 ]) N! G7 ~) i| MCASP_RX_CLKFAIL
0 E- @- q6 o; d; i$ J5 c| MCASP_RX_SYNCERROR $ |+ |; B; t$ L3 a
| MCASP_RX_OVERRUN);) o+ `% A$ x, p E" G
} static void I2SDataTxRxActivate(void)
2 n4 {" ]' n: H0 a6 Q{3 A0 F8 l. F. M: X" t x; K& ?
/* Start the clocks */
+ F5 s4 \3 K ?& W7 I# NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ V4 H5 h+ S! V* \; J5 C$ }3 fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 ~3 Y/ G( f( [$ p0 |; ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% e; ?2 ]! {9 e; ? REDMA3_TRIG_MODE_EVENT);. e8 Q t; T- R, i/ W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : M5 P: z" J# [' e/ L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, Q5 d; a6 ]+ t0 xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# M _7 E, J+ a! I7 {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 S( j4 q$ M9 w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 [. A% C- h# B$ h/ t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& G% Q" b3 ~& a4 \1 n# `: C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / B2 n3 t, a" d [
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