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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 U6 X& l2 C% C6 H% k' \, _
input mcasp_ahclkx,9 a. D" Y o: ^" u. r2 j
input mcasp_aclkx,
& A8 }! z+ C o, S* c+ S" H. j, r5 Finput axr0,
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0 \: B& c9 i P) }* W! ioutput mcasp_afsr,
' d& q# R A. M- W$ D( e, m( ?output mcasp_ahclkr,
# `# ], }6 I$ z Coutput mcasp_aclkr,4 Z) h& s p3 g3 Y5 A$ g
output axr1,
) X2 o# V! N* s( T1 ]1 ]* W/ A/ u assign mcasp_afsr = mcasp_afsx;
' M3 z# v* d& C- R% B( cassign mcasp_aclkr = mcasp_aclkx;
! ^! [) ]' ^! g+ x! I dassign mcasp_ahclkr = mcasp_ahclkx;
! E) I9 u: J& [7 xassign axr1 = axr0;
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6 t; A6 [: N- s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' z8 F4 i2 x% T4 U. y) R
static void McASPI2SConfigure(void)
! k" f/ }% E1 z- ~% y" q: M* h k0 y' |( T{
7 k9 r. c1 \9 x9 t9 c, hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* U$ E6 o4 c7 n0 r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: }+ h' q' m/ k; U/ n# oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' l5 ?* E6 j; Z6 S5 N8 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* F3 ^- F& S' L# W2 f4 m+ fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# `' Z- @' h, ~MCASP_RX_MODE_DMA);5 ]3 f/ O, x9 ]7 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 ~7 {* k0 s7 U3 W4 o$ `5 c# X" F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* R; d/ v: M" @1 d% [2 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 D" o* H( F6 L$ C$ I) NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- z! B. {# y) N; p/ z+ H& z1 w/ U7 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) O: V6 L" Z2 |% L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 ^* K% ~9 H( Z8 L4 m5 q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; k2 v+ m' I) V7 Y& S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ @ Z1 {7 W* O# N3 [/ Y: a* NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* C- e, [4 } O/ |, @5 w ?8 r
0x00, 0xFF); /* configure the clock for transmitter */+ m. ~4 I, ]& V: f2 R1 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' x: l: y* n% o. s% x- }7 o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % m, A v0 Y% J/ W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 S6 U3 G( k, g$ K3 a
0x00, 0xFF);# t5 c" D! O( g# q% x) t! E
2 O/ A* S8 I8 l/* Enable synchronization of RX and TX sections */
5 S" U @: O; t! Z3 q; mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% X1 N! V: H2 J( ~* I! T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- o! L9 }" ^$ ] E$ W; o5 |4 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ ~7 [0 }2 M8 F3 l
** Set the serializers, Currently only one serializer is set as
9 G6 {5 J6 o4 L+ [' q0 \** transmitter and one serializer as receiver.% P& f$ e2 C) Q5 S5 T+ z
*/) X+ Z+ P) _& I" {, U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; Y1 ~3 @5 O$ h- @( l2 W, \+ r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( E" ?' l" k# }+ M** Configure the McASP pins
9 X6 R- Y# m# b* l. u& K6 f3 {** Input - Frame Sync, Clock and Serializer Rx
h, b7 v, o6 k9 p x8 b0 _** Output - Serializer Tx is connected to the input of the codec : z& E5 T2 _" b2 H" u9 B
*/
5 V* |' [, Z) S) S$ @8 K, X- a3 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- |' n% E5 W- Y1 G& l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ ^9 W4 C( L% [3 y& x9 d- t2 C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% D. g( _5 e V% U+ v| MCASP_PIN_ACLKX
+ ~" n2 N( K8 x. h| MCASP_PIN_AHCLKX
* t! A/ j% R& d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// E* f/ m( W7 k2 D! A- e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; @: Y" S# `1 c: E% M( \5 }
| MCASP_TX_CLKFAIL
( k( [ O7 B/ j, _- E| MCASP_TX_SYNCERROR
; i; [) h8 `# j2 }5 U- a `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; U6 ?) T/ f% C$ B
| MCASP_RX_CLKFAIL
. V, l& @0 _ N: b! L7 o| MCASP_RX_SYNCERROR 6 k. ]: O: `; E' B: ^
| MCASP_RX_OVERRUN);
, b8 r; Y$ E; e @. V} static void I2SDataTxRxActivate(void)
4 |+ x7 g x) ?& [{" P. z$ w; ~$ P; o
/* Start the clocks */
" t1 Y1 k# K4 i* Y6 `, Y/ \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! Y, C/ W5 [7 }) x* _- ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) B- E' |/ N: a; s7 K; ~7 B( M! sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 x6 k: F9 Y$ u4 _! }1 Z1 r
EDMA3_TRIG_MODE_EVENT);
+ y: m3 M# N! m' O* R8 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# C, e7 l( G5 uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 X: L- o3 n$ A& n! E+ S6 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 E- {& C/ P3 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ c7 j- U! v& r# U5 b4 N9 p D9 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! T# ^* j& ^6 Y: t4 _0 ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 d) q, b3 Y& v" B5 QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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