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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: l. _$ s* L; c" X( h1 k2 j
input mcasp_ahclkx,# e2 G7 n3 A6 K3 {
input mcasp_aclkx,, r( T2 r+ ?) g; a% ^- O5 V$ J
input axr0,& y5 I/ W+ q# e" x* l, `
/ I9 l- f' l: G0 N1 e
output mcasp_afsr,
& s, n l( p' H. _0 m0 K- |output mcasp_ahclkr,
- @! H5 y! m. Q% q, Noutput mcasp_aclkr,3 L K3 \* N4 i' E
output axr1,
: S7 G8 R* G* }% e7 u assign mcasp_afsr = mcasp_afsx;
) U, I! V/ s5 }' u( |/ Wassign mcasp_aclkr = mcasp_aclkx;! r0 U( [+ }0 ~
assign mcasp_ahclkr = mcasp_ahclkx; n' i9 e* `0 ^; _+ K: A
assign axr1 = axr0; / l- T1 |1 `& ^/ d2 Q2 K
9 r! M* c7 Q8 i; r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - C2 A4 r3 v7 V
static void McASPI2SConfigure(void)
/ X9 `$ D2 Q( y$ j5 z{; ~0 I% v; b! N# b: F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 O# H, _# \# p& o. a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: F7 T: X) p( }6 O1 HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) {6 n4 }) k4 T1 LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ J/ {9 L7 c" p$ `6 k" |; \8 n; V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ G. ]9 A1 c* ?& x _1 P; U7 |/ NMCASP_RX_MODE_DMA);9 Q7 g8 B1 w$ a& D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ h9 c% L! h1 _2 x0 z7 ]$ AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
O; H) H1 _( n' W0 C4 ?8 k" Q6 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' N0 Y. `3 T# B( ~8 y; _6 i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& |* N. k) U/ WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ B) I0 z* `3 e9 W- E& G% X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& u4 ^& C' n AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( F% e8 Y* `% g. [' K' ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 g2 ?9 B9 k4 [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. u- s( f$ ~- p0x00, 0xFF); /* configure the clock for transmitter */3 ?- c! c4 W! N6 L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 [% A: A7 P+ c, u* _/ BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & x7 [& W5 \+ K$ _+ m& L, d7 ?0 A9 Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 O& U! Z7 c# y- `" ^
0x00, 0xFF);; r! C( S& q: h4 u% h
, J, l6 S2 O; ~& ]$ P) u# l
/* Enable synchronization of RX and TX sections */
5 `4 [0 n: G5 i1 J6 m3 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 a' V8 _) h4 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 E$ Q4 C, b \3 c, ]% UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 F, S- D# C( O3 L! S8 j** Set the serializers, Currently only one serializer is set as5 b3 ~" [$ N D& q5 D1 Y
** transmitter and one serializer as receiver.
$ c M4 w2 u, V+ ]5 k/ i*/+ z6 P2 @' B8 I+ {& W2 H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" h; Q2 y* g8 m1 X$ X* f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 S& ?7 d$ P6 y6 B8 \** Configure the McASP pins
6 D0 N% y9 v: T- D! r** Input - Frame Sync, Clock and Serializer Rx; m$ G" }6 F$ v' f, |; v7 I+ e
** Output - Serializer Tx is connected to the input of the codec
& I, U9 s6 e, n% j* l/ M*/ H; H7 Q1 t6 L$ R( @9 m3 N$ f! M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. v1 c9 F/ h% x( b" m! R" x! r& IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' j: l1 H, S+ [8 K# a8 HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! ~4 ]8 h" w; H- f| MCASP_PIN_ACLKX) g. P' _0 M5 k3 t- A X' y" F0 b- v
| MCASP_PIN_AHCLKX
, I2 ?' R+ s E% }) h. x" \. b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: a! s6 C0 Q: D1 q# N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 M+ U+ ?1 c7 b, ~# W* b6 s4 M+ d
| MCASP_TX_CLKFAIL # [0 c9 O0 v) @
| MCASP_TX_SYNCERROR+ K2 b# v+ K$ J4 w2 q/ z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 y+ N4 j/ k& z6 O3 S+ Q0 V
| MCASP_RX_CLKFAIL# {$ [ E. s( t/ [! t' D$ {
| MCASP_RX_SYNCERROR 7 C# ~1 h: v( j' p% a( ^
| MCASP_RX_OVERRUN);
) Y f4 ]4 ]4 ?& Z} static void I2SDataTxRxActivate(void)
$ l- T/ Y& X* P, Z% Q: [{* i W" K d% x
/* Start the clocks */: S$ y6 u! [! @; _/ X0 O' W" w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; i* j/ m2 g+ P3 ]7 J1 h) O# ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: T/ \9 n$ }: v; Z7 y' d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ V" z# c5 }9 Y( ~0 P* d- ^9 C) c
EDMA3_TRIG_MODE_EVENT);$ W/ F9 s! S' O4 M) c. n4 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 ^( z% C3 [7 B: i& M, O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
R. h- N; e9 kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 f- ?# ?3 ]" r0 ^$ O7 w2 v2 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: ]) H$ H" F w" I1 i) G) ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' P. M- n! {8 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 e2 I, e( b2 L* W, i( I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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