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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 p' Q8 h/ w/ g" v
input mcasp_ahclkx,
' ^+ Q6 j u' G' o9 B2 tinput mcasp_aclkx,# @0 i6 P' B7 I. |7 Q. ]
input axr0,
. c( ~* t. x" K$ m
# I) h% M2 O7 J' v8 y1 v. Routput mcasp_afsr,2 s; n& C5 Q# x0 {1 k) L$ \
output mcasp_ahclkr,3 y* l* R' z2 A! }# ^
output mcasp_aclkr,
8 m" o2 X; F W+ l6 \$ D- H# Aoutput axr1,
' g s- a) N; f' G& |9 I" w* L" u assign mcasp_afsr = mcasp_afsx;
3 R5 Z* n$ l: r: N: s1 J5 j2 U' zassign mcasp_aclkr = mcasp_aclkx;
6 F# w6 `! T7 Massign mcasp_ahclkr = mcasp_ahclkx;
7 H# g2 O$ z1 E+ }% U: w+ O3 qassign axr1 = axr0;
# f& M. f% }8 `- ]8 h9 h+ }/ c, ]& j1 l! b1 H; b. N x' w% F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 J: d! W: L5 R$ jstatic void McASPI2SConfigure(void)
$ m$ d: D# e2 a9 j* y/ L{, E. h) `8 T6 S: V+ Y, ^0 `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ e4 W5 T2 i5 j, Q7 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 K$ D0 g# v: D9 i0 I2 R+ d- H. O; h5 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
]" Y+ b0 U" ^) N! EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 a, u. {/ x, V/ \' U, CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ j+ j( N% B2 V, E# ]
MCASP_RX_MODE_DMA);
( O5 A" m5 v8 J' e! ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 n! }2 l" s* n xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 M6 x: U1 h; a' K2 R9 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 ^, `8 C- S4 V) b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); b( B) N. N, B( d) y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; t, {! G8 b% P! h. [5 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ Z6 Z; p" h- S0 x7 s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ v* [! D7 O* l- y# y) @6 IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 p. M3 n' q) v) i1 i0 B/ @ e5 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 U" }( |7 [ C; K+ D9 I
0x00, 0xFF); /* configure the clock for transmitter */
]' o# O3 y& r# G) w1 g f2 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! Q8 c5 D6 Q- J% @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " A. E% J8 G6 t: }" U5 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; i4 g9 }9 k3 o; d0 ]# [; d0x00, 0xFF);
! O3 u5 E% ]! U. ^9 M1 `( N$ C, j; F8 t+ a
/* Enable synchronization of RX and TX sections */ 0 v: M0 u3 i6 b7 |% V. y+ H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
f6 y1 d3 V4 K, X8 w; \0 @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ |' s: b# o7 e, _' \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 c9 {0 l" V: O P6 A
** Set the serializers, Currently only one serializer is set as
6 T. o* {, u1 Z** transmitter and one serializer as receiver.
+ [/ a/ A8 p6 o*/8 p4 g# O7 S% `' c# \# P2 d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ }9 j% T# W0 X1 E) G: H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- X$ K- P4 R l; X a
** Configure the McASP pins / n; u8 ]* ^% ^- \* @; t L
** Input - Frame Sync, Clock and Serializer Rx \! H: N9 u* o' Y& ~7 _
** Output - Serializer Tx is connected to the input of the codec 4 d8 T7 S+ b* E$ F( q* h
*/
; P I, h, v) j0 o" u& b$ h: m! YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ t4 m7 z" u* u2 g/ Z; J( j A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' d! x5 }3 b" [( n# n; IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 H7 }* _, s% H: k# n3 {" A| MCASP_PIN_ACLKX
+ y& x# ~" v# H, J1 d| MCASP_PIN_AHCLKX T% ^! d# Y' i; A8 Y. m3 j! D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. F: Y; ^4 ^0 p" I+ l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& E# u e8 c+ O! p7 R* E, i4 `" i0 N( ?| MCASP_TX_CLKFAIL 6 k( n' F* B0 M" n7 H9 G' ^5 I
| MCASP_TX_SYNCERROR2 p) [+ v+ Q2 u$ M- L+ J" W e, ?: D# m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ k; y' D* t- G5 \
| MCASP_RX_CLKFAIL9 _% L, w9 U6 M. u2 B6 u3 I! Y
| MCASP_RX_SYNCERROR " x6 T' g+ Q; W4 |5 ^3 P
| MCASP_RX_OVERRUN);7 P* {6 j; {. d5 w6 F; v
} static void I2SDataTxRxActivate(void)1 p7 p3 ?+ ?# G5 e& S, Q
{3 ?1 e' q$ f9 z1 h! j$ }* t
/* Start the clocks */6 g: \# g4 Z0 y( I D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 ^* u$ W! }6 }! ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 |9 f& H2 K7 T4 @& P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; q# f6 W$ p" q0 O+ _" X4 j
EDMA3_TRIG_MODE_EVENT);2 A, [# \$ N% c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 [- I) C' j7 }! h9 s, i- K& uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 H* N& ]0 ^' \: w! X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, b( \- [; \. Q! s6 R X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. s# n; l* O. Z" j9 Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 z3 q1 M0 |$ M1 k/ ]) t, ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
]* p: a; d4 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, a" y& ~9 I$ K/ V
}
8 r& W" \% F& g4 }& k" _# B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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