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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 Q3 V) p' k. v4 |( O; J
input mcasp_ahclkx,
1 A5 ^0 }! M% x! U6 Hinput mcasp_aclkx,
1 P7 x% N+ y8 E0 E# @" @" tinput axr0,
; S2 C+ c1 W, ]8 R/ e0 }! U5 B* B% R- N- a' V# W
output mcasp_afsr,- ^) _5 q; e$ e4 Z4 s/ `
output mcasp_ahclkr,
+ Y7 [' F% I7 r* Eoutput mcasp_aclkr,2 _0 X5 B. W, g! V: G3 p* U
output axr1,6 u% V; d6 k+ [0 q" y" S
assign mcasp_afsr = mcasp_afsx;
+ ]' n* [- y' ^, H' n- |assign mcasp_aclkr = mcasp_aclkx;
1 I# d( a9 y& C8 S( Lassign mcasp_ahclkr = mcasp_ahclkx;
- w! V \$ x Z7 A# V- ^" ~ tassign axr1 = axr0;
3 z% ^5 j, t. Y5 M7 i6 w/ K4 e& W; q) i8 U h/ O7 n9 }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 U$ L& q0 K' I7 \$ \ D4 U6 o! Xstatic void McASPI2SConfigure(void)) o4 a* z( R4 W. X5 e% ~2 m9 O
{7 y8 b2 |0 L- F( i0 x; S. \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ D, K, Q7 W/ O% V0 v& TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" f$ ]- ^; v% n; d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 v4 p9 Y R1 b1 o5 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 \, p* B' {7 l& W$ fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 l$ A' r7 ? ~6 j
MCASP_RX_MODE_DMA);! e2 `+ |8 H# q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
S! {; E( e% R' _! IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ r& S& c) ~( P9 F. `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
S+ F$ M1 Z3 h7 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 l' `# H) R z- r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 P0 p: J. R9 b2 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) m% q4 z5 Z0 QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ Y. j- k, B1 F2 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # ?" {/ F& Y3 z8 C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* g e( w/ n! m6 w! W0x00, 0xFF); /* configure the clock for transmitter */
9 ~- o; p3 `" y0 |: D4 SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. K; Z, i7 ^3 ~! ?" L0 eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 G. p( i. {9 \' d5 s: wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 i! H3 E$ j% v: }/ o3 e8 `1 t0x00, 0xFF);
6 n% V' }7 D. y/ o# J x3 ^! }5 V9 F L* P" ?0 U- \3 E+ ~
/* Enable synchronization of RX and TX sections */
; g6 r* o w( ^1 z+ q+ XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* t% B O( k# n9 X; D0 ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( e5 Z4 M& j' P7 _% y8 rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! `) m2 q& W$ F2 Y8 h3 h8 {/ ]0 @. e
** Set the serializers, Currently only one serializer is set as
6 I! M& z: g. k1 ^** transmitter and one serializer as receiver.
) p" [1 } ]/ i. x+ u9 E6 b1 R; T T*/! B- l, u. M# s+ [9 D, H0 _) K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 ?* v" G) L$ L" uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& V* O: ]: r! q" d/ {6 {2 n
** Configure the McASP pins
5 H, {/ `: M, V: m3 [" g. R** Input - Frame Sync, Clock and Serializer Rx
$ U K u j' \** Output - Serializer Tx is connected to the input of the codec
& W+ X4 ]2 ?* m3 {2 a) C+ `/ ]*/9 `4 |3 M# d5 G$ E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 C! A2 d6 J1 z) R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! V6 u: W9 U' V6 n: w) r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 b8 q" ]- D$ x| MCASP_PIN_ACLKX- i( f; [4 f/ p" ]9 ]
| MCASP_PIN_AHCLKX5 s1 M# p8 x8 _& C' p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; Q7 m* n( r" m u* KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# K0 [7 w ^+ f6 C2 B8 z! d: P! j| MCASP_TX_CLKFAIL
1 S& h/ i0 `; i( g; ]! \- n| MCASP_TX_SYNCERROR7 ~3 B# z% L& V+ W* B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) _5 I6 K) O, w# e6 N! Q
| MCASP_RX_CLKFAIL
4 x$ F# F$ P6 r/ S9 }| MCASP_RX_SYNCERROR
1 ~, z0 J2 K0 k) u2 ^- y+ y1 h' G| MCASP_RX_OVERRUN);2 C& e% t) D& z1 q" \
} static void I2SDataTxRxActivate(void)7 X1 n, c& e! @4 `0 r4 v( V
{
. w) N6 o, M- k. j3 H- g2 X/* Start the clocks */
9 U. I3 l& b# IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. V9 |: C) U8 k% GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 Q. W0 T; z. H. A/ q* vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 t) ^( a2 H8 l4 lEDMA3_TRIG_MODE_EVENT);
0 k) r/ p6 ~6 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 j F/ b$ x) ?7 `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* N% k8 G/ `: z9 n; z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, E" V/ E/ Z; g5 R/ p1 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( _8 E9 `% D0 Y4 ?! ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 }) Q1 `. A" { S; j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& a7 d1 p& h0 M, W/ mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); ~- a( T7 ]' M8 c# _
}
' ?* c! u' t, L! O# l3 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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