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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 ?! m6 m7 k6 j( K% Z" l0 [input mcasp_ahclkx,8 b5 k4 O! w" R$ @1 }8 `$ i3 c
input mcasp_aclkx,* Z+ o$ W1 k' E1 W5 r% i( i
input axr0,& ?% m3 M0 A- \8 t) C
/ }% s# l/ Q$ ?) M
output mcasp_afsr,
1 l6 O4 n( \6 b- R. }output mcasp_ahclkr,4 R% x$ W# H5 D4 R1 L
output mcasp_aclkr,0 k+ @* v. \; U$ x9 u5 R( V
output axr1,! h& I: m# Y8 H7 `! }0 c
assign mcasp_afsr = mcasp_afsx;+ {) V9 ?! i/ m+ W W# F% [
assign mcasp_aclkr = mcasp_aclkx;; L) t, C! [ s! _# J( ? `# v
assign mcasp_ahclkr = mcasp_ahclkx;) l0 n& ~' q2 a7 {% u5 G2 j, p
assign axr1 = axr0; 9 H2 r" w3 S8 |4 X, Z( d# q
! E9 e$ u& E0 u. X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( p h# N0 p% ^static void McASPI2SConfigure(void)2 O. _5 ^$ g, U2 n i' H9 b5 E0 H
{/ O+ j- L! J5 X. q3 `1 b5 M7 O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# l& ~: F4 q/ I8 w" t! oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 D8 R. l2 i3 Q; M5 z$ e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
L2 x) t" e1 M) I! K" i& cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! P' B9 X4 t7 J! s! i+ b: PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ C! z! y0 M( ^- O; iMCASP_RX_MODE_DMA);
+ z) {) F/ I: NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( R9 C1 N# h! x0 K% i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" r/ Z8 f; r4 L1 P2 E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ Y$ D3 n. F0 b: pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 z3 [7 u$ j* h& q7 p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 V' Z+ w$ E. [! BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* G w. D" u* N4 S5 x. R8 N/ l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); H9 i+ j4 t5 z7 Z. C2 Q$ a& c; y' Z6 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' d3 \& v/ B8 z5 k+ g9 H) b! I: o0 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 f" y7 O+ q9 h v; i
0x00, 0xFF); /* configure the clock for transmitter */, F5 D8 T- d O5 i/ |3 G$ v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 ^1 u8 b! }" V7 O* V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # x; ~) ?" M0 q/ C v; D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' P' M% ]! D; Z; y% p/ B- G1 R; m0x00, 0xFF);7 C" D7 { ]" ]; p
C6 x/ M9 u0 f9 z& t6 a7 Q3 Y
/* Enable synchronization of RX and TX sections */
; [% Q7 ^3 ]+ a( \" E1 n S1 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
{6 b& ~ z7 s, V8 k1 I( IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 s% y4 X1 {9 N: ?3 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 N7 M6 x+ V) `9 ]" \9 V; h3 q0 R/ H
** Set the serializers, Currently only one serializer is set as c9 c1 `! Q- ]. O
** transmitter and one serializer as receiver.7 S" t. A0 `/ M# d1 b- u: b) {
*/, }% l E; P, b/ G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' F7 H1 Y" \& R& |3 n# d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 k$ X" a$ z7 v( Y** Configure the McASP pins 2 }: `/ o, e/ r4 N
** Input - Frame Sync, Clock and Serializer Rx
5 O) \4 @# V+ |" T7 Z: z. _+ P: u** Output - Serializer Tx is connected to the input of the codec
/ `1 H( b+ ?/ `" R- m( ?*/5 A( y. r2 ?# C4 R" `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. V8 j- ?9 O+ ?- w' tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 j# A& p0 y( ^8 A- F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 S; m8 z& b) I* z
| MCASP_PIN_ACLKX
! f( a1 y9 v" M) a# H8 ?! m& n, R| MCASP_PIN_AHCLKX
: s) ~; X" z1 b' A% U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; V; v A: ?9 j* }% L0 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % L' |) x& `* i, w
| MCASP_TX_CLKFAIL ! Y" ` H0 E4 k2 w8 v- ]
| MCASP_TX_SYNCERROR. z3 k( g* i+ N4 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% X, m( {- _. |4 D" C' J5 L5 x| MCASP_RX_CLKFAIL/ n3 [' k, f0 g, T o
| MCASP_RX_SYNCERROR / u# O { s1 P0 N( R
| MCASP_RX_OVERRUN);
7 B: W) O3 o: u} static void I2SDataTxRxActivate(void)$ _3 w, S- L) `0 l2 k5 \' y1 C* S6 I" @+ T
{" k8 E3 H0 A& B+ W
/* Start the clocks */$ ~6 H; c4 N7 I5 @# ^3 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 z: Z5 M5 _- D/ ^0 D0 S3 gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' J" \8 m B3 J/ LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 p1 U- ?" F0 L
EDMA3_TRIG_MODE_EVENT);0 g I4 ?- M" d2 E; j, @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( W% s1 V, p. ?) m! o( w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 n# ]5 H, S/ L, C( c) @; I2 ^8 T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. i& Z' {8 E: H" K+ S9 ?* B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% m% |/ \% J0 ?: t6 Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ C3 \& j6 ?: I. o3 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# S/ S7 I4 R( G( a2 P; GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( `/ j, i* K) f5 I" p, ^) r} , Q0 _5 @" M6 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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