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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 F# k( N5 S$ e' s9 \% J* s9 q7 dinput mcasp_ahclkx,
7 s& T- W9 [# O8 ^+ pinput mcasp_aclkx,
/ X% t: c B* Q* |* I5 Sinput axr0,
! @! i8 S% K# f
2 l3 m0 T" b* d4 o4 Zoutput mcasp_afsr,
0 r0 y3 U& m$ y* q+ Moutput mcasp_ahclkr,
' s, L/ d: t9 c) D7 ^$ r/ h" {output mcasp_aclkr,3 P# j+ {+ ?- \* U
output axr1,' N c' E s2 a+ I5 V ~& {
assign mcasp_afsr = mcasp_afsx;# z4 y& J* ~/ x4 h* o8 d( Q- Z
assign mcasp_aclkr = mcasp_aclkx;0 D, W" X. f) S! l" f7 S
assign mcasp_ahclkr = mcasp_ahclkx;; c5 x1 G1 w1 L2 Q- K
assign axr1 = axr0;
4 O- g! J( I. v. H1 G5 e1 x0 ~
) f9 w0 M& w5 G |" N6 A, ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' Q* I0 y3 } E4 g- P4 P" L( b8 Rstatic void McASPI2SConfigure(void)6 @1 r- B. l+ W
{' {* K3 E/ W8 v% N' o4 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) S4 Z6 w- s- x G0 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' G: L3 B9 x3 j7 I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 e1 s' R5 F: b" [. k# fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// [+ V) O: V k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. |5 s: P8 E$ N1 RMCASP_RX_MODE_DMA);' v- f O3 d3 o0 y1 S1 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 G1 n1 T( _, d# J# _" K& YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- t0 R( H# x H5 NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- A# r7 }& n) [: K; n! LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& K% w# g7 W( j6 K' b+ U. S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / l s( m. i* t1 N9 t+ b' F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 a+ }2 {6 _( {* R: E) C8 C% RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; V# S2 G/ }$ e1 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, n8 S- P+ q: M, K' d ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: {6 V. ]: V o1 `8 W* I0x00, 0xFF); /* configure the clock for transmitter */
; M- i5 _' l5 IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ \# I) M7 i' [6 R, ]8 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% k* t" }' k5 f" n# \3 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 Q. `; v1 R$ ]0x00, 0xFF);/ I- o: S9 B; B2 }
) @" ]0 c8 D& N2 _
/* Enable synchronization of RX and TX sections */
, M8 _8 L4 s$ D' N5 kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- P4 W! w9 @ a6 S* \( jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 q) u3 M) b2 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 { l l; r8 a p( l/ {+ Q** Set the serializers, Currently only one serializer is set as+ y, W4 }! w7 O" ^( B& @* s
** transmitter and one serializer as receiver.
+ }$ H2 q \2 Z. ]2 ^*/
: J. n k- X7 F# |/ m& R# n& WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! N: E( L% C3 P/ J* S; c5 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 ^0 q+ w# m8 e4 n; k** Configure the McASP pins . z: V. q, A4 l0 }) P
** Input - Frame Sync, Clock and Serializer Rx- B8 M7 K- J$ e" R ~3 J) f) ]
** Output - Serializer Tx is connected to the input of the codec
, T9 j" W" s W) t/ Z# y- R# ]* T*/
3 X. X" ]. c$ ], H5 @% W- \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
z4 t* Y# `7 T1 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 f: D* ^- Q0 S% B9 l/ w" eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% g* t0 N0 m9 G; ` x| MCASP_PIN_ACLKX
9 @! b" L5 F' E) ~& F6 m- }| MCASP_PIN_AHCLKX$ s: E, t4 Z* F# X% D1 A b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( Y, K' r( u6 k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' E* y0 q3 c( h/ O& V| MCASP_TX_CLKFAIL - @* [4 Q- E- E! j/ d
| MCASP_TX_SYNCERROR
" K+ W- s0 a- e! {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 s4 H$ Q4 c. @: E. v* {* G
| MCASP_RX_CLKFAIL# \& A2 E j: r7 h! R2 z3 A
| MCASP_RX_SYNCERROR ! ^* F3 u% H1 Y* r* p
| MCASP_RX_OVERRUN);5 c; Z! C) k# A2 r0 B8 z1 o; [
} static void I2SDataTxRxActivate(void)6 {+ Q4 ~' I- N, @4 T6 v
{
2 [; {8 T" h6 y# B0 H7 L, Y; q/* Start the clocks */
9 V' T2 f+ X, P O! `5 m- ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 M# g/ r8 S |& H% `6 y. |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; X4 Q+ I* ^) K. e3 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; ` d% M3 n" q
EDMA3_TRIG_MODE_EVENT);
3 f: C5 O5 c _. R" A/ l3 b& N/ SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 s) w9 W+ z: B, F1 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ Z5 c/ q7 {- p# I1 n! L2 m! w$ ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 D2 u) x. Y+ M2 o+ v H; X+ N! EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 w( M0 E0 }8 m4 q) V+ i7 _7 s9 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 c: \; x6 a, w, t( KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! S! E- f/ Y; O- T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" N+ K5 F; P; r: j% k9 w7 U" @} 1 o% C$ w6 |8 B7 {4 E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / k8 r; V. Z. }( D/ \
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