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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& e/ P1 D# ^4 pinput mcasp_ahclkx,
7 i" w7 L6 c" L( q$ D; B/ c& Rinput mcasp_aclkx,
* @) i: E4 O" i s& Vinput axr0,( B& A: R! @, J1 i) q( Q
6 G$ a. U4 U& P/ b. h4 _; c$ h( Toutput mcasp_afsr,( ~ S0 f$ @; G9 `+ U/ E9 I
output mcasp_ahclkr," M2 R6 x0 c, _" ^) I0 g
output mcasp_aclkr,
1 v4 C. P+ Z/ l! voutput axr1,
* g3 u j3 Q; Q: ~" n assign mcasp_afsr = mcasp_afsx;- {! Y0 D1 f# Y% i$ E+ d7 t5 M
assign mcasp_aclkr = mcasp_aclkx;& ~1 e# z- |! w/ x" n
assign mcasp_ahclkr = mcasp_ahclkx;
# Z: n& i$ Q3 {( A( i; j1 E6 Massign axr1 = axr0;
: ^0 V1 }, Y' Y8 A3 w \1 W% X+ \8 h! e& b$ z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 X! r6 @, ^% Y5 \6 P
static void McASPI2SConfigure(void)
' k6 S& W7 b8 b3 ^2 }" b2 i: ^1 r5 g{
3 r" R3 L, f/ n0 P" v6 b3 q0 [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- k0 I7 M0 l4 i! x/ t2 h B/ IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! U8 F- w; `( f) A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); k$ T! [2 v9 b' r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& x& x" ?( r$ X2 b+ GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 v6 s! K8 b& O+ s9 i
MCASP_RX_MODE_DMA);2 R# W; y! ~1 X m+ N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! U8 m7 R" a R5 i# B; h4 B/ k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ x# Y* f; V, g! j+ G7 ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) e' T/ ~7 e5 D' g9 y! d6 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 i5 R# ]4 }4 t$ Z& r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ [0 c: ~% r6 l9 S* t4 v. {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ y3 Y7 }5 X: z7 {% s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ r) H+ j% R2 U4 gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( y6 C$ q4 R! `( Q& M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; X( q( V0 h! L* Y5 I0x00, 0xFF); /* configure the clock for transmitter */
; P( w9 f. U/ _* _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& x9 k8 E( d! ?) ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / ?# b* ~" G8 s9 l- A8 X: B4 R0 q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, c3 a% T: ~1 [1 U# t) w6 \4 ?) Y+ j
0x00, 0xFF);+ C( D4 k. q, G. b. s: ~/ O- G; d
9 Z$ H& X' V3 Z2 ^
/* Enable synchronization of RX and TX sections */
( ? A6 c- z9 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- ]* u% f% g) Y3 ]$ MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); g6 v; \* ~/ E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 p' ~: P# Y g5 e2 x
** Set the serializers, Currently only one serializer is set as
: o7 d1 J/ R) q0 Y/ u: W** transmitter and one serializer as receiver.: S3 d) \+ Z0 p# Z9 w( t. P
*/
3 Q2 U ^9 u) PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: L) P: l, ~, o& l& f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 l& p( ]2 I- c" `: g0 h4 ?& d. U! k
** Configure the McASP pins
& _" P/ i( R2 j* q% B& S) F* e** Input - Frame Sync, Clock and Serializer Rx! j! S; m2 R: m9 ?5 V) [
** Output - Serializer Tx is connected to the input of the codec ; H+ y5 w* W# j* U, y+ W
*/
; \5 `3 I5 s9 dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; e: q' ]( b9 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! ~' w$ h8 S' m' }* x/ k8 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ z4 Q' c! i3 t- L r
| MCASP_PIN_ACLKX$ w9 }& O$ a/ T1 ]6 t8 t/ v
| MCASP_PIN_AHCLKX
5 h0 Z' y+ o% R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 U# _8 z" |+ G, W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & A5 e' R6 k# G: J$ k( w- @
| MCASP_TX_CLKFAIL ) a" U% E2 `: Z
| MCASP_TX_SYNCERROR6 a& l2 N# v8 {2 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + m" h7 F( G1 O' X
| MCASP_RX_CLKFAIL' h0 [% _* j& B4 U& m
| MCASP_RX_SYNCERROR ) j3 H6 Q; D, W/ v1 y2 T4 C
| MCASP_RX_OVERRUN);% O* q" K. A# Z- s- K3 l: Z1 t
} static void I2SDataTxRxActivate(void)
: {6 V3 T3 t% T) Y4 {* f* ^{
" ~% t* L+ i+ F5 k( T1 a/* Start the clocks */$ p$ ^9 ^4 ^" H0 {; d |! Q g0 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 ~, w: O8 C) G' [0 L4 Z4 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ |3 R1 G7 L' a6 q: pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: G2 g9 ?' j0 K, ^ [
EDMA3_TRIG_MODE_EVENT);
" r1 U6 d* W% A$ R9 _+ dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ~4 O7 z9 h$ I( |& y1 K0 A2 S0 \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) H/ |4 T) A& g! s2 |, u& DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 A* `( z1 L$ X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% L% |& M6 L) Z3 b' O& n; o) Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 j! k8 h% S, K1 v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! b0 Z9 U" x. t8 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* S; n3 E5 a. W& d6 r/ r& l+ }}
/ j" X2 j. R+ P6 b- w" T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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