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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 ^$ R; a6 Q. z q8 w2 A( Y4 R3 ] Winput mcasp_ahclkx,6 e2 l# H/ D3 Q& u4 W( R6 z/ h: L
input mcasp_aclkx,
9 |% a. t! l- P' n& binput axr0, Q( P+ U5 x- c1 `
& b" ? j3 Q- z. m
output mcasp_afsr,
0 Y! V' u( F$ t5 J/ Woutput mcasp_ahclkr,
3 [7 x- y& z( {' p# t2 Noutput mcasp_aclkr,. k& B" X1 }1 ]- w
output axr1,
* Z- j, E& t( ~$ {" o% M" n. |5 ~3 e assign mcasp_afsr = mcasp_afsx;
: W: G0 e& b2 I3 vassign mcasp_aclkr = mcasp_aclkx;1 T( E: A$ V9 [- G! B; W! }
assign mcasp_ahclkr = mcasp_ahclkx;
5 b. W+ I0 k# Nassign axr1 = axr0;
2 V* i. U3 i' v8 r- A. N5 i# v( S s8 E( J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 V) z; u! y' g; z F* wstatic void McASPI2SConfigure(void)7 t- E2 K$ j8 ]7 a: r5 Z/ c
{/ l0 D# D: m8 ^& ~6 |% \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 `: E3 J1 B* g( |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& v% h# j% ?. C$ ?! H* J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) I2 d- y& F! T$ }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( G9 ~# I* F2 B4 c: n1 r1 mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 r, i/ q" d; q" _5 @# x
MCASP_RX_MODE_DMA); ]" e% b/ H; t. Q& ~) w/ C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; J, n( _- |/ y. `% {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
n+ _( O' l8 m& S6 V& r8 ]% }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ p! m5 o" {1 L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! S9 D7 h5 l* p' K& q4 YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 h' M- ~( E# W# IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" ?; v6 q ?' ]' j$ F# ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, l1 N7 P& q/ o7 Z( a/ l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 u# C+ V1 F: @7 v- P8 ]3 V' KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) i1 z+ u3 P( `1 D- N9 }/ Y0x00, 0xFF); /* configure the clock for transmitter */! \6 [) V2 y0 z+ r: L( F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 b$ \% o1 r; r( ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 z& @! s. j) B [8 r4 P" J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ s' `# _/ Y& h& h9 J3 e0x00, 0xFF);9 l2 F" f S5 ]. ?' I/ W0 x$ k6 U0 w1 D
3 s, @+ P p; F0 W i+ N/* Enable synchronization of RX and TX sections */
# A8 b, p, a$ a' [" H% Y5 y1 d! gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ }7 G, v9 q- {1 c6 L' Q* P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 i( d& P# e' m7 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; m# A) ?2 \! V# j2 ~** Set the serializers, Currently only one serializer is set as
. W1 r" |" {2 x9 F l** transmitter and one serializer as receiver.; Q/ I5 a. J- _7 k
*/
* H* G+ E' u4 X0 c iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 k5 k7 Y% ^3 t% f- MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 e9 Q* b1 c$ {5 l
** Configure the McASP pins . ^$ Y5 ~7 o' E2 c' m
** Input - Frame Sync, Clock and Serializer Rx
0 C# Y& \" e; f5 |' Q" ^** Output - Serializer Tx is connected to the input of the codec
/ u u* L) l3 [- N) Z0 f5 K*/5 k1 A; m+ Z* v/ t; _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 F& Y9 Y1 l, l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 v! Y: f9 f% p, J9 |" ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% V5 q" t3 ^& u3 ^0 A1 m
| MCASP_PIN_ACLKX
5 d# b0 z V; b| MCASP_PIN_AHCLKX7 M7 m Q$ x) S& q; E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 q4 S" }4 H+ m, z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: F. L4 A3 }" U/ B: d2 v) q6 j* V| MCASP_TX_CLKFAIL
7 B: f$ v3 s) [| MCASP_TX_SYNCERROR' q% } v: g/ p! m" _# b/ ?9 j4 r% C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 P3 }* C! M5 c, E7 s. f1 R7 p
| MCASP_RX_CLKFAIL
9 _: f$ D5 r0 F* ]| MCASP_RX_SYNCERROR
0 t4 r* R! {+ x) }* q; ` l6 Q K) R| MCASP_RX_OVERRUN);
6 F8 k0 t. K4 r. k) H} static void I2SDataTxRxActivate(void)
$ k( J" {: ^5 b1 J1 t{7 H- e2 u; F5 y# b
/* Start the clocks */
9 t$ \# Q( ?! V4 c8 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 x) w, n1 K% P% h" t8 i/ S9 _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* ^; Q. \; `* z" y8 o* T% uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' i, _8 H* h; h# u$ U8 m
EDMA3_TRIG_MODE_EVENT);) f6 o2 u1 I' K, F- {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 u! j1 {. E, ?( b6 w2 u" U. m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- c8 Q; y& A7 H. r5 A4 q& z' NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 p# r7 G3 ]0 ~; ]8 `1 aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ _& V+ i5 Y0 s/ @* H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% k9 y! S$ @" M! ^& K' L! nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. N6 [9 V3 g/ L: P' TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 y4 N; n: m. L} ( \* I+ {$ m( U- j5 M4 j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ m- O) q, G$ L4 ?' {% j L1 E9 D& a
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