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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, e5 Y3 e3 Q+ U( ainput mcasp_ahclkx,
$ A5 B* I1 q1 b- L7 ]$ C" t" w& s3 ninput mcasp_aclkx,6 N9 ]; a; T) p; R
input axr0,
* H* i( z. x5 b1 I3 E; d2 G" o6 Q0 n& n
output mcasp_afsr,
/ n. x. g% j. }( l9 X' Ioutput mcasp_ahclkr,6 C1 k$ n; r) m. Z
output mcasp_aclkr,
$ j' R0 l: p1 ?2 A! zoutput axr1,
9 \& W; a8 B6 T8 Y assign mcasp_afsr = mcasp_afsx;9 q2 w4 B5 e o0 s- u* E
assign mcasp_aclkr = mcasp_aclkx;
. q+ v% `$ J. iassign mcasp_ahclkr = mcasp_ahclkx;
3 \1 f3 O2 d2 a& T% bassign axr1 = axr0; 0 q$ i' k! j4 k" d9 ?% G
" {# O F5 E# w" W4 z' V. R7 U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . ~7 b, l; J$ w' C9 y. f9 r
static void McASPI2SConfigure(void)+ Z, {" f$ Z$ K0 V! S( F+ U
{
! p" B( h4 L* zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 x. g7 f4 m4 Q, K. z6 d/ G7 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 o. W2 q, x( n, ]) _% XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* o6 n" z2 ^- S8 t' G5 I8 l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 P0 M* |0 J2 X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ A( b' }4 W1 M
MCASP_RX_MODE_DMA);
' u3 O$ z- n$ g# eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) ~* Y. ~% F+ d( R# u7 P+ q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* m9 z: D- T4 E; g, S+ d W" OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . J6 u7 K1 |9 d& y( F( o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ j# h0 F4 U$ Q- R: Y q6 |! `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 C1 w( N2 E$ w5 b3 k! pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# ~3 e3 L1 X; Q* b0 a- b; X( V$ mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ X7 }6 W! U5 K U* O$ z- a& _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ B7 c. v& U8 O+ `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, f! M3 u+ o- z, I0x00, 0xFF); /* configure the clock for transmitter */
~) C% P$ L% K, J7 C5 u# XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ F- N! N/ L5 n( @: |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& ?3 ~$ \$ X4 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# N; ~3 z6 A) i# w; O, n3 h0x00, 0xFF);/ ^8 w: _ E% @ g/ r L$ k& V
1 T% o3 d7 L) f1 c" Y/ w/ x
/* Enable synchronization of RX and TX sections */
& d/ C7 I9 w# ~ P v* T; _/ Q- @6 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 ^/ r$ I2 i _) I2 PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 `- O/ t8 x* T; \" P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# y! i) E/ D% |& U* R** Set the serializers, Currently only one serializer is set as
! ]! v8 y; W: T$ ?** transmitter and one serializer as receiver." M9 k; F( E9 w3 W3 \4 m
*// ]& Y: ?& {: O ~( ?- G+ O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 i$ `: n8 Y% O! n+ j+ ]$ K- u8 f5 ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& ^7 L8 h5 y: I z2 `( v
** Configure the McASP pins ! b0 B K9 O: v" f/ A8 z0 C
** Input - Frame Sync, Clock and Serializer Rx! `1 g0 o7 n. _$ v
** Output - Serializer Tx is connected to the input of the codec
4 f/ C6 V: O) s& D*/5 c6 h/ @7 @2 o1 R* A' K \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 i9 Z* W% t* z8 d1 b9 b* I7 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: }/ u, o3 I* P, KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' y! m' g7 v/ F! t) A/ o$ v
| MCASP_PIN_ACLKX
" D' A" M! Y3 \* \, R| MCASP_PIN_AHCLKX
! [" n5 s9 n0 ?/ O7 J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; I7 h8 E" G4 s! d! Z! J: X2 A) N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : V w: \5 b: N4 e* D! t
| MCASP_TX_CLKFAIL
5 L9 n* c0 S' o/ M| MCASP_TX_SYNCERROR
" C- Y) \9 Q! t6 f# }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) b- A Y4 g; Z| MCASP_RX_CLKFAIL
, g7 O R$ A9 `5 T! v| MCASP_RX_SYNCERROR ( T' Q( n; f: e7 M" {
| MCASP_RX_OVERRUN);
, a: s, z0 ^1 Q# `} static void I2SDataTxRxActivate(void)' H _; z1 J8 \, S# u: g
{8 R2 Q( ^' t5 o* @+ ?# {
/* Start the clocks */& [4 ^* i/ U$ q5 }' |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 l7 p' V) G# S3 j. {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 _" i% t1 Y2 m$ z5 z; F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; e: p, ~4 C& S/ h- lEDMA3_TRIG_MODE_EVENT);
, i6 z1 L2 K3 a% [3 o" mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 e% L) ~! a. I, ?2 H8 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# N- K! }4 H* VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; Y! S7 a3 G" l) u7 w: d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: q1 _7 K- |6 R; p# owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) L8 e2 O; Y5 x" z S1 sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 w+ {2 d+ V4 Q# l: @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
D% q" ?, X" S" W* D} k; h& V! X! @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 C2 O7 w8 G/ S; \7 Y; t8 i! J, ~
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