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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 n9 `0 B" ]9 jinput mcasp_ahclkx,1 r" n, r! m0 C( @6 P, z# N2 h6 N$ ?
input mcasp_aclkx,
2 B4 O% C% b9 V3 V) E% M/ z" @input axr0,
9 K* Y2 p8 c) h k6 a
7 [/ [/ F: Y" Coutput mcasp_afsr,
. F, G0 E% r& woutput mcasp_ahclkr,
) H w# \' b$ Loutput mcasp_aclkr,
/ f+ l2 H7 o4 |& W5 r& toutput axr1,
7 E& X G/ D: }9 N assign mcasp_afsr = mcasp_afsx;
3 S& h3 @9 ^& W9 V. T& n3 j eassign mcasp_aclkr = mcasp_aclkx;
. K& g r3 F# G9 bassign mcasp_ahclkr = mcasp_ahclkx;
7 ?$ i( r" E* v0 r6 [assign axr1 = axr0;
( v# [$ l' J5 O2 [
/ T5 ^2 f8 l# b K5 V" }: H8 e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" [0 t; j/ L- p9 T7 g8 h; ystatic void McASPI2SConfigure(void)+ H" O+ l! M) W
{# m7 w6 b9 {6 z) f0 G: f6 j1 D @8 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS); f3 L; e, Y, U+ \+ I& q1 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 ^: W( ~0 ?. L1 Z9 v% CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 C: V2 E- l5 g) V" g! @8 ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# t3 k+ B ]2 r2 k" l! ?7 H# ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' p! `! A1 Z, Q; m; xMCASP_RX_MODE_DMA);
* D. M4 |( J( A3 D* T% ]% `# MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 K4 D1 i5 d E3 F* M: v5 y. A, [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( V0 \: ]2 } r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " Q0 N- @0 Z# A0 J* T" W: ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, {+ i' p0 `' t0 a9 G0 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# U% R4 q" e9 K- hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* `% N u7 w( V7 h- g/ c7 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# }# `4 o6 d w; HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * v% c/ V, |; \1 x& Z* a% }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ T* y& O6 U M$ |6 y
0x00, 0xFF); /* configure the clock for transmitter */# l, Y7 ?# ?0 K+ Q. y. M* H/ k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" I" L5 K' o: V; T4 qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 U& k) f* c9 z2 F* s- H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. d2 A u) l7 n: T7 j& V
0x00, 0xFF);; b- ^. J6 |- O. A% a
: _( M5 a6 U. s) P/* Enable synchronization of RX and TX sections */ ) y# y/ P. N% S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# N# M! ?% n# ^1 F( U% _0 IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* k7 g+ \) |5 J& a7 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% `8 q9 t" O4 f** Set the serializers, Currently only one serializer is set as+ R" P5 ~+ Z C8 A$ `+ p+ C
** transmitter and one serializer as receiver.
5 m1 z" \& e) {: Q" h! w*/
- |7 {2 ?9 B n3 oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 H+ l+ }+ p4 a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 u9 f1 `* j V/ h0 A4 z& m6 w* b** Configure the McASP pins & [, ~: `9 R L* e' ]7 L
** Input - Frame Sync, Clock and Serializer Rx
: J' A2 _, L8 P** Output - Serializer Tx is connected to the input of the codec 4 c0 g4 i U' g# p5 }2 ^! g
*/
7 d7 ?; y0 h/ P# {8 L& aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* _1 G. K' D' C5 I0 |0 f( J( j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ f+ _8 R3 \( }# {! |0 FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ h0 N! W+ [; k+ B9 F6 q# m
| MCASP_PIN_ACLKX
& O4 V" c: ^. i! Y: u| MCASP_PIN_AHCLKX4 k* B! Q2 }( k$ ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: G) h9 _! R) C9 X, `$ V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; f( w; Y: n6 U( A9 s
| MCASP_TX_CLKFAIL ' r" a: ]% \/ Q3 ^) E+ f
| MCASP_TX_SYNCERROR9 U3 {# h# Z6 `9 _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: e% Q. H* t. ^( || MCASP_RX_CLKFAIL" `0 J- n8 S! r6 A. t: T4 s
| MCASP_RX_SYNCERROR 3 D) U f9 G" u9 c/ k
| MCASP_RX_OVERRUN);* a+ l( V) Z( l4 X8 S3 x
} static void I2SDataTxRxActivate(void)
5 o; Y6 D1 V* e2 c* o l{
0 e) S' @; Y) J" u1 q x/* Start the clocks */
& k5 N! m0 T4 T3 ^6 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 a+ a# J! W$ L/ [! HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 C7 P- L; Y+ {2 e0 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 y' @) H6 T2 i U1 A0 f# ~$ e
EDMA3_TRIG_MODE_EVENT);
% ?* W5 i$ T3 P0 x9 S# w' QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 ^: Q8 M$ U0 K8 V( tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ V/ Z8 {2 t8 @) ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% w. t; |! T2 J2 {! d9 }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; b& R7 O$ B7 ^2 T1 [4 cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 ]9 S. \6 @$ k4 c: c1 y- v L% X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 q! ^/ a& X# k K/ i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( A+ l# l/ u% K; d
}
3 m& Z+ j8 e' W* L: f. a( E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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