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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, H9 Z4 Q A' Y* X8 p4 {
input mcasp_ahclkx,2 I- o# n$ J, v
input mcasp_aclkx,; T$ ]" R6 n A5 L
input axr0,# Z& J) j$ s5 X1 p& u0 i) ~) U
' k; U, d6 |. N0 w2 i7 b2 }% [output mcasp_afsr,
; k, x2 S& w# a# \. E$ ]output mcasp_ahclkr, ]8 c Q0 ]) f" X- _
output mcasp_aclkr,
5 I* P. c3 [: T, o L' o) Goutput axr1,4 O5 W4 j3 k. ~- P N; i# e$ |
assign mcasp_afsr = mcasp_afsx;
! k# M0 }- _9 o' N- [# Qassign mcasp_aclkr = mcasp_aclkx;: x8 H3 ^7 `& U( [) c5 y. U! F. G
assign mcasp_ahclkr = mcasp_ahclkx;& v$ W& p: C: s
assign axr1 = axr0; 0 y1 h- p( w1 B% X: G
$ T0 V% w7 G9 g2 ]7 e+ U. b6 _6 u: G- f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : h0 ?5 k1 B0 k: G
static void McASPI2SConfigure(void)
6 H, b8 R2 K3 q5 R+ k$ ~4 Y{# u8 E- R+ j1 y. P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ P' h1 X# B# C# m) E" M, L$ N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 u( _5 [& n2 w& Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ ]& O) O) o* SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. w5 J* s; U- i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 y+ j5 X J7 m& Z: E
MCASP_RX_MODE_DMA);. S- O! B7 M' c8 T3 O- S9 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* k" Q- R, l6 aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// [% }4 L! K( [/ }. g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 c* j5 y7 r- v# T: N5 LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" u" ~) e/ X6 M/ ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % J3 o1 [8 @& I8 D1 l( ]& j7 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) o: j, E0 s% L. Q9 O, v! K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: _( S5 b2 c& ]; N0 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 Z$ Z, x4 h R3 C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, k% h3 ^4 `3 x/ ?' Y7 b4 w
0x00, 0xFF); /* configure the clock for transmitter */
1 b- g0 s* y/ i; jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ `- e9 R8 K- ?* ?4 Q1 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' c+ v: z4 z3 r0 e( q4 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: l/ k7 E4 ?4 N$ A* k4 |0x00, 0xFF);, m/ A: l$ p+ A9 a$ ~* s% U
* Q! U1 n+ z0 \# p/* Enable synchronization of RX and TX sections */ 0 u: A" h# |1 Y/ n6 @3 b8 ?' x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 q% J6 q2 f0 vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ F" d- U2 S! U" x" S% R) z6 ]5 w/ vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ E+ F$ B3 N: f. _% L7 V
** Set the serializers, Currently only one serializer is set as
6 U' L$ {' ~$ Y A' O7 u** transmitter and one serializer as receiver.
6 D" {8 P4 e) ?; V6 B% c/ c9 v*/6 U& o. t. [3 X4 l/ E8 _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ D% z2 v, X. A* `% |* nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 `# S4 }7 t* Q$ N! Z
** Configure the McASP pins 8 Y) F0 M8 f+ H$ ?4 K/ y4 H
** Input - Frame Sync, Clock and Serializer Rx
" u: p: _/ y3 `8 J" {0 B** Output - Serializer Tx is connected to the input of the codec 1 b; v# b2 B( D3 u& Z/ Q4 \
*/% [ y3 c) _3 R) n+ W$ s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. L8 M8 q/ \( O L/ wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! w M4 w2 H$ V( B h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* b2 q& B4 r3 F- F| MCASP_PIN_ACLKX
+ `# C% a! A4 Q- j2 q| MCASP_PIN_AHCLKX
7 N1 U9 t) v1 `- T" {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 c1 p2 J2 V" u LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! h G7 V8 g3 V- o& ~, ~| MCASP_TX_CLKFAIL ( q+ B7 o J, R: d& q) F- M" r
| MCASP_TX_SYNCERROR6 w4 I" \% h# ?* F) Y# `2 b; ~+ ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ f1 s1 [, W( m5 o5 i5 l. @
| MCASP_RX_CLKFAIL
# f( G: n, n& S5 s1 @| MCASP_RX_SYNCERROR % z3 n" z8 [3 M5 `" b
| MCASP_RX_OVERRUN);+ ~7 c3 O" x9 }; }
} static void I2SDataTxRxActivate(void) i- }+ x& s, K8 M$ g) }1 D% o
{& p" g1 D8 Y; F/ p& v
/* Start the clocks */; I! b& g& ]+ l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# ?# x* G- y+ \; n0 y" ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# p9 G J1 b& mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 e& N4 Y8 Q; dEDMA3_TRIG_MODE_EVENT);6 o" i/ A* Z/ `3 c! N0 h- T; q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* p# s* ?/ U8 XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' V E) E k1 f3 X4 i+ RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 @. Z$ K2 {, c$ }3 n) g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: `# Y& ]/ ^$ c5 R- Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
X# n1 m: I7 a+ U3 K# EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, p* M2 Y2 ~9 A2 u0 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' W! r" i" f9 r6 q! V" u) M. F5 G
}
& W3 W; V$ s8 E; a- W5 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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