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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 e9 A! L# X% x& `
input mcasp_ahclkx,
' d. `5 Z: K0 D3 oinput mcasp_aclkx,
( m+ R: P" J: T9 Ninput axr0,/ Y( u# Q; L1 U1 j* ~( T5 u
+ @; d% \2 Y+ w7 G; l
output mcasp_afsr,
/ |1 K7 q3 l/ e. l8 l7 poutput mcasp_ahclkr,
. n4 ?! v% o# x* @2 Eoutput mcasp_aclkr,
5 ?( Y; l9 T' B( a$ |: x' zoutput axr1,
* c' ` a, R1 f assign mcasp_afsr = mcasp_afsx;# e5 Q- g, T, ~! J8 F, s) r1 `
assign mcasp_aclkr = mcasp_aclkx;2 d+ }" Z5 F$ e7 x3 S, x1 W! j8 b
assign mcasp_ahclkr = mcasp_ahclkx;
& r+ j, s- d2 A oassign axr1 = axr0; ; C! N! b0 U @
& R3 s, k' E( Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ @+ O t0 y) I6 Jstatic void McASPI2SConfigure(void)+ F& O9 Y8 a, n% d8 J2 J- ^8 K0 o
{; j1 K- C3 @: N# L2 V6 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 E- n8 B1 d8 _6 zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' V3 `$ @5 `' Y) {0 H V A ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 I3 g0 j/ b5 Y$ m/ X4 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ |$ C9 M2 h# n% @+ |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 J# ^- A: E2 Y$ P! d2 H# g# VMCASP_RX_MODE_DMA);
! E' ?4 |" d: d/ o9 V; wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 e: l6 i( m/ n/ D( C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( ^; w& _9 a- G4 f0 vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" m) k/ I* a- s, o" b7 D& nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& H8 V! J+ v$ o. E6 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( m( I; m8 j; c: D; t" R/ q4 v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 v8 l4 G( V+ _) s N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ c; o1 D* L: \3 H% d* h6 L% J3 L) j" Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 H+ ?) P. B0 g8 t* A, S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# Z" ^) q: h4 m0x00, 0xFF); /* configure the clock for transmitter */9 }' w% m+ I! n9 Y; f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ C2 l! T9 h8 D* Z: o! r4 A9 e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' i/ a2 u4 J# [4 w* m6 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' n" r$ M0 \5 v. j! i3 W3 J
0x00, 0xFF);/ d: p% W6 z E) S3 ~
, c4 |) ?; T1 p7 [5 ~! Q; `
/* Enable synchronization of RX and TX sections */
7 L" Z, M+ C6 _: AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( Z% O; U% t6 O7 b6 s. u' k5 aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 F' G' f: E3 c6 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% O. E' ] _8 V6 ]: m, B7 a- @** Set the serializers, Currently only one serializer is set as1 G8 h, n* _5 b0 d. E! R* `1 @
** transmitter and one serializer as receiver.
! i' ]8 Z; Y4 R$ ^! {*/( V. q8 m' ^ ~; |; f5 D& w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ ?& ~6 o" _$ e1 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 [ ?+ ?6 R5 N: q) u$ a5 l/ A
** Configure the McASP pins
4 M, \3 X/ a4 @2 @/ l** Input - Frame Sync, Clock and Serializer Rx
8 M4 _2 A" N/ e, H% D** Output - Serializer Tx is connected to the input of the codec
) U1 r( [8 {' q! a& @*/7 l3 X$ x; e+ I; V5 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ M$ ~( ^5 z' H* gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. U! E* w1 |5 I0 ?+ h. h5 PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" r, B2 D; l7 B4 C0 K
| MCASP_PIN_ACLKX
* B6 ^* ~. [$ i: v| MCASP_PIN_AHCLKX8 I. v' ^9 R2 O& U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% i% ]2 r0 E9 ^0 e' IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; j$ i! h4 ? R, Z| MCASP_TX_CLKFAIL 1 i# ~" j- o7 D; t2 D5 s1 C8 n% g
| MCASP_TX_SYNCERROR
* Y$ v& f, q$ x% w: j9 O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( _' O( @1 ~/ u o7 B0 w( P6 B! F| MCASP_RX_CLKFAIL1 ]) i. R9 x, F) A9 o" N! j' }
| MCASP_RX_SYNCERROR
0 W4 v, s: M+ S* @2 J; i+ L| MCASP_RX_OVERRUN);! B) H" T- N0 p9 U* M
} static void I2SDataTxRxActivate(void)
& D2 P+ f: I% R$ ]' z# \! [! D{1 e$ A4 _4 L& U l6 O$ X
/* Start the clocks */& [8 v A6 i9 @$ D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- W! r0 y8 H ]" g1 N4 r" b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, I8 j* {& }, a4 T8 J+ I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
A9 u6 F. P ?: j) G+ lEDMA3_TRIG_MODE_EVENT);
9 C* {+ @% G* ~. L6 X. OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 d. v: t, w {) l6 lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 H$ t+ R! Z4 o3 F2 r% m& {+ Y8 r# MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ G% T" V5 J8 C; L6 oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; M' D- L: T8 R: m( l, T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# o3 y% ^; k% z! z) GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, }7 j0 r J. q! ~$ G( Q" g/ CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' Y; Y; M# A; K: f6 i
}
1 s, O" F+ K. h# d4 `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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