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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 ]! B+ R3 t2 w8 _, ^1 i* {input mcasp_ahclkx,
% X! y% U1 d7 ?input mcasp_aclkx,
/ q& g& \2 ?# h( C8 N+ d% ginput axr0,2 p% s1 s- f0 `& ?( o- R
/ E4 r9 i6 X: K* A6 \) M; I" uoutput mcasp_afsr,
' E: N4 Q, I ?' `" f( Foutput mcasp_ahclkr,
! r a& ?3 J; m' goutput mcasp_aclkr,
3 x/ ] Y F& Foutput axr1, r. C: a) R/ u
assign mcasp_afsr = mcasp_afsx;
$ u3 g3 N* F5 T) D" fassign mcasp_aclkr = mcasp_aclkx; ]2 a1 e3 K; r, u
assign mcasp_ahclkr = mcasp_ahclkx;
9 u; F1 d5 a9 o8 ?- s( Oassign axr1 = axr0; + ?2 P% P; r1 t6 s
/ E. r( f5 h2 _4 n F5 H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; y) K+ P- R' b8 Z8 kstatic void McASPI2SConfigure(void)
* h6 e( t0 A# ~9 L5 ?+ q: R{
% |" B6 E! G3 L% p, }* Z6 c+ |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# Y3 C% j, a0 [0 a5 m' Y( E4 ~& ~8 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 M# R7 j& T9 U7 G. t: j, e( e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 V) j- a' {( X$ A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ }4 |1 {4 Y6 U0 w& O. TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ T: d% f7 g1 C7 w% [MCASP_RX_MODE_DMA);
. M. g! R! |5 q: d4 RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
_6 e& y0 z- k2 J! BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' Z5 n& s3 K6 z) n g T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" `. J& Z; V9 q. z+ c' G* E; ?( MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 Y& a( \+ y5 }! y0 v0 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 E7 W; P, B/ k/ ?9 ]% K. a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* {6 }7 o" ]) t) @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& K. q- `# J5 U6 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' \# A5 T+ h0 n$ |# Y$ V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# A8 N( n% D0 l3 E' F0x00, 0xFF); /* configure the clock for transmitter */! r1 F+ ]5 K8 d5 j& b+ {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 A0 T7 ], t) G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 o6 P& F# q( [& \; e* v1 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 V) Z4 q W1 R' |: E0 Z3 v
0x00, 0xFF);% x: Y4 f7 ^9 }$ m, F
# i' T) F7 ~) ?' ~" p Z/* Enable synchronization of RX and TX sections */
e, \, A4 @' p4 S/ e' \" nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- d$ c. n) C& [; O0 M2 H) y0 b9 t5 yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 Q: f8 i7 M0 ]7 o( E: L2 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 n8 ]7 _) u( D, R2 Q) W, o5 Z
** Set the serializers, Currently only one serializer is set as3 i% h3 m% V+ j0 J
** transmitter and one serializer as receiver.6 u% ?" I* y9 N6 Y3 N _
*/: N# K L; q* ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ _8 f7 b$ }# F/ v' T8 qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& P+ x$ l" _6 y' k9 Y( }& Y
** Configure the McASP pins
4 C; Z; ^4 z- H1 E/ R0 p** Input - Frame Sync, Clock and Serializer Rx
. P' j/ Z7 A' l- f, G r** Output - Serializer Tx is connected to the input of the codec z* R8 o) g b3 P" }( [1 u
*/! u0 W; Z' K+ M; y z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 O, Q! t. W3 `! e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* N0 f' R, y N, b0 ^0 R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 u: `7 M; ^+ ]! l4 k; Z& b
| MCASP_PIN_ACLKX- ~* p/ [5 \% I$ q1 E
| MCASP_PIN_AHCLKX, n1 j$ P1 l9 z/ a4 \ J9 M7 S+ v: R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 Q8 i; c; M8 e0 W# {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 A1 y4 W& C8 M0 [# q, R* O/ d: n; P| MCASP_TX_CLKFAIL
* x! w" P8 k7 X! _8 x: O| MCASP_TX_SYNCERROR
|9 W$ G' a9 @. J- r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + L2 @% q& A r" X% U7 ?' Q) H$ S
| MCASP_RX_CLKFAIL7 T/ N( [" H: U. @$ G7 `
| MCASP_RX_SYNCERROR
. I# v |; C4 `& W, X: n7 w1 \| MCASP_RX_OVERRUN);& h3 x& A8 p- D4 {
} static void I2SDataTxRxActivate(void)
! M6 a @1 p& S. Z' Z4 V{
h) m- Z2 F1 [; F9 P/* Start the clocks */
' [4 u0 F( N3 I8 O) I/ ]: a8 iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 s) [ ?$ h6 b: r* z( f5 u* e- yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 D2 p5 F; G5 L- t$ i# e0 e( VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ w9 c" T8 h u4 ]3 U9 E, v# N2 H T
EDMA3_TRIG_MODE_EVENT); i% Z' D \, p9 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' X2 L' h8 I3 w5 j- F6 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 }# ?$ C* N! G- z- P7 \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' R2 O* ~. a8 q# j3 @; e: VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ W: L3 M" H# I! r/ c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% x$ L5 ~1 S q# i4 r' b( nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 i; I1 r# H& `) w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( \+ K, v5 R1 R! B# g} 4 t- ?6 j5 J9 y$ }! Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # ], z `) x; [
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