|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," c% u1 ?) Z: g( z9 H. g( g3 d0 c
input mcasp_ahclkx," L- Z9 U' n7 X$ T+ @
input mcasp_aclkx,* F J) [" c( V. G0 m
input axr0,7 k P0 s, N% B5 U, |, v
2 C# e7 E& D" ~$ k \, Coutput mcasp_afsr,. k7 u* o/ _2 ?: q' C! R
output mcasp_ahclkr,7 S" I, a: N$ r+ x
output mcasp_aclkr,
( C% _7 m2 H' k' M8 Poutput axr1,0 |2 | f- {& _/ Q! |7 t
assign mcasp_afsr = mcasp_afsx;, p& t. a: g+ O, f5 t1 L1 H* |
assign mcasp_aclkr = mcasp_aclkx;
+ ^( ?/ |% |5 n& A/ R2 ^ `! Bassign mcasp_ahclkr = mcasp_ahclkx;( j( b. }# R$ |* w4 ~. {; x
assign axr1 = axr0;
% Y2 h6 p8 ~* G. y7 w1 s h
; G+ X& _) G; l7 K& ? U! ?0 b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 u( Z- E, V' N. qstatic void McASPI2SConfigure(void)# D" E4 }3 a; S2 o' U! y. ~
{
v5 s* V- D, X6 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 S9 E; E( G3 ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& Q: R" ]5 r% p: U' ^, DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 L8 Q' X; c/ C P/ s6 X: A- S" |" \( F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 R- L) q2 q7 C1 }7 nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( z1 F, x$ h' A; N
MCASP_RX_MODE_DMA);
: [# d" ~7 x) D8 K B+ QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) S3 M7 Y0 Y1 @, r# _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& ^: \, a% a1 ^9 S, {& V8 K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 u9 Q8 x& N- r: o9 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. X# A& A5 }3 h* F* S" C- OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 e. P2 E2 R0 D4 s, M- m5 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. Y4 Y, t8 a5 w) p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 o" W9 O) p0 `) X; Z$ Q, ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 l, E' O0 @. q- f0 p* h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 d: y9 f* i/ Z* O5 Q$ W9 W
0x00, 0xFF); /* configure the clock for transmitter */5 V; X) c; X9 W; ^4 k9 N. O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 X3 {, P' m) N+ @9 f( E5 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 X0 q, U3 _( m, `6 M @# ^4 I3 xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 w& n/ k7 \7 Q# C0x00, 0xFF);+ X! f3 t: q6 E! _$ [# k/ Z' \2 l
& J9 E4 U" c/ [/ Z e/* Enable synchronization of RX and TX sections */
5 h* ]) E1 o8 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! ~# L* u3 [7 F+ @4 }# YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' g; n* ~. o; d; C& w KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 `8 B: T( J+ b+ q ^4 ?9 Q
** Set the serializers, Currently only one serializer is set as9 E- i+ }3 I. L( L8 S7 N" s7 J
** transmitter and one serializer as receiver.. a$ b: ]- p& I' r
*/0 t+ v, x- [# \2 F0 B9 t5 M* G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ u8 R6 f9 \' s% R aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ S9 d% j f7 t. A$ ~, r** Configure the McASP pins : c8 \6 R8 F U3 T8 f
** Input - Frame Sync, Clock and Serializer Rx, J2 |: z/ F! z ^9 M. D
** Output - Serializer Tx is connected to the input of the codec ( ^, z; t1 i( r0 O- S9 s- v
*/
( a a) ?: p" _ _7 `: q) iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ A! p' y* v1 z: G) @1 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ b1 ]! H& u* L. A" @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& A( y7 d8 k0 y# y
| MCASP_PIN_ACLKX
8 T$ U8 v8 a1 A" I| MCASP_PIN_AHCLKX$ O4 b( V y. E" Z y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% ~2 e% h* m8 Q" H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 |; x; f3 ~& D0 B9 P| MCASP_TX_CLKFAIL
+ \3 |: u- z0 i. ?: Y' W( W+ {5 ~| MCASP_TX_SYNCERROR: F+ C7 D* T5 @$ ]% P; J) T8 S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 i! A" E* W ^: [. E' q
| MCASP_RX_CLKFAIL
+ [, t5 w* Z; n* S" u w* V/ {| MCASP_RX_SYNCERROR
# l7 W4 ~- z2 {& V$ D| MCASP_RX_OVERRUN);
4 a& B) e1 K2 Y* M0 \ }} static void I2SDataTxRxActivate(void)
* E+ F {& y- Z3 T% M4 r- m{1 n. M. {- S0 }: ]4 c/ W* Q8 i
/* Start the clocks */
$ H- G' J3 l! a* sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* ^8 N* q2 I3 S& G" `# S! ?3 Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ C2 @& Z7 z; B8 X( FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' t" X' |7 q, H( _0 G3 C9 f& L6 a
EDMA3_TRIG_MODE_EVENT);
4 n! ]0 \3 F: V$ @9 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 Y* D* d9 v o6 @; c3 }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 v0 ?: S! k9 z/ A; e2 fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# V, x9 z* u/ y2 \+ F+ Y6 mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ E- J& D" }( |6 z' t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. n* k% g8 H; a& o; c% q: a, O5 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 l G8 ` E ~4 p+ ?4 k! q" RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& L6 M' v* U6 v4 X& r+ }}
' `: U6 V" n! {; @8 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
/ m- H" H1 U. i, z7 ]3 \" F |