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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. d% l. e+ b, l9 ~! \. {input mcasp_ahclkx,
( L% M! P2 G M3 a9 D5 binput mcasp_aclkx,2 F) t! V, O! ~0 L
input axr0,
* d$ T" i9 R6 }% q9 J" q
/ n5 e6 j0 e* K! q- B4 Eoutput mcasp_afsr,- u4 d( G* j: S
output mcasp_ahclkr,
4 j/ u* e# G& G8 Ioutput mcasp_aclkr,
0 b: q& v4 ~0 C# y. k6 j9 [output axr1,' K- J% u; |( a6 s
assign mcasp_afsr = mcasp_afsx;+ B; H( I. l# l8 x4 p8 `' v# O
assign mcasp_aclkr = mcasp_aclkx;+ @) {, a* U& P8 e. B9 i- a8 n- n8 d
assign mcasp_ahclkr = mcasp_ahclkx;
; c: k) `8 V5 @% T& }2 \assign axr1 = axr0; " H' p' [' N9 s6 B+ Y- n# E/ ]
5 [/ Y7 U$ s% z: p( t2 d2 j9 h% h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " J4 @5 v7 ]5 R( O2 K* I
static void McASPI2SConfigure(void)! S5 c `5 {: i, {$ z3 L4 Z2 T
{
, b# [- k0 v8 o5 B+ R. BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! O& N! E D, H! H3 U" h- P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 i7 J$ G: o# y9 L; m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 h- S% k, r% k8 B$ x- U# Y* X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" f5 |2 d9 _* q7 ^+ M8 Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ U; x6 f2 f' S5 f' i: A; y
MCASP_RX_MODE_DMA);
9 Z% j2 A4 @9 O9 qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% Q) `1 w* `- `8 wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ w( } ?1 b; T; g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* c" y; Z& l$ fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 N2 e6 r- I# @! o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 a: `) r4 r# P! k2 a& `7 z- }4 }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& t5 s5 {7 K6 o# }. f6 w, K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( r2 w* C" s' b, G# wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 Y3 J; K: a0 O0 ?5 @7 F8 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 p+ W) [. A' ^, c0x00, 0xFF); /* configure the clock for transmitter *// W" A& b S. X( F0 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& x; a$ v! x9 o6 T( Q7 ?4 G: m2 I& sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' \4 D- Q. h. Z; PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 T2 }& G6 d2 l" e, L7 a8 s( Y9 I7 c
0x00, 0xFF);9 D* z" ~/ d2 _3 K& Q- `6 [7 Z
. C! b2 R+ N% ]0 T/ G6 a' r
/* Enable synchronization of RX and TX sections */
' D+ t/ T5 i: u [8 X8 p" uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 q2 V% E: k+ [; N9 ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 X; m( h: v% P( ?7 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* S: f; C8 g. h
** Set the serializers, Currently only one serializer is set as
}& e8 o/ P/ l" D8 v q** transmitter and one serializer as receiver.) E, P. O0 ]' p
*/" k% ?1 ]7 V+ h) ] C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( D% m+ f$ Y& m& t5 E, SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# u1 J& o# a0 @( K
** Configure the McASP pins 5 z* U1 G/ E; k* c
** Input - Frame Sync, Clock and Serializer Rx" _9 Q1 e1 j4 @4 V3 R
** Output - Serializer Tx is connected to the input of the codec 2 y; n( U4 E' e4 _
*/
: l; Y" f+ i% ~# r& e0 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ h9 _0 H9 W! e4 N/ @8 J# q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# t8 ^% B4 [7 |$ T: a3 ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 d8 V$ r" K& n2 o$ \4 X+ S
| MCASP_PIN_ACLKX3 K) H& g1 _; R4 [& p
| MCASP_PIN_AHCLKX
6 I4 w; P! {* S' N! p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' e9 h8 R0 s( s: J4 H( `2 \ K5 D; K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / F! f: d$ Q/ t: }8 n/ j" g/ t
| MCASP_TX_CLKFAIL ; m2 r4 K1 R- C, ]" j
| MCASP_TX_SYNCERROR# v7 m$ p$ \( w+ V/ h+ [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# a; M9 x. _% a+ b| MCASP_RX_CLKFAIL1 }, i- y( `# n" _4 s$ K. c" h
| MCASP_RX_SYNCERROR
+ h; s/ I, `7 X% {8 p| MCASP_RX_OVERRUN);
1 q6 P& {8 _' x7 l} static void I2SDataTxRxActivate(void)4 x( [& F, l2 T5 G1 T- ^
{6 Z# `, f' j* l' l2 t( A
/* Start the clocks */
( ?! B) f& b2 u# w4 L& y; HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' j" A, z7 d: K5 x3 QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- K. ~; {, p9 ], n* R& }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( b9 u. {& c+ ^" L" `
EDMA3_TRIG_MODE_EVENT);
, t3 W2 O5 b) I" h: jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % E$ ?: `8 _; Z- c$ @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 @" i! A; c% k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" h( z5 [7 a) WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# y* q8 i+ {. A5 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& w3 e; m( x& S- }8 N8 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* e8 b, v- v8 rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) O/ V/ A; a: u+ i. q$ g% C8 I: C* o1 e$ A}
; {! {( F: [2 G8 y$ b0 N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
" i" V7 _0 \1 |+ a |