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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 ]% Y7 I. a j9 [4 A! S
input mcasp_ahclkx,. _$ F) K7 P! j5 P
input mcasp_aclkx,
- h( A/ u0 `0 C1 z; m8 _! }$ P# Sinput axr0,4 ]0 f+ ~& v" @. V# F# J
* c9 _6 n" V# v5 R- ?/ i# youtput mcasp_afsr, Z( t7 _" H; |2 [8 c& g
output mcasp_ahclkr,+ ]* X: ?- q" H8 u9 h$ \7 ~
output mcasp_aclkr,
* Q2 T, g5 J( `$ Q8 C1 ^$ g5 |( youtput axr1,- f1 B: x( e& D L+ T, c
assign mcasp_afsr = mcasp_afsx;8 O$ l. l/ W' O9 N
assign mcasp_aclkr = mcasp_aclkx;
7 `8 P$ L# x0 L( g9 J D4 iassign mcasp_ahclkr = mcasp_ahclkx;& s# o4 b1 {& N" X/ C! |" s
assign axr1 = axr0; 3 F, [8 T5 t2 Q* i- S1 _& q, n
& ?7 q1 d1 E- Y2 k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 ]6 q6 X7 W' g
static void McASPI2SConfigure(void)
5 `; v9 |& q( Y" @* k& D4 \{
6 X4 K8 ^ E+ w0 t7 o9 f% J# VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ C( ]3 x% { H! j2 g% B+ i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: i. W. d& \5 O6 _, V; @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! s+ z# a% q& Z n( n: Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 ^1 t+ p1 N% l5 @0 {. @; S! N+ dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- J; y( b+ Q$ P1 D& T7 J
MCASP_RX_MODE_DMA);1 ~' V" q5 t7 n- _6 g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 i! d5 S7 U( {$ y8 }' h z3 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// ^' s$ E, ?( G2 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 L* ]6 S6 q7 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 W& \3 ^2 _5 j/ {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 b/ x& B) h8 p1 T9 n. ~+ L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 U5 {1 H/ ^9 I% e. k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); S& K- {, t5 S1 x) Z2 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " W1 _& R$ S5 p& T( E9 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% s8 w5 [2 z L @" F
0x00, 0xFF); /* configure the clock for transmitter *// _% `! V7 I6 @0 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 ?& O+ V- h+ e0 A I0 z* e! RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 V9 I5 R, E ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& a+ }" S! ^2 G2 N- x4 f# T
0x00, 0xFF);9 F) [+ z$ W# s
" m+ D& h/ l V3 W) I$ M
/* Enable synchronization of RX and TX sections */ ; q2 | W8 h; B% d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: I5 h+ j0 a, \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' r6 s$ V! Z+ S5 k" k2 z. k; nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* i" D, |. Q Q' @
** Set the serializers, Currently only one serializer is set as$ J1 {7 j& I1 g1 P: Q
** transmitter and one serializer as receiver.
' I9 v( A, o* B/ ^*/9 A# C* _( n7 T' u( W1 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 h( _$ `! Q1 g8 {- P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
d: Q. q& s7 U6 |8 y6 O7 v** Configure the McASP pins 7 c& I- B8 A7 g. z3 \
** Input - Frame Sync, Clock and Serializer Rx! X2 P) K. ~; Z
** Output - Serializer Tx is connected to the input of the codec
3 }( P2 S8 s/ o* A! T* M* M& u e* s*/7 A' f6 r$ Z" D- J2 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 `( L9 I( d9 f6 Q# g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- j1 |* W8 Q$ f+ O# W- CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- [, S. X' A9 A ?' s+ y
| MCASP_PIN_ACLKX9 n$ Z3 r! S2 {8 `
| MCASP_PIN_AHCLKX
% f! }! S6 H( }( c3 i9 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ s! z5 L& g7 s' J& {3 C; m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * _7 G9 \& c! C+ Y- q' w' r
| MCASP_TX_CLKFAIL
+ e9 I. c5 d" J! ]3 k8 H| MCASP_TX_SYNCERROR$ M, s7 F0 J: S8 w- V4 r" f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , G% a# R6 q I, D9 K( |
| MCASP_RX_CLKFAIL
' ~& S; e& T C1 ^| MCASP_RX_SYNCERROR
& ?; G& x) u4 _4 G/ R9 _; U- u. A; _| MCASP_RX_OVERRUN);. o+ o& ?) K6 w' p8 _0 C
} static void I2SDataTxRxActivate(void) B- t3 j) p f. k" E
{* u7 ?- x. z0 [" Y2 `
/* Start the clocks */
. \' i. ^2 M$ [, GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 F8 w* J1 L |2 q: }) Z: w$ g5 c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: T8 o u7 w" {: x3 ?7 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 K4 U6 H& @# e# G- R
EDMA3_TRIG_MODE_EVENT);) q( z0 ]. A" J p; Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 x/ L/ U1 F: ^# Y" c0 j. C2 F8 c/ z4 @$ iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: `& x2 F" p: f! H2 T+ K/ a& w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 {9 y0 R9 I" X. I/ X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 y, j! K# ^, _" uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ _- o4 k8 W6 J) J' @" Z3 WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' K+ }3 j' s6 H Y G6 \% ]/ z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- i7 F* X5 {2 L) x' P) e( L& Q
} ( C& M- x; [* u, {8 H! l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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