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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) h3 w$ d- h$ a: w
input mcasp_ahclkx,
& L# ~* i* Z" q7 n2 finput mcasp_aclkx,
+ A3 q* H. u) |! ]* o" g0 n: ?input axr0,9 u* d9 {' i' ]
1 y7 m. G# `8 a! ^output mcasp_afsr,2 R6 @+ V' x% n+ K# m# V
output mcasp_ahclkr,5 W: K9 h5 }2 _; [% P) J; n
output mcasp_aclkr,
% o$ I8 {0 {, P2 U. [8 ioutput axr1,
0 f5 z/ s; M0 X! O assign mcasp_afsr = mcasp_afsx;
( z+ g C7 M h! |assign mcasp_aclkr = mcasp_aclkx;
1 _) }6 w6 a/ w* }assign mcasp_ahclkr = mcasp_ahclkx;+ u) c G, s( k- t
assign axr1 = axr0;
/ E9 L9 ?% U$ E8 e% L
) s% ?+ X T6 M" s7 ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: Y+ x7 \7 l3 C& H+ Qstatic void McASPI2SConfigure(void)
+ v7 W+ T' l' D" y/ o% s{. H4 v/ @; ~1 v& k+ X4 d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; E1 ]* Z% L7 |6 ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ V# G) @: k, }) c2 e3 a0 {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! f5 f6 d l0 g8 Z5 L3 l9 |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" M* {9 Q* y R1 S* YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 i7 l2 o- o- I- g* l
MCASP_RX_MODE_DMA);% E1 y/ z7 U: O& u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# i! v6 m5 T- t9 `( n0 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 ?1 D5 T, X5 @8 b, aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 t' x3 ^$ j7 D6 s. P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 Y& w; ^- G D) ~" G6 L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 _8 c0 C9 z- i9 W @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( }/ y6 D9 l0 s) h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) l1 D) @- _/ C7 l# {7 l1 M( L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 `4 X# @( B- l) u: T- [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; x0 h% O& T* g1 n' v
0x00, 0xFF); /* configure the clock for transmitter */
/ s' [ J- I( q2 Q* ^& Z2 C5 r0 mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( u, g9 }; g1 L* Y/ L; T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " O0 z$ U/ o% _. n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- m1 N _, Y u$ q3 j- d0x00, 0xFF);: @; V4 ?2 {: a. V$ N
: \' J7 x6 v2 f7 C/* Enable synchronization of RX and TX sections */ 4 E0 t1 |6 g2 m; S6 W6 E/ `. [1 ?) o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 |7 ?0 l4 T2 a' N( W+ J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. k' c$ ~, Y. e$ w0 d1 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) z' @# s) ~4 U9 y1 S
** Set the serializers, Currently only one serializer is set as" F1 |5 n# ], a: o
** transmitter and one serializer as receiver.: O: U2 T% T. @. s
*/8 z% p' C( A+ S9 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ ~- `( h; p9 q! f2 rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 S/ ]; Z. W9 Q; q7 [2 t' J4 [** Configure the McASP pins + L2 y6 _. G3 A: S; Y% E
** Input - Frame Sync, Clock and Serializer Rx
4 c s2 h& i- V* \, ]** Output - Serializer Tx is connected to the input of the codec
" H- O8 A. k) g( M8 X# a [*/
* T: n1 x; X' t/ E% ~2 p* O- y0 XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ w! p4 B( w" v7 _4 {7 G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, z3 R* o4 a9 }( f; Q7 y A# q* R9 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 L- C6 B9 s& Y
| MCASP_PIN_ACLKX* s& Q b) N+ L" m
| MCASP_PIN_AHCLKX' Y# D% n; P9 X* G2 w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% C' o4 J2 |! s# z. g: ^0 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! C7 Y) J# i" S, l2 `. ^! B
| MCASP_TX_CLKFAIL
& G9 y: \. V# M6 s8 d| MCASP_TX_SYNCERROR- L* B5 p S5 v2 s8 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / ?0 l5 s2 [; P2 F# o
| MCASP_RX_CLKFAIL
0 u3 \3 f7 C; W& R| MCASP_RX_SYNCERROR ( @5 }# R: |1 H! |
| MCASP_RX_OVERRUN);: o* u3 p) y: \" w/ V& k+ B5 g
} static void I2SDataTxRxActivate(void)- G3 ]# B/ X3 S% U
{7 Z, x0 G1 S* U. d% x3 w/ T
/* Start the clocks */6 K4 q" h: p! P$ O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
v) m- P4 i. yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& H c2 V$ F& M& ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 _! n+ w0 X- c+ T+ B0 O3 uEDMA3_TRIG_MODE_EVENT);% ~; [6 v& ?! A( L) }, [* H* M8 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% H0 J& y. E, p* I& {5 oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 Z1 I3 X. L9 v! w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: I" I7 l2 F, W5 i2 D0 M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' g" n+ M9 o4 O7 e( G+ Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: E6 y# V7 R" T% J! xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, b5 G6 C: t5 G8 D7 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: a! r% o) R2 R} + V8 a) V+ O/ m0 `0 o4 F3 G/ D0 v* E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & _9 W0 ~2 @: e
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