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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% g! o' Z" a' Q; p$ \input mcasp_ahclkx,
{5 |3 U: r7 P0 M/ S/ v0 Dinput mcasp_aclkx,
, t4 O) ]* h( m* @3 C5 o" A. dinput axr0,
2 c! b3 r! q6 Q6 f2 }; [- s4 L
) z0 j% [! F, n4 R loutput mcasp_afsr,! H9 E5 T- t. r8 i
output mcasp_ahclkr,
+ d( C9 u: c6 y. H6 P% xoutput mcasp_aclkr,3 H$ J* f$ B O. e
output axr1,! s8 g" E5 {, F7 B1 z8 D! t5 u( Q+ W
assign mcasp_afsr = mcasp_afsx;3 S) \& _ S( ]! f& u
assign mcasp_aclkr = mcasp_aclkx;
k4 U5 c: ?: wassign mcasp_ahclkr = mcasp_ahclkx;
; a- y* E- V- B& \: `. z+ qassign axr1 = axr0; + y- R7 E0 {+ m! d
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 E" C3 n- s7 S% F
static void McASPI2SConfigure(void)
5 `5 B0 \7 w2 l) `/ V{
4 W$ ~- l" ~" I4 M% fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' V. f6 m1 E$ I0 X$ [) X6 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, L' [; U/ W( }: T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 K6 O* @$ G8 ^% l! Y- M- V" S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! `! h; |% E6 ~7 m1 y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) f, O; x8 [" y& O1 H- x1 q
MCASP_RX_MODE_DMA);. _; `% m0 j9 t- |* c/ F- F, O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ [7 Q" v4 ?+ m4 l" e% F- @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
g5 d5 {1 ^3 ] q A- q! `3 bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, j' D7 b! W3 p- AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. x. r: z& `3 L$ S {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 v0 @6 w6 B2 M2 y$ aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 s f0 e9 o) G7 ~# g5 u' C T3 ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ E" L) E( F/ L" A" V# RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 K, d8 |4 w- F! f4 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 f: H" W, {$ Q1 F4 S' I' T, s; D! R( m
0x00, 0xFF); /* configure the clock for transmitter */
7 O% r' j6 ]; y! p& [% T, r, n* RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 \3 x; u+ ^9 @; L! i3 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); _/ h! f3 B: O$ {9 Z6 `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. H) m2 }. z+ ?9 k
0x00, 0xFF);' p0 i; ~% P1 K; i% ^% D, p6 i5 M
; \& k9 S& x; T5 Q, X/* Enable synchronization of RX and TX sections */
( s4 z7 O! M0 f9 P( q- yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ p7 t( l% r1 C9 k+ }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% f) w& g. `0 Z. N( W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% E$ v$ ]4 s: a2 U3 n
** Set the serializers, Currently only one serializer is set as
D; V. t7 M& O** transmitter and one serializer as receiver.
) B2 `; s+ B1 I5 O*/
. q7 T% G- Z* H; @+ LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& } c6 i+ u3 T0 e+ v) F. [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 [' w8 {' P0 A5 _1 l** Configure the McASP pins 4 I/ B3 U( o) E1 s- \
** Input - Frame Sync, Clock and Serializer Rx
7 q( ?7 }/ _! b** Output - Serializer Tx is connected to the input of the codec 0 T) q& m- C0 C1 Q- Y# z! Y
*/( a* y; C2 k/ q4 @, E1 C V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! \; {" r. b* T% n$ ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; [- G+ n! h( X: `1 a$ h! N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, q/ p$ h. f# y0 L% Y
| MCASP_PIN_ACLKX& I' p6 R" e) a9 f7 ?
| MCASP_PIN_AHCLKX
6 T' g, q2 C2 C( U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 ], R5 E6 A8 A2 h+ q) ~' ~9 j8 e, GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 J, L4 S6 Z! \& k. V
| MCASP_TX_CLKFAIL
7 t* } A6 p# |# o0 h% y/ ]( ]| MCASP_TX_SYNCERROR2 z# P$ W9 }* V3 D1 L" O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! l7 f6 N! N6 H4 _% B6 l4 F
| MCASP_RX_CLKFAIL$ @; k' ~8 \" Z' \
| MCASP_RX_SYNCERROR ' u8 Q) ?1 I: d! Z( q
| MCASP_RX_OVERRUN);
; P1 z4 s# P) G( L1 @2 }} static void I2SDataTxRxActivate(void)3 E! ]2 B1 f, h# ]2 Y" I1 A, W& n0 b. P; G
{
- A. L- n+ h0 n+ q$ r9 M/* Start the clocks */+ A! O" R# ~5 F. ^5 n; \( t' M! o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 Y" p' g' o4 T0 q4 L" O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 N& B' Z+ R" ^& v7 P& ?( LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 ^$ J: K- W9 ~$ M6 _EDMA3_TRIG_MODE_EVENT);- v$ u/ p, F/ w3 e2 X9 c9 L: |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% F+ W" c, y4 y# @& B8 X; NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 a2 L6 Z& E6 ?: U+ Q0 wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ B9 ] I1 F$ D. \9 w" UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 w6 X: a0 ?% l7 {1 ^, g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. @" B( V$ e2 C: z6 ~5 N$ e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 k' s+ g+ m/ x% I+ F9 B# v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
`; S1 j& z1 p) s} + v) x% r3 E5 O% M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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