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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; V' s% y( R) O* oinput mcasp_ahclkx,. W$ Z( M% x2 f* S3 O" T) c
input mcasp_aclkx,7 y4 `0 N: i0 y6 a3 Z
input axr0,, H. A" s R6 r- M; ?! |
( i/ h3 s. x+ ]output mcasp_afsr,
8 |4 D! `7 j" `) N) xoutput mcasp_ahclkr,$ U+ W2 [8 n9 f
output mcasp_aclkr,
( d8 O/ k4 H! Foutput axr1,: u* B+ i0 p/ }1 g; t+ a8 H
assign mcasp_afsr = mcasp_afsx;
$ E- [ r; Q0 Y5 u' U9 q2 `, b* Passign mcasp_aclkr = mcasp_aclkx;5 q' [' n7 n. N% Y8 d! L- v0 i2 N
assign mcasp_ahclkr = mcasp_ahclkx;8 A0 [% T# {' X9 |- d7 d. U; x
assign axr1 = axr0; ' a" c' [, ]1 A
- g; w& c" }& w1 `+ Z9 ^* m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # k8 |/ Y- F5 |9 {
static void McASPI2SConfigure(void)
# Y1 u- }; e9 y: j1 F{
9 y1 |9 ^( g/ \0 b7 a W5 O" @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 e6 \: P- |; Q' yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 \+ s9 C# U# c. g0 o% `5 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 ]9 d8 j! _8 t6 O( [7 f( NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* Q, S6 H6 { iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 l# R% F# @; I: {/ O
MCASP_RX_MODE_DMA);
1 o4 N) ?& w$ _6 i% [: kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( R2 z1 `$ g. ?2 ` G4 n1 Z1 [( NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) k+ w" n3 h! N/ |7 x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 l: Q, A; J' o* k- ^7 T" s* kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% _+ N: I5 t: Q* w/ I, z& N/ g8 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
g* g$ K' l! C" A3 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 S O2 ]5 @. m8 Q0 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 h, {7 `" v# o+ e; o" yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' w# r& X3 E) }& I. o8 J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 x1 C6 [* o. \/ F
0x00, 0xFF); /* configure the clock for transmitter */
; U2 `, c2 \( ~4 n7 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% d( N/ h6 ^( `- \7 A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. V- i; ^" e/ T5 K+ pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. U% I. J; G4 ]4 X" h0x00, 0xFF);- C# A4 u, w2 g' L+ w' u& n
% u" o* X; Z6 @/ L. r# q
/* Enable synchronization of RX and TX sections */ 4 F j* H. s) v: L1 w1 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 M" Y6 Z# H7 ? n2 S7 I; i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- a& ?0 S5 f' _" nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ g5 C8 ?5 |" k8 G/ B3 a/ h& }** Set the serializers, Currently only one serializer is set as
& d& t) i5 U8 I) i** transmitter and one serializer as receiver.& s0 w7 i5 G5 x+ W" L& B- H
*/
: C+ D! r8 n1 V1 `0 q- Q, ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# j' l, o1 d/ \4 |+ |4 W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. }; a: I( j. C8 f. |** Configure the McASP pins
+ I. t, K9 B. P7 B F4 [ |6 C& S) M** Input - Frame Sync, Clock and Serializer Rx5 |: }2 J6 H( n9 \; A5 x3 c
** Output - Serializer Tx is connected to the input of the codec 3 {, O, V+ X$ {' ?9 r
*/8 Q7 h( ~9 m" S$ c3 R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; B& \& k5 K z2 [$ r7 x" pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! ?3 |2 v' t, U6 p# R- ^6 S6 JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 s( T+ |* i( c4 }3 t- L! y+ P; ^0 j
| MCASP_PIN_ACLKX
) V% d8 H3 }4 d9 E| MCASP_PIN_AHCLKX i9 K9 X; m1 ]. J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& `- N+ t& E/ h( pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 L5 D$ R% Z5 G1 C| MCASP_TX_CLKFAIL
# i# V1 @; y' ^0 ?' c| MCASP_TX_SYNCERROR6 C+ u- A8 Q2 b( v6 D; E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 @' T. m9 z B- |' D$ V
| MCASP_RX_CLKFAIL
( f+ R* R* s/ R| MCASP_RX_SYNCERROR 7 S( j: l# ?8 a7 x0 h
| MCASP_RX_OVERRUN);
/ G4 ?4 B" R4 |( C8 F" ~- V4 h} static void I2SDataTxRxActivate(void)9 r- @" P x: Z3 n' f5 ?! Z) B
{
3 R/ P( N( r! e* d/* Start the clocks */3 @1 T* @! b" W7 k. E. m5 y* n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# ~+ P3 [) B* H" l& @ Y* V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; @* P1 a$ d$ ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 V+ }& k( x" u2 I9 l! b% u
EDMA3_TRIG_MODE_EVENT);
, H( W8 n% [2 r M; ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / ]: _- M! ?5 l: I9 ^+ }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; |3 g. u' N! f7 h: d( Z: aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( R* h3 z$ \: _; Q2 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
k) F- J1 H5 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
Y9 x7 C: M6 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" A! z- }( z; w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 O$ p6 O5 t: n1 Z/ F* F6 W! @6 j
}
+ o, J( s- L) z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) ~; U7 ~2 Q% m
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