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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: W2 }6 E- b c+ L) y# N2 s4 Qinput mcasp_ahclkx,
+ [+ R: g1 n2 @/ n- q+ I- @* Iinput mcasp_aclkx,& _0 ]9 M( F+ d: W9 R! F) [7 [
input axr0,
# T B1 ]0 a, m1 k* i Y* w6 J6 y. ^+ k
output mcasp_afsr,
4 {- J6 l4 j* T( b2 O0 ~5 [. z) U$ soutput mcasp_ahclkr,
0 @1 M7 t7 R: u7 ]& doutput mcasp_aclkr,
, m, R% Q6 `" {, R/ p- Aoutput axr1, q$ I8 x& C. {, l0 j
assign mcasp_afsr = mcasp_afsx;% w' B7 o0 P. F- R+ }3 F6 j: k
assign mcasp_aclkr = mcasp_aclkx;" D1 E: ?8 H9 Z0 {2 \" f( K! j
assign mcasp_ahclkr = mcasp_ahclkx;
* z7 l4 s2 _6 ^* U; ?+ g* Cassign axr1 = axr0; , V$ s+ P/ q6 u
3 d# L2 [/ Z/ j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 z( ^' |2 l, n e$ cstatic void McASPI2SConfigure(void)5 C T% e5 m- T6 ?5 }( u
{
: `$ x. ]6 B' tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' o) l+ ^+ w/ y2 q) a) a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 H7 ^; Q4 _/ K6 H; q0 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# q1 q9 S; n x" W% U! p: @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* w3 x! _+ q, I9 Y9 l4 \6 i# g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 v" \; c$ _% w6 Q9 FMCASP_RX_MODE_DMA);+ M* i# x( i/ C8 i6 r4 V( D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ^" i' a# Z; @7 |/ h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; a' Y. }2 d( n" b! s" ?- e- ^9 G# y G( U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( N' ~( Q; v" }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; L( f) Z- Q8 p8 E! [3 R0 V+ Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 Z4 n' [. z# ^, h; a. e) RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 ^( [7 I" N- b, w$ bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 c" q/ s4 x. {# u! JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 O5 ?4 [7 D0 i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# j, f! o9 P) p. [) R3 ^0x00, 0xFF); /* configure the clock for transmitter */ _5 B! f" k; e, o% I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 J! v& m5 ]+ f, ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ D; [8 _& r9 O3 B lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 G5 E0 U7 Y, p/ ~) {
0x00, 0xFF);
! m% u$ L) j, ]1 C# _- a' |3 h; @$ i
/* Enable synchronization of RX and TX sections */ " O7 Y" H* `6 Y' N4 s$ G0 z* R4 ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- x/ [2 {2 p/ e! F% FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 D8 f0 H( W4 K# s4 @( ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 w! l6 y6 k, d# j, e& s) f** Set the serializers, Currently only one serializer is set as1 w% N' y& [4 W3 {" C4 l0 V N
** transmitter and one serializer as receiver.- V; j1 U$ S) i `
*/: v- _- Y6 @2 x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" L1 q* \; A* v2 H& q( t$ D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 M6 S# o8 D3 a2 @0 L8 Z; g0 \** Configure the McASP pins 5 m* A- n( N! G5 L
** Input - Frame Sync, Clock and Serializer Rx& ^7 J& C) R9 g/ J, P& p
** Output - Serializer Tx is connected to the input of the codec
$ n! s( u* @* ~9 |1 J0 @- z* y% Z*/
8 R$ Y$ w! S- U5 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 [. K! _* D1 a. H# u" U+ [( [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 p; m9 _) l. m$ w' F; T& c/ _: ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ E5 T; @. ?$ ^$ \- q9 i
| MCASP_PIN_ACLKX
$ \/ O" A9 O4 b8 ?8 A( r| MCASP_PIN_AHCLKX
! Q; j8 e. [' g" }; `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 y7 s, h; W- O0 S' w# A3 |3 n; S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ U& Q/ F+ g6 f! K+ {- [0 F| MCASP_TX_CLKFAIL
. x+ H, f1 n; y2 |# G3 L9 g| MCASP_TX_SYNCERROR
5 K. c6 _* a8 l0 C$ ]8 ~3 d7 [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 T! c0 B' d- U| MCASP_RX_CLKFAIL7 t4 b' A: B- P, L
| MCASP_RX_SYNCERROR
J2 @, d* K/ k! x ]- p| MCASP_RX_OVERRUN);# K8 ^, Q' j) @2 u z; y
} static void I2SDataTxRxActivate(void)# D D0 P+ V+ ~$ Z% \- ]
{
- F5 L* V4 G* l6 ]0 x W [/* Start the clocks */0 n8 s0 v2 G! r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. M. m( h3 c* o6 x: K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. r% L' V# k- w5 o9 h9 f6 p9 v- B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- \7 k* S2 L/ m: j0 h# X; P1 p8 V* m
EDMA3_TRIG_MODE_EVENT);# @# z7 |+ P- R4 h7 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; y4 g, O# P' j8 U! j( i7 L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ k) h ~1 I: R3 \3 X3 aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: m5 y2 e/ ^* y( d2 P' a+ K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ ?) J! j$ [+ |3 k% V h2 Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) j s4 s: R" Z$ r7 _# q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% T$ {5 X2 r7 D$ S: F6 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& D/ }* J; ^- Q* D' m1 r' q} ( @! Y; [$ f. q' Y2 r Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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