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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 H$ z. N! j; h+ s- g$ dinput mcasp_ahclkx,
, H- C# N3 s6 H8 M5 ?8 f$ h; Cinput mcasp_aclkx,
9 V: e5 U6 j% z* o& `input axr0,
9 p- @5 _+ n- Z+ |. j( W U( @2 L# |1 N5 p* s/ H* Q# |
output mcasp_afsr,* M+ K& z; q8 f; W0 k
output mcasp_ahclkr,
" Y* r% g; S4 F" N E' _output mcasp_aclkr,, P0 L0 c! N" _9 z% ]" B
output axr1,
/ L1 B/ F; x' Z; ? assign mcasp_afsr = mcasp_afsx;: M& d3 G" g- n) i+ F
assign mcasp_aclkr = mcasp_aclkx;
, Z: f/ q. i% S# k% x8 _ h2 o; tassign mcasp_ahclkr = mcasp_ahclkx;( n& ^) t& R# b/ A0 y5 e1 \% H
assign axr1 = axr0; ]5 s$ v3 u4 A. _/ m
# u1 Z/ ]2 Q: C& t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' H- v' `% ]7 d+ Y
static void McASPI2SConfigure(void)$ N: M- E# V# `# ]/ k* ~, h
{8 ?- C8 M7 g) ?$ M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ U1 D) g7 w8 ^$ I2 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' l: {& q: G# D. S5 _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ O3 r- M5 v8 F4 K; e1 ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 o7 a* S4 W. s' g2 Q1 o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, _0 t& R1 T; a4 {# i6 r- M
MCASP_RX_MODE_DMA);1 D5 w( K2 H1 r) z% q" Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 E. N6 R/ ]9 v$ W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' r; H8 z4 {# d1 |) {& J3 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 d) `$ w" @; l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 p; l/ V$ @3 q$ n- y) ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, x9 W( l, d! ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, ~2 K% P9 N; ^0 _* H2 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: r' v) U: Y( M( {2 E* yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
Z/ ]* i' a* L1 g9 H; QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" z% U E% ]3 O& t; y# s9 H0 |0x00, 0xFF); /* configure the clock for transmitter */
" e7 m# | A4 Y! l- t0 m3 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: Z7 v5 E! o! @ J' M) UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & n9 v" b% x0 }6 c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& V: x3 ^4 d7 o7 v' q2 U
0x00, 0xFF);% k; |# r4 `+ f$ m$ X
8 |- b. H. U3 C# W( K2 f$ B2 d* |/* Enable synchronization of RX and TX sections */ : B4 P* W$ h8 T& h. ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# L( l* t7 Z. v. gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 B$ |$ m* i' \$ v7 t4 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( O/ s1 f$ _' @3 _** Set the serializers, Currently only one serializer is set as: u3 \1 m' y4 h( g) b. P8 V
** transmitter and one serializer as receiver.' o4 ~0 V1 D# n* o* S
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- H, j6 b* B; K8 H) c% J5 P+ g" `0 z- GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' ]8 V/ \& S5 ]- u% e** Configure the McASP pins
% |6 K2 ~" D7 |7 P' d: j** Input - Frame Sync, Clock and Serializer Rx
: F; T, M5 e) s1 A h ?' ]** Output - Serializer Tx is connected to the input of the codec
" v- K" n5 K! m$ V8 r/ r' l*/* t4 g- H3 J0 {7 s+ J% D! v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& P5 W6 d7 Q4 t1 p1 p9 b& l2 a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 T* H7 R. q( o0 e2 S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ p I9 v( j6 N& A/ Q
| MCASP_PIN_ACLKX' F+ }+ ~* @# \2 K t7 U3 O
| MCASP_PIN_AHCLKX9 H6 N$ S) Y3 j# a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* o( B: l0 r* D5 H$ }$ Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 a1 d: E" Z9 T7 u S i: o& b
| MCASP_TX_CLKFAIL
( g* M+ ]# R* K) S) A4 B- ~ c| MCASP_TX_SYNCERROR
. |: h7 [- {3 ~1 O% v1 a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- D0 U" `2 p% B, A# A. R$ G; g. s| MCASP_RX_CLKFAIL
; J0 G8 D/ D% n) d: s: c| MCASP_RX_SYNCERROR 0 ? y: z X7 n$ I
| MCASP_RX_OVERRUN);3 t# |! P' |. x) U$ t
} static void I2SDataTxRxActivate(void)
` c* ?( v; v) n{) x0 o# \4 J+ j& p. u9 P
/* Start the clocks */+ {. g7 Y# t$ [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' h8 [& _4 l2 Y& h% t' B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( |% i) Q: [2 d, b( N# x3 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( o8 h5 E4 D& n. R2 AEDMA3_TRIG_MODE_EVENT);
. e+ g) p( N0 T; TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( c# B% z! P6 R& O7 D u, i ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 B; X- {5 Z" Q( b# s9 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 Z- \! Z; ?; p: }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ C+ _2 A' }5 Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" m) A4 d1 }7 _# tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 ^. T* H1 Y. h! ~' v- ~4 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; ?' n8 ]# W y, _' _+ u u: ]+ O} 7 ?/ e( }! g/ p: S. _' L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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