|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 E8 H1 `- d# O. B5 ]( e6 g0 H3 l. x
input mcasp_ahclkx,3 N0 j9 C/ D" i* A
input mcasp_aclkx, z0 v$ C/ q! ~% n
input axr0,
( ~4 B) Z9 M# ?7 a" `9 R7 N4 S2 k* l3 B
output mcasp_afsr,6 }/ d# A9 z9 [ K1 S# q& _
output mcasp_ahclkr,$ ]/ m3 v1 O" r) v, k% \2 K0 R
output mcasp_aclkr,/ o+ H6 b4 \8 B9 v2 L' T9 @+ [
output axr1,& C: {; E' M9 _) y0 c) M
assign mcasp_afsr = mcasp_afsx;2 S- H4 K2 S; T
assign mcasp_aclkr = mcasp_aclkx;
7 D9 S$ R; ]" H* D5 e6 uassign mcasp_ahclkr = mcasp_ahclkx;
2 Z4 c+ B2 A+ f& Aassign axr1 = axr0;
" g1 p. Q2 t3 A) m$ Y
9 W3 E: q- ]# X4 a: n: t8 V: D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) K& D1 S! t, E- I2 E- I6 sstatic void McASPI2SConfigure(void)
1 @$ S3 V) a: N9 ?0 V4 v{
: {' t# c* z6 q3 e wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' B7 l- I( W1 D* ~) m6 A& A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: T4 ?/ q' l3 e9 S x/ |3 o, b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 @9 r% u! A( b. s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; S3 i8 _+ G4 \; {/ }3 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( t! b% X9 m! ~$ lMCASP_RX_MODE_DMA);
! Q; V3 r% `) |4 AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," w# K: w" D5 t, q1 \9 w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ L9 I" K$ p, f: d8 p( I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . W9 P2 l* D+ `( g0 [5 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" _' z) w' T2 t6 |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- h7 _+ F8 n% X3 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 P" `, s& Q# C; DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 x" p3 k* q: i, y) SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, M% d$ h# u/ TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- F* q2 j& u: p7 _* L# Y
0x00, 0xFF); /* configure the clock for transmitter */
3 y( M6 `3 [7 b: o$ t t2 lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ H0 {. Y: k G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ j& z8 V/ |5 }3 W2 S& ?( }7 Q9 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
V4 g* d& i" p- B0x00, 0xFF);
0 B7 d" g" f9 x% x7 I; N6 b3 `. i7 U# P; ^
/* Enable synchronization of RX and TX sections */ 0 D& J3 y6 g! {6 w I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' [% C$ y3 o6 wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. l2 ^9 y7 f& \: J4 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& [% V( d2 Y/ \% X) ^' a1 \** Set the serializers, Currently only one serializer is set as1 ^# n$ @# Z+ X, j- I/ C. M) [0 O
** transmitter and one serializer as receiver.
( J, r2 o7 d2 K+ m+ e" M. X9 {*/
% Y8 j+ X" a. y( GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 D5 i' {: C+ d* m5 e2 N6 ^6 {: N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 G0 X! t: \" {: f
** Configure the McASP pins
' D& v1 ^7 q, b. i/ B D" f, _3 i** Input - Frame Sync, Clock and Serializer Rx& h$ U: m* W& d1 i# p. F
** Output - Serializer Tx is connected to the input of the codec " [5 e( }8 S1 g* N' ]
*/& ?$ r3 v+ r0 N0 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ T2 p' ? E* A& B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 S; J$ J2 S9 f# ]$ x" AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 q3 N' q/ ]/ E
| MCASP_PIN_ACLKX/ [6 Z" V! m! A, U! c. |1 o
| MCASP_PIN_AHCLKX
5 G! K8 F# O3 e `, d: K1 ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# `2 l( g) M8 p) d3 J! {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" M, y" b: d, N6 T1 B N5 w| MCASP_TX_CLKFAIL 7 Q, O2 i+ Q! J3 ?: `
| MCASP_TX_SYNCERROR" `# i7 H& j$ g. q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 c# s9 ^6 s2 v- \7 w5 l
| MCASP_RX_CLKFAIL; j/ X6 H; g! ^+ p
| MCASP_RX_SYNCERROR
0 j: `& O# U7 d, ]| MCASP_RX_OVERRUN);
% s8 Y/ s4 R3 |- N C} static void I2SDataTxRxActivate(void)$ X, N' k, ~% B8 M
{
% N- E5 G/ N3 X8 d X! }/* Start the clocks */
$ Z6 j, h4 p7 }! H# T+ N: KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 @5 w! _2 s; c2 i( t& h. m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" t0 [4 P& L, _: Q; Q' a( eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- V+ ?3 v' B% f6 zEDMA3_TRIG_MODE_EVENT);& B) u- o, P2 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , ?0 o/ V/ m: `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 S _6 B# [ |8 e( wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 V" y' r1 v. t( e. u3 K; W" I: SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: j7 m0 D K! I2 ?: lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. g- O. l0 K5 V( @+ W) F zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 t( Q; B& X j1 P4 i% t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 r l+ g- ?: C$ g& K" B0 i} % n. L- I. p5 ?1 b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) @5 Q5 w2 \9 u! o9 a; Q0 m+ E
|