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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) m a a7 O1 N) V6 c; Sinput mcasp_ahclkx,7 m! I, d$ f$ R8 K. |* z8 h
input mcasp_aclkx,
! \& {) Z( _) _( uinput axr0,
|* e l: K/ K& a( {+ E) e: S: B! Q" w8 \6 I: e1 p
output mcasp_afsr,
8 k3 c! k3 O! Q8 q( E0 ~/ uoutput mcasp_ahclkr,& B5 Y3 q. ^; ]
output mcasp_aclkr,* C/ {/ }) V" w' [
output axr1,6 R9 t3 c* B; n4 a
assign mcasp_afsr = mcasp_afsx;5 s: h& e, _" H( N! t" P
assign mcasp_aclkr = mcasp_aclkx;1 L+ c* c) C( W
assign mcasp_ahclkr = mcasp_ahclkx;( }$ k& G% ?( q" j
assign axr1 = axr0;
+ }" v$ `/ [0 T
( h8 a# |/ g5 [9 U: M3 ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, o1 d# ?' m! H, K7 Z7 N( tstatic void McASPI2SConfigure(void)
+ B7 u. n9 }1 Y{ E5 U0 I) C" K+ r! F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 u+ J1 S% ]2 w$ \7 W( q0 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% D: [% P) r2 h# X4 M- @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 Z' ~% k3 B+ o( n, m$ ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' C f, i" y# N( IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 d; q! J0 ?0 k" |MCASP_RX_MODE_DMA);
8 E5 G! [4 F2 o8 lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 b$ g! M4 M3 E% t7 K" d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! A; @3 B8 `% c4 N( J6 N* o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 B4 r* A$ d, y4 _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 Y: O L& A! Y0 u; d1 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 k `8 F+ S7 W+ u. Z3 oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 j# B6 Q, x+ ]' t) BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; ?4 D9 Q9 ]3 @# H: ~ b5 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 i: c6 v+ a1 D$ v+ @2 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, s P& g/ f9 u3 Z2 }# h6 W: [
0x00, 0xFF); /* configure the clock for transmitter */
& e$ L. I5 z* [) q9 MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 M/ @& i' h8 a9 I% _& [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 l1 F- O( e FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 c. Y0 E+ r! h% \. M0 s5 o0x00, 0xFF);
4 z9 [' C9 `! o4 ]3 [: {% D) @' c; p, p
/* Enable synchronization of RX and TX sections */
3 v* \4 H0 \% ?, p- BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, u' ]# g+ t- J: x9 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( Q) v3 `4 T- H, d* [8 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 R* T) _$ P7 p0 g
** Set the serializers, Currently only one serializer is set as
0 ~) }9 f. O6 q4 h7 f' J** transmitter and one serializer as receiver.
E/ B6 e4 ?2 r* I7 O*/) M K7 c" [- _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* y5 y( o% U! k: [) q! b) w- BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% B x& R/ |: T2 b% p
** Configure the McASP pins + s( i% l4 P+ g- t& b
** Input - Frame Sync, Clock and Serializer Rx
* C F* s2 R& U" W7 a- S; |+ @** Output - Serializer Tx is connected to the input of the codec
* W, Z8 K1 ]! k* n8 S& D3 \*/+ v/ z+ I/ L Z" c+ @) v3 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% E: p9 \. l9 q- ^& r) Y. p/ d2 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ x w# P- k9 F; z+ {$ E6 V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, ^5 R& R4 o. B0 J7 e1 H| MCASP_PIN_ACLKX9 v5 N3 u8 _! |2 C( e5 M6 f9 S# r- t
| MCASP_PIN_AHCLKX( M8 Z$ t; z" j; e8 K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. P! \5 g* a& S3 e$ ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! j: p, w& D, J. ]
| MCASP_TX_CLKFAIL
' d9 k, S/ A1 y9 i+ y: v/ Z! y| MCASP_TX_SYNCERROR
+ {5 j: O# i, R# ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ C+ S) O6 I0 I, j! {+ ^0 k0 B| MCASP_RX_CLKFAIL' x+ O' q/ h- D/ D) R9 c
| MCASP_RX_SYNCERROR
( Q3 F: L3 J4 P2 J| MCASP_RX_OVERRUN);$ u" |2 x$ s, L0 O
} static void I2SDataTxRxActivate(void)
; d# l4 Y/ w# f( p- Q. V{& I5 ~6 }3 I3 p+ [% s0 f. c6 z
/* Start the clocks */
0 W3 |: a6 V: B- Z; cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* D; L8 ~$ S5 a; o3 E) G3 V9 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, \! k+ F r' G( C fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 C- y1 X. o( F; z0 _0 TEDMA3_TRIG_MODE_EVENT);
5 u, M( a* z3 ]& U, `! Q9 ^ R/ mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 z0 h% Q1 |& _9 Q$ ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. h* y' s5 @' ?5 f, E: fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, N/ T5 m! k3 ~* U& ~2 Q& I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( }" ?7 I2 ~- W; E, |4 G$ J/ Q, Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 U6 m: x; G/ p: n4 w2 R2 LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: l& H3 r3 F7 y; |5 c* OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- r! h7 H: c' a: B3 q( F: M( Y
} - d$ ?* @5 X/ ] u, X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 E3 Q, A6 m5 n3 U; ?, Z
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