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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ }6 W( K4 C7 p" U+ O- I7 M3 Cinput mcasp_ahclkx,
1 N* ]! }( d+ Kinput mcasp_aclkx,
$ W; `( }$ g* Linput axr0,, H3 I0 R' I0 D. ~- ^7 |$ W1 [: D
9 u. N0 }& w* g- o" O4 b
output mcasp_afsr,
0 S v' W; i3 G- G, F/ G6 U: r! c9 goutput mcasp_ahclkr,9 L3 h: g2 W$ z9 T- B
output mcasp_aclkr,2 c) D# b" h5 l$ V
output axr1,
" i) X, Y4 m) S% z assign mcasp_afsr = mcasp_afsx;
9 U$ S$ k5 a( F* \assign mcasp_aclkr = mcasp_aclkx;+ @# C( A! k: r
assign mcasp_ahclkr = mcasp_ahclkx;. u8 n( |+ K: K6 E* d- R: u
assign axr1 = axr0;
4 C0 T/ i( g- @& Y3 S
) Y: S) `; R# P @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 c" [0 m) p6 P, k5 ?static void McASPI2SConfigure(void)
5 m8 k; r3 e# U1 b{
& }$ X; k: M: l: h R2 r; l6 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 A1 t& l4 q9 Q( c8 q0 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; {3 j9 z! n5 X5 a$ C7 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 o4 ~& I$ I0 k+ r7 n3 |& N( b$ C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 q( b4 R/ h5 o/ W) d/ M7 G- EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, q4 _1 m9 Q, A. r! V
MCASP_RX_MODE_DMA);& X. C, ?$ ^. k8 I9 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ~ A: Z/ D. S' h2 M) |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// e) z8 w# I, m7 p: P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - g" ?. f- C" V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, H* y/ o5 ^ S4 X! L; ~+ {/ hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * Q) B0 q6 \, g% f. Y% W- a4 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 X; y5 ?! Y. n6 g ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 u7 h5 G' ~# I) ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* t( g1 i/ ^6 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! P; q- [% X1 f0x00, 0xFF); /* configure the clock for transmitter */
3 E' i6 C+ x" {6 F3 n( K' ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 t1 e# r: M, I2 e P) O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
f* }4 |0 D/ }) t! u L OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# [. ~. t6 S+ b
0x00, 0xFF);
: q+ o9 T# O2 o; K c6 M- a
4 Y7 `: ^: n2 }/* Enable synchronization of RX and TX sections */
! y4 p2 r. i6 w: D9 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ [- K# a: P6 ^% j% `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: J5 Q7 I3 n7 a1 l, J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: {, v w3 \. _ L+ G
** Set the serializers, Currently only one serializer is set as
' }! I; h- [- Q; u8 I: s, X, T. W** transmitter and one serializer as receiver.9 m6 }6 l6 C% M) E* j
*/. t0 c: Y" |( v& j; f+ A/ B* P0 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- x1 k/ \2 j% C6 w- n' nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. a* Z( d7 h4 r; V9 W' |/ @
** Configure the McASP pins
% n' s; p: o, I; F- e, F, h9 _** Input - Frame Sync, Clock and Serializer Rx
% v( {: \5 R+ w b& _** Output - Serializer Tx is connected to the input of the codec
: J" k Z' |: ~4 H8 _# y& K. j*/
& n8 ^; ~! w+ W$ wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 H s: ]. r) I2 O% E9 H1 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. k' l! X/ c: @1 @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 k0 r6 S. S1 M+ G2 w, t- [| MCASP_PIN_ACLKX+ ?* s* u+ ?; l
| MCASP_PIN_AHCLKX
+ ?& m* {2 C' m: `/ W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% Z9 p6 J: p- C5 X& m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 V) O+ x2 ~6 i5 K/ ?8 ?; k
| MCASP_TX_CLKFAIL
; q% {) W) a9 I: y# H| MCASP_TX_SYNCERROR: W6 B( ]& B z, E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- Q. }" _ K4 g' B3 [0 || MCASP_RX_CLKFAIL' s8 }- Z, P3 @* h. y0 P
| MCASP_RX_SYNCERROR
9 g4 l- z9 M1 Z3 Z- O0 M| MCASP_RX_OVERRUN);
- y5 C$ i. J+ G2 U} static void I2SDataTxRxActivate(void)2 q( }2 |0 A( O! l4 P; n' q
{5 H! K0 x& g6 Z9 g1 ^! z. P
/* Start the clocks */
; M$ }' `. s0 X" ?- AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, ?6 P: G1 z4 t8 v' N3 Z/ UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ m) W9 A! p9 C# e% p' B5 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& y% U1 g1 X8 @& n c; OEDMA3_TRIG_MODE_EVENT);
! E: j$ j0 B! c# [" YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , N2 ~, `6 ^' Q0 k. X( q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 E1 Y* w! x5 H) U j0 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* A! \4 o4 s. f: @5 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 Q+ T6 |1 k: S4 J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! ]3 c0 @3 |4 K6 K0 O: B( @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. F3 }; i `$ t0 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( @1 t; n& B- z- F4 m7 w( H
}
: Q: y5 R. W: j L# O! J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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