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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# a3 l; @0 h5 M$ b* g4 s
input mcasp_ahclkx,' m7 ^4 L7 q2 t" N9 P
input mcasp_aclkx,
% t: j, l2 ]" \- R5 i0 ?2 pinput axr0,
# k! j$ t5 t. l8 X
1 e3 P# j- m- f* q; D+ D' A1 {/ Moutput mcasp_afsr,4 A6 f) `0 L0 c3 X; Q
output mcasp_ahclkr, ~/ @# j5 p* Z7 U( O. k- a6 |
output mcasp_aclkr,
2 W5 q% J1 x1 ^: S( Z$ R9 O, {& ~output axr1,% f% v0 Z6 p k" Z; U; o* Z1 I
assign mcasp_afsr = mcasp_afsx;
0 f/ k7 @* j- O; H* G% v) t( Hassign mcasp_aclkr = mcasp_aclkx;
: p9 D/ E: R5 {2 ]assign mcasp_ahclkr = mcasp_ahclkx;
0 y5 E" O% l$ {3 E; fassign axr1 = axr0;
+ ]% {3 Q% Z1 z7 E1 v7 V: a
( R1 g. ]9 V9 g" y9 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 n) J, G5 _: \% F# C3 zstatic void McASPI2SConfigure(void)
: O; H: Y( z' m) d{
9 B$ K1 T0 \2 h! X, T/ GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 @ [8 G# I1 e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 n; f4 j' j4 i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. v3 }2 b4 X L- ~8 o7 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* O$ u' }1 K9 D" ]) w' RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ r3 I1 m0 b8 Q0 F4 B
MCASP_RX_MODE_DMA);- Q/ l4 O' w v, K, `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) x- [9 X- U. f0 w9 hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! g$ ]6 E C! AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ E1 j/ c, q) J8 FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 G( W6 a9 S" w6 @, gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : C ~" i1 d8 r- u" ^8 }3 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ A! B1 i$ }$ i! [8 L, M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 d' g: O# {6 x5 l1 p5 m8 F* Y+ U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & B3 N, l6 s/ A m% y9 g) C9 K+ p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
C6 x. O* g9 Z$ j. ]/ d0x00, 0xFF); /* configure the clock for transmitter */
) j& q; m. s3 S) R$ k( cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; {" t& @% K1 w9 q& r0 d* a1 eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( q5 J3 {5 ]( X0 U, i9 q+ J/ ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ a1 F- |) ]7 ~% q# [5 k
0x00, 0xFF);
$ j- w) [3 }9 ^8 d: [; W
( t- t! f+ V- I! j5 {/* Enable synchronization of RX and TX sections */
( E* z; u8 Q; @4 p1 _6 VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! D+ @& j, A' @. sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: i+ i+ I5 r* WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: M/ `# p5 P, f1 x; g
** Set the serializers, Currently only one serializer is set as
d @1 E' w V/ c+ d9 k' H" P5 ^+ D** transmitter and one serializer as receiver.* n( b4 ]$ D! Z& V
*/6 K3 ?% |! U8 s' a2 a& `& e0 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ a, \' t7 x2 y3 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 i* Q5 e8 q% w
** Configure the McASP pins : e' m, r& c! k9 Z/ P8 i( z4 X
** Input - Frame Sync, Clock and Serializer Rx
. B+ Q: w; T& q4 N9 F& ~/ ]** Output - Serializer Tx is connected to the input of the codec
% a! w2 S. J: B2 Q8 ~( D9 C( C*/: E( q: u# I3 P. X# {) B6 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; a: G) e' T) ]9 tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 K! k9 f: b, S8 U' ]. ^7 j2 c" cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# I/ A& O4 Q& l$ b+ f0 y| MCASP_PIN_ACLKX" M. ^3 Z2 |) g( n) C+ r4 Y! @
| MCASP_PIN_AHCLKX9 i" r' q- x: P# z$ d9 e$ \" x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- a; N5 I% Y/ ^) o; C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR h4 |3 t7 l6 m: s4 H
| MCASP_TX_CLKFAIL
$ L+ Z9 D5 |4 Y* Y$ V| MCASP_TX_SYNCERROR
0 k2 _& O) e8 d9 @, q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! R, B) w; ]0 x+ S6 ]
| MCASP_RX_CLKFAIL
- _1 k# [! [0 t r" ?" |5 ~- _| MCASP_RX_SYNCERROR
% T. R4 \6 z3 J/ W6 e) ^/ s3 F| MCASP_RX_OVERRUN);
7 L9 u1 O, w3 `, X. b3 d9 }} static void I2SDataTxRxActivate(void)
. I4 w) c' ]; z4 G- _% x{
8 C5 o* Z. J- z2 p8 P/* Start the clocks */
! h0 H o( j0 T8 p8 w2 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; N8 T" C, r; M7 Z5 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- D; ]: w% s" y: h& ^$ \; B& E7 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 j3 |1 Q' X" i0 q& R# q2 f
EDMA3_TRIG_MODE_EVENT);
2 \( a- N# m; U! o; r JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, u* r* h$ k5 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ H* l/ Z( ]. \2 x: V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 ?0 w* Z- {$ c' I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 J; ^% s0 k a' d3 [. M$ N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* i8 t5 B) N U M/ |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; A b) w: a6 P5 G& I- j2 F& NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% Z0 H& Q5 }6 [! D5 j
} * d3 k, K3 h; I _( [9 o8 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 n) d* t+ A. W* s$ C8 \) P
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