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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( e/ b: q! l3 @# u! A1 a( Oinput mcasp_ahclkx,4 P& r- w! O; i" N
input mcasp_aclkx,
8 T! S! I! \+ i" _, j7 A2 v; Winput axr0,
9 \& m7 W9 U8 Q* }. l. L: T; K- a3 j2 T# b% E& F, C1 T) I" _
output mcasp_afsr,+ W2 i2 [6 y$ `% h
output mcasp_ahclkr,5 _& z7 H7 l9 k, R& O4 A! | Q3 y
output mcasp_aclkr,
A5 c( V& I2 _( q( J' b! Aoutput axr1,$ t. L/ V- q5 L; w7 e9 t& x# O7 |& m7 [
assign mcasp_afsr = mcasp_afsx;( n: Q+ e! y* k- {( B0 y1 ~
assign mcasp_aclkr = mcasp_aclkx;
) ]! k4 u3 @+ c. [! l c ^7 Sassign mcasp_ahclkr = mcasp_ahclkx;
0 l7 ~; E, Y6 N: P6 k( ^# yassign axr1 = axr0; ) M1 b; k; S6 ?+ D
F5 U" J. f9 O' K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 X* T% z- p* g9 Y. E( w3 ^
static void McASPI2SConfigure(void)
% ^6 H! V1 {) y4 {2 }/ B. D$ l2 t! d. g{0 i: z3 x) A' `9 Q' w' u; }3 _5 m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; h5 P3 X0 e/ w& W+ DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
{+ ]7 ^. h: x4 T+ TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. J1 _" [1 u" H# T4 J6 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! J: |1 ^; U; k5 l" Z% LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# \4 l8 Y9 H9 _) \% nMCASP_RX_MODE_DMA);4 N! G7 Q# H- \/ V/ g5 m# N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, R1 B" K. j E6 C/ f7 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ e! x/ B! c \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 T* r1 o4 L& a7 @& EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 k* v9 |) d& {, \! T# Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 a8 ]& b% D, s# v" r7 s5 N2 w) n, s! V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 {) v( e2 m7 r- W' a4 g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( i2 Z. P" _9 o' n% S K3 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 ^4 B: y. U, F; j4 A/ h" ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ m7 X/ w6 ~% [1 V* l6 B) m0x00, 0xFF); /* configure the clock for transmitter */
( G2 O* g' z8 l5 @* fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 y X( E/ j8 r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
s( V7 M0 b& [: B5 GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
f5 {; g5 t, R2 M: {* S* [4 z3 d0x00, 0xFF);
/ g! O R; H) }2 P( I
$ `- ^3 S# i0 c. h0 n* r* }/* Enable synchronization of RX and TX sections */
) T+ h, H/ \+ C! o4 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- A G4 K- s" E+ N3 d4 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 C! p9 N) M% c% M( iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: z3 f0 J4 K! ~# u/ [** Set the serializers, Currently only one serializer is set as7 p3 I; I. t6 q1 {# S4 y, D+ i
** transmitter and one serializer as receiver.
& }+ @. `9 |7 E9 m$ x- t" ]*/; F. }) F2 d) X5 n8 ]0 u4 O" F T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
\5 P8 e, H( j( j FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** ~- g& b0 L4 G5 e
** Configure the McASP pins 5 x& G3 C- }* B$ a2 d) s3 L0 g
** Input - Frame Sync, Clock and Serializer Rx
/ V4 k0 F+ N. K! L# q** Output - Serializer Tx is connected to the input of the codec
$ G0 a$ M2 Z; W' Y* x; k2 r*/" S& Q' {+ h' f6 d/ c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 N- n' ?) O- W6 V0 ?; iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" T! ]9 q" Q4 TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% H% `( c9 E4 ]# t6 g| MCASP_PIN_ACLKX
& ?6 a9 W- q7 K* F3 h| MCASP_PIN_AHCLKX3 z: { X; b0 z/ G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" j2 `: t! F" o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! q: G3 C z3 h; ]( a6 x* L| MCASP_TX_CLKFAIL
/ Z" B* w. ~6 i! i) ?. K| MCASP_TX_SYNCERROR
$ N. D; d0 h+ E. Q) U, Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; q6 I& Z0 _7 B+ ]! N* S S- ]
| MCASP_RX_CLKFAIL
- K( }/ l x+ ?. W q3 _; c| MCASP_RX_SYNCERROR 5 J3 v4 A$ @* G8 [& J0 l
| MCASP_RX_OVERRUN);, t9 }" i0 n- E$ G
} static void I2SDataTxRxActivate(void)" G. Q+ x1 `, R0 K2 a4 X
{
- |4 w0 Z% A4 j, P0 S5 B7 T& P/* Start the clocks *// F3 i5 i% S* h7 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 `: E/ }4 P" J$ j3 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ e1 A, u" W+ |6 ?+ p. z8 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 I) i- b" T+ qEDMA3_TRIG_MODE_EVENT);
, O1 m+ C2 t5 g( q( vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 y5 I/ b$ x w0 V0 s- u2 Z( @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 D: k/ }- w; B& Z1 ?+ ^: l; {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' K# K: e% t5 g8 `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ E1 t4 Q1 \ m0 h3 V5 i! t& Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! |$ Z, F& ^: [+ f, Y# I6 S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, T" o. O8 o2 b, F! K. j6 a- J+ ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 T3 Y P' b! @1 Q3 Z} . T* J- g& c& K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . F# W7 g- I% F
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