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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, p" P: U2 r5 b! jinput mcasp_ahclkx, `* x- q1 L+ m5 ]: L& o- n% G
input mcasp_aclkx,
' U! l7 ~) L1 j3 minput axr0,
/ K# F; V H) i3 \& T4 P( j
; Y5 _& l5 X+ aoutput mcasp_afsr,
) Q; H e Q% O- Uoutput mcasp_ahclkr,3 e& D; e& X% c: c, p$ w! o' m
output mcasp_aclkr,
2 x1 v- B- t( Q) Noutput axr1,, j" _4 A/ O4 M, T$ |
assign mcasp_afsr = mcasp_afsx;
/ k# p! r+ v7 p" H" V& e9 sassign mcasp_aclkr = mcasp_aclkx;
; h9 q8 e7 \5 }assign mcasp_ahclkr = mcasp_ahclkx;: M* o$ H" W! K. r3 M, y
assign axr1 = axr0;
, W7 K0 y& G$ s
6 i7 `+ u* {/ U( M/ U6 s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) d0 }+ A% M K1 H5 O1 A5 {' V
static void McASPI2SConfigure(void)$ v8 t ?/ C+ R1 M- E7 ~7 ]6 c4 ~
{
2 }$ b% ?( p1 u5 K! Y) kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ k0 v5 K5 ^( T9 Y! V0 t5 t- nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; y! n8 e5 \- v% _1 ]+ ~* {; cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 `1 V5 Y: ?% k7 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- z* w4 P5 M' p0 w2 O8 k0 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% i5 p T. C4 C! M! i
MCASP_RX_MODE_DMA);4 _- X; i5 H$ ^ W% i: n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( N! s: n' f; g% }% ~. {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 |/ e, v- S# k ]9 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& }# h) o& z TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' v5 @) L5 a- I, T+ F+ r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 k' c' v* b' \, a7 GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 z7 d$ U/ s4 r0 k4 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); Y" e8 r$ ~( d& B) F# j% d# h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 O8 Y) H- ~( H4 qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 l9 |& o) I2 F; H9 s5 T* x$ z" P0x00, 0xFF); /* configure the clock for transmitter */" p, r7 [9 m/ y3 J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 N* M+ @) n) `7 p% j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 D3 ^8 Y( y3 F, E& H7 Y$ m. B$ dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 K9 q' ~* X2 F- G7 J7 B
0x00, 0xFF);. T, o8 ]9 a4 c% N) g
( q5 T6 a0 h2 w1 M4 H( I0 L- z" r
/* Enable synchronization of RX and TX sections */ 3 i$ i" Q6 s6 u# Z; u% q( D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- a; ?8 n) z1 s# CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, d8 h/ x5 [' M( b* y& f& w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) R/ U: s7 ]; U" _$ s0 E; `** Set the serializers, Currently only one serializer is set as
& t4 L# k/ {; b A3 a2 ]4 U) h1 F** transmitter and one serializer as receiver.: E4 ~3 W" H% u* E, o: O2 Y& Z
*/
. o7 M9 [% ]/ J @: ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ ^2 r* C5 F; n, B+ k$ K6 QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: ]# @0 d9 K+ {6 o
** Configure the McASP pins
1 L" y! W: H* O' c! c** Input - Frame Sync, Clock and Serializer Rx
9 {! U( \, X& s. i+ z** Output - Serializer Tx is connected to the input of the codec 7 d3 X) B2 D# A6 N) _
*/( n" W" O+ U2 }9 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" s7 b; O7 _: mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* @% g- Q' Z' `' i( TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- a! O( l( [, ]$ d, }1 `
| MCASP_PIN_ACLKX
& m8 {! M4 V1 h x2 n| MCASP_PIN_AHCLKX% h( R* t0 B y* D. E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( G3 n- v* U' ], Y1 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ~& {& l$ @2 E0 I, J+ \/ P6 _
| MCASP_TX_CLKFAIL . ], s/ e) K, u" n8 I$ ^
| MCASP_TX_SYNCERROR
& _9 w- J( ^* w; ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) K/ T+ B/ f: x/ M
| MCASP_RX_CLKFAIL) J, c) J; ~4 `% u+ ?
| MCASP_RX_SYNCERROR " {8 g7 Y$ a- J/ w4 }
| MCASP_RX_OVERRUN);
( Z$ T: |5 x6 u} static void I2SDataTxRxActivate(void)
$ l+ q7 M2 M5 o6 k% m3 D{2 X: R) D+ o6 e
/* Start the clocks */( w1 X% b3 Y8 m0 |* u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; j6 B0 t- X6 i9 R3 oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 f7 U5 W2 m* QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 \ e- z( a' i+ HEDMA3_TRIG_MODE_EVENT);6 y3 m, A" l) T. I$ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ P+ Q; a: [( a' m- y+ z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& B9 Z3 D( V8 z8 K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) b! t$ {* d% h0 j0 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 i* b- Q0 K0 r9 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 a1 _2 Q) W+ l; d0 K, N$ c8 I" g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ @! F# G# x7 @" R1 N0 N& t0 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" r x: c. U8 Y8 o+ C; [3 G
}
/ ~; {* k/ h: e6 ~, L4 L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 y; h" M% W& L$ c/ `
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