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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 N, K# r4 {8 W0 Tinput mcasp_ahclkx,
9 H( N# \* U' U) s" k' b0 k4 finput mcasp_aclkx,: x. P7 W. Q! m3 y1 N$ T
input axr0,5 ^8 G0 M0 a0 T2 h: K* }
5 @" ?, m0 H9 Foutput mcasp_afsr,
" y5 w- E3 _% M5 r! ?" loutput mcasp_ahclkr,0 E/ G- p3 N7 p
output mcasp_aclkr,
/ W; h3 i* B* Foutput axr1,
+ C# S! O- F% A& R1 s assign mcasp_afsr = mcasp_afsx;9 A) B1 A, S! B, G
assign mcasp_aclkr = mcasp_aclkx;* [ z) U( p5 i$ s0 L# `
assign mcasp_ahclkr = mcasp_ahclkx;
5 v0 w6 b1 u/ ?4 D# i# tassign axr1 = axr0;
" t5 d- D) M1 \; t' s! i( [8 R: M4 ~7 p# ^" m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & b' g3 A* ^' l- D; V4 x! Z
static void McASPI2SConfigure(void); s) z: U) ?1 j3 M! V
{* _) e# o- }5 @; x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- h$ [0 ^/ z' v& S3 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 ?4 p8 C1 \; e9 b, @2 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 b9 Z6 L2 v- w* v- m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# e i. S! V. [! ]" X4 k, N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 z( I( }7 ?. `2 e; |MCASP_RX_MODE_DMA);
% t8 ^. Z4 I+ b; [" ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- ]0 f( H9 Y9 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: k J. q) T# [) M: q" a nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' ]) P' c/ D3 Y- }1 ^2 [! O3 _0 v9 P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; v; U9 |$ D. h( B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 i6 O7 ?; j0 x9 \6 M; U) ?% ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 Y# f5 M. ^3 d( ^; Y5 G6 j n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 C) P8 Q P, M' E3 D7 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & u. ?4 C# u' @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, U, ~6 e$ |. k6 S
0x00, 0xFF); /* configure the clock for transmitter */
7 d; @- N3 [% J% ]. A7 H( UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. `) K$ M5 u! b6 Q* o+ S) z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + b( q) ^ ?2 t/ v+ a4 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 x, z& ]$ K7 F; y& ?3 x; h
0x00, 0xFF);
5 Q* N7 L5 P; `% h% m
! n8 b$ L8 @/ {/* Enable synchronization of RX and TX sections */ 4 l0 W8 g2 A: F( y7 Y' o# Z# F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ s& ^; T8 L8 _$ sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ f6 N. y' A+ t3 d. f! M( @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% j; B* C' {/ a** Set the serializers, Currently only one serializer is set as {" q0 o: H, R" J" I! g0 H" S5 S
** transmitter and one serializer as receiver.
2 K3 E5 G+ P: j( b) R8 O& e, ^*/
) w8 O3 R U tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 n" {3 @ `# B n; s! B+ s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' g- |$ v) V0 @* `0 c" f2 Y3 [
** Configure the McASP pins + \! o* _7 g; M+ s
** Input - Frame Sync, Clock and Serializer Rx3 F2 W+ w- y, f! q: k
** Output - Serializer Tx is connected to the input of the codec ' u3 ~. v4 ^2 j6 `
*/; x5 r' a" j" ~8 L7 X D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 E0 `8 t, P' |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- s( T; \* s+ m8 X- H2 ^- F HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 a& j/ A7 |" q) I% L| MCASP_PIN_ACLKX
9 |! h+ F# y* K3 z0 d| MCASP_PIN_AHCLKX C. \# j* [+ K9 X J% H, N+ {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" K) u* p1 q: D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! G; p% H+ Q! x6 v4 [
| MCASP_TX_CLKFAIL
9 b, Q4 q4 E2 r) b F9 E7 q| MCASP_TX_SYNCERROR
; y3 e. E& a$ M1 b+ V$ v* X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# f) d8 X- q: F6 @( ?9 K| MCASP_RX_CLKFAIL' j- N+ ]: u, h% F- j0 j
| MCASP_RX_SYNCERROR
4 P+ F% M0 F3 [2 ]1 c3 }8 g| MCASP_RX_OVERRUN);
% {# O2 L, e7 l! m4 t} static void I2SDataTxRxActivate(void)
8 E V! t# @+ E/ K. x- B4 {- Y1 O{- F: G% K- [4 G# I3 Y# @
/* Start the clocks */! {3 D7 F% E/ d# S9 u( i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& U' D6 H+ @" V- S8 u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! s4 ]% W7 Q9 Y+ B' T, e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- D1 @& u, J( p
EDMA3_TRIG_MODE_EVENT);, h& J: f8 b" ^4 J+ t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # A. }: G k# _5 q; |" e; N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ P* @. M4 i" B! R6 H4 _, hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 q0 t' C! a6 t7 {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* G& q* Y7 e4 y2 X5 Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' `+ r9 o# M7 }! b4 A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 Z! J' J9 J3 W WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- |- [9 C1 ~2 y# T9 D% {
} % I8 }! v: `9 K$ z& C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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