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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
V( x) z v( T6 U! O; ]) H! Tinput mcasp_ahclkx,
- G- M, u0 {- ?9 C& \3 Iinput mcasp_aclkx,7 H9 g0 E( O6 n4 k7 G
input axr0, t" a% F% }9 p4 u
- f# {5 [; N1 Uoutput mcasp_afsr,
, I1 R6 j; v6 M& ^2 B$ T3 Qoutput mcasp_ahclkr,
5 ^7 \5 t! W- L) ?output mcasp_aclkr,
$ j! R' d& i- y Z+ t' moutput axr1,
! w! v$ b. A9 N$ s9 A assign mcasp_afsr = mcasp_afsx;5 g; T1 E( D! s0 \
assign mcasp_aclkr = mcasp_aclkx;
/ w5 c4 ?6 S, f0 W* `assign mcasp_ahclkr = mcasp_ahclkx;6 \% f6 C) R2 X2 H9 F* Y+ l% P
assign axr1 = axr0; " B. o' V" M* Z5 Z7 f/ }( D t
/ i4 R8 g' o) [3 h* ~3 N' `! W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 Q4 n1 v" n# W8 Kstatic void McASPI2SConfigure(void)7 Z) J; I i: D: ]" e
{# x4 Y% [' x4 I' c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ W; z+ B$ f( O; y& {4 g1 \% O4 jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! l( C" L. x! T+ PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 o: W( W3 g. D: b: ~1 M" l c6 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 `4 z o2 ~% J* o$ I5 L4 N, o. P- T9 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ s+ \6 X! n3 C
MCASP_RX_MODE_DMA);; e) |. b/ a0 n3 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ~1 g9 x, b3 I+ s2 {& S3 X: ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( m9 y& ^% A. o& X& z* t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 ^/ n, d0 @% v# I6 g. h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. ~( d. C4 M) D, ] UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ u) o9 w ]0 _- h1 rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 {) k$ D, y; t: ~3 U. ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 I) P& K" U& }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # X7 c# m! V$ A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 O z+ j4 R" Z% o. d: f0x00, 0xFF); /* configure the clock for transmitter */
6 {7 k0 K6 q5 x- W. [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: y2 k. V* ~' e9 E3 X. [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ O, C1 ^' g& m9 pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# p* M$ F3 m# J; m; {$ `0x00, 0xFF);
7 A: V7 s5 d) l x- w$ T$ K8 l$ Q+ _) ~! e" ~5 ?2 O& A/ L! ^# F
/* Enable synchronization of RX and TX sections */
5 t- i# p/ s: N9 T/ sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- h: m! b* l' n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% B$ f. w1 j. {# y+ o8 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# j5 K* I' I2 g1 q
** Set the serializers, Currently only one serializer is set as
7 d% }' w: N( g9 z7 Z& K1 v' Z! |" e** transmitter and one serializer as receiver.
) _7 c! L/ U3 s5 r*/6 Y" o9 R. w3 z. N$ |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( r7 ]# O4 B5 v% G/ h$ hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ h R7 C9 [' b+ P** Configure the McASP pins `* G3 g) {6 H' ]8 y
** Input - Frame Sync, Clock and Serializer Rx
' j2 r+ z- z/ |1 C5 R2 V** Output - Serializer Tx is connected to the input of the codec
. u9 R% n& M. ~ M% D*/7 X& D) H3 _% R0 H+ y) s: `+ p; c5 }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" Y: Q" F7 z) y, o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. L3 y" v& f- L* L* ?: W0 HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! `' y& L) x+ Z4 u2 a( z| MCASP_PIN_ACLKX
, j+ d: T7 H+ n8 l( C8 r$ F| MCASP_PIN_AHCLKX2 p% X$ |- u @. f/ W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 N& r. Z5 D1 s5 W" e; CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - f) X6 `* C4 |! Q! Y ~4 `& e
| MCASP_TX_CLKFAIL 4 l0 Q$ [. H* x+ Z1 F3 @
| MCASP_TX_SYNCERROR2 O0 G9 C9 e' ]3 }4 a$ q6 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " c+ d* e! T' ]2 |% a
| MCASP_RX_CLKFAIL
$ S6 ?& a( a" p6 O9 B8 }& B$ I| MCASP_RX_SYNCERROR ( O( h) q9 H5 m* p6 y1 D
| MCASP_RX_OVERRUN);
, r& x- n" b( V7 n} static void I2SDataTxRxActivate(void)9 Y% U% \# q9 ~0 F6 i9 A
{
- C5 f0 I8 ]' g/* Start the clocks */
& Y0 I% D* i* i2 s% x6 uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- W. i- I" h1 ` e' ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ O+ X! z+ n2 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 _' a5 i2 [, @% o- @( o$ h
EDMA3_TRIG_MODE_EVENT);1 u9 e- {7 a/ O5 t# A9 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( }. g! N" Z6 X( N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, [1 C V6 {8 y. d6 x4 N0 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# t- t% {; W* {3 n" p- OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ f0 V4 \# Y. q" F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ p" @2 ~ t: k- ]% I/ M7 ]: ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' b- }) X0 ^2 T* o6 o! ]5 R7 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ p' X5 V& z4 ?: u4 N
}
. b% L6 p8 n9 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. ~9 Q- V- E) R0 n& j |