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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 |- d9 ]; b A* A$ d. @$ b
input mcasp_ahclkx,/ Z6 e9 L4 y5 x( M! A5 c
input mcasp_aclkx,
9 o; W4 E Y7 C; }& M- Q! \1 J6 ^input axr0,
0 Z1 \( e N2 W0 H# L
; x* L$ O4 S) b+ x) M/ m) o: ooutput mcasp_afsr,
6 J/ A# H8 c: C5 u# qoutput mcasp_ahclkr,/ A: [. ?9 A: X- a/ Y
output mcasp_aclkr,
8 ]" e+ w- L$ ]: y/ b( g( Moutput axr1,- ]9 [4 I# J! T$ Q7 i- g
assign mcasp_afsr = mcasp_afsx;. v f9 p/ Y o( h3 [) |
assign mcasp_aclkr = mcasp_aclkx;! B9 d( D3 @0 o2 {1 P
assign mcasp_ahclkr = mcasp_ahclkx;
% i5 e3 G/ z# [4 \; [# j. gassign axr1 = axr0;
; E; ^4 r: t1 Y5 t" H( a
4 p0 s" S: \+ _% t; x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 I. X/ ]4 V% {) |) R3 S
static void McASPI2SConfigure(void)0 `$ c% ]8 n4 I6 r' W" Q! F9 [
{. @# `/ {3 c3 O% }, x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& s4 Z% n2 K( G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 N/ l5 O1 A: l* j) k2 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: d2 a3 B8 r3 HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ n" I4 W( w) W. j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; {! S, y$ L, Z' d
MCASP_RX_MODE_DMA);5 c5 }# M: _5 V0 @) B/ J* u% ~" @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 q2 E3 c. O) o6 l p! s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- ]% i) |! J: X( o$ {3 ~! ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% j$ r, t& Z2 Z% a* h. [; i- c2 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' j/ f( e% ^0 j* Q' M' W0 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % I" R' `8 |+ \7 {4 Y9 J4 y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 g) l& f; b% P; w4 ]! _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* A7 n6 e! \6 P. C$ L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: N$ a2 W# d( h# K' UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ |( A S3 R! b6 B' i0x00, 0xFF); /* configure the clock for transmitter */9 e1 y, W. j6 e, ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ W8 K( o+ @( k- mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , c% f5 d) ^- Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 B- L: V5 R9 \* o1 o6 V! N" `/ [5 s0x00, 0xFF);! R0 R1 h P8 p4 L7 i6 u
* L1 }' m% G- P+ f/* Enable synchronization of RX and TX sections */
0 B C. ?5 c" c, T( a: b( N; F: NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& }& u9 V' G0 E& o: {/ N! R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" i0 e' `- X4 v( {# N5 i! q! N- M: ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 J( X# x- W# V! e# S3 ^# R2 K& o
** Set the serializers, Currently only one serializer is set as
4 C4 V; J* n6 M** transmitter and one serializer as receiver.
- ^$ W& K0 ]% H7 [2 L& f* q# W; t7 D*/; i# Q, E- @5 W/ j4 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
m" p n e3 o: \& m5 |' q$ ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% m2 x$ \ K0 n6 g
** Configure the McASP pins
/ i# C4 s4 ? T3 O1 }6 f** Input - Frame Sync, Clock and Serializer Rx* |' q4 A6 p. i$ l( P( k4 d1 T
** Output - Serializer Tx is connected to the input of the codec
7 {$ d3 y& a" N! d*/8 I# X- u; Y( }4 M- H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' |( {$ x7 A+ z, D" x8 J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" d+ i; ?6 Q' v9 k' X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 ]' n4 F- z: |
| MCASP_PIN_ACLKX: Z2 `5 y& Q/ z* o
| MCASP_PIN_AHCLKX) s& I: f5 u! h" I4 n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% i* J; i& V8 y; L/ W$ hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " Z D! Z4 p3 {
| MCASP_TX_CLKFAIL
4 g; C" t4 N! I6 o9 v0 o| MCASP_TX_SYNCERROR
& p9 q- q) o/ R/ h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # A2 V# L# B# ?6 J7 [1 k/ m0 }! c" |
| MCASP_RX_CLKFAIL
, @. R& c# Z8 B3 ~$ K1 Q| MCASP_RX_SYNCERROR " F1 N1 z/ A/ d/ h% L
| MCASP_RX_OVERRUN);& w/ s- s j4 V, f' C, I y. Z/ m( E
} static void I2SDataTxRxActivate(void)/ }$ U. G3 @7 w7 j1 e
{
; O/ @8 P3 l; m8 t5 t" O {/* Start the clocks */0 H% N% W5 g* T4 K% B8 e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' D% s$ I i' {% t; I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* d: y! z" b4 g& h8 b, }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ ^9 V: i4 w; S# r
EDMA3_TRIG_MODE_EVENT);
6 W: G% |$ H3 {3 n TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 N5 A3 M8 I! J$ x: C: L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 C/ Y$ R4 z' j8 \" }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, [8 L2 M, ]6 {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 T/ f8 V7 c/ \* b, U. Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 }; _$ ^ J, S* r( ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% P! x- k# \3 \* B0 D. _- z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. B$ N+ l- U9 b$ c# L}
7 r. [- N$ V1 e3 t) H3 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - ^$ d3 c+ x% ?: A; C% z
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