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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; C& K+ d! q/ k0 J. w& E3 |input mcasp_ahclkx,7 X3 h* F- B& M- B- t
input mcasp_aclkx,
% H, F; U- W E4 T- i3 F4 T- qinput axr0," f2 I2 x! f7 z: m5 L8 J
. W/ t& Q# S+ z* X$ Loutput mcasp_afsr,
( a+ v2 }4 x! t- t, _: ^* routput mcasp_ahclkr,
+ D* H) n' B* J+ r; F% Goutput mcasp_aclkr,
3 R' |3 Y' h$ n+ eoutput axr1,6 z, Z: X0 S8 ]6 E
assign mcasp_afsr = mcasp_afsx;
3 W6 P0 L1 l( E, R' |; [assign mcasp_aclkr = mcasp_aclkx;
# @% O; H v3 B4 [assign mcasp_ahclkr = mcasp_ahclkx;
3 [) f. z! O G1 m5 Y7 ?& Yassign axr1 = axr0; Y- |& \ p$ s
- d; c- b z o7 X) ~! V; x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 }! o2 @4 ]& B6 t( W
static void McASPI2SConfigure(void)
" R z+ p, p' \8 a: {0 N. B( Q* Y% \{5 Q7 i2 ~ B6 b, x# f2 P; o* ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 J* p% R, h+ U1 d* a/ \8 fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* @+ u9 z1 _. N3 ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' j7 I! G# N4 y+ G; AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 c5 K9 Z3 o G4 `% w. d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 {; `5 Q2 [; w
MCASP_RX_MODE_DMA);' g/ O& L9 j! H/ T& K- p1 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: {8 z" m8 t. R! a6 r: uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 D" \, p j2 g# \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! ^1 r" m4 A9 jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' @( b! O4 _' Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) ?& r. H! L4 |6 m! U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 S; d; x2 w6 X/ {2 r8 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: P* J, l3 B: ~4 `! z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' x: u6 n; I! Q' ^! j3 R: h% dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% ] I* N" C$ A- K) z, S+ e p. N5 g
0x00, 0xFF); /* configure the clock for transmitter */* V Z0 s C, N5 s. j, L$ f9 C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 p0 M# n5 j( f+ X) @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 q- b w) O& [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
U7 h' A8 R4 Z; R0x00, 0xFF);$ g' m: x' \. I; k9 q2 F, k2 M
# T7 Y5 k+ V- l( t/ i3 O. k/* Enable synchronization of RX and TX sections */ Y1 `% X, _5 ?3 ?+ h- [4 Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 v0 K ^" f A9 i' o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 B- m; S5 L" a9 G# pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 |+ f# d9 ~6 r3 }' Z5 U** Set the serializers, Currently only one serializer is set as1 K/ R9 U) Q$ F/ g4 c# o3 I
** transmitter and one serializer as receiver.! w% J( _' m8 U8 n; O m( d7 n
*/+ M9 p7 C/ i8 c/ n& P7 X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ }# S8 y( ?! h. X1 U+ M, N K5 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ }4 `7 B# f0 W# P& ^
** Configure the McASP pins - v& W$ x8 P r+ i, j. C/ [! _
** Input - Frame Sync, Clock and Serializer Rx8 z a' \9 k9 J
** Output - Serializer Tx is connected to the input of the codec
: ?5 G; [9 I/ l" u*/! U" E/ M/ [8 [" a% H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 w. l: b N* i2 \5 m* b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 \2 m3 e( ~" l6 D$ K9 T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 i% h( k/ F* B8 A| MCASP_PIN_ACLKX9 b8 b& m2 f d# s- I
| MCASP_PIN_AHCLKX6 U$ o( ]; D! v8 @$ {" v+ |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( J% s% ~! Q' J& E) b8 M% ?0 |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / P8 Y) E& E) D/ j4 B4 X
| MCASP_TX_CLKFAIL % _* x/ C" p) o3 g3 d
| MCASP_TX_SYNCERROR# ]% h$ L! E; K6 A8 b- Z$ e/ [& K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 m2 e" C3 f$ ]8 q$ P
| MCASP_RX_CLKFAIL( E7 h4 V, | T0 Z
| MCASP_RX_SYNCERROR
; ?, ?- h( X. n4 e5 ~8 A| MCASP_RX_OVERRUN);
/ l! K5 H% o3 k. b! L* Z k \} static void I2SDataTxRxActivate(void)' X6 d& ?! F4 w5 @' ^* N! I
{
4 c/ T- |- v8 _% `3 x: A: B1 X/* Start the clocks */8 l- V0 v0 v0 X, v/ |0 }# K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 h+ O# R: O- W) z4 w3 N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 ^6 k; X/ w- J& P" F# j5 ?: D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; g) w+ @, u) a
EDMA3_TRIG_MODE_EVENT);
0 [* c% ~+ j& d5 P. yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * D; A: R1 l7 Q6 j: ?2 g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// e" C3 r6 Z( r* Z; X) B' r6 z2 K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 G8 l0 M! d5 Q; h4 n- B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" Z% n4 |/ S+ E5 b5 M7 o: ^$ \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" U0 F; j/ L+ V- J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ F3 X O8 N B. D' |- y+ Q9 b- k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: D9 i% [5 X8 H3 K: ^" o# x
} * I b$ @- _! Y* ^* I2 b7 F1 ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' {% _0 W0 y k) L3 K( B
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