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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 l0 E9 x! Z0 d. A
input mcasp_ahclkx,+ }7 {; u% k8 w- ?: z$ T5 D3 V/ S* v
input mcasp_aclkx,
" C1 b6 q. r2 } O1 _input axr0,
2 a' @2 y0 a H+ g, W8 t* Y
1 ~" O) Q! |$ z* l% r! ~) v% k& doutput mcasp_afsr,
- g: n# M x/ [ Z1 @- u" foutput mcasp_ahclkr,( o. [) K0 O" _. K' S. D! E$ z
output mcasp_aclkr,8 E6 S8 u: o& y! n. U
output axr1,
' C& @) t7 R! {% L/ `; G G7 y assign mcasp_afsr = mcasp_afsx;' W$ F" d5 R8 A- S' K* [" Y
assign mcasp_aclkr = mcasp_aclkx;
5 S% R; l: o* R% ^) {2 Aassign mcasp_ahclkr = mcasp_ahclkx;
# c1 q3 Y4 I, P4 jassign axr1 = axr0;
$ x8 z1 t2 l& n* C/ [! K& g# A; B/ ?% m, N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 n+ r7 h' U9 S( H0 V# G7 Y! Qstatic void McASPI2SConfigure(void)
+ {/ l) z- h/ q$ }' q! ]{
/ g( C0 P/ g: B. J6 j% fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 l7 p) m/ X" ]' W9 ]3 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( k+ {; u/ J6 p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 ~% T! p& M$ P- e0 y* ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: D, O; w; k$ F- CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, U9 l) i- a3 h7 I* h, r
MCASP_RX_MODE_DMA);) O* w5 L7 r m. Y8 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 E* g7 X$ y3 o+ }$ }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 Y# P% c" [1 d7 n( ~+ sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / H- Z& e; q% @7 P, z! I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: w5 B! y/ Y R) D% nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , o( U0 t0 z r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* E% v2 l& u& w0 x1 f; }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- f, Z- c& x6 i. _4 u% WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % a% H) Q' H, x* t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 p# b9 Z4 F, V& D2 p
0x00, 0xFF); /* configure the clock for transmitter */
& m# O2 i& E/ ~* DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. b) a$ c' P; T+ P B& [; qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & q) C2 G: n; s9 A, [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, e! h4 F. I" I2 w, H* @: P0 _
0x00, 0xFF);* ]3 [/ y: I1 K- x! n, x! |/ ~. M6 s
# z! i! h) }+ y' ], O/* Enable synchronization of RX and TX sections */
5 j) Q9 W* m. O" ] h; \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# p" L" L( ?' R I- B4 V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 z9 y. [. d% k' v8 D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 A' y" {5 x" H& O' J* y** Set the serializers, Currently only one serializer is set as( B$ m* ~4 q% e0 C' l, F
** transmitter and one serializer as receiver.: w/ d% i8 d) e0 Q) ?2 U
*/6 _. w0 v) h; `* ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& L: o- T5 @% j* Z3 F& v$ w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: w& u/ u8 Q7 N3 V3 ]1 N5 ` S8 f** Configure the McASP pins
7 F1 x: ~+ D9 `4 `** Input - Frame Sync, Clock and Serializer Rx
5 p- ~' K* X# E** Output - Serializer Tx is connected to the input of the codec ) L" y1 M3 ?* P; Q- P7 a$ W
*/, N7 d8 E9 ]# t9 T) D' j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' E) T0 q1 E5 Q7 |4 R9 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ a) J6 K! I$ F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. _4 @% H0 Q; L1 B& ~, G. ^
| MCASP_PIN_ACLKX
/ z; b! r+ r |2 O* D0 g| MCASP_PIN_AHCLKX4 t# f% t. u8 A& q% `- h; @9 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
_" V3 D0 E }1 BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 } n& t$ a9 g! H! o7 T1 w# D0 ?; J| MCASP_TX_CLKFAIL
q8 ?: ~8 i, ?; D: a4 V| MCASP_TX_SYNCERROR
. Q& ^( b% T; `/ Y' \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 l( |, W+ Z, S' U- N3 {; L! F
| MCASP_RX_CLKFAIL
$ L' S; p3 L/ u, X' u D| MCASP_RX_SYNCERROR + D' i& S* y" D4 S7 Z2 D
| MCASP_RX_OVERRUN);
# D! I0 h# ^( r' z) Q& p2 A' z, _} static void I2SDataTxRxActivate(void)" u: g4 _- ?7 j, G
{
' C1 ^7 B4 W: H6 I" Z/* Start the clocks */
, Q) H7 u- {$ t7 O1 Q$ zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' f+ ~) |7 k% d# UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 |' s+ w/ r+ N! O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# {. B. J5 W$ I6 }5 I; |" ^
EDMA3_TRIG_MODE_EVENT);
. k- p) t' ^2 J; n0 S: yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 H1 A3 x& }8 m+ ^- @2 bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% W: Y+ W Q6 u* o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ [7 z: L7 T' _) Y( d, jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// T1 c) ~0 X8 ^/ g* s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 p9 Q( a5 ~, E2 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. Z j6 i! k" I E. s1 A/ S1 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 K& X3 P6 v& ]2 J}
6 h4 G8 g8 L7 P0 y, Y/ i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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