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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' ^2 Q0 q" E+ Z8 i0 ~5 @input mcasp_ahclkx,
[" q% Y$ ]4 Y* V8 \input mcasp_aclkx,
- I6 D3 f# w5 ]2 y# {' n# ?$ iinput axr0," z& H1 Q* n2 Y* E; [/ _5 a
3 U2 P8 w$ J8 z' U8 Foutput mcasp_afsr,
* s6 `# }! P* Woutput mcasp_ahclkr,
: P7 `' X& q! i) a! ioutput mcasp_aclkr,' S' N( }/ `7 k: Y; E
output axr1,8 N' c: t: k/ J
assign mcasp_afsr = mcasp_afsx;! e( z$ T9 l9 e, _0 p
assign mcasp_aclkr = mcasp_aclkx;# e" A6 B$ I) B% J1 Z' M
assign mcasp_ahclkr = mcasp_ahclkx;: {2 n- ]/ x4 x) s: y) g4 }
assign axr1 = axr0; c9 r/ z) W# h0 x. L6 L% T
3 V9 [! Z. T A/ M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ ?) s% p1 d, G# M+ u/ |static void McASPI2SConfigure(void)
. z2 }* x; a2 [1 o& s4 S8 h{' J) }6 N, o+ @1 B5 _8 `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) q4 M2 E: K+ X: _: [1 _2 P! A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: \7 p6 r; }; w- g* G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- Y6 r" c C4 _) v2 l. c4 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- P( l6 o, G$ p% yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ e8 X& `! x7 s3 ]8 E. T) S
MCASP_RX_MODE_DMA);
b* ^( Y8 L$ }0 QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 s' x4 v4 q* u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" V( t6 v$ C/ b" Z NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 p4 D) L5 S! K' t# [0 W5 M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) V( L. u% I- i# T# A. EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! {1 k8 i; V* Z; YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ l( \) @2 G! z, i( o) I" zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' w L+ K3 u$ T( [: p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" u+ k0 m( R: o+ t. VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 b/ G' Z4 W. s) P5 g+ ]0x00, 0xFF); /* configure the clock for transmitter */
% ?' F% Q) Q. ~1 W5 {, X. U* J% z/ x0 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ Q' @# \+ C1 p# k; E) Y! b. p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' Y" w3 k, [. X/ D' u; t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ ]/ |. ^( N& D; G
0x00, 0xFF);7 y; p% f0 o/ Q6 x8 E. C- O. E
% p! K& x. V" i. S; }2 q/* Enable synchronization of RX and TX sections */
0 Z$ H3 G3 b' UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; ]: W' A3 b$ {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 n1 v' S Y! Z4 cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" C2 [: z" N) H4 {+ D
** Set the serializers, Currently only one serializer is set as, I) s5 A' L7 |$ o4 O! `& |
** transmitter and one serializer as receiver.
% I5 p/ Q% s) F) Q1 h2 r$ C U5 a*/
2 F: q+ u0 \+ \( W) BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 }% k/ r7 C) f- ^6 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ H. u; D/ U# o: h) W" s* F6 i** Configure the McASP pins 4 L7 i+ L& o5 |% a2 X
** Input - Frame Sync, Clock and Serializer Rx
4 U6 V- ^# w/ a- Q$ N** Output - Serializer Tx is connected to the input of the codec * Y B+ N2 Z; ]# \% b8 x
*/
& A) `, Y6 z/ [( x5 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, i1 Y x& v2 }2 @0 Z4 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" |/ {/ Z5 f- b" b6 ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, s' ~" \2 D2 g/ E6 l9 l| MCASP_PIN_ACLKX
9 A0 L% j6 U9 G) P. i| MCASP_PIN_AHCLKX' V* U$ I" Q5 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 @4 U; M- q8 G& h, P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. Y, B! \$ H, F, v/ V% J+ M& b| MCASP_TX_CLKFAIL
8 i& F. T' H2 l K4 z/ g2 T: N| MCASP_TX_SYNCERROR
& N. ~% a! ?8 m) ~+ o! B6 O. D( `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( f+ r. R9 J& m1 b$ D' w| MCASP_RX_CLKFAIL$ v2 F7 O/ ?( a$ C$ c
| MCASP_RX_SYNCERROR # H) `1 I7 T1 I: {; u
| MCASP_RX_OVERRUN);
/ {( r9 z9 {5 B% J/ ?: _} static void I2SDataTxRxActivate(void)
# v, ^+ f3 D2 U( L9 {" }, m{
9 B; B( L2 [& P; ]( v8 t/* Start the clocks */
$ E' X: k7 Y5 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 U; _1 i7 Z6 ~0 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% \' \2 S( V7 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ l, J5 R I3 ] c- q% {
EDMA3_TRIG_MODE_EVENT);/ J+ Q5 z& a3 c- \- b9 z$ V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 X( S2 o: }# b8 ?+ B; p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. C7 z( H0 O6 a; ?' b4 ]5 g8 h$ H# e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( o, ~+ i) C: ~ ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. C! i9 P3 V0 ~. c7 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 z& p9 r' \( f" o2 e sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! T% |/ W \+ Q% [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& ^. [0 R+ P% K+ G& y6 A}
' C" n: m" [1 K& d4 y: y% o" r% B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 Y- m" D+ ^# n9 o: ?; L- ^
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