MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
* a$ j0 Q  k6 u; a' K4 q, ~0 yinput mcasp_ahclkx,
7 f) \- Z) x3 t: H% i2 [! Yinput mcasp_aclkx,
# }+ E+ w/ j8 V+ G3 V+ j/ A, zinput axr0,
! e/ V* ^8 b) m$ s/ C
1 a& G% k7 s$ E4 g# ~! d# o; f; Moutput mcasp_afsr,
output mcasp_ahclkr,
+ a, \  @: g# @9 b; eoutput mcasp_aclkr,
output axr1,
' H8 M2 S( v9 N% z+ K

assign mcasp_afsr = mcasp_afsx;
( T  l! a5 F: ~( t! _assign mcasp_aclkr = mcasp_aclkx;
  L' @3 e, w: _3 x6 L. o& d1 a0 ?1 Kassign mcasp_ahclkr = mcasp_ahclkx;
+ w" L; l  m8 ?: ~* ~/ j2 bassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

  ^9 X& B' U: @1 i( j7 {

static void McASPI2SConfigure(void)
. g. @0 ~# Q& F- ~: ]! u{
( _) s% d5 s0 }6 _1 T' s  OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 R9 h6 c4 A3 H( k5 j+ }& G- HMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
4 o+ p' j2 c2 g- m7 b! SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
* k, p$ R- f( J& q9 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; V7 e# T3 x4 m% Z. ~8 [MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
: A3 y3 [9 E7 W, m& G8 V  ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
  V2 K$ p/ ^- ?$ b0x00, 0xFF);

/* configure the clock for transmitter */
' B; U! _) @* h, y$ S$ zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

% o7 q, r* h- ^/ D3 c2 U1 \/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 e% P6 h* ?: g* Y, Y# eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
, V: R6 Z" V3 H3 D** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
  S8 Q, Q. `: d4 ?0 [3 L*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& o& k5 U( f* D5 ~1 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! H. M0 N2 K* b: q* D7 k1 A' s/ W! VMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ K4 _* H) e+ x" m7 W% x| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
* P+ ]" t6 z3 |( `$ I| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
, y7 T0 |4 v7 l# g+ kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 j: z9 x& Z( P2 Q* {2 x| MCASP_TX_CLKFAIL
0 j1 s% I% c; `! w% T, @| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
( j* B7 B5 F- x}

static void I2SDataTxRxActivate(void)
{
& E# w. n% {$ u0 Y- U, R' m4 T1 C/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) \. C* x% ?( h' wEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! ~! F- N. k8 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.