|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 ]0 }# b1 W6 ?% R4 oinput mcasp_ahclkx,
5 J$ e- ~! x5 s% T L, | u: winput mcasp_aclkx," @$ A- ^8 M& h
input axr0,3 K3 }0 u) m4 b8 K$ O- J5 E2 b
& K: b9 z% b" N& G5 M% Loutput mcasp_afsr,
- N; I" |3 ?! g5 Y& m+ b0 T7 woutput mcasp_ahclkr,7 ^4 X P( D V0 L
output mcasp_aclkr,
- A7 c4 N" j, u: Z' Y& _output axr1,: b/ L, H1 Y3 O
assign mcasp_afsr = mcasp_afsx;
7 Q2 y4 @( s, Qassign mcasp_aclkr = mcasp_aclkx;. C* X" U' j5 y( O2 |) A% L$ W
assign mcasp_ahclkr = mcasp_ahclkx;9 t' u+ }! t3 t, Y- H. G7 t
assign axr1 = axr0;
- x. M. G, S {1 B+ }) @, o* [) A8 M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; U, w% x3 A" Estatic void McASPI2SConfigure(void)
# r! `2 O4 [' K8 ?: w{
: b2 d9 E3 Q" V6 h6 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- X5 y0 ?: ^$ s% N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ N0 L1 c1 {, |& J! A: c a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 U0 E/ d9 F1 i7 z! mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, ~5 K. Z0 ]; ^2 m% fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 n# \5 D) q; r+ }5 T FMCASP_RX_MODE_DMA);
7 D. D r- x+ O1 d! ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 j, X: T4 m( n8 h+ m0 oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) p q ?/ V2 c$ L5 v1 c8 L3 _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ j! ]' K7 ^ i8 v7 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, r9 z! [ G0 b3 t+ [* v: H; yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * [2 W( M9 z. N8 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// J. A9 U$ P$ j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 Y+ S3 ~( n. z8 C u' O. cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 u; L' ^- b' d8 f) w5 d7 L/ D0 I; O* EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% t& Z/ Y8 l7 N- y8 d$ O, _, O
0x00, 0xFF); /* configure the clock for transmitter */6 R) y: U/ _* Q& y' Y r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" ?3 s, d- N6 x ^( C' L6 B% QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 @5 R& k0 R; Y" P4 |8 K7 cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: f/ F- |) l9 Q$ s4 n( f! g
0x00, 0xFF);
: @, ~' U3 F+ G7 \2 {6 u% W& T8 \! `: E4 N; o
/* Enable synchronization of RX and TX sections */
0 J4 { k9 G2 s& s+ oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ _/ R$ V0 Q* `6 L! j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* Z4 F4 a- ?# o) r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ P/ G n' D1 ~1 @( |; N( P** Set the serializers, Currently only one serializer is set as4 Q; y E; w. Y2 u
** transmitter and one serializer as receiver.6 P9 l, _7 H8 Q j7 L/ x+ i$ M
*/: G/ L1 N" g( j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 Q8 U# ]1 G1 F% TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 p: A- }" J3 ^5 g0 f: I; h** Configure the McASP pins " l1 J, L# L# \; X7 r- ~
** Input - Frame Sync, Clock and Serializer Rx. ], q0 C; l$ h
** Output - Serializer Tx is connected to the input of the codec
( m% p5 W; O- W& W& J6 D8 }*/$ V" ~3 M" L4 I) P+ W4 J6 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* L m. C8 A" G7 B" g* g9 V( @& rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: F5 k7 U, Q* E# M" Q: o6 y6 Y, ?9 n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 E7 z+ Q! o# ?| MCASP_PIN_ACLKX
2 W# a1 n: c' F. z5 n6 x| MCASP_PIN_AHCLKX
2 w. u ]5 H7 F' |* B/ @2 @1 M5 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" r1 A$ J" w5 U2 |2 x" Q6 O. p+ M. wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( s/ j' O! x+ d) l7 E" @| MCASP_TX_CLKFAIL
* ]! Y: ~9 |5 Z| MCASP_TX_SYNCERROR6 M* y4 M" w$ w. M' @3 w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 }7 d/ S7 W% p" }! \& w3 v2 j' b| MCASP_RX_CLKFAIL$ R' L$ ^6 c7 A A+ p
| MCASP_RX_SYNCERROR
& ]# m2 y8 W' N8 b| MCASP_RX_OVERRUN);8 ?+ {5 H, Z" i$ n# t# ^2 |7 i( y4 L$ ^+ U
} static void I2SDataTxRxActivate(void)/ ]5 A, u1 N- i3 M
{, F- y7 @' E- ?; [0 T8 j. B$ c
/* Start the clocks */, |! e7 z' Q& {3 |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 {4 P t! m8 N3 o% }& R; eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ H5 g) E- i, Q# y# c8 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 H3 f! ~( P/ G0 _2 Q$ l
EDMA3_TRIG_MODE_EVENT);
% {9 z- h8 y ~+ c% nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 ]. I: v+ p4 c$ I0 E+ D+ G+ yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 R& b; a& q, QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ ~, m6 x/ s$ Y) }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 I N; i5 F: z2 I+ ~: ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 w( k' [5 A! U% i: K zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 g, M1 ]) m q" N% t. d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- s+ H( S( g c) i ^7 |; Y9 D" @
}
# j B! J7 Q% x3 q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) F+ _ R# m# x; r$ d: K |