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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* a4 Q- A+ J. \0 Cinput mcasp_ahclkx,# n2 o% o8 k. Q+ J3 N. ?* L* S
input mcasp_aclkx,# H" v7 g6 @# ?$ R& D! {
input axr0,- v; p; F/ ?5 ~) V; a- b( x2 U
* F$ ?8 p4 {$ c, u" T
output mcasp_afsr,& `8 f( O4 d6 z8 ]" V' N, v- l( e0 E3 O
output mcasp_ahclkr,, m8 g$ y; K; j9 S3 F
output mcasp_aclkr,
+ w5 K" E) O& t& I* J) toutput axr1,
# j) @. J+ B1 G4 y y% B0 ` assign mcasp_afsr = mcasp_afsx;
, Q+ X- i" m2 Q! ?& A$ t' tassign mcasp_aclkr = mcasp_aclkx;& H5 p# x9 l( z) x0 M9 E, I5 O# q
assign mcasp_ahclkr = mcasp_ahclkx;& |" m# i& J! j" |! U
assign axr1 = axr0; U G; r$ K0 }1 g/ W
* j! w+ c+ z2 x& L$ T! l) Q# [' s9 z! B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " ~, E! c/ A& |8 M2 w. ^) k
static void McASPI2SConfigure(void)
% e9 N* ^4 ]3 H! d0 `{
$ O) b+ o) ]( F( yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) v' K0 b* J7 s! H! _% s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# c2 g, o/ V6 k. ?1 |+ z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 q: ]( b K& Q% J# mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( g& g' r; k) TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" D8 I+ A4 ]1 tMCASP_RX_MODE_DMA);
- q7 ?; G( h. i* T) eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* ^6 E6 `6 c, I: H' wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 w6 R& C9 N: |) `' Q; x8 c+ gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 g/ z1 I) O% qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! O6 f Q6 i+ I9 j! @. w. ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 R' ~- T8 F% m) n* hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 D2 ?9 D$ d% o$ W4 L% q H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. X" R$ K3 | ~+ c6 G" J; u$ V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# t" u6 ~2 L- ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% s* j3 I/ r" |' L. u! ]0x00, 0xFF); /* configure the clock for transmitter */ j$ q* ?- M6 B4 k4 \& I) ?4 O6 r1 s- J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 x' v; v0 h% A4 [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; w$ Q5 o z, ~$ U. A( AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( T# ]4 [. T5 J! b. a+ [
0x00, 0xFF);5 b; a: w) e- s0 `
, N9 V: Z$ L `& Y( H5 B/* Enable synchronization of RX and TX sections */
; M5 r$ R9 W6 A3 N! @+ y% WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
T+ n# ?2 m aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: S% l6 l: {* H0 q$ wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; h! R' R* J4 r7 _, P9 `4 u** Set the serializers, Currently only one serializer is set as
q, e$ F L9 d/ \** transmitter and one serializer as receiver.
1 B% F/ C, G% Y$ x0 ^- M. b*/' h" _/ k+ d# i6 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! C9 G, u8 C! i% y$ x- f8 M9 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 b8 j2 d: t1 B, V6 y9 G c
** Configure the McASP pins
& S1 c$ ] Y# f8 j* \; B+ ^** Input - Frame Sync, Clock and Serializer Rx
8 W) ]$ `8 x5 i, @4 `4 z** Output - Serializer Tx is connected to the input of the codec ( b6 d+ ]3 a3 H5 _, T0 H
*/
F- r; ~, A/ p' NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ G4 r; U% r8 f& [) c. |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 D; e4 q% E& x5 K6 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" [+ W6 `$ P7 k" J* \6 j1 M5 b
| MCASP_PIN_ACLKX
0 D4 ]0 E, `+ E9 g7 ~4 r2 R1 Y| MCASP_PIN_AHCLKX0 Y- K3 s% E. z( T/ B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 }- I3 w3 @9 |5 ~& k& q; n7 Y# ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 v8 ~1 Y: C# n6 l0 S& y5 x! P| MCASP_TX_CLKFAIL & o+ g% e: T- q# A y1 N5 z
| MCASP_TX_SYNCERROR2 c$ Y; ?1 b1 ?: O: T' r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 q S8 n* ]2 M1 d$ e+ p
| MCASP_RX_CLKFAIL7 c# z m( Q% m5 G: G
| MCASP_RX_SYNCERROR W2 h$ k- v6 x$ n
| MCASP_RX_OVERRUN);
1 m# p5 C' `6 c4 Z} static void I2SDataTxRxActivate(void)% {8 I0 A/ G3 R7 n2 o6 o) H: u
{
* x. C6 Q8 G+ `9 ~: w6 r! p1 g1 t/* Start the clocks */+ f+ ?- F e/ e: G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ j+ K1 T* Q, |! G+ Q. I) d3 o' h# ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// W5 g0 F1 z- H" t3 Z, _- |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 O3 J- K6 ]4 U9 s- V9 j
EDMA3_TRIG_MODE_EVENT);
' E8 G' p* Y. b g* W8 _5 A3 n8 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% X( x4 o# p8 m$ [$ g& }' AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 M/ j1 V/ [4 w2 RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; T5 |& T, {! n) R8 ]2 EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 g; a0 v% e$ F; Y8 F A9 n, @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 O) ?" ]5 ?& j' H1 z: d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* F: S: q# B' {* r0 W# y' }* w/ @8 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, Q6 H1 G$ K9 m- c}
! \$ [3 b T! F8 z" f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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