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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: j6 @) q$ [+ [- a- Einput mcasp_ahclkx,
1 Y2 ~: q5 T h# }% U. _input mcasp_aclkx,5 f# u+ O6 Z( I% C& U; W
input axr0,
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4 b X4 d$ U8 z5 @' N! k5 Ioutput mcasp_afsr,. @" {$ v) c4 g
output mcasp_ahclkr,
, W8 j) B; O) a# p4 s9 u; g, B' B2 `output mcasp_aclkr,- w& E+ k) M1 K% z, F7 I
output axr1,
. k& R. c) U' V) w e6 `! k assign mcasp_afsr = mcasp_afsx;
! f7 |* p4 H( N; Sassign mcasp_aclkr = mcasp_aclkx;
% J7 N5 e. |+ _ N5 A- v9 G5 nassign mcasp_ahclkr = mcasp_ahclkx;7 ]: q- ]5 ?2 u
assign axr1 = axr0; / E- ?3 j p, ^4 t
; G! K: y8 r& }; L8 L" ~7 r. d% h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. v+ q, \" ]: ?static void McASPI2SConfigure(void)$ ?0 B6 l: b# m: Y8 m: g& E. @: }& c
{5 J i% @( J' v/ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" K4 f9 d$ V2 [$ _/ P4 vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 K2 E# ^+ s7 i" V- W, X8 p% vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 \1 B5 \' Q6 y2 \) \2 w: e" q8 X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# c% y/ p7 h2 ~2 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% L1 r+ ?1 W6 M% }1 s0 ~MCASP_RX_MODE_DMA);7 a w2 X$ `" g* w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 r4 U- b0 R9 R; ?# cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 R2 u. H2 H# e& l0 P9 Z; d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: \& t4 `, w3 f2 OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# y0 b' {1 `$ A. S$ \: uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & O& N% q& m$ h' X8 J7 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
H j+ b' ^0 C$ Q" R5 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 A/ I* ]: [1 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 _; Z9 r% G j/ a0 D3 n dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 Q4 T2 W5 R0 ], ]2 ?8 E: w0x00, 0xFF); /* configure the clock for transmitter */
; o& G8 U5 K. M! C; Y7 jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) }7 l/ b# P+ i/ c% x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & H$ W; y- S* b) Q1 l8 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. T5 {5 j# T F( b0 D# k% l. ~0x00, 0xFF);
' F/ G7 a8 O! n# ^# X; q8 I& q7 r, Q
/* Enable synchronization of RX and TX sections */ 4 A7 L0 E s( }; `- D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ W7 B2 g5 U; A2 r$ V0 }. b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- b! G4 |- M. z8 v. m' w, x6 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; C- H- g' J' u4 }
** Set the serializers, Currently only one serializer is set as
: e& x# R/ z# S) `( u** transmitter and one serializer as receiver.9 I2 s0 {8 @$ s. m/ ~
*/
! s2 s6 G6 s' V+ ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 c X( A8 e- k( dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- Y! D2 p* X$ o** Configure the McASP pins ) f) i; b( ~% V1 E
** Input - Frame Sync, Clock and Serializer Rx3 z: p1 r. o) ^. \/ ?
** Output - Serializer Tx is connected to the input of the codec . B3 M% R* d0 e; \" K! ~7 I
*/
4 l% F# z9 f2 t- eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% B1 v( z8 h3 M, H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 p# d1 M( `& |8 F, G7 m7 A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ T& x/ @6 h% j( J4 g- ~4 S6 p| MCASP_PIN_ACLKX
0 O1 L) R" h' f/ f8 p, h' `# E' v| MCASP_PIN_AHCLKX
5 J/ w! T/ Z k0 U0 E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' j# ]+ z3 O$ f1 ~4 n$ [# {: L8 ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! C7 Q& ?# A& p" G- _/ h h# r) ]/ c
| MCASP_TX_CLKFAIL 1 g7 M. r7 }4 m$ b- F" `; i# a
| MCASP_TX_SYNCERROR U# t4 f4 `! {2 n. V1 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 P8 L2 x: k- c/ ^/ J1 e
| MCASP_RX_CLKFAIL9 u5 d* A, W' i6 o" K& T
| MCASP_RX_SYNCERROR 6 z1 C8 |" n, b
| MCASP_RX_OVERRUN);
; s0 S( C) D; ?3 f+ B6 j- q} static void I2SDataTxRxActivate(void)& t0 E% n3 K4 h* D6 d
{
; z. v% ~8 A+ K) X7 A" Z, A* ?/* Start the clocks */8 t. @. M, v$ L! w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. \7 }9 R4 z/ cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// f! R1 H, k# S3 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 M$ D0 n; g8 ?- \4 \3 [
EDMA3_TRIG_MODE_EVENT);# h8 q3 G7 D$ W5 c0 ^' P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * T% s2 D, \$ i5 P1 U ]. _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" Q- }' [" K# \: p$ J2 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 H2 N9 F, F6 x! o2 _2 o& R2 HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ T7 v+ N# p5 ^8 c3 qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ m0 l5 s/ A7 v4 D$ F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* k5 F* I+ t# [* y. `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! D5 h0 I! {* j7 ~/ z# S" b2 v. B}
8 e/ K- t6 j b7 o# x5 l/ [. S4 d+ x {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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