MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
$ e1 E) [! H1 C2 _input mcasp_ahclkx,
% P' ?3 Y1 {  \. ginput mcasp_aclkx,
" g0 T9 T1 b- q. |3 w% oinput axr0,
9 l, b+ _# o( \/ j2 n
- J, {  g) Y7 |1 }. soutput mcasp_afsr,
, [" J% u& R( }* y- ]* n+ v8 Uoutput mcasp_ahclkr,
output mcasp_aclkr,
+ n% M1 W( C0 m0 Y5 a  ~' {% }output axr1,

assign mcasp_afsr = mcasp_afsx;
! ?+ j3 H. m" Massign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
( p/ R: H6 a' W/ s0 jassign axr1 = axr0;

* z- B% N2 h9 O0 V. l7 ^# q. N( w
1 Z8 G, ^8 J" G4 r9 N! Z

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

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static void McASPI2SConfigure(void)
{
* P$ I% Z6 l: |+ F" _0 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, G* W7 L3 f$ p  f. _. w, uMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 W' R1 N6 ^9 s+ mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. G7 p6 j! Z+ j4 f- yMCASP_RX_MODE_DMA);
) }" N% W/ w) z, H) hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- S  b( b: d  o0 b) tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
! i& r0 h% o; q; X8 R. yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 M* V5 S* A$ @- q5 _5 G' B% u0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
  x- m8 \: V3 I' @0 N! N2 y8 {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
* A! Q& T) f( ?( r& N1 N
$ V  _4 [' G+ l2 I9 L1 @/* Enable synchronization of RX and TX sections */
3 ~0 W* H9 G" vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 t" q1 F  z& [% t. d) SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' l- f7 m8 E# s! Q( p# j3 xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
8 R7 V' ]9 O; J** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
2 J+ t; E. l0 f* B5 ~** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
1 A! c! x2 {( `6 E" m  P** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 ]6 {- F% w# @( FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: F, ^. J# |" E( S| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
% z6 d" ?0 _6 ~/ @+ J| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
9 N3 P/ d( t, w5 c| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
+ d1 g1 p! b# r: {/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 b+ a/ N# _8 b, SEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 v- e/ w% O2 i) WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
  R1 E" p$ k- m: l0 i$ p- v2 FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' ]+ K% C/ A/ gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 O  @4 W2 p% s: e' b}

% W0 \! v. f' s

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

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