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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 G" T- V9 _) s+ M) `
input mcasp_ahclkx,' Q: S5 ]% G' G- f; L
input mcasp_aclkx,# u8 ^ P1 |2 { D
input axr0, v) ?' \' V: E5 w3 `$ M9 s
/ _. K2 h7 _( I, h3 b6 routput mcasp_afsr,
' X% |, R) K1 O. @" r. D' @output mcasp_ahclkr,
' z( B! ?$ u# u% Woutput mcasp_aclkr,
G* k9 o- s8 \output axr1,
$ G4 c: D+ q- M# I! X assign mcasp_afsr = mcasp_afsx;4 p: C5 ^5 x* n8 b
assign mcasp_aclkr = mcasp_aclkx;
" S& m! i; @8 Sassign mcasp_ahclkr = mcasp_ahclkx;1 n8 \7 } @4 E6 ~
assign axr1 = axr0;
4 `' `# s0 i" B: g. n9 X9 X* R+ O$ R5 V. d8 H: E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% j2 `& ~0 S6 `static void McASPI2SConfigure(void)
" S( s: n b, B5 ?; d8 @{- F' Z5 i- T* [2 P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: ^, T: u; q; B' L9 w2 \: f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! F$ t# Q( c; X; _& _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, p8 H4 n0 ^7 V+ ?7 q$ MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ }% d' l; `* s8 `6 M* s5 e+ ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* u$ Y, C# g. F7 B7 e) t
MCASP_RX_MODE_DMA);' X+ _) f+ G2 S+ h, I8 T0 z8 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 D' t6 r+ m6 C% Z% t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 _/ ^9 z+ k$ K$ k& a7 L7 a% }7 `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 ]' g) F5 g3 @! ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 P3 l9 R7 q2 d3 K: `9 `8 z+ H0 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 T4 c- K" H( V4 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- U8 [. g' e( W0 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, p- K, f- |1 n& Z0 j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# X9 D: H7 @/ z7 _6 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ o; e1 l, v: ~( E' f1 _9 R
0x00, 0xFF); /* configure the clock for transmitter */
- T$ S* n" b: v T: O. ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' W& W7 ?1 X9 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 A2 p; N7 m$ U1 X# J; W, I# N7 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# i& ^6 f$ `" a/ n( f! r, \
0x00, 0xFF);. f# M: O( D/ Q
9 v( A' T9 s. s6 \9 ^8 w* `5 ]
/* Enable synchronization of RX and TX sections */
- [3 q* r5 ?) C0 Y% DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ u, l) `- H% ]7 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 e) }; t( w8 d* d( t! xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ I4 N& T( o: }
** Set the serializers, Currently only one serializer is set as4 L7 @6 E6 L. e7 {5 ^
** transmitter and one serializer as receiver.
0 I) f9 B# \9 D*/: v( r* W1 J: M {: `$ ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% ]- o% y! i7 y3 H& CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 T- r5 N+ E( \1 a
** Configure the McASP pins
7 g+ T! X; T3 Z( W) J** Input - Frame Sync, Clock and Serializer Rx' h. c2 @* D' @; ?: n
** Output - Serializer Tx is connected to the input of the codec ! Z. P$ [/ {9 N) Z
*/( t" Q& f& Z* w2 L" d. y+ e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: B6 Z0 j9 S$ t' ]9 T& [0 X. D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 Z, g5 {4 |- B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" _. d* N3 C2 @+ G% D
| MCASP_PIN_ACLKX5 n# u% X% t% S! W/ Z0 T$ d: G$ t: ?6 a4 d
| MCASP_PIN_AHCLKX
. L6 t: Y. `0 L" z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 O2 U4 \1 @" g/ j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( \9 b& y/ k1 N| MCASP_TX_CLKFAIL
% R- B/ m' Z: h; l, p| MCASP_TX_SYNCERROR5 i$ z0 D8 G) a6 t g! {, r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 P! x" M ~, v
| MCASP_RX_CLKFAIL: S9 D3 K9 m" h i F; D
| MCASP_RX_SYNCERROR + A' n4 c6 }9 Z
| MCASP_RX_OVERRUN);
) n/ E; e# x4 _0 K+ l} static void I2SDataTxRxActivate(void)
4 J0 X6 q6 _$ @, R{" Q3 S( l$ p- V; Z! i2 x
/* Start the clocks */
1 X' _* X1 j, R5 G _" K9 L, WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& Z9 ^2 B! ?, R9 n; ^# R9 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; H8 ~1 Z4 X, p c5 `2 n) I* wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' b9 }0 s6 Q/ ]4 `6 ?0 `& Y* \EDMA3_TRIG_MODE_EVENT);: i7 i2 v( ?+ v6 M# y2 S: s8 \+ V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! \9 I P( ~" K* U4 C* h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ s; |) q2 R4 X3 E: f3 W- p; `! U' I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' F& K+ g- x8 i7 ^' W/ o! Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 [) \ X+ z6 ~! uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! N* \8 [$ P: Y1 d$ M( n7 p2 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" K) N6 b1 F/ }9 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 K) v9 A3 n) \" i
} L+ g, y3 p7 \) c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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