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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ V3 G( o1 o) n# ]; ainput mcasp_ahclkx, M6 c1 c3 P+ ^* u+ |
input mcasp_aclkx,' {$ P7 c9 j6 m( K) x7 Y
input axr0,
n' _6 F% J( I, _
" K, Q6 l/ U/ `/ @5 aoutput mcasp_afsr,
- G. U7 K/ ~; d$ H! }( Ooutput mcasp_ahclkr,
6 }/ b6 [1 {2 v5 g+ M& A9 c, Aoutput mcasp_aclkr,
0 m4 V7 o3 _4 {5 A" I& Loutput axr1,
0 X5 ?7 b+ B+ g0 H+ j8 s% l! B. V; F assign mcasp_afsr = mcasp_afsx;/ E D: e( [$ _+ I3 W) e
assign mcasp_aclkr = mcasp_aclkx;6 Y X0 w8 u% f* v
assign mcasp_ahclkr = mcasp_ahclkx;; Y) x/ C: n! z5 e0 [6 Z+ n+ j
assign axr1 = axr0; * _1 w& n1 P- l6 I9 u
, [9 ~4 v5 [, z$ l2 h6 r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 G6 g5 z& o; k
static void McASPI2SConfigure(void)/ R p) E X- C! m W
{0 ^5 D1 ]2 F6 ]9 P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ y5 ^9 A# m6 k" L4 T% f2 _2 ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% D2 s. G; O! J& j; G' Y0 O+ c& d1 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) \) v% u: H4 J& Y r* E; I& vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" U5 m: Y! k: h( ]( S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ q- S/ S: I! ]3 N7 j8 f6 `" W. r8 fMCASP_RX_MODE_DMA);
3 V* y5 l, `! G0 r: J! YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 T" S) Q: k, z' z) ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( X [# O% p9 Y" U) J. ~8 PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . t$ x" g3 F& ]. z1 C8 T6 T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- t8 w5 @. C; H+ r& f O \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 J4 o. n4 u- s2 R7 ~. {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& m' X6 X) D$ q7 D( j1 F" p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
Q; t, C; D5 T7 D! f% B8 ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" f8 j7 A+ b8 G* e0 qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ M1 n u# R- g7 \/ L8 G; e: w d
0x00, 0xFF); /* configure the clock for transmitter */* a0 j9 c0 p' K" N4 U! J9 Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) _% f- l& a3 {3 P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; A( H# y. J& q I, x8 y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& i+ g2 f# Z/ T
0x00, 0xFF);# ?1 J0 @" `* g& F; i, _
. W, ~# d( d% t: s" i; ?* U
/* Enable synchronization of RX and TX sections */
: L5 Z$ ~/ R! s; y' G: Z9 t O) W$ [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" e. j# s# V7 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% r7 |: u3 N9 P, TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" Z9 w' Q w% i4 \5 _' R! B, E5 ?
** Set the serializers, Currently only one serializer is set as1 J) x( u+ d% {' ^" o3 q5 `
** transmitter and one serializer as receiver.* [3 u j5 r) y8 y+ X' c4 ~
*/
8 r8 N! O( b; LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 B2 f% \3 X7 I8 I) k) L) R( YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ d, m6 d+ d b( g* N/ O5 N7 A1 Q** Configure the McASP pins
?4 e) [! W" S0 I2 `) t** Input - Frame Sync, Clock and Serializer Rx
. f* i# E! ?4 k# g! k1 D# Z9 A** Output - Serializer Tx is connected to the input of the codec
. C: I/ M2 ~) _$ q) H*/6 K, ?# Q$ b8 q6 [! Z: m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( C9 T# m9 J0 @1 ^) N: k& v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 }1 Z6 p L& g. I9 X6 E6 _) iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! ^9 Q6 V1 r9 Z c6 v
| MCASP_PIN_ACLKX
' A* J% J8 T1 [: B/ b2 s| MCASP_PIN_AHCLKX
1 f4 D. O$ E8 m' {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% @2 B+ Y7 P/ ^% ?# UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - @/ R% V* {* o7 V! y+ ]0 X
| MCASP_TX_CLKFAIL
$ [. N: g4 y; n6 ]| MCASP_TX_SYNCERROR
9 E6 w0 {" Q8 |" g% O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ], j0 g5 b1 N) ]
| MCASP_RX_CLKFAIL
2 J5 `' \. z. t| MCASP_RX_SYNCERROR
! U# a& r4 s7 K# M5 \| MCASP_RX_OVERRUN);
; Q2 J! P; l; f( F" }! \' o} static void I2SDataTxRxActivate(void)
O% k( o% J& e- V" r. i{
! W E3 `" L, {/ ^& t/* Start the clocks */' W0 L& x, q l) i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 A5 v4 C" {$ T/ J& ^! t1 WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, x3 o, F9 {$ I/ c- T' Q6 L4 n6 s, L( q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 U: c; q8 F$ x" Z
EDMA3_TRIG_MODE_EVENT);
~+ l( J! a' m7 t, ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & f6 R& e4 R5 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# R2 H- a, W" E$ D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 y6 K1 o9 U9 k& \3 D& N* W# A4 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 G$ k7 B4 v+ z/ y Y9 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; g2 e) d& m. p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 u/ e# ]+ H; H) p/ j, C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 H9 J1 Z3 S2 x% W
}
" @' M: I. V8 @! s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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