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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( U4 v4 i; m4 |/ ^/ R$ O( y
input mcasp_ahclkx,
% t0 R' X8 d a; y- Rinput mcasp_aclkx,( g; B# A1 H! j4 x7 o
input axr0,. C, w/ ]3 X$ J: n) \. i! q
" T6 ?1 T7 o( D7 i$ ], U9 {6 y$ Doutput mcasp_afsr,
* n$ H ~. C6 [! B6 K) eoutput mcasp_ahclkr,
8 X! R- s4 y0 M9 w, Y4 Houtput mcasp_aclkr,, q2 C! H! T7 { U% L Q9 h
output axr1,
h& y& K: o% H9 r/ O assign mcasp_afsr = mcasp_afsx;- ~; n* X. D6 i) \
assign mcasp_aclkr = mcasp_aclkx;9 p3 v3 X; Q- u2 g3 S1 l
assign mcasp_ahclkr = mcasp_ahclkx;$ c- m7 V( B4 g: }+ O$ ^; Z
assign axr1 = axr0; 2 h0 N+ V- ^: d. E, [7 g* H' u# `
' D4 S3 {9 b G$ X% m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - h: m6 y8 @' _3 X0 B6 B
static void McASPI2SConfigure(void)! n: y+ J" d$ B5 o
{
k5 e7 k, U! uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& B) |4 v% u! q( t$ j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ q6 l+ I' p: [ nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- m) J7 X/ B5 Q" K1 {/ V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ A* j4 M$ C# }* y0 y. ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 ?1 \$ a8 |+ K$ F7 ^MCASP_RX_MODE_DMA);& ]2 X: r$ |! F0 u8 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, l& }' U; T. m8 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. I9 L; a3 g' g. h+ Z$ l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! `! F$ g) Y9 \; n" n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- u& @7 x) K: ~6 q2 O5 {8 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * i* v$ t3 N: Z: o) S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ F; o+ G2 n2 n* v7 {" x) ]9 QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 W+ c3 L2 d0 t+ M. Q `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) _6 j. V. N [; a' w( E, LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 s0 ], _" X. P! ]" p% r
0x00, 0xFF); /* configure the clock for transmitter */, _6 R* P2 L7 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 F9 D) ^/ @. g0 o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( q/ \+ D# o/ ]& l) T, @; q9 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," `6 t1 L: I2 m, }4 f
0x00, 0xFF);; E4 [/ _$ S. B5 R! y
1 `' ~+ F& q7 `& L, A" D5 t$ U3 r
/* Enable synchronization of RX and TX sections */ ( m& W4 i' A, S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( l9 ~9 B$ s- a) `1 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) X) @1 x/ p& Z, t: E2 eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& D) W a' f! h3 _0 W5 ]1 ~** Set the serializers, Currently only one serializer is set as6 L2 t/ U2 b0 [/ R0 x# `
** transmitter and one serializer as receiver.2 }, ^% p& ^" ^1 S8 u6 i
*/
8 S! @) a7 Z, |! O' \) [! m9 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 |; j, W/ V' S+ A* HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( @3 _. D" H9 e5 n1 r
** Configure the McASP pins $ J+ ~; }: ?: T
** Input - Frame Sync, Clock and Serializer Rx
& L: D! m+ H. [$ P** Output - Serializer Tx is connected to the input of the codec 3 Q2 M5 L0 f# E- ^" G" |$ K
*/
" ^* [3 a9 r$ e1 F( FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ P- i* N3 `* _; DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: E; T+ d: ^$ _3 M. J, t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 v- O% I! Q: g* u6 c; K) v' j- E
| MCASP_PIN_ACLKX" s1 C) {) |( _& q+ T6 v( D: x/ V
| MCASP_PIN_AHCLKX2 i3 l. a, T% S- D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# Y9 i' Z+ K" h7 H8 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- \5 N8 G- {2 D" V, j1 s; o; ~| MCASP_TX_CLKFAIL - i' k# ?& v7 Z& f4 _
| MCASP_TX_SYNCERROR
! q6 _2 S+ u; L0 C3 s6 L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & n9 p. i2 k3 L4 O. c
| MCASP_RX_CLKFAIL
, R% c, O6 T' A3 x4 j| MCASP_RX_SYNCERROR
G7 A: { | k$ i| MCASP_RX_OVERRUN);3 n' n+ [8 o+ [ s p9 r x a
} static void I2SDataTxRxActivate(void)9 q6 m8 v) i% l: x$ y! {% d$ H
{$ n0 m8 X1 V8 ]" Z+ ^
/* Start the clocks */
5 c G" H* j. Y3 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! z8 D. O, r3 M1 ?. G2 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 x2 J( H/ B+ A- Y- L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ c9 N( [% i. f! nEDMA3_TRIG_MODE_EVENT);" b2 W" `: U8 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 w7 L" K/ k: e' S0 e& c4 H) }8 N* k, y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# v! S$ t. R8 K7 {/ o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 e+ a& w% a$ F: F' W$ }3 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- K. n2 ^7 { D/ O7 G! Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( ?$ N7 T$ m+ O/ ? B3 W! W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ L2 M" @/ z4 x" ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- S5 S5 v1 X _7 y
}
- }4 {9 W8 w2 J! A/ z+ j5 H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : t5 E6 c! U5 Y
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