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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 I' ]2 Q# ?2 h0 Z/ L
input mcasp_ahclkx,
& y- b& V5 h3 D0 C, Z8 s+ Vinput mcasp_aclkx,
) S$ T' x) r: B1 W# I* i& Iinput axr0,$ h. i, t" v9 l( b5 {2 H) z2 @
' i! L8 j$ c6 E8 S$ g4 Q) ^" u {output mcasp_afsr,
( U( y# Z$ A7 Z! `output mcasp_ahclkr,
+ {- \& E P( L' J0 |$ Toutput mcasp_aclkr,/ K1 p' A$ |& H( j9 F+ R
output axr1,& a/ j. n+ r' O" D
assign mcasp_afsr = mcasp_afsx;5 ] o+ b9 f c3 Z, _
assign mcasp_aclkr = mcasp_aclkx;: c: U9 f" M6 E2 _ ]. Q
assign mcasp_ahclkr = mcasp_ahclkx;
# f0 Z( k" P7 j4 @" z& massign axr1 = axr0;
/ v$ e! V I# l, b, n0 h0 R
& _4 C( H' i2 x# _+ g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ P+ i5 v9 |# e
static void McASPI2SConfigure(void), Q' l- g- t7 }! @
{. M% b1 W3 {7 Y; k, f& W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 ^, U0 D0 A& g( t* S. F; \' |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' W; {, G) F2 M* o9 D+ N! xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 f/ I# ]) \# a4 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. ^: M% U! ^, w. FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 _2 z7 W d# ^: M7 }# X8 o
MCASP_RX_MODE_DMA);
9 ]; [% o# `* |# A6 n% O; FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; n H e: ?3 A0 w% |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 v+ D6 k, N7 [. h4 M" wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ j3 e( ~# J' IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ J; G. T$ u. FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' ]6 P. g6 i& I) `- `8 v- v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: o# T _, ?" m6 W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. P, k7 H$ g5 E$ ?' y4 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ u" o4 l: S/ k L& u+ Q7 h4 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* [( f! ^- [ z1 Q# w0x00, 0xFF); /* configure the clock for transmitter */! e9 h! ~3 }3 l( ?( v+ z; g3 I6 `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; u2 G( r- f7 h- B4 m& l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' Q: H; x X2 p% mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: i4 m4 f9 q0 Z9 X2 G0x00, 0xFF);# P! q w0 B( }6 r8 B# |. O$ I/ ]
& [) O6 ]1 u, P; M; Y; c+ n
/* Enable synchronization of RX and TX sections */ 9 o* S8 g* j, l- N/ f; o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ x# j9 x$ n7 h$ p* \1 M/ R, FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* a/ o5 |1 I- z% f F6 e! w: s% mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& B9 y( Y" d0 G! v0 V$ v4 L8 O
** Set the serializers, Currently only one serializer is set as, P1 ~( }# r6 O
** transmitter and one serializer as receiver." j3 j) e! H0 i! b: u
*/: ]& B7 H5 G* a5 w# S/ E! C; s4 o5 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 s" e- c; W5 V7 M4 R8 u/ t. q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 h1 t0 a) t/ B1 v$ J7 L- `3 u** Configure the McASP pins ) j, S: V( |! H! `$ Q
** Input - Frame Sync, Clock and Serializer Rx W" A, z6 [! v8 J' Y" t# v
** Output - Serializer Tx is connected to the input of the codec
: ^) |: _ x8 `' W- B# {; t# u*/
6 {" y- j. w7 M3 m8 j! EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: ?2 H/ }9 ?& I& O- O) h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 ]4 F( l- ] \2 f R2 {7 ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, H/ L$ C' m$ t! q& j( P
| MCASP_PIN_ACLKX
; E& V, z$ y' _3 }| MCASP_PIN_AHCLKX# X, I# d- u3 Q( A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& ^1 M. f+ a! a2 w; b! O4 Z& @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 K p2 x9 |( ]3 I. L3 Q| MCASP_TX_CLKFAIL 8 e$ f0 h9 G# Q& g8 f+ E* S
| MCASP_TX_SYNCERROR, V9 q/ y3 [, {- ~8 ?- f# _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * u7 j& ~& s8 ^% V; l$ N
| MCASP_RX_CLKFAIL( y+ T1 {2 S4 o- k
| MCASP_RX_SYNCERROR
) r4 i5 ~5 H7 o' |% b& N| MCASP_RX_OVERRUN);! ?8 @) z+ z& t/ D" f1 t% m, J2 s
} static void I2SDataTxRxActivate(void). T0 M d- d. o1 G/ L
{
; b, ]" p$ Y9 J8 B2 g' {/* Start the clocks */; o1 R2 |6 m9 I- h5 q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ [2 m" n' r7 S' A- P7 i$ F* @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 r2 }0 `. M8 ]9 w" @, m! U( l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 ~7 c+ ~' Y4 R0 yEDMA3_TRIG_MODE_EVENT);
/ `4 j$ Q; ]; X# m7 c* yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, d5 i! @" S1 C) q3 m2 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 _+ y2 D% x5 u& Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ s6 I1 _, W# w% S' {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ Q5 \( Q4 t3 E* j! y" Z! {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ w' z" m) Q% Q9 s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) l" q- o( c: [! T; I0 O+ h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 c$ ^/ L" K& ?' t. \+ l
}
, d9 Q- d( v$ W- l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) r; b6 J: l' I N3 U2 l
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