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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( k1 ~, f" O) q$ N
input mcasp_ahclkx,. ~9 e' Z/ M" w
input mcasp_aclkx,! q/ A( P5 i ~5 j! W+ T
input axr0,
- S- B, R) n1 S7 u0 y: b: H: ?7 G9 a9 E! z$ i) T/ \: {5 k _
output mcasp_afsr,
% W! m8 [8 ]% i! _3 T& t5 q4 X7 v# D) |output mcasp_ahclkr,
, [; n$ A: i2 e2 s7 r6 o# V$ }output mcasp_aclkr,+ c& ]9 w- `. h
output axr1,
3 [6 A4 p% u0 o ~ assign mcasp_afsr = mcasp_afsx;. u5 ?# @9 t! d# G
assign mcasp_aclkr = mcasp_aclkx;
% O9 m5 \" V$ Wassign mcasp_ahclkr = mcasp_ahclkx;- e9 s, o9 ]- C6 e" N
assign axr1 = axr0; / K, k! T% r4 D' f) i) k" O. Q
# n1 J6 A- c* h1 M; ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & x; r5 c6 C9 |. }
static void McASPI2SConfigure(void)
2 e' g% w7 f0 f( u7 J9 g{
( g: j* Q/ F6 g. `- w+ A4 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% U$ \0 W8 @: ]( B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
h+ P' L8 K% T& X. M8 x/ `+ Z) nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; E( L: N7 c+ X/ D( q2 x- D7 E" d7 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, j9 K+ M: @! q1 J4 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 A. ^' P. T; W3 S( G' o! [0 pMCASP_RX_MODE_DMA);8 ]2 `6 `4 I/ K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% c# O* T$ B: ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( n' D" e1 [" O' i% tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 e' D! K' E) B' G* x! m' j \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. x1 E' F% r# H, A( x5 W6 @/ TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: u+ M8 }& N3 QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ e* o; e, c/ ]0 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ J; B4 j) T% @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 |5 I9 P' i' h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! D! c8 A/ I8 u1 c" `" L0 L, J0x00, 0xFF); /* configure the clock for transmitter */& }1 ?5 ]) {0 T4 `, E" U \6 h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# ?+ g5 v, u, Y" T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ z8 j. \4 o1 w% k$ _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 Y4 T: u( W7 H- e0 h6 {0x00, 0xFF);2 p7 S# z5 r; ? e
6 E& W8 [+ @( B) x/* Enable synchronization of RX and TX sections */
6 |2 F$ W) A) W% P3 YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 G. [' @$ R! c) I- P# y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 k0 a Z' N# O1 Z Y* E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& ^/ i6 B" W! | f6 B& c% o** Set the serializers, Currently only one serializer is set as
; C7 m# U# w. h9 H% H, n** transmitter and one serializer as receiver.
9 i7 T$ G8 i& F, q3 E8 ^*/, |4 B2 h6 @% u, W$ o7 v0 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ o& s: `- p1 \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# M+ d$ [1 i" f; S+ a" g% i** Configure the McASP pins
% B/ ` a0 N7 m R+ q. T- E* V** Input - Frame Sync, Clock and Serializer Rx
7 w6 X' P+ D, N8 `** Output - Serializer Tx is connected to the input of the codec
! r/ W# a" D. w3 j; X, f ?7 y6 y*/
2 ]1 H" F7 Q9 J0 aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! A& M2 Y8 D* b: U: ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 I5 M3 y1 X4 C2 y, D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ E$ t! w' i# b- S0 ^; y2 x| MCASP_PIN_ACLKX' }( y4 Q. Q, b, d, g' X
| MCASP_PIN_AHCLKX r s+ U8 W- W1 h. U* u, {' {5 w+ k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; F* [0 `/ N; D- c _; @: CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " @. I7 a9 u: f7 R
| MCASP_TX_CLKFAIL
8 R. O R0 P) J2 d| MCASP_TX_SYNCERROR
1 i3 ?' M! j# `& ^% @ l6 F5 {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : l. L4 `, h; @$ p
| MCASP_RX_CLKFAIL
+ l7 D: D' `- \ {( w| MCASP_RX_SYNCERROR
# Y; `8 u3 O6 g; X# Y; w+ I3 z| MCASP_RX_OVERRUN);8 E' T) ~3 H ?( I
} static void I2SDataTxRxActivate(void)
( f( @9 F) W; F' q# O+ E( h{
. Q- a+ |8 z7 O% _. A6 N, A/* Start the clocks */" R- P- e% j3 D7 a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. P6 P" W( d2 a9 |& P7 L: iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( V( F* W4 A/ a: s4 A5 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 S' ?, _3 w' WEDMA3_TRIG_MODE_EVENT);
6 f2 c' \; a. B* i( A+ X' sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- O, [9 g5 G- ^: u! ^$ V$ ^% ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 E: j, v8 C$ r8 T1 V6 f: Y, ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 j/ H7 F( r2 W4 s2 w6 Z) VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" y) i+ c0 i+ d: x' T. f3 }% Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) q- d, b8 C8 q7 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 d8 L2 s0 x8 Y* q: r. E$ X3 e) UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ R, Z. p- J. d; @5 B}
' A2 m% F. i6 l5 g& y5 d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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