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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ @4 n) }. |1 t( N# K
input mcasp_ahclkx,0 ]% T0 w, e. F1 B& C* j- k
input mcasp_aclkx,
4 j8 d5 \. u6 h5 m, P: ^: zinput axr0,9 J0 ?7 E% ]$ w" g0 p( }( j4 w- r, U. N
- b8 @" b7 E6 J( a0 Q- j
output mcasp_afsr,
; _7 V O4 T0 T) woutput mcasp_ahclkr,. r% M% d5 U. c5 Z/ ^
output mcasp_aclkr,
) N: J3 ~, O* ?: [output axr1,. M5 F& A/ l2 k- Y
assign mcasp_afsr = mcasp_afsx;
: q3 a8 f( }- {, }assign mcasp_aclkr = mcasp_aclkx;! f: Y( h8 E1 l3 F! U+ C
assign mcasp_ahclkr = mcasp_ahclkx;4 _4 m. m9 z7 r$ ^8 Z9 a6 [/ j
assign axr1 = axr0;
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" s& r( e- X/ m+ V1 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! V1 e/ Q% |4 `* _/ c1 a6 Nstatic void McASPI2SConfigure(void). G! h6 {, q5 {
{) }! d' E; I$ V& b: s4 }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 O6 q2 u2 F( x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( F) S2 x/ Z# n; S3 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 s- u3 P) S+ P7 n$ h' u. V7 T8 v/ }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* a; `. i, _! k% _# k6 K/ y6 dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! j7 `1 U! B w8 K+ P5 x3 x* Q4 w
MCASP_RX_MODE_DMA);
0 m; m; f+ H, P0 E0 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: g/ m: c- p( d% D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" c3 \! O3 j2 J9 @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % q+ V6 T' b" c6 a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% V/ }- M- O8 Z0 \# ]$ JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : I* ?! L% ~. B. z& {# O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 R" k" g) u$ X K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 h% r& [( g t' ^" Y) Z Y1 Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : y' x2 `) A0 M9 z9 Q' C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* J4 D; } ^) U/ K' o( b0x00, 0xFF); /* configure the clock for transmitter */& X) y6 J" _: T5 J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( ]; @! K9 }# t; V' a* P, C- IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ {( o- g; f9 o* Q( u* L4 \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. w, q4 A$ e2 A3 {1 @+ ?# x
0x00, 0xFF);
) d1 c3 D! _% M! C0 {) l
* u! ]7 H4 K* G, ^$ t/* Enable synchronization of RX and TX sections */
2 O4 [+ ?6 _8 iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( g& ~ r+ }4 d$ KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& w0 O/ q2 K- [0 b- {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! N% n' _% R1 d- R. ?** Set the serializers, Currently only one serializer is set as9 S5 @% h$ ]% r2 i0 u! P; z3 T
** transmitter and one serializer as receiver.( O4 k" `+ z W6 ~0 A1 Q
*/. O* z/ m5 j; n& o5 |- t8 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: Z5 q6 j+ M; ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; s; E6 _. ~8 G! D, {9 P/ d! i** Configure the McASP pins
& l+ D6 h! ^1 I; R6 |6 F** Input - Frame Sync, Clock and Serializer Rx& U5 }/ j4 x( `& A0 c: E
** Output - Serializer Tx is connected to the input of the codec # h' U6 I( h& k' n' V! q
*/4 z0 l" Y7 c" ? X: H- |$ R" j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 w# z3 I8 y! {, YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 f& C s5 f- l6 T9 ? O! q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 h6 T$ y8 ?. H% r+ H8 O, W
| MCASP_PIN_ACLKX, g& A- V# A. ^; I+ P
| MCASP_PIN_AHCLKX
1 b# z; z( Z4 l0 A2 ~; B7 Z; {: ^1 ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: u0 @& u# [5 \ A1 {2 W( @) S: |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & L; s$ x( v+ {, U4 j$ B
| MCASP_TX_CLKFAIL & Y' F7 L5 O( F4 [# J# A2 x
| MCASP_TX_SYNCERROR5 V/ S: p" G2 h. D# B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 t$ d) T6 X) x- b1 v4 E
| MCASP_RX_CLKFAIL
! p+ t5 C" e$ j1 N| MCASP_RX_SYNCERROR ! {+ E. d7 c/ C
| MCASP_RX_OVERRUN);
# [3 }0 y% x5 K/ r" |5 m; B! a1 Z. A} static void I2SDataTxRxActivate(void)
+ F, U2 F9 p6 O, M, V{
% m: s; v6 [7 G: V% }; C/* Start the clocks */
6 c+ {# A; N9 S/ L/ \9 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- @6 b8 v. x/ V r' IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" d- A8 ]# _% {3 X# f: k7 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 h- ?9 z. k# R6 X
EDMA3_TRIG_MODE_EVENT);; L( u( o* O7 s, `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " ]7 k8 b: B4 _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 j( \% d5 k e8 g# T4 u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; @$ I+ t6 j, Z8 L P2 S8 I0 C/ z: V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" ~( j' U# w K; `8 S! p. q4 C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" c' ^) \+ N% t0 kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; A- l" e8 i( R) X2 T) S) y" [2 \2 K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, V4 {% x- [% J* s: q1 Q3 S. z} . Z! A8 C" I( c X4 I3 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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