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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' l$ h! y8 {1 S m' D
input mcasp_ahclkx,8 v( W+ q6 W( z& g4 j& Q
input mcasp_aclkx,
/ }' Z% ^6 W! _: O! jinput axr0,
/ M; n. H' H$ A7 v, c- Q \9 J; X6 d
output mcasp_afsr,4 o( r0 |1 b" t& w6 @
output mcasp_ahclkr,3 |, l# Y4 A3 a% E
output mcasp_aclkr,! M* U5 c& a! H4 q2 r t
output axr1,$ c2 D$ j v4 G/ y* H) |- j
assign mcasp_afsr = mcasp_afsx;
, `% L: ?1 G) g2 z! N2 `assign mcasp_aclkr = mcasp_aclkx;
5 {) s6 L+ D0 n' r1 T; s7 _7 i& Eassign mcasp_ahclkr = mcasp_ahclkx;
* q* e8 |% v$ [! Eassign axr1 = axr0; 3 A& i$ C3 Z( L" n' Y$ ^2 \
% ~' [! q, u$ H9 X! ?0 ^! e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& I/ ^: ?% v: fstatic void McASPI2SConfigure(void)8 g& ^' N& t8 _
{
" `# e. c1 y6 `4 M, F, gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# H: C' y+ R3 z: `, x" v4 S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 Q/ J1 T* n. l$ v5 K" ?: cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ O2 W& b, k, S. s% T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# S$ y, g( Y+ S4 dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% x( T: t: p8 D) ?0 J7 g
MCASP_RX_MODE_DMA);- d0 ]3 _% Q% l" n9 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; z! m4 J' c5 i' a1 D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 Q8 ?6 r: z5 _* U* |$ BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
J% Z% A/ ~' P1 X& }5 w9 i/ ]0 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) h! P5 ~8 P: D- ^4 S# f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 o4 o6 W* b9 F9 \% s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* j( `- O9 h" N5 \4 MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 H6 _+ l5 I4 s5 _+ a* a; N# r9 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% R2 S, j$ O# K/ V, g& i" w9 p) x& pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' ?. D+ I& C. k. B: @ c# ]0x00, 0xFF); /* configure the clock for transmitter */- h# F W* ~& Y; [$ b& w ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& ^; e9 V' F" k- Y5 R8 v0 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 a. ^9 q7 `% f/ T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 m( ^/ j% P3 L! U) |$ F3 Y0x00, 0xFF);# `' Q; Y$ _( X) K
& J0 ?: B$ d, J2 H6 [/* Enable synchronization of RX and TX sections */
; K6 }- l4 ?/ R/ {& A" wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: A* J" [0 l* h+ P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ O7 H/ x+ d/ b- T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! u0 N3 J7 q. N& S$ @** Set the serializers, Currently only one serializer is set as
9 J! r& D9 Y( l** transmitter and one serializer as receiver.
# F/ |! t2 |; P* z# s% z*/7 @' O) R& {. @# M \. W ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 c, Z% A( g: M/ X5 f. X) \, mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" l/ u5 B9 y& ~6 |
** Configure the McASP pins 0 m5 z3 r0 ~6 [1 t2 P; b2 A
** Input - Frame Sync, Clock and Serializer Rx* A+ b J; i8 M j! c; c$ O
** Output - Serializer Tx is connected to the input of the codec 4 o: C4 { K5 i) l
*/5 {; @* s; w: _% Y" {5 }" k) }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ j2 W$ d: C: A6 w' [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 M a+ t: `9 T. _) [( Y9 s0 ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 `7 ?2 z+ C% n0 C' ?
| MCASP_PIN_ACLKX
. @& N8 s2 u- T3 h$ K+ I/ m: ]* s| MCASP_PIN_AHCLKX
* e- E, w! J) ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ I) l4 b% L0 F2 g( EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 A# ^" N( q) `( j| MCASP_TX_CLKFAIL
+ I9 }5 l7 e0 Z4 S| MCASP_TX_SYNCERROR$ a: _( _) C, O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( z9 l4 T: l; D
| MCASP_RX_CLKFAIL% z) r7 Q! ?' w+ K- p4 G0 L3 n: p1 X
| MCASP_RX_SYNCERROR
) A2 W4 T! Y: L- w/ L0 }| MCASP_RX_OVERRUN);
) ?2 c, t+ @8 ^} static void I2SDataTxRxActivate(void)9 w4 a/ `! Q# k+ `+ N6 l! k
{
2 N& \# V% [8 O i+ {/* Start the clocks */' C# D& Q& ~2 x* k$ g3 d) v3 q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); m K3 U9 z) [( | L6 W" R, ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 h' o' N% T* EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- F; f9 K: \9 R# C1 [
EDMA3_TRIG_MODE_EVENT);1 ^- ~9 H' u3 y2 U1 W5 v* p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 p; }- A! P% |; A# {# p, n% ^4 K) h$ K' P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# v1 j( H o6 P2 E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 S; p0 Y% a, y6 Y2 w+ MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ j- u- P+ v' x8 o4 S; z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 w" n) j5 g3 g& M" vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; h! t8 Y$ X1 J1 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 Q, V0 i4 Q% @7 N5 n9 Z% ~} x) d- G! d( D. @8 i: W; j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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