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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) K6 I# T- t% t% `/ [9 I& N* w
input mcasp_ahclkx,
. i2 g! f) i i5 F' m yinput mcasp_aclkx,2 l& i' G, X5 c+ i8 H3 y2 Z
input axr0,1 w2 b6 B7 _" o: p. j$ C: F
/ ]0 b2 K3 g, S* I, S3 I
output mcasp_afsr,
) O2 J+ h& c1 w, `( x! Goutput mcasp_ahclkr,
: |; b$ J1 k/ }1 S) z z- P7 Soutput mcasp_aclkr,
# I. O, X( O* {- N' S7 soutput axr1,0 f+ `4 R. X8 H0 e
assign mcasp_afsr = mcasp_afsx;
9 ]7 B2 [8 a/ K: k5 h1 f; ^assign mcasp_aclkr = mcasp_aclkx;9 Q5 q B2 r8 {; A) e, h
assign mcasp_ahclkr = mcasp_ahclkx;
2 k9 N* Y$ N6 U, _7 zassign axr1 = axr0; : C+ f2 b" O8 ^; @* k" W
0 [; ?1 b/ c8 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 y& e. T+ h9 @0 e
static void McASPI2SConfigure(void)
( Q" N% I* |# z{
0 x( G' h$ A; K' F3 TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ @: H3 |; O$ T$ dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 y. s! r- i H8 ~5 i$ |* vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; A0 A9 O \, q% m& H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 ]) w: G ?0 F* ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 C* Q' u& e1 c/ q. [MCASP_RX_MODE_DMA);
2 e! Z. h7 }0 u( ~( d4 wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* `2 d3 S) b' x4 n4 u. |/ A. zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 W4 K- l6 q* \. i. UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 O1 w6 q# }' I3 q) d" Q" Q: MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, {4 U% _- N/ ?* X- y# p& v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 r5 P5 W" r d: Q: N8 m: [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 a. P4 `- F* ?7 s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 Z3 g/ `6 N0 i8 A6 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 X! y$ I& i2 O* v! V& qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) X$ Q, h6 l5 h0x00, 0xFF); /* configure the clock for transmitter */* S3 R; e7 L2 A7 l, J; L7 i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) V9 O; n2 B3 I% WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% c0 u+ s9 a2 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- N6 ]5 f6 U! [2 w$ E. p8 z, m [0x00, 0xFF);4 `- m4 x/ L0 W4 U0 m2 w; w
/ @$ W/ ?. J. d6 D. W% c/* Enable synchronization of RX and TX sections */ , |. H0 B7 q; [2 F" G* U+ x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 }/ r. f# _9 j+ u0 n1 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- A: A) F/ h( n2 t" d$ a; q t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ o! O" k" U: G# y7 ^** Set the serializers, Currently only one serializer is set as
5 \- [4 R) E; N% @# {* q5 _* y** transmitter and one serializer as receiver.+ p6 Q3 A, [$ m* ^
*/8 ?% t, u1 A. I7 v% j$ |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' ^% v7 r' I* M, d" o- P9 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& q$ c# ` K% b3 [
** Configure the McASP pins
& I' D+ f! O( Q/ u** Input - Frame Sync, Clock and Serializer Rx2 y( N2 N* \' U
** Output - Serializer Tx is connected to the input of the codec
% q, [- O" |5 Y$ W*/
4 a# I- ^1 S5 P1 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! ]' _4 j M% A+ S$ c2 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 d' @6 E$ k( X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# i( |) b2 z, h3 f3 e4 c| MCASP_PIN_ACLKX: ]! R6 M+ m; V
| MCASP_PIN_AHCLKX) \) \, Z: S) T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: Z% P" T7 p6 Y t* _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % I- n' k! ]2 u2 z B; D5 t
| MCASP_TX_CLKFAIL 7 R# x2 q1 D& s2 g* ^2 P
| MCASP_TX_SYNCERROR
* l. R* L1 C5 [1 O/ s: Q% F. c) J* V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 S1 P9 |" Q" j+ b: M
| MCASP_RX_CLKFAIL) t4 ]. o8 w l
| MCASP_RX_SYNCERROR , I+ m2 l. N4 p
| MCASP_RX_OVERRUN);2 _4 [( s0 ~3 L) n
} static void I2SDataTxRxActivate(void)
, C5 G' X+ H% s3 s6 g. x# z{: k, N* Q5 w5 `% e
/* Start the clocks */) i; q+ @ N. O& B0 m# ~. |# L5 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" }% s% V# a- A3 ]8 j/ c+ w- H% V$ LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- E/ _# q8 L+ g. `8 `, N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- {: U( H7 a& y3 Y" Q: |
EDMA3_TRIG_MODE_EVENT);
8 {0 x$ }3 U5 o, V KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% C9 p) l9 Y4 a- ~$ n tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) O* F; |4 p9 `# J4 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ D& d3 k9 o3 W; y. s' ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 Z9 H8 W: D0 v' H9 E/ \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' G, ?- c9 v) e) z5 `/ y- qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) C, q1 u- o2 R3 V8 y8 }5 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 D; Y1 n' X6 Z: h
} 9 b7 r) @# ~9 r' O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 h w6 Z) C8 g8 ]
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