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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 G# Q+ B. q: _" k8 m
input mcasp_ahclkx,
6 T, e: S- r, L, `input mcasp_aclkx,
9 |- O7 i O% ^8 Rinput axr0,
' w" ~/ c6 [7 [% k
( Z- u" `0 ?/ Goutput mcasp_afsr,/ f( V4 q0 X: I
output mcasp_ahclkr,, f8 T3 |. o; N) y* \
output mcasp_aclkr,
; Q" \* A0 Z9 `output axr1,
! Y3 N. d, h) |( _( F assign mcasp_afsr = mcasp_afsx;
7 c- Y5 E- u) z* xassign mcasp_aclkr = mcasp_aclkx;
/ j3 @, a. t! \* q8 f9 r* bassign mcasp_ahclkr = mcasp_ahclkx;
' c- e! |# c# T: B2 E- I: Lassign axr1 = axr0; 1 J i# @8 N e" T3 {( U" R$ u( ]
4 A* C) G: G& Z, P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; ?# f* n8 F0 W& F' O; O* w
static void McASPI2SConfigure(void)
% X4 X% J4 z: N{
- ?( `7 [# B0 Q( C& G! O+ u3 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- @) i6 P$ c+ u# S8 O: e2 M8 s7 c: l6 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% P4 @2 k: ?* h5 j$ q6 a7 U- iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 b. P: t( O( a9 m5 {/ E1 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ q; z+ g5 @7 ]' u7 N$ kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- g y( T3 Q9 v# _& ^2 n
MCASP_RX_MODE_DMA);7 w9 c- t6 a+ h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& f T* }5 J+ B6 K' i& b) L) ?) S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ S8 K, ~+ r" ^. I& oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# f' `4 W; x5 OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 ~% Y0 k0 B; O: DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 G* @. _" x% vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 T7 {" ^& e5 i% B/ t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& W0 f3 y" o3 s) m- ]* _4 vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 ^) e. n, R- ?+ B$ L+ d/ FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 B( O) X7 |* \& b4 A$ W9 C0x00, 0xFF); /* configure the clock for transmitter */. I5 U5 Y1 `. N U5 m4 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 S. V: \! i5 k* MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 ~+ ]3 ~1 G+ Q" mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; f$ w; n6 w4 g0 L0x00, 0xFF);
2 y' r6 l" Y! V" J" |9 @
9 |$ \. Y5 \4 q2 ~9 G/* Enable synchronization of RX and TX sections */ 0 }, `' a h. r4 I$ o1 q7 Q& p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 g2 t# w5 I! Y/ EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 j; N$ n1 A& iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 U n/ X- l1 O: K! ?** Set the serializers, Currently only one serializer is set as) v/ r' W. p+ V" w- i' s
** transmitter and one serializer as receiver.$ f L1 z! i$ C5 F
*/
0 w' d/ s" C* `6 R: h* {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 y8 O, x; J3 h/ |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* r% p# ]; f- a; [$ u
** Configure the McASP pins # K6 s0 ?( {- p1 y: x
** Input - Frame Sync, Clock and Serializer Rx
4 w7 y& W' m+ v. v** Output - Serializer Tx is connected to the input of the codec
% E+ ]2 v/ U* T1 L*/
1 G- u: s9 }* P4 {7 v3 u* UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ K4 `+ E: A" i. P$ p7 u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* h6 }6 V1 U3 }# N+ uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% N% J: |3 ?2 P5 N1 n
| MCASP_PIN_ACLKX4 Y0 g% _3 j+ `: p8 g' q& A; ]
| MCASP_PIN_AHCLKX
( r( ?5 ]. k, y( X8 N t1 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 _" ?+ C$ P* o# z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: R2 F$ e+ Z; N* A| MCASP_TX_CLKFAIL # d: H5 \/ b; q0 G1 E2 f
| MCASP_TX_SYNCERROR
; H. Q9 v! j7 k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! a/ @: k( U! N% S( {| MCASP_RX_CLKFAIL \( x# f1 y6 c, ?
| MCASP_RX_SYNCERROR
3 E* V+ O8 Q- @" ?| MCASP_RX_OVERRUN);/ Q0 T* D4 `- l8 ^( w/ l$ U( l$ W
} static void I2SDataTxRxActivate(void)6 Q& e9 `* V% v# B2 H1 [
{9 F Z4 n; P- }! r, J6 ]0 q- _
/* Start the clocks */
2 {" h! k q) U0 t2 ~# y8 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% z& j! [1 F3 G$ ]" }4 ^* M/ N( j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ O$ P' O4 S! s3 ?9 f Q2 X2 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) g, d! P3 V, Z7 r* U
EDMA3_TRIG_MODE_EVENT);
( x$ q3 u0 `. mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! c' d! Z8 J0 {3 u6 WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( i- h6 A& O# J' S" {% r9 E) _3 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 l! [( o3 }/ ~3 W2 D, Q2 U& ^, BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 S8 [ k5 L4 v5 N0 x! u% L$ }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, k* ~& ]4 a- z8 ]- Z0 M3 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; O& F* \' M7 y3 l$ d$ p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. ~/ ]& `# B$ M0 O' [$ `/ E# m
}
/ w% z; n. t, k6 D, z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) A9 ]/ |% ^- K2 g- n
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