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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 K: h" ?* J* [% ?$ h
input mcasp_ahclkx,: c* L& {# o% Z
input mcasp_aclkx,
8 N, x( Z- j9 n" [1 `1 ~. cinput axr0,
0 Z$ g9 d: Y5 o: W: m4 [: M/ @6 _. H4 d# S- J6 B+ H, s+ O
output mcasp_afsr,
( [' q4 O! J' z/ _! U7 xoutput mcasp_ahclkr,7 A& B, h; f0 `3 G
output mcasp_aclkr,6 @# ?+ \. e. Q/ d4 d% _
output axr1,
0 \) K% N5 O/ B; ~ ?) @0 P6 Q( }2 N assign mcasp_afsr = mcasp_afsx;
3 [; ~& t' G2 Z! Oassign mcasp_aclkr = mcasp_aclkx;
C$ W2 U) z# w3 A, b" Sassign mcasp_ahclkr = mcasp_ahclkx;
* H1 ~- ~% z0 d' p6 Jassign axr1 = axr0;
) i! \( z6 G2 }8 O; o. @! \, a9 c% b, @! C9 ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- \/ i1 r. M$ k5 v- {static void McASPI2SConfigure(void)
/ ?1 H. X6 A; }! n% ]) U{* ?7 |3 A6 Q/ s6 n3 E. b( c% X- `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ Z5 }5 W8 x r5 r2 f! L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 q9 q& [ p8 @9 ?+ ~' q3 i0 g0 WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 x+ V4 F, I& F" @. d! w; BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. c' ^8 I/ G V$ S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" m( D4 N5 |7 `( M) qMCASP_RX_MODE_DMA);4 O3 p0 J& c- W0 o& v' [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 R' c8 @% R7 ^4 w* {/ {0 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! p; a v5 ?: W: s; \* f# Z$ AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " y" x$ U& Q3 N2 j: o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! _9 u! N7 z' Z" N, V. IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ J5 a7 A$ ~4 G/ i" H! p$ ?) S3 H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) n* P$ b4 G* O- S/ {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 B3 ]; o2 P3 ^ _) JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 Y; [. ~+ j; f4 K- T" P# X2 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% u# J( i6 p& V5 x0 a/ h0x00, 0xFF); /* configure the clock for transmitter */0 X3 s4 j* a" l" S( C( u8 C3 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 n) _( m; L1 @, ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, z7 q7 o" x1 `$ t. vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 |* o/ ^9 D. V& E0x00, 0xFF);5 a( a% W) z4 u, x
6 G3 s+ r8 u8 `) v7 O [; y' P: w/* Enable synchronization of RX and TX sections */
/ X. i& @- A2 h1 N- a& G+ O$ S# c, B( VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( o$ K/ i Y% N* ~( f. G8 j& T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 l# b$ L I3 S4 Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
T, _1 ~- w8 x) V- X3 o** Set the serializers, Currently only one serializer is set as
5 V0 V# W; M( ~+ r5 S** transmitter and one serializer as receiver.
' u C( U! a; v+ G# K+ A: h8 G*/
' _+ k) d0 T9 N' Q j W# jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- f" z" g, B* u4 m% J' d% r/ ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; i( {, m" m- N. S c) m# k! y
** Configure the McASP pins
2 ~9 E9 y0 T/ A& g( J' W( s7 O** Input - Frame Sync, Clock and Serializer Rx8 c8 \6 @! Z3 N- Z7 @1 }+ p8 k
** Output - Serializer Tx is connected to the input of the codec
w% \1 g2 ~5 D% O5 C" m*/; @: v+ Q/ V$ S, a" G) p$ M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( p& [- v8 l# [ V/ r4 N5 @. Z7 v/ d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 }! t7 |$ T3 d, f7 p2 G. L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% r9 O. W+ ^ J& P! X| MCASP_PIN_ACLKX2 W; M' F3 P" n, D2 r" h6 J
| MCASP_PIN_AHCLKX$ M+ j7 z$ y+ b' F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* G0 l& H) k2 W* }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' N7 ~6 q* G x1 i) f/ X| MCASP_TX_CLKFAIL
& E" b+ z$ a3 l/ \; W% i4 _" t( Q| MCASP_TX_SYNCERROR( {- [" Q; I- E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 V. S9 h8 q( J4 e- ~ h! D
| MCASP_RX_CLKFAIL: r7 R1 X' S8 C# s4 E e' t
| MCASP_RX_SYNCERROR , ?# m0 K {6 ]6 I$ }$ x
| MCASP_RX_OVERRUN);
+ k2 v$ `+ m" O9 v} static void I2SDataTxRxActivate(void)
- Z( c* O$ }) p{
, ?7 x0 a$ \/ _ Y: s/* Start the clocks */4 G. r0 i7 E$ K/ d- m" A" F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* f. P; }" d s' i& w8 z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# J0 F" a& [, \# vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 e' h' U/ M5 a' F% ` d# S
EDMA3_TRIG_MODE_EVENT);9 }* ~7 ]7 t0 c) A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / A5 K+ w. E% A9 U* X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. s* }5 r0 P( |9 Q: _2 D: U& WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 g/ [$ K2 ~6 a9 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; k; M8 c8 `/ ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 |. i: I- y- b _% r6 h/ |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
y* `% t4 k1 ], E6 c/ Y3 FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 ^1 \. a5 N6 _1 i: T6 w2 I
}
# A9 H) W _" P* z( _! y6 t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 z, J3 l( ^. |" S9 L' Y/ O
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