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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 R' h! V! T# _9 M5 Z" ^- X$ y0 Ginput mcasp_ahclkx,7 O7 \8 m+ S( `/ Z8 Y
input mcasp_aclkx,
! A+ E# o1 ^4 L9 l/ g0 uinput axr0,0 n7 J5 @6 h: ]
9 c& a9 p9 ~4 `: i/ f) V: D
output mcasp_afsr,/ r9 m6 |" {. M, J8 K$ z& H1 n6 C! G
output mcasp_ahclkr,
6 J% K7 W5 ?: N- U$ Q; b2 A, joutput mcasp_aclkr,
! a/ O0 t* @5 J, N* J# i/ H3 Voutput axr1,% w* C( k/ p; |4 P; m! A
assign mcasp_afsr = mcasp_afsx;5 w% P$ @( C* {1 a- a. `
assign mcasp_aclkr = mcasp_aclkx;
- x% y5 D4 i0 Y5 U. a( P$ Xassign mcasp_ahclkr = mcasp_ahclkx;
8 S* ^" Y3 v% g/ y9 w1 k( Oassign axr1 = axr0; . P- N1 b" T4 e, H- b, o0 D
9 w# d6 q* R& T0 R- b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 b6 y; Q0 Q( W9 W( Istatic void McASPI2SConfigure(void)) f& Y* T: q1 A$ p
{8 v! S* ?, z2 i6 q" T0 d) i$ s' `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 T+ b+ u" D( k4 y% |* BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: V6 p4 I# a: Y( p4 U; D3 Y8 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; m8 s# s! M( A/ ~2 v% [3 B( c9 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, @$ {0 d! o7 I# T/ ^& y/ w+ S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 s0 d: ?, p: G. W* E
MCASP_RX_MODE_DMA);
! J. o0 P/ Y2 k: H# Q- g1 iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' B' P5 E/ M9 q; b/ y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* h8 K6 t- Z3 o) l4 FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 p; e4 s2 ]) v" b2 y U S* ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ c# V$ h# n2 P- r6 H8 ~) UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , n2 w( |* }. e) W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: _; f7 ?( Y, n! iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 @% `- V3 T( I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 K8 e! ^8 O- `4 i g u4 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- p3 A+ B0 h1 g0 ~) Y( R
0x00, 0xFF); /* configure the clock for transmitter */: j* V2 c9 p p. F( }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 V" D. T! ~, `- U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # c5 t4 T; Y3 ^' d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
J3 j7 j) E1 H0x00, 0xFF);
0 @, O$ q. b3 J% @7 v6 I5 X3 e3 x4 V5 o5 h$ v/ I7 S
/* Enable synchronization of RX and TX sections */ 8 d! Z2 @9 G& {2 i5 f2 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# e+ A0 i" p8 f' D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 V1 I6 W5 u- r9 j: r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 W( h! D/ G/ s. ^; c
** Set the serializers, Currently only one serializer is set as
$ u. j* _* L" H, c+ a** transmitter and one serializer as receiver.
0 \! w4 V+ D5 a" k4 Z1 D*/
. d @9 }- o7 m* R! O; z+ y6 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& T: a$ U ?9 c' L) r' i/ jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ m2 @" Z: V. _
** Configure the McASP pins " I) F$ N; t- v- H& a: F
** Input - Frame Sync, Clock and Serializer Rx
/ w e/ g" S$ q3 U* K0 K** Output - Serializer Tx is connected to the input of the codec
H& e- ?) T4 ]; p*/
- {0 S; m" k5 C( m% E9 L& oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ A% j9 T9 Y* t5 G) J* I, T% v5 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 p) g: U: d6 j! C# \9 v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ {- z* F4 ?* ~- ^* g9 m+ A| MCASP_PIN_ACLKX; y0 ] z, @; b* @1 o3 N
| MCASP_PIN_AHCLKX
B: }! Y/ I# d o8 w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 S% E) G4 _8 {6 I& @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 t* m7 {0 T4 i0 n1 g( c' d. Q| MCASP_TX_CLKFAIL
8 m4 ^6 U8 n: c4 B8 s( `5 @| MCASP_TX_SYNCERROR
9 E# L# ?6 V ?7 f0 x5 @, j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' L+ f( H7 n5 ~( O! s' \# ]) G& I
| MCASP_RX_CLKFAIL
+ L. M' }0 W0 S, W' P. Q: V| MCASP_RX_SYNCERROR ; J, v' c4 }+ M9 \$ b) L
| MCASP_RX_OVERRUN);2 K; h1 `8 I, n# s. ?
} static void I2SDataTxRxActivate(void)
+ t1 e6 m$ Y. w+ E- H' i+ N{
; R: k& x n5 k: L0 Q/* Start the clocks */
" n0 ?4 u6 h' _9 qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 N7 T/ C' t4 L- S' ?+ z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 x) `* Y4 S' P7 P* K) U) W, p! M" P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* e k; j% X& U \4 _EDMA3_TRIG_MODE_EVENT);* I1 Z% T9 }* m. F1 d) c9 T7 T5 @! U; j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 T u" g- E8 I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 U; _% `5 S L9 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ r a' N5 Y" ?3 ?2 xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; u' w6 b9 A4 v( f: n. E! gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( ]7 E) ^+ t( V% V& PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" a! a Z: Q# U8 \. f" H! V7 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. N8 q- r1 P- Q$ S1 ~7 Y} 3 |+ R( y: Q+ J7 j7 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. s2 R; ~5 ~1 F; y1 O1 E
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