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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" s; w1 x# \$ Z3 c, a: j+ einput mcasp_ahclkx,
) A9 @, A1 V; i/ ^# Q) E& i( winput mcasp_aclkx,- B- S& ~9 X- Z) O
input axr0,( d3 `$ r; {4 a. Q% b5 }: e9 ^
" e9 P# c$ f$ s7 koutput mcasp_afsr,
l7 \5 X+ j& E& goutput mcasp_ahclkr,4 A! H) L9 {- [2 L
output mcasp_aclkr,
6 ~4 F# K" X w, X0 Ooutput axr1,
6 d) I K" k7 w! V$ T ? assign mcasp_afsr = mcasp_afsx;9 q7 r8 E M6 |* Q' O$ ?
assign mcasp_aclkr = mcasp_aclkx;; Q+ o* E: k" F2 `. p1 \& B+ _7 V
assign mcasp_ahclkr = mcasp_ahclkx;& g; M: {! O+ W
assign axr1 = axr0; % _5 o8 R* M4 @3 I
; N3 O: \, P5 S2 F7 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 u2 k8 L9 E1 v) g% M, Astatic void McASPI2SConfigure(void)
( ~. P! Y: N& ?+ o4 l# v& D{% Z" T. H2 L9 m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% `4 H$ n6 O& D" y/ y% `% i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' e( ?7 F7 f: T) C/ p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 }& }7 A- {5 p" T3 T* w4 }/ c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! R7 V1 F1 l8 A8 p) _ h. z! L- v, ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 ~! t4 V; b, z2 d( G! P- r7 W
MCASP_RX_MODE_DMA);6 `; B) r! O* q* j* `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ^7 |: D# r1 S3 `/ |: ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 H* P7 j) |" h; `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * {! o$ [ K- P! _" N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' d0 F4 s4 n& m3 }5 r, q5 VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! e: ?3 M& |1 b, N: L: q6 G: `1 SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ U: f% i, B! Q2 f" \1 \2 eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 X* _8 c' M0 B" c2 ~, i2 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 r5 W" m( G" e3 e+ e7 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 A* E3 s1 ]) Q2 C5 V) ]4 ?0x00, 0xFF); /* configure the clock for transmitter */6 g/ F" z3 p8 _6 F4 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); l& G3 Q" w$ s5 m4 e1 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ?7 u2 a' p1 L9 Y) o7 F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 J3 Q7 I% P- v+ j$ a8 Q& \0x00, 0xFF);
, f5 T7 B4 j. k* R- k u. B5 J, o4 P1 L
/* Enable synchronization of RX and TX sections */ 3 m$ H# p/ t2 I6 [- t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, h5 o+ u! g$ I% Z' n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 }9 k+ N' O( C" ]1 m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** J6 a6 _4 W; ^3 Y" b- w* [
** Set the serializers, Currently only one serializer is set as6 M, u( ?( Z" @' N
** transmitter and one serializer as receiver.3 p2 }% w7 B& B' `1 q+ @: O
*/
% l/ L' n8 H% W$ }4 p9 c9 ^+ M$ OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, H2 }( O1 ?8 r9 \: a+ h0 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. d1 _1 ?. k G( y( l* t** Configure the McASP pins 6 c1 b# }, R( m5 G/ i
** Input - Frame Sync, Clock and Serializer Rx% L8 F. ^9 D; D3 h$ Z4 T7 P
** Output - Serializer Tx is connected to the input of the codec / Y# o* G; R* _* f
*/
# z6 v, i+ i* B9 M; HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 W6 [, Z3 `" q/ a) {# w" g" t x. \# FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 j- k) ?% D. \9 o: Q) P8 TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ C ~3 X7 T5 P3 M| MCASP_PIN_ACLKX
% Q6 b1 i- w y8 R$ ?( q1 ]' `: `| MCASP_PIN_AHCLKX6 f, J% N' C( H, V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# s, p+ T4 ~5 {$ L1 ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 @+ r3 |' K" W; a% f3 ^9 T+ X| MCASP_TX_CLKFAIL . s9 x" n4 W4 c P$ F3 b
| MCASP_TX_SYNCERROR
f7 T# z0 l; K' z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; F: @4 J: y; Q2 W7 Z3 F: Q| MCASP_RX_CLKFAIL
; N j+ L. U, L( s$ I7 \| MCASP_RX_SYNCERROR 8 k' m1 x- i$ R% M. F
| MCASP_RX_OVERRUN);2 K& x9 F9 F7 H, X. |
} static void I2SDataTxRxActivate(void)2 ^8 J0 \% {# f1 E2 @: `
{
9 R! j" G }4 I/* Start the clocks */
5 g! Z0 d: w( {' k B/ BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% M( w1 i" h$ }- X4 e; U* W. XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ t ?2 _' ]: a- t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
T# \4 n; k8 m+ U! W9 B+ {+ iEDMA3_TRIG_MODE_EVENT);2 b* L! d; _$ j2 o( H! d( A9 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ?( B, [5 K7 P% w3 c+ Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 c4 m# S" a/ o. T5 L0 G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; g" N9 t, @( F( S% D1 `: o4 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 K! t3 i0 r/ f9 X: P6 Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 _, ~3 P" f4 G& g% n) o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 i8 s+ k1 O, d5 }( v V8 b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 r, B9 a1 J: h! ]. P
} $ |3 f" @; L Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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