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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# R* D2 f4 r' z- T, _$ ~input mcasp_ahclkx,
/ j+ H/ i. e0 |9 L5 q0 dinput mcasp_aclkx,
* B: x+ a, `/ j% n. yinput axr0,3 a9 T. s! m, ` p" g
F5 S ]7 ^8 K9 I. G
output mcasp_afsr,9 a8 }- i% q7 q) X" i* g9 j- [
output mcasp_ahclkr,- Y. k0 V5 G( Q* Y
output mcasp_aclkr,) j. k) g7 ]) Z9 w$ s. ]
output axr1,
* \; z( W* N# Y. A3 w/ J0 W/ N' l* L assign mcasp_afsr = mcasp_afsx;
3 u; p" _5 \# [% s7 G( Tassign mcasp_aclkr = mcasp_aclkx;
h4 {# ?& |7 p* c8 \- S Hassign mcasp_ahclkr = mcasp_ahclkx;
! N* K9 ^+ F+ }1 B- l% \( Q7 g' tassign axr1 = axr0; ; Z3 G4 B8 j% m9 S% r5 B
# w$ B4 g. s! k% s( d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( }. g$ Q! C+ t; ~" C: f
static void McASPI2SConfigure(void)
# |* H) s6 M9 M{& e& G$ r$ r; j' f; }1 k" a7 s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- c6 O! }) G* N& h4 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) i" h9 d/ {- I7 N# ^4 Y( ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 j, f% `8 v+ @3 y1 @" y' R3 G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 l) I2 m$ K/ P. [/ J. N0 z9 f; vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: l. B" I! z6 U8 _7 {2 _MCASP_RX_MODE_DMA);2 s) `# t- X ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ ]. _$ Z9 v2 s+ l' o# f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 q6 W D! U- c3 }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ g. a4 U7 U2 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 x$ P3 a8 X/ ]3 m5 }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 x% ?+ H) O/ A2 Y* F) NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: @' b+ J: @" ~+ Q! L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 E- S4 d s" O& l4 L0 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! K: p! b" G& X$ f" m& Y% w KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! H& Z: s; F; d0x00, 0xFF); /* configure the clock for transmitter */, X2 q |2 ~; U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& P) P# k& ^% r: p: l/ G3 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . [; o, [5 ^; b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 Y; w* a, b5 t0x00, 0xFF);
7 ], g$ O( B% n; w; @" T7 l* V" d$ v8 ]
/* Enable synchronization of RX and TX sections */ & L5 h" w, Y! Y2 e `! u2 Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ G. A* A1 H# N8 n& B( J) pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* Z' j+ ]7 n9 e2 ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% T- c# K" d- H. [** Set the serializers, Currently only one serializer is set as+ b" n3 y1 ?" s1 k( o: u1 N. A' x/ r
** transmitter and one serializer as receiver.# k0 r% L! Z- w) i, S9 P \. }
*/
& y! J. c; k: R& g& [5 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); e8 V$ c3 n0 ^. N0 _6 j. Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. ^" P3 r# I7 y; N% A$ |/ k** Configure the McASP pins $ B4 d' w: A8 i, x6 {
** Input - Frame Sync, Clock and Serializer Rx5 N) t' L s5 K; m3 N& R
** Output - Serializer Tx is connected to the input of the codec
- a8 A) g: v$ C*/- i" ^; t% U( o1 e/ s+ `3 X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 D0 m4 n; s* q2 j2 [0 l! QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- [/ z1 R; p1 p' q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' B$ v& |% N( e; \& Q C| MCASP_PIN_ACLKX
, o$ c' x5 ]2 \! {$ _9 J9 r| MCASP_PIN_AHCLKX6 Q7 {, E1 i; Y) F6 j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 M Q: P" t( a6 T, K/ U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 O7 G% U. `9 @9 L/ }| MCASP_TX_CLKFAIL
1 W# L" D8 b1 Q/ J' F% E| MCASP_TX_SYNCERROR. b. c) V6 G P5 Z' i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / Z+ O! a) i6 \0 R0 h" g
| MCASP_RX_CLKFAIL
: ^8 T* R, J" w- _6 K; D5 _4 ]| MCASP_RX_SYNCERROR
! d: z* u' s4 w9 ?| MCASP_RX_OVERRUN); g6 g) b1 J3 [: j% F" F+ v: y
} static void I2SDataTxRxActivate(void)- _( |# I6 z! q! @% R( |
{ n. Y0 U3 G' r! |5 h, O% V
/* Start the clocks */
" \6 }3 [$ |* x2 P% U- ?% a& gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- i6 |* J4 |6 p; K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# |" S* X8 @1 v' FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& ^$ Y$ X* g( |( U) I
EDMA3_TRIG_MODE_EVENT);
2 d8 P0 ?" h; d* i% UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; d8 l% ~5 f" X2 i. S- sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; r% x0 s; w$ X: V5 o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 C8 Q! a0 X& y# f6 y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* s* ]# v+ q" z- F0 Y: J: ]! ]6 O$ Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 v4 I4 ]$ D& y5 ]0 j! W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% m& u, G5 I) g0 ]0 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! n& `; |( u. Y( I
}
9 A+ i }4 P+ J. Q/ q* |0 B3 A1 b% Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 N1 V" O/ J: B2 H b/ J
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