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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 j# t( k$ R7 a" `# Y S8 N Hinput mcasp_ahclkx,
4 q* A' |; q( D% e1 Q ^- ]# R. Oinput mcasp_aclkx,! e0 M* E ]+ P- ^
input axr0,
2 h" X" {* u0 H& v0 j2 }0 I: c3 i& G g1 O
output mcasp_afsr,
7 |( d! |' l$ o% y/ Q! ^- `" Qoutput mcasp_ahclkr,
1 ^! e7 r Y3 N) Q! Poutput mcasp_aclkr,
/ h% Y* y; j" q( h2 U. `1 {output axr1,
. r6 J7 Y! e/ V- c assign mcasp_afsr = mcasp_afsx;) A5 V: W1 y y* ]! J" V Z6 G8 K
assign mcasp_aclkr = mcasp_aclkx;
/ w" c) g% i, a# T: t& R* Oassign mcasp_ahclkr = mcasp_ahclkx; S1 w" t7 M# s+ N) M) [; b, {- ~
assign axr1 = axr0; ! m8 p, e$ }( p* U/ b2 l {2 I
" [$ @" c( c& A- K3 [( a+ v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! U5 R; l0 K$ sstatic void McASPI2SConfigure(void)
( U3 h" S6 M% W! c{, G a) t4 r: ]- x0 A7 `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- ]$ z# L" U4 t9 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' B5 u# t7 r* v! n8 ~% F$ _9 r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 m* ` v9 v6 @9 ]" c, b( D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 K# X# t C# q" _1 B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 G3 J# x1 c2 W4 f; y- UMCASP_RX_MODE_DMA);; B' Q& I, r% B' @% P+ Z# x7 M2 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; @$ }1 V# X1 T7 Q3 J$ U) ^! \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' I9 ^6 u1 s6 j1 \6 z3 N5 [; [/ N d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! h. o3 n2 c& r$ m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% V3 H, V6 e& R' T9 r0 Z) XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ J+ G0 I( E. l1 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, n: a7 q" a+ P5 s) j7 U$ C9 p8 S$ @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 {; `; A9 ^) {( e: \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) n& g# M# ~9 X6 o. L' d: `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' o; V3 s4 q* \" Y' g# }9 t) X6 m8 q
0x00, 0xFF); /* configure the clock for transmitter */
d+ L0 a5 _6 X! G& u `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! k$ \6 G) O- n5 t5 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
k' F5 s, }) y7 a4 n- NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& t$ L9 t7 Q* S" x
0x00, 0xFF);& x6 L; v3 t" [# ^) K
! }& b3 k5 U9 d0 O5 K" T& k/ r/* Enable synchronization of RX and TX sections */
- Y2 i" x7 O% H, P* P4 l1 N) l3 x8 VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& g& z. y3 g8 Z8 @" h5 H# Z' n* L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' i" P: l3 [1 ~7 N/ uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. i, d3 `1 k) e
** Set the serializers, Currently only one serializer is set as
0 [+ a; @, l" Q. E) g" G' l** transmitter and one serializer as receiver.
3 e7 p8 q5 G( q9 P `" @& i*/, [# f; Q z [7 N2 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; \+ t& ^- K% hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. ]# k: u2 i% |& k0 S* U: }
** Configure the McASP pins
. ?) i) p4 K$ e, [- v }** Input - Frame Sync, Clock and Serializer Rx
; W# _. @, m0 j** Output - Serializer Tx is connected to the input of the codec
/ i+ H7 c1 o7 W, D/ c1 W9 @*/
, D4 G- g) M0 B5 \ I1 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' K' X) B6 e8 NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- D0 o- b9 R4 B# j. n# ?9 e9 ?# q5 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ M0 H2 w U. U$ Y+ H| MCASP_PIN_ACLKX
) w# Z9 f/ J* l5 x1 F2 {% ~| MCASP_PIN_AHCLKX2 S/ P3 E' c4 `: ~: I7 a# A) s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) |' N0 O2 L6 O V' s+ N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! M5 V" k2 x6 J/ x- n8 m
| MCASP_TX_CLKFAIL : f% g, D- j9 V7 M
| MCASP_TX_SYNCERROR
2 I9 o0 E4 x, f) T5 ]5 F# v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 Q1 k0 i: i! d
| MCASP_RX_CLKFAIL
2 b# I4 S \) R6 r! W {| MCASP_RX_SYNCERROR
, x; y( V6 K5 V& i7 t# {2 {9 Q3 b* t" C| MCASP_RX_OVERRUN);* L+ u3 E/ B; a! l% T
} static void I2SDataTxRxActivate(void)& Q6 L: e% l$ H6 v) C2 T# |3 H& w
{
& @* Y1 ?( }5 E) H1 \7 ~* r/* Start the clocks */
* K: i& d3 F9 I% x+ b8 j) MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& m T( Y/ u" nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, L {4 y2 R4 G" B' pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( G n) n; @: S8 L& m) N m) R) u6 E0 bEDMA3_TRIG_MODE_EVENT);
$ a" b! \, r8 n( C" n6 w, ?0 J% vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - F! D( C" C9 p2 }* z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 T5 z% A, E5 Y5 R: R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* ?; q p' U7 ^0 z5 F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- z2 D; e) I* W; y9 Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 X7 O3 ~# n) [& h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) ^ B3 _3 l @5 z. E% W s7 O4 J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: K" {" |- u F# V# N3 U/ q
}
( @" Y' _1 }2 z4 h' l" N* X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ l& G* [; {! A
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