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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# k( ^/ a6 [0 s) V) \' X# ]
input mcasp_ahclkx,
+ M# P- l" l6 ~5 b- |) v: Hinput mcasp_aclkx,
2 F$ f; }8 S- minput axr0,2 U" G9 ]& s) ^5 i+ v
- k e, B6 h% M3 m8 Q8 T- b3 ]output mcasp_afsr,
, H; O* u; @. c. M+ boutput mcasp_ahclkr,2 L) J' W% ^' n' u Y
output mcasp_aclkr,; `0 ^/ S* S0 D+ Q. G$ A. C) l
output axr1,
+ G' y8 y, w$ L/ \2 O1 o assign mcasp_afsr = mcasp_afsx;
2 K; m) ]" w8 J6 [; E( E& ^1 Xassign mcasp_aclkr = mcasp_aclkx;
L( \3 p2 y5 f* vassign mcasp_ahclkr = mcasp_ahclkx;
0 n' U" c% Z/ T, F+ y" massign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% i2 g. t" d8 U2 {, p2 rstatic void McASPI2SConfigure(void)' T) u+ [3 W8 _8 U- R/ ~3 E8 S7 X
{/ e4 P& h1 ^% n$ U6 T% F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 t" E) r' t* y) n' _2 SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. F2 ]; [! T: h, J6 P$ ?5 U) a" L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& |4 Z( g W, |5 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. Q; @ d% @: V! J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( g# O! U# p: Z5 y" Q) M; L' G
MCASP_RX_MODE_DMA);
4 v) T6 Q- E3 R7 `: p% zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. s$ P4 }$ P, F! ]" n" G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; x: o/ _! n) i" I2 W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 W2 u( S% l4 t: f" R' j) \: y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 j! b7 ?( ~0 r1 ?- H; tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ }+ l5 S& z+ T7 c* x% C+ p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ Y g) b) A( ]( I; |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 S, T. Q0 L8 n) R4 N- ]9 BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; y: I9 q4 F( k" ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ }# \& P' k+ q' t8 m0x00, 0xFF); /* configure the clock for transmitter */
, M2 w, l3 [' E3 w6 @, ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, o8 A- `1 A2 l7 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ a. w7 T# O" F4 R, GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 Y' J& `; w% u3 t( j& u
0x00, 0xFF);8 r6 E5 p+ W3 k# r: `7 v1 u
" B& p1 \5 ?, W9 m( F* x3 y/* Enable synchronization of RX and TX sections */ # [2 j2 g. M2 ^2 s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& L# o) Y1 j9 X- Y; N1 |/ oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 r, k$ K: S4 j& x' i' `- J8 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 Q0 w% p# ]7 g* i& A: R; h
** Set the serializers, Currently only one serializer is set as8 F4 O( r: c9 _1 ^' o |
** transmitter and one serializer as receiver.
' a( Z! K% K0 }: i) u* W; o+ \1 \, t*/% K, ~, L! D+ N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* m# x2 }! g5 R4 u& P, |: N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 r) A6 P' m& N& R P2 d6 u0 t
** Configure the McASP pins 2 e# D/ l2 `+ n+ g: S9 V) ~
** Input - Frame Sync, Clock and Serializer Rx9 ]2 Q, U4 x' k- R, U* L; J
** Output - Serializer Tx is connected to the input of the codec $ f( x. n& ]1 g% @* D
*/
* ^7 S+ ~' F4 a3 h( G3 R aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# R: {6 X4 j. T1 J4 K2 C% u& K' t0 y9 }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, Z7 w/ z9 Y |( Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, [8 p" E: o# q2 w; S- U S| MCASP_PIN_ACLKX3 B" W0 S/ Z$ s4 ^. u
| MCASP_PIN_AHCLKX
6 E: b% Z0 ]! o) [& B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ p) |5 f' c' v4 F$ m2 ~$ YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ T% t E5 K$ P( H1 Z
| MCASP_TX_CLKFAIL ! I( O4 R9 C& C4 O s. o
| MCASP_TX_SYNCERROR# L- y- z/ a6 C1 |4 R2 g. U; q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" v1 o' O6 ^" y, V( B1 `& a| MCASP_RX_CLKFAIL
: x( Y s! \4 x; b| MCASP_RX_SYNCERROR
1 c- \) U" o% K4 L( Y# ~; D| MCASP_RX_OVERRUN);4 H7 E) F0 Y8 k( T: M
} static void I2SDataTxRxActivate(void)* l0 ~$ _; V( {, S# {" w0 [) ~
{
0 i' @- @, L+ c6 ~8 x/* Start the clocks */7 n: k4 M h9 j5 M! r$ l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ Z9 L+ N2 { I3 Z/ @; [1 V/ M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. f5 Q5 p6 q: I, Q/ Z% e7 o$ u7 c k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ E# G7 E5 H3 S) O9 j: c6 r
EDMA3_TRIG_MODE_EVENT);
' r' f# s* t( x% r& g- bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. Y4 |4 ~+ A+ U8 N3 O' VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ m4 K( ~) N4 W3 c6 a1 K3 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# k" c7 ~4 h! ^3 [1 z8 ^$ B) d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 `2 r- @8 O n) n, b3 o5 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 l4 A. n- E) |) @& Z% wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& [- D' f, V& [$ _2 J/ {$ r5 Z0 Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' c& V2 W# O: _* M# ^0 w9 w$ t
}
, h* I, I* S# i% u& M8 k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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