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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 X+ t7 x0 D% Y: ~' v1 I
input mcasp_ahclkx,0 G0 X! R) q7 [! g# ]. v1 Q. v
input mcasp_aclkx,+ |2 i; X0 S# s h1 X# o
input axr0,
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8 k. g! q1 l- i( P" q6 Z) @# ~0 W& poutput mcasp_afsr,% S( w6 m7 n \% V( X$ E( d2 D
output mcasp_ahclkr,
1 `1 E5 r) Q4 S% Y# N% _+ goutput mcasp_aclkr,: Y; O& }! E3 Q1 F& ]! e8 ?" A
output axr1,; y% q9 q) e5 T8 [4 ~% M: e' K6 }
assign mcasp_afsr = mcasp_afsx;
7 f4 u- Q/ k: O8 Uassign mcasp_aclkr = mcasp_aclkx;
" K" ?" m$ P7 \3 Massign mcasp_ahclkr = mcasp_ahclkx;7 q- G1 f* @* `, G2 [: ]+ w
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 K$ `( i0 Q4 e( l T% J9 i
static void McASPI2SConfigure(void)
4 j W9 Q% T& Q* n: w( y' `{
; z( z/ Y5 n* a% I5 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ a" h/ P6 x1 z, r. S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 P8 z P, l8 _ t- n5 T @: v5 u8 ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 |6 H* e1 ~3 p% w5 B+ Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' q. u" @1 C6 b! J4 `. U9 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) o- Q" I/ j2 q% F; E, C
MCASP_RX_MODE_DMA);9 A8 o& V' u. {- R* ] y; Y. ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ C& C" f5 \& ~) Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: O6 E, }3 M/ S+ Q( y) e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * ?# h( _) }" T& H- j" O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 f9 |; q g) ~. v1 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ j* ?- p" |+ Q' P3 _6 [6 @6 f7 dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. `' S+ |, y! C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 k. \1 t+ s$ P* ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 u* i+ Z' K4 l/ s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- }2 i' B! z4 P! c1 i+ g0x00, 0xFF); /* configure the clock for transmitter */
& p7 V# D0 v$ z; P4 K0 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 v* r: x) H; g0 c& y: M- RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % J, r/ _' @ k0 M" \5 A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ y1 [4 Y. s7 e& ?8 e$ k* P; \0x00, 0xFF);! M. n; \! c+ R' Z5 ^7 d
! P+ Z6 J4 [ t/* Enable synchronization of RX and TX sections */
$ x1 [/ t* O$ z3 ^- M; KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; E9 y0 p" C8 C2 fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# `7 V6 G& B5 `3 T7 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& t2 |1 R0 o4 m, K** Set the serializers, Currently only one serializer is set as
2 r9 T# a1 [* v; X' R$ P1 ^+ S** transmitter and one serializer as receiver.
/ q& W6 Q- x& A4 B3 m$ h*// S8 ~( z# W; ]3 P# C& T9 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) D8 C5 P0 O+ d$ SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' V6 U7 x! T/ z% Z+ B5 g2 b
** Configure the McASP pins
3 H1 V, ?7 T# x! M8 b5 H% G {0 ~** Input - Frame Sync, Clock and Serializer Rx/ V) ]3 Y3 @4 _8 _( d
** Output - Serializer Tx is connected to the input of the codec
6 Z$ n3 H$ O( n" }*/
' _: g, b% X5 A Z# ?, dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 t1 @5 k7 I3 H1 i7 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# @4 u+ M. k# f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ C( r( f. ?2 g C7 e# }
| MCASP_PIN_ACLKX
- ^) M) g h& H9 H| MCASP_PIN_AHCLKX
6 z* m7 Z- H: F0 F5 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% ?2 F" J4 x! [4 H, w+ _$ SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 ]" N( n+ o0 m( o6 X! i6 u3 u| MCASP_TX_CLKFAIL 3 v0 W$ c0 O/ Q% j& M4 S/ s$ ]
| MCASP_TX_SYNCERROR6 r: l0 z1 F2 }) F7 d# r/ q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - A3 A$ w- G4 m8 N
| MCASP_RX_CLKFAIL
! `4 f" J s1 y/ s& l| MCASP_RX_SYNCERROR . U" V; l8 ^9 p/ s4 {% }
| MCASP_RX_OVERRUN);' T# D- |) E9 M/ z" G
} static void I2SDataTxRxActivate(void): a4 O) j5 ~- Q& u# k$ E! }- C# S+ n1 F
{' r8 h; o, d2 s) F! ]: L
/* Start the clocks */' o, u# r" o% p4 y' J! m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: r5 D0 H( Z' A! V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; f8 N; x0 g2 p1 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' u; h9 c, T2 m2 b, Z& N" R. w0 h' GEDMA3_TRIG_MODE_EVENT);
! G8 o1 G3 \7 m( d/ p' c, ~7 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. a: i) D- s) [- D2 H G9 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, V: T& m* j% c. r$ `, E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ q3 t9 a9 h1 z7 c5 d' OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* p5 B7 t% \. l0 u+ N0 F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 q' b2 _, H& r4 s/ r! J6 i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: R3 @2 W. I+ D; W$ r$ K1 g6 d, I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& f( B5 H1 D* @, |
}
2 o( y8 `+ \) L6 l' W0 J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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