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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. S9 @8 X8 t& ~0 sinput mcasp_ahclkx,
# _* T P- V/ l% v. T; O3 s, Uinput mcasp_aclkx,
; {! L) O* k2 m, Xinput axr0, C0 K& B+ ^9 H+ c/ C8 l; S
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output mcasp_afsr,0 x. B# Y: a7 i. E
output mcasp_ahclkr,
0 `' K8 t3 G N% Y% Loutput mcasp_aclkr,4 f5 w! v8 a+ j& d/ h6 M! T6 Q
output axr1,2 [2 O# @ \$ @( c1 [! Q* H
assign mcasp_afsr = mcasp_afsx;
, }6 e. K0 G. D1 |; t8 Wassign mcasp_aclkr = mcasp_aclkx;9 V5 H$ `; K. P/ q
assign mcasp_ahclkr = mcasp_ahclkx;
/ g! X: @( D0 C' E- ^5 nassign axr1 = axr0; 3 l& k: A9 u' b, T1 Q1 P! o
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 l- C# p! s& ?; c: {4 B
static void McASPI2SConfigure(void)' ^8 d' r9 S) M9 X1 x
{
" D: H' {. E- xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 i. K: h, _, @$ Y% wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" U4 W& G" {0 x6 D0 k7 O2 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 e6 [7 u# ^, s: @4 _: e* V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ N2 E, p) V: e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: R+ G: N. A" @4 Q0 ^) T( ~MCASP_RX_MODE_DMA);
! b9 n( u& @' ]1 G* o& G& B# t; |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," E9 S, b, }, W8 \- O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 d. x" p- R% eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: n$ A1 \7 z: C) \, ^/ r- jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) I/ t7 [6 S9 F4 X, _# F( p7 q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . c) B6 M! d* N8 l9 d3 n; w {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( Q0 Y& c) D% A" XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! R% O. J, v; @6 F& p7 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& e# q( j. @- [8 e1 ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 Q I7 h5 }5 f5 B! p5 P
0x00, 0xFF); /* configure the clock for transmitter */
6 b. s* F& p: e4 R5 V* C' o. D xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); O6 h' J' I% c4 X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 P5 \ E7 b: MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," G2 x& o% f" k0 ~+ U7 H; R. O
0x00, 0xFF);
. X6 ~! H/ n5 v0 ?; }0 @
6 R' g M. n0 ?" I' _/* Enable synchronization of RX and TX sections */
7 V A( B" K7 _5 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* F9 R: Y. w4 n) i" m( MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 h2 f1 ~" g, }6 ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. a5 W9 C7 K$ E T7 j** Set the serializers, Currently only one serializer is set as2 O7 w. j0 u6 u3 S
** transmitter and one serializer as receiver.3 [5 r: } |" z# z9 I" Q
*/6 w6 e2 P/ O$ T" c+ P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' K8 m( [+ k1 G8 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 `# c( S) }+ j1 k" I# R** Configure the McASP pins
/ A8 _/ p: r) ~0 L. t/ V, B$ i. B" n** Input - Frame Sync, Clock and Serializer Rx! Z2 H; F/ b! D
** Output - Serializer Tx is connected to the input of the codec
& q2 k! x# C$ Q, A$ L*/
4 R: q9 \/ F0 p% ^2 ^- v3 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( n" E" T: p$ w4 Z# r) P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 L |9 c4 ^8 ]9 Y' J" S. DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( {6 x4 H1 f! r( e| MCASP_PIN_ACLKX
% H7 J, s# k3 k$ `| MCASP_PIN_AHCLKX
5 x1 d- z4 I) Y# p) [. M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( W' n- i3 O% K- y, y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 b) |) P6 x/ v! {2 J$ `5 J8 i
| MCASP_TX_CLKFAIL , n! |* }3 m6 d- w, o5 `
| MCASP_TX_SYNCERROR
% ^4 m% W' ?+ \+ \4 e0 K# t; T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. ^! `5 V- G6 J' j0 z4 H| MCASP_RX_CLKFAIL
' B4 v; S" ]0 F Q9 W4 q- O: N4 v| MCASP_RX_SYNCERROR 5 t# F1 @% a8 X2 Q! C
| MCASP_RX_OVERRUN);
, c& N9 L3 z, M ~* }} static void I2SDataTxRxActivate(void)
6 G0 X e- L/ {1 u{9 y, N$ v! L1 m. B+ Z# D7 b9 {
/* Start the clocks */
0 c+ R" K! A2 E$ e7 i+ EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 F6 G2 s) I% A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 w2 I' S' B l) D: S5 U6 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ d# j+ t3 y2 w4 g! d+ v
EDMA3_TRIG_MODE_EVENT);- i' M! O8 o8 C6 S$ d4 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 E: I7 s& [" s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. J' h0 d0 g/ y% \' V5 ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" y X0 Z1 U4 e! q n) ]2 \+ z* _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, k& |2 E8 Q. `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. @, s3 D. T$ M% l' lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 E; S7 p& F1 W* C) a% ?+ [( |% f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 c0 X, l0 y1 h. H} 4 D4 b( B( `# ^5 w3 \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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