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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. n2 v# _7 k: [# r% V* ^$ |3 Pinput mcasp_ahclkx,. J% V. Q) S3 X3 ~8 }! F
input mcasp_aclkx,; D# d; h1 k$ P* b+ A
input axr0,; P4 p9 D) N6 e4 Y& w4 N
; m! ?( _1 X4 l4 ]) `! S) foutput mcasp_afsr,
2 u# Y3 ~" {/ Y7 f& s- F& s% Poutput mcasp_ahclkr,5 j. V3 b4 O+ N- `& c3 X* W2 l# s
output mcasp_aclkr,/ J- Y J0 p1 ]
output axr1,
' v2 @) j& N- {1 |+ ?$ [ assign mcasp_afsr = mcasp_afsx;
8 }6 e1 T5 ^# ~% V% Y, Vassign mcasp_aclkr = mcasp_aclkx;" o* F7 t; h+ ^) ?0 R* ~$ Q
assign mcasp_ahclkr = mcasp_ahclkx;
n" z% y+ T. w+ N. ?3 vassign axr1 = axr0; & Y w- p7 Z2 W" L: ~0 x
[0 Y* H! A- e* Q# h0 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 U! w, F$ t3 u! J: m% p5 e' Vstatic void McASPI2SConfigure(void)4 U( s) h% r9 F3 m) q3 a7 Q& X: }
{
% i+ M9 C2 P$ a) h0 @9 P) PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ O9 f; G' V) @4 Z$ jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 A5 p+ R& a: G5 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( d4 _4 t3 O! y7 F* I/ X @' eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; G. k+ M6 F+ N$ S, ^/ b8 G0 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 D4 c% e" ^- `4 R y; l0 b
MCASP_RX_MODE_DMA);
7 Y: O. ?- ^, t( {' {! R2 JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! a0 e5 U3 s4 K+ @- FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ l+ V1 r4 C5 [: H; A n3 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & z2 _$ M, s4 f: a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& k5 Z9 M! M* m: b5 S/ Z' M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 P3 n- ~/ u: E ]! T) v+ u& e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 E% K+ N( ?0 W& ~3 tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 O9 t# n/ g% |) Q4 xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; @; J# c7 v B3 o3 p; ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) V r6 N( J, ^! m6 e0x00, 0xFF); /* configure the clock for transmitter */
0 d! h: p5 I2 X8 ?& q: ^, [* wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 v5 B: a6 p, Y3 M. W; BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 i9 O8 s% G$ |' hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ b1 t( n/ y& H0 q4 m, [! E
0x00, 0xFF);7 t" J0 Z2 {0 g' i2 N, o
* O2 W% f8 I+ ~/* Enable synchronization of RX and TX sections */ # b' o7 K* _1 Y. l$ @: A5 U8 R( ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 e9 \/ X( r' I( ?# uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ E. s! s$ i* k# |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ ` S1 m/ x0 T+ X1 |2 ~
** Set the serializers, Currently only one serializer is set as
e! n* ]2 [0 W: f7 t- e( _** transmitter and one serializer as receiver.6 o$ W% @/ ?' `& w3 ^1 n
*/1 w6 O4 r7 N' s: \4 @9 t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 B8 d; ]" b; `7 n. A* }& Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, C- F, ]. _! \( `1 T& X
** Configure the McASP pins
. G- e9 n/ g5 M( J6 V/ }** Input - Frame Sync, Clock and Serializer Rx
, \! o7 B$ E8 @' m, L** Output - Serializer Tx is connected to the input of the codec ! P9 M/ {$ r/ x7 P% ^7 H0 j/ m* b7 \
*/
$ p" V2 L& m% j0 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- w2 H; M, [& o( Z$ y* `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( V9 p: t' |- {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( A- d4 u% a D, W
| MCASP_PIN_ACLKX% V" x8 N/ H# t! Y, c j! b( U8 |
| MCASP_PIN_AHCLKX7 i/ I. y! i2 ]0 L6 }& X7 K7 q) G: D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, V8 _( Y( J6 }: W$ TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : Z+ a4 Q4 I+ ?4 M) S. R+ ~' w
| MCASP_TX_CLKFAIL 3 N8 s7 ]/ e* l( i+ |: _" B0 z7 k
| MCASP_TX_SYNCERROR
! ?; |, X% m: {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 n( X$ e3 S) w; H0 |- p6 [) z
| MCASP_RX_CLKFAIL
! D, y4 a4 W; s |1 J| MCASP_RX_SYNCERROR % i) x. Z# M6 S/ W) Q6 Z
| MCASP_RX_OVERRUN);
r# Y9 `% L7 O} static void I2SDataTxRxActivate(void)1 h4 s6 b7 c+ K
{
' \# N* m0 V% w) X+ q/ I/* Start the clocks */
+ l- L! _. j4 `6 _; EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! g9 Y% P# ^& ? V, V- ~% e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 [ h u+ C3 U% F4 f/ y* z* L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 u/ x3 c+ P& S0 M4 ^2 u& Q2 E& r
EDMA3_TRIG_MODE_EVENT);; p; s9 t* m* e4 G8 Z7 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 g x6 v2 H+ g: U+ P1 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 H8 t" }# F/ w- ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% P( ^) I4 A$ c3 j, l8 [" U8 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 R# w( D4 f6 Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 a* B* D2 C/ n; t! Z/ I5 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% T) p V' V! a1 F$ O) r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( T8 d& m' M0 _/ Q6 _1 w} 7 z6 @# _+ N) G1 Z4 d; Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 c$ i1 R+ V+ i2 \- L1 Y
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