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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 U0 s4 ?3 @+ D) F5 O7 J
input mcasp_ahclkx,/ [4 ~: i/ |/ j$ X/ y( R
input mcasp_aclkx,+ T6 C4 w9 U+ b6 E5 d: i9 N
input axr0,4 Z8 Y0 i M/ V$ @; m, ^
; o- _) J, p+ {8 @output mcasp_afsr,- a( y5 X2 q. I- B3 {9 t S
output mcasp_ahclkr,
) |0 z6 R7 U8 S" Ioutput mcasp_aclkr,
. A* z# P- k- L4 I$ A0 Doutput axr1,
5 I6 V) d/ A: S+ c5 M assign mcasp_afsr = mcasp_afsx;4 [* ]) K9 h/ o+ r% j/ V3 ?6 g( g
assign mcasp_aclkr = mcasp_aclkx;
& r' L0 `7 ]& q4 h9 p0 N6 Yassign mcasp_ahclkr = mcasp_ahclkx;$ Q9 L0 K2 r) }7 }7 ~0 ^
assign axr1 = axr0;
$ n' C# g/ g3 Q( c
) l) X+ }- F$ _9 N; l7 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - [$ ^3 ]: V( ?3 M; H I1 g9 Q+ i
static void McASPI2SConfigure(void); l6 Q2 \% y: K; ~- i' Q7 p
{1 ?/ U' }0 s! C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# A7 }/ w2 |, T, m& h! A1 _ eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ Z0 [7 T0 t" a2 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( ~! k3 o, e" g; T. D$ b6 f/ kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 v( c3 B" x* n+ n/ x+ ^& V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. s" d n( I$ g. Y8 k. [
MCASP_RX_MODE_DMA);2 r' P* b' ]' l8 g$ y4 r6 A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# K n# Q7 D% Y+ p/ [$ }7 [8 B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 a- d* ~9 z& c; z% E! T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) G" q$ h' Z E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 y2 o( Z9 z' |$ c$ h$ ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 V/ o7 D$ O) s2 f$ ~2 oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 G% m2 i' X3 M- U, ~! I3 Y, PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 B% _( z( f% c) QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 A3 C2 x7 L) Q' Z2 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* H( x& @) `( P1 z. H' J
0x00, 0xFF); /* configure the clock for transmitter */2 W; c J1 c( |; G$ }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. p* g. k* x& d" d. A0 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, Z$ N7 P+ B& n0 K7 {3 GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' O/ p7 X/ L4 Z8 V6 B
0x00, 0xFF);1 S5 d' F4 q/ m# X' s
+ S- ]) q( Y, {; j Q5 K* G/* Enable synchronization of RX and TX sections */
1 c5 z$ r# {# z4 _( EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ }4 ?# P$ H: e5 tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 x2 j8 ?' C7 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 D+ ]& W; L* t7 ?4 z8 L** Set the serializers, Currently only one serializer is set as
0 x* S1 V, \' Z, Z** transmitter and one serializer as receiver., a3 B* w* @- V& G- P5 S
*/4 O6 |3 |8 u Y# i" [& H1 H& t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& x$ M3 O: A; @- w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 x+ \2 \- U% c** Configure the McASP pins : Y4 n3 A, Z6 M5 c3 q* P
** Input - Frame Sync, Clock and Serializer Rx
. U+ G ~8 P, B' S* O' V) A** Output - Serializer Tx is connected to the input of the codec 6 y, r$ u* m6 U A
*// ]5 E% l( O7 L1 }# o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 S% j9 I) ^+ @$ Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, r; k2 R: V, |3 [. l: b6 a8 M3 H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% T1 z7 Q: ~3 @
| MCASP_PIN_ACLKX0 q% B1 |1 M' b- t# v
| MCASP_PIN_AHCLKX
9 A2 Q& F8 G! g3 t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! P5 l- G4 d& X, Y* wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( r; q6 ]6 r& `% n: x% o( T| MCASP_TX_CLKFAIL
7 W$ N, n5 F M8 X| MCASP_TX_SYNCERROR
! j& J5 \) W$ I% a S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& _& ^5 I9 O9 N: Z+ v" C, b. Y& s! q* J; g| MCASP_RX_CLKFAIL q# ]! @. ?- k4 Y3 ^
| MCASP_RX_SYNCERROR * q! e" B5 C" g6 ~
| MCASP_RX_OVERRUN);
; C/ z9 E" @8 h- J) z3 L8 s# Q} static void I2SDataTxRxActivate(void)
3 [0 i+ Q: d9 ^9 n4 H' ]3 `{- ^7 `' ^- L/ u: d* j
/* Start the clocks */$ Y; T3 _8 h! s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 y+ u. |6 i; i' }! n9 R* z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; ?$ O6 Z# r5 H/ R! K8 Z B' IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& p. a3 ]6 g+ z OEDMA3_TRIG_MODE_EVENT);6 u8 u: W( }0 p, E- `( G. _3 N' [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 C% q- ~* T9 m" d# U2 ]3 O; V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
K7 U7 ^) }9 s u, ?( pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" a" {1 `7 C0 \+ I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 E9 x7 n9 L7 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. h& ?+ q3 y% G: u7 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( P& G3 E" m9 X: q0 D- V6 @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% f7 _( f: H4 G S! G3 q& a4 l} w' D. q: U3 }2 u+ H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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