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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ }8 m1 G% I# k; l& [) L0 J
input mcasp_ahclkx,
% V' P& A+ O$ n9 {+ }input mcasp_aclkx,
8 R0 S: N- s+ ginput axr0,& c# N& U# J/ \2 z' W4 S+ K
( U; c$ ]& I* V/ \
output mcasp_afsr,
& U R3 J; C7 k: m0 A, ]output mcasp_ahclkr,, a, H( }7 r, p: l3 X
output mcasp_aclkr,, T! c' A F8 {; A0 E( r. b
output axr1,
. \- U. u/ T3 \) j assign mcasp_afsr = mcasp_afsx;
: S: l3 b. q' F2 D+ Oassign mcasp_aclkr = mcasp_aclkx;
: P; w3 Y# G3 ]: x- q2 Uassign mcasp_ahclkr = mcasp_ahclkx;9 o6 u, i) E4 {0 u6 H% o
assign axr1 = axr0; * v/ F5 v: V4 Q/ r0 U. J7 J4 O/ |
( B5 s- G$ y( A8 R; Y- C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
H5 u) A( k3 q) L; e% u/ pstatic void McASPI2SConfigure(void)( i2 _+ ~+ `' R, o7 h9 }( n) u& r# J
{- t, O6 j7 s7 F' Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! S/ l5 w6 m( } mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* m+ G6 K% i. L! B7 G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 o- X0 W4 J+ M# U/ jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" g; L8 W' C& U( H/ T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: t1 n0 b6 ^4 R0 N5 G. J
MCASP_RX_MODE_DMA);+ V0 @4 w& Q# n, O2 u5 }- O4 {; _$ P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) i$ Y8 W2 w) [" m) q4 D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ |3 X; B' Q. y' h3 z+ vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 h5 Q4 y( I% V" c0 F6 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 _; r2 z2 u/ c' I/ ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + b; l, g. i: q: x( Z R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 T8 o0 ], q8 l7 A+ G3 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
D* H4 V Y. r+ S- Y6 k& KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 ^5 v3 v6 e0 t% ]3 J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 N7 K, F" B# P2 z, C1 ~0x00, 0xFF); /* configure the clock for transmitter */
$ n. m7 {: b' Q7 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* I0 _. q7 b9 Y X- h# EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , }3 a! R8 j+ c& ]5 M- _% M6 j4 \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! n1 X5 b( M) u0x00, 0xFF);
; Y. }, q8 r8 `
0 x7 o& s# k; V1 f/* Enable synchronization of RX and TX sections */ n) }/ O; A- e% d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( i3 Z: k' ?0 M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 w; `) L! h( `( D2 C9 k# Z8 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& m6 L! T) ~( Z$ m3 l' R** Set the serializers, Currently only one serializer is set as X( b% x0 [, L/ F1 ^, L
** transmitter and one serializer as receiver.
" \, T8 O/ F9 N* w+ t' O*/, u) J/ T& w# }: z. r3 C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 g a0 v- w& G9 P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 P. b2 A' e4 v1 ~, ~% h+ ?** Configure the McASP pins % s0 e2 N; k& S# W. z; k
** Input - Frame Sync, Clock and Serializer Rx+ \: X. N! A1 x" {" E& S+ x
** Output - Serializer Tx is connected to the input of the codec 7 h) P `( V, ?
*/2 O: n' G2 h# b4 V' {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ W( z7 O K4 x$ ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, d; U8 u: ]7 D5 K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! X( h+ O4 `' ^' F$ [( \
| MCASP_PIN_ACLKX9 e8 c! Q; B; W- G2 \) d7 }; ~. L
| MCASP_PIN_AHCLKX
, X b+ H6 L7 E; \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: O: W8 ^& l! A9 a9 h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: [3 d$ a! w, c| MCASP_TX_CLKFAIL
& D1 ]5 B4 W8 T5 z) R; _| MCASP_TX_SYNCERROR( V9 y( |; W2 _, ^/ @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- h) T0 I0 j6 K4 i- x| MCASP_RX_CLKFAIL
9 z b) O) @0 | |' ]$ }9 g% t# k| MCASP_RX_SYNCERROR
! E, `3 U& H5 f4 v8 V| MCASP_RX_OVERRUN);7 b. @9 W) F: @* {- N2 u' ~
} static void I2SDataTxRxActivate(void)
2 }5 z0 W8 R/ x8 ]/ U3 b! \+ ]{5 b' ^3 |6 C K) \3 c. r3 z
/* Start the clocks */
( F8 o6 D; }) E. }. F% ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); x! I8 |. L5 X' R7 A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& Y5 f0 T9 f0 v: U2 ~7 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 `- k+ `. U+ Y) b! D
EDMA3_TRIG_MODE_EVENT);
3 t) L- m. F/ e- l) F) M3 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 P# [$ D* |" F3 A% G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 n2 O1 p! d4 ?, k# L, a+ F5 a: x2 LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 f. W' I) j W0 E$ qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 B2 S: \3 ^# ?9 g: p7 f4 e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. a, B1 {, n" BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 A* p; ~9 ?6 M; WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 G( J) M h! S% R( c8 K
}
! G+ S7 b. z4 S/ E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 O! ] J+ ~7 A
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