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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 p2 P+ A6 S, Linput mcasp_ahclkx,
/ {* X5 ^8 o7 {input mcasp_aclkx,9 y# s' z3 W- C3 G1 a' E
input axr0,
4 r1 h- b" e1 B/ k% V R8 Y9 D
: B3 M `3 e/ K: Z7 z. _7 F9 Qoutput mcasp_afsr,
) m1 ^: h3 }+ t& B" eoutput mcasp_ahclkr,9 p; v4 R( _! K
output mcasp_aclkr,
3 u* Q* T3 W! ]/ Youtput axr1,
8 x+ i( x) q( Y0 p% T assign mcasp_afsr = mcasp_afsx;
' I7 D* z1 v/ n; R! E: Fassign mcasp_aclkr = mcasp_aclkx;" G b1 `' E& H1 N! ^
assign mcasp_ahclkr = mcasp_ahclkx;
# j, Y- S2 Z, M+ D0 Rassign axr1 = axr0;
& t, I2 ]3 x0 U$ E: N3 ^9 `" l3 d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 y0 n. e, j2 A; q! B0 n+ K; c: n. nstatic void McASPI2SConfigure(void)8 F9 a/ {: ^4 j
{+ z p3 N6 e3 C$ a% o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 g9 T( O# a; p$ A" N1 u# T& CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- Z% z$ ` C2 m% n+ hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ _0 E+ C& e! j& h, j5 J+ y6 q/ u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// x9 D2 z( F; y- q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 d7 N5 H: M6 Q
MCASP_RX_MODE_DMA);
% D D3 J: s/ T, VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 A4 Y* W; b. q" lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" i: o/ n: K+ \# e; E1 j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
v8 n B7 u0 ?) yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ d0 ^, W$ R; y q* h' ]4 }5 k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# X# x, @, X- J1 F( `, d3 D! WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 z; i+ l" n0 }" v9 q& i: U; t$ SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 E, i: k o& g0 x% h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! q' d& K# \# T% L' p, H ]8 j8 [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," {% Z; G+ D& u6 a) c! ^9 W
0x00, 0xFF); /* configure the clock for transmitter */3 n7 ]1 c/ f' v' Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. Q) M6 Y# U2 T X7 f$ n& T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 p' z% Y$ |" a' f' q* [4 D+ _/ e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) G$ V$ O4 t3 k5 [
0x00, 0xFF);. g- Q- n6 x4 \& Q
% v9 J% q* x2 o. E8 E/ v+ A/* Enable synchronization of RX and TX sections */ 1 C; e$ F( s& I$ B, b3 a$ \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 n5 Q3 H! T5 x5 e6 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, w* K. o" q% ?+ w$ W. S( T l/ _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** w. C& G# |$ z- A& Z- n
** Set the serializers, Currently only one serializer is set as
2 a! s- g& p; a, R: Y** transmitter and one serializer as receiver.8 g; i9 Q' l* |1 k& ?
*/5 N! n% Y; X, ^0 u+ k5 P/ P: C' o$ |5 T# u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' t7 ]- k$ `3 I" B+ B7 RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, I' x; y C2 g" a. I4 L. ]** Configure the McASP pins
, Q: W7 i# W0 s! c% U# l+ Q** Input - Frame Sync, Clock and Serializer Rx
) c# [+ ^7 U$ `) H- |** Output - Serializer Tx is connected to the input of the codec
" v; F* V0 |1 @*/; U+ Y* T' g1 V( W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 R/ _, ~3 I& i9 WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. V+ o5 t" w! y% |2 H( qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 s# V8 @- l1 M: p9 O| MCASP_PIN_ACLKX
6 r B7 U1 l* k| MCASP_PIN_AHCLKX
2 v Y. L; [' a5 @, k% x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
T3 T: ? d7 \& C: X# rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
]/ K6 L* F# }' y2 y! t" q+ b| MCASP_TX_CLKFAIL ) a. @, E* C6 a& v
| MCASP_TX_SYNCERROR- O1 ]( O* ~5 m( X% X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 U- Z+ d3 _% A: x! K| MCASP_RX_CLKFAIL
4 ]! \# ?9 b* A& o" U: Q| MCASP_RX_SYNCERROR
2 A+ S1 d; E I# L| MCASP_RX_OVERRUN);
2 q( w1 _6 C3 _% k6 P+ m} static void I2SDataTxRxActivate(void)+ o7 v" r# C2 \& R* B
{
4 l; T' N& Z1 q9 }# e/ F" ^/* Start the clocks */+ b1 I! Q6 P7 M3 s) Y' I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; h+ A4 X7 T! W" J5 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. `2 p" `9 d9 J3 r( _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 \, Q5 u$ L( M
EDMA3_TRIG_MODE_EVENT);! s$ b6 \+ Z- A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ w/ I2 O* e1 ?* \4 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 X' a- x5 ^7 [ O' H. m. TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. D; W; h) u8 l! ]& w9 @7 c! qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- |& _$ ]' `( c: J2 \" c. jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 {* L7 t7 \, Q; z& IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( k& J2 g. ^4 H' g" T8 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* x4 {4 C" R" ?( n( K} ( d0 S! B1 Q/ m: j* L4 N( n- r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ J& n D3 B9 ~; b& n3 W
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