|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' H( F& f; a3 G C
input mcasp_ahclkx,
+ Z8 B; Y/ R. l' }% p+ \/ @+ binput mcasp_aclkx,. f( q$ v$ f4 e
input axr0,$ \7 }, p3 B7 v/ h: i
' M, O, C! v' B5 L+ r
output mcasp_afsr,/ I+ ?& ?7 Q6 h0 T$ p+ {
output mcasp_ahclkr, D7 _, W( i7 Y6 m$ A# V
output mcasp_aclkr,
" d0 u% G4 W) V' [output axr1,# N& e/ u- k2 i9 ?/ ^3 u
assign mcasp_afsr = mcasp_afsx;
" W1 Z3 i# C! b6 u. Y! t5 `assign mcasp_aclkr = mcasp_aclkx;' u2 F9 ~7 B8 Y$ j* a
assign mcasp_ahclkr = mcasp_ahclkx;
3 Y: J: C3 [0 ^1 l$ K! I, C( zassign axr1 = axr0; ! `% e3 J0 `( f" ~9 s, {
: g4 [# l$ @7 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 v- s( ]) ?+ S" I8 rstatic void McASPI2SConfigure(void)
6 h9 ^% H4 P, Z7 L+ ?% [{
5 S. o, l( O* P' L9 c2 VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ u; j- M& I: d& H( iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, Q9 m0 V9 \* ^9 `* q$ S h* zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
G& J; j% d# c: gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ H) x& v" P- n. r8 HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 z" q, C% F! ]$ ]2 QMCASP_RX_MODE_DMA);7 v: f9 D& u" I; Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 c8 C; N) J1 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! J) B: r; N* t* [3 H9 U$ X- gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " o5 k- U' B. A [# J8 E% T- L# ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% Q2 ~) ]( B" v7 E% T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . Z( ~* v) Z6 S* w& D# g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 u$ X2 u: Q9 O, ?: s/ Z2 y& XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" ]- Z) U. {( V/ t" Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( W9 {6 {& [" a/ c' rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! J0 w3 K, ^( I" i, o7 ^" {) v0x00, 0xFF); /* configure the clock for transmitter */
% p6 T' r: `6 X9 m: O, \: f* M5 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; e7 W& ^( q9 g/ `% V% n/ g% RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) `( k! F6 y; h2 ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ b, X! y! v+ N/ Y: r, b3 M# r
0x00, 0xFF);
- H- I! C5 S9 U3 u% u
3 f$ R2 @8 x8 d/* Enable synchronization of RX and TX sections */
3 n/ v( u. E( ~5 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, ]" V9 I- B6 Y2 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( Z. {" B a( Z! y8 t/ @5 v( |( wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 [5 a4 `5 A8 x9 |; {# w* P& T
** Set the serializers, Currently only one serializer is set as
6 a/ h: W. j3 e6 U# z** transmitter and one serializer as receiver." K$ ?) U8 c9 K. _
*/
& z& t8 ^2 W. W0 L! m8 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 L2 z* @* k3 a& J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, Y8 c4 J! A1 ~* S
** Configure the McASP pins
" e& P, X6 S, ~8 w** Input - Frame Sync, Clock and Serializer Rx3 p; g) G. @" t0 G6 I3 h$ s
** Output - Serializer Tx is connected to the input of the codec
+ |& b7 k2 L# Z7 |: u) |, Z*/& w! I( ^$ P+ m& G- S$ k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ v# I0 O# I' D9 T- lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! M* E5 Q% e# Y% c9 Y- I, bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 |: I; M& M$ [# c4 P: p" T8 X2 @| MCASP_PIN_ACLKX
1 v7 P# G, Z& L4 v& Z| MCASP_PIN_AHCLKX- b" X( ^6 C* G7 u7 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ X% m4 |3 U2 v$ a; ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ R5 ~2 v) J; [- h. M| MCASP_TX_CLKFAIL
6 v' e6 w& Z9 d3 {2 Z0 Z| MCASP_TX_SYNCERROR
! X6 x2 S0 O W0 U, I) z6 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * ]1 }; a; s6 c, Q& n9 Z
| MCASP_RX_CLKFAIL* [& K0 h# X2 T; @) ?+ X
| MCASP_RX_SYNCERROR
4 `- w$ s; r8 ]! i4 ]| MCASP_RX_OVERRUN);
: k. [1 G+ W- L( i5 e8 m; Q} static void I2SDataTxRxActivate(void)
- I' M9 p# x0 M- q+ @{' A7 @4 a5 B/ J. F
/* Start the clocks */3 n' e/ \2 n- w7 U$ m# r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 z' O3 S, |6 B7 U3 FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 B/ A- c3 C% r' e, Q" S/ NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 G- {. a5 C/ d' f
EDMA3_TRIG_MODE_EVENT);# @1 t0 R; \% u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 ^* S7 ^9 R, u' j# Z6 w$ YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# Y$ F: j/ l* B2 K/ e9 U9 @0 X4 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 k: A5 N& c, k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 P3 \1 a. t+ ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# [/ ~, R/ {# B# f; UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' ?- `7 O% ] q5 x: ?, x' T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. L; ?# k$ j# `2 l+ d7 s}
! \5 }) e$ H H! T. l1 l5 V0 ]$ L/ v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 ^1 q, k2 s( s
|