MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
3 ?0 j4 z: l+ d# D6 i% [4 B5 R- Binput mcasp_aclkx,
input axr0,

* a# K% [# Z6 }: T; coutput mcasp_afsr,
. P0 M  ^! s; z/ v9 t" U; k. p( Eoutput mcasp_ahclkr,
output mcasp_aclkr,
$ S$ ^1 v9 x  E; S5 x* Eoutput axr1,

assign mcasp_afsr = mcasp_afsx;
6 R# V5 T* k* D4 V+ u6 uassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
5 y: d# S) Y8 _- S7 r$ @assign axr1 = axr0;

9 @" U9 M( \) J, {- [; @0 j2 o0 a
$ m7 e; N* A6 ^1 ~4 W

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
2 r; p$ ]* s) I4 @  p  Q/ w+ ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
' l" W# u( B( V/ fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ g6 C8 _+ @2 u* N7 a7 }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 P7 X$ x! z; P( ]% I9 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) f  P& p- U0 N, F$ v1 Y; ^) ~9 U8 G0x00, 0xFF);

/* configure the clock for transmitter */
. u( f% W* `" v0 X+ J% ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ K; q! H& @0 J/ ]7 B! _% WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 v+ m8 Y$ [' Q& T1 B( ^, u0 L0 M0x00, 0xFF);
8 a* V0 L5 Q; r& L8 b, T
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 g' s( z, z( \9 o& C/ nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* x; u6 Z8 B: iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
- k- f5 i7 _3 l* M9 Q  H1 H4 q$ I+ J** Set the serializers, Currently only one serializer is set as
( i) g6 `- a+ }' b0 d$ A** transmitter and one serializer as receiver.
+ W& i: A0 o2 q* [*/
& l; D2 [/ y7 TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
( h' G; f8 E7 _/ R4 P* V/ v6 F  g*/
+ u0 ]: V% E& t* m: c' ?8 K2 M- LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ M+ r; M* `2 K+ C, }+ C/ k) q  @) jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 H* e6 l  T0 G| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 D0 ^4 E; f  Q| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
$ q; k- c/ V0 U| MCASP_RX_SYNCERROR
- u% X5 ~2 x4 U# f7 z/ H| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
( I- @& w2 S) s! X" T{
/* Start the clocks */
! a1 {0 j2 K. n9 S, y4 S1 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. q* Z- `# u, E/ c7 F& wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
& z5 m2 f/ @  j& V' s( s) SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& j- ^! P* h2 W6 r& bEDMA3_TRIG_MODE_EVENT);
. L2 @) P+ ]: A, u# K6 A& A1 E5 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
# ?9 u0 r" l, U0 w+ PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
8 f& h( i  [6 o* t; O  J0 qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 ^* M* t2 H% `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

8 `" `8 Q( u  A4 x, Y( L2 x. R4 }

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.