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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 H% P# p. X* a0 l k# V8 zinput mcasp_ahclkx,2 @8 z! s, q( Z% w; o$ U7 b9 m" R X
input mcasp_aclkx,. L7 Y! X; m5 m0 d! }# K
input axr0,
/ E8 Q* @, s0 ^* _; u; E$ o: \
9 u, O8 h3 C; soutput mcasp_afsr,
, H6 B4 t; D$ ?output mcasp_ahclkr,% C/ ^$ f# b& ~: k/ n) @9 i
output mcasp_aclkr,
# Y: v; H! E. e! Q- _4 X) [* moutput axr1,
8 d3 t2 v2 O+ L! s$ e assign mcasp_afsr = mcasp_afsx;
7 w: R% [2 H6 I$ [0 X% r, |assign mcasp_aclkr = mcasp_aclkx;# N1 @8 N' ^ N) o7 Z$ d5 {2 D
assign mcasp_ahclkr = mcasp_ahclkx;0 L3 g( ?" d0 E d- Z
assign axr1 = axr0; ; t; e: w. i2 Z1 @0 r
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 e4 d5 }( F. h, A& ?
static void McASPI2SConfigure(void)3 ?/ A" o# g, v7 x: Y, D
{
7 F8 a0 ]) `* S( ]7 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# m8 U" r% p g2 t/ ~ N& L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* L+ P+ F: Y! v9 Y$ D0 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& Z/ M: @2 ` ]6 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: H3 H, e( ]% ~8 B2 Q" }1 K: x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; n8 x7 F& j% }; Q) p+ iMCASP_RX_MODE_DMA);# V4 f" p/ U0 a; S8 l- N! w* n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, P2 h* v r7 ]% S. h: c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 y6 C9 L* R9 Q( o( AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 X6 M/ t! o5 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 c2 v9 A- U4 v# I- {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. A; h$ S" b: v/ T; @5 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, E: T% B' g- G9 K0 F8 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 j" [8 X' m# a9 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: b$ R6 E0 Z6 N tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- r) S8 s9 g4 G; a
0x00, 0xFF); /* configure the clock for transmitter */( o* |+ @1 ?0 Y* Q4 C8 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. v, z0 J% {( H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ Y) w- Q$ n! l0 x" pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ h h1 i. n) \% Q% R7 v0x00, 0xFF);! ]7 O7 g4 F) C- `* Q
: M& j# v- K+ X6 [; P. }/* Enable synchronization of RX and TX sections */
* Q% n" B+ a/ Y- h2 i( d7 {6 P5 u9 hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 G* x/ S6 s* v4 N9 gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( N/ l' ~4 ?" M/ f5 `( N3 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ K& j8 m" o" R$ l: V% u; W+ P
** Set the serializers, Currently only one serializer is set as- G+ g( B9 R0 x" q! X, E
** transmitter and one serializer as receiver.
$ M+ u) r/ H N% B6 ^*/
, h7 a# A0 {/ e2 c/ q2 LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 y' U7 ^* ^ ]( j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 F( X9 B7 I* n& w; x
** Configure the McASP pins 1 K( ?. _: H' x( Y, `
** Input - Frame Sync, Clock and Serializer Rx
' W( f: A, v( S# J& u" p* i** Output - Serializer Tx is connected to the input of the codec
4 g6 F# G% p8 ]5 I) R*/
, R3 w, B# D* ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 q0 L( t, y& N; W5 \' R6 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ L) l: d1 i" m& N) O! |4 ?0 G' x$ UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ e' N( n# m- {( g2 |) ]/ O. H% }' ^
| MCASP_PIN_ACLKX$ ^. K, o6 p* b
| MCASP_PIN_AHCLKX# C! T2 t: B, Q( ^0 l" L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 S l& k( P9 M1 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 o* ]5 c. U& P" S| MCASP_TX_CLKFAIL 4 N1 K0 y; Z) S
| MCASP_TX_SYNCERROR
+ a; ~- ]% g( k: r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 b' @) E6 h2 M) \8 e5 c| MCASP_RX_CLKFAIL
* U) d! |& ?) [) |$ v3 }* ~| MCASP_RX_SYNCERROR % e: A* J2 O" @4 p O7 A+ T8 k
| MCASP_RX_OVERRUN);
! x! @0 C3 ~; R3 i} static void I2SDataTxRxActivate(void)3 h8 I/ Y( m% W6 {7 }# T$ P
{3 t/ O: Z/ a) U3 v
/* Start the clocks */
- S7 U: W$ w3 ?3 ]. B# XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; o; K5 Z4 p6 o$ r+ V8 iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 B' l' p3 t, i, ?) [ S* qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! v4 U7 t c9 }; U" R- o+ T/ w
EDMA3_TRIG_MODE_EVENT);% E; o4 |8 a% P8 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 L% C2 I4 U- x5 o4 F* S0 HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 b" G! [/ z3 k; W" M0 M' ?3 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ I b8 H& t. h% x2 j/ {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 S; M1 e: t5 \- m, [! N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, t1 K6 v! T' g& b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 {3 ^- J+ s- F5 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 @3 b2 f; R8 [( g. g7 [+ U}
6 }" N5 T$ N3 \- I' C( M, L" m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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