MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
' ?% V" d9 Z+ m8 P! a( hinput mcasp_aclkx,
input axr0,
' w5 d/ A6 p$ s8 e
output mcasp_afsr,
output mcasp_ahclkr,
" {4 S* D( b% ~output mcasp_aclkr,
. J% J$ q* C- n4 d9 x, D: coutput axr1,
, }$ c5 h7 m/ ~. u* f

assign mcasp_afsr = mcasp_afsx;
1 L( n, M. G" `, uassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
! _4 e# w( o0 ], ^assign axr1 = axr0;

# G- B7 X* Y2 I0 Q8 f2 A" F2 v

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

) ]5 B( n$ k1 Z$ i- l

static void McASPI2SConfigure(void)
) u/ T& X. M6 b7 `# G/ H{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 C: F: q. _# gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 l( i( p/ A. D0 {( mMCASP_RX_MODE_DMA);
4 Z! @4 z1 A4 cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 p) g% ~7 J$ _0 n3 |: UMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' O+ k! ]  w% G9 C/ ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ u- u, E. Q; V. t: H7 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 Z$ K% o* _0 [9 c  CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( p) M9 G+ D) Y3 g1 M4 k. yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
9 `- c) j$ t  H& cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 i& E3 U* C' Q; PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' e! d, O( N, m- C, C0 ]+ ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
" z8 P: s& Q! [  n; a
/* Enable synchronization of RX and TX sections */
& e' Q( k  Z' g  F) E, s) f% y) O$ V# _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
; H0 }6 Z0 i3 O) X9 b0 z# S: gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. y9 Q; z! S6 o' pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
7 z5 m5 _, V, s" o: k) [** transmitter and one serializer as receiver.
, C  I$ Z  A9 u/ f* W9 D6 n*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
9 k' }9 N. d5 V/ {- O) O* N** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
) a0 E6 l3 D+ b) [: u9 k; h** Output - Serializer Tx is connected to the input of the codec
1 |5 P* o( v  i* G- L*/
9 ]" x5 s/ Y  Q& KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 s+ @+ R3 G! d) z( d  o4 e; CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ G2 o7 f: E6 _& d| MCASP_PIN_ACLKX
. l* b9 M, _4 O. e9 N7 E, i| MCASP_PIN_AHCLKX
5 C) ?# k% h' a1 a% Z, I| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
/ e. h; A8 [& c! p8 }& XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 e. S1 E; _; K" y' T| MCASP_TX_CLKFAIL
& E9 g. [8 a8 F+ q( o| MCASP_TX_SYNCERROR
; a6 c) l, {) o, c( Z| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
$ H& i/ P3 ], }1 Z| MCASP_RX_SYNCERROR
( j6 K; F. W9 \| MCASP_RX_OVERRUN);
3 l3 B, a+ A2 `  l8 h8 ~% f  F}

static void I2SDataTxRxActivate(void)
, o3 L5 \. T+ r9 h% T. T7 w{
/* Start the clocks */
. u% S2 i8 w8 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- Q6 R: h3 b2 D2 F' GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
* g7 M" |& X6 u+ ^$ cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ \6 k, i; ^. _& l8 U7 A2 KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
9 t: i' g& ^- ^9 |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

* f2 R  }" N' B& M: k