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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' H0 d6 K5 a8 z
input mcasp_ahclkx,
R/ K- k3 K7 b% Qinput mcasp_aclkx,
6 e; f: A$ W2 @' xinput axr0,5 x9 D) ?6 O& g) Y$ _& Q) T
* W6 Q1 R* d# w2 x# j! }( noutput mcasp_afsr,
/ ?/ z M1 p6 y- N* S3 Zoutput mcasp_ahclkr, N$ q: @. r9 ?' a+ Y# c2 B
output mcasp_aclkr,
j6 b- @7 N W6 f3 T/ n; Noutput axr1,
5 A+ J8 _( |0 h% y& C( p- m" A assign mcasp_afsr = mcasp_afsx;% M( ~% a. l- g
assign mcasp_aclkr = mcasp_aclkx;
" d2 x* V5 W( r; Z; Nassign mcasp_ahclkr = mcasp_ahclkx;
; a& I- a. }9 l1 g- S) _assign axr1 = axr0;
. i( g' A2 E0 j* P6 ]! y9 |* e# ]9 ]' W& |1 z9 d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. V7 o3 V/ E& L% S: @) n; dstatic void McASPI2SConfigure(void)
; l' s& h0 s- e$ L6 {2 E{
6 ~* r' @/ w2 E# O; g! }& nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' h7 I9 z6 z' w9 V$ \7 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 X% t0 z4 [, ]# G) b; z5 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 s" L- r o" D. r" l) j7 `# mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. d6 G! X4 J( E2 Z# p: c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, B- k/ @% U, L5 Y9 j# r
MCASP_RX_MODE_DMA);2 h! {+ Q, u* G O5 [4 F) ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# x& u( g1 O5 m9 x8 k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 o( ?$ }- n$ U: Q6 d7 w! h& ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, C/ w! w, n% |9 `9 p; g3 H7 B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ U5 Q% L% c( Q* O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: e1 W0 W3 I; O- A4 n' U3 M6 SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
j: ?1 `, }/ `# pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 O' A3 k t$ b* DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 O/ G8 G/ X0 I6 M9 _5 J$ YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* z& e! w4 q' p. B G7 ^6 x7 }, N! Q
0x00, 0xFF); /* configure the clock for transmitter */
8 p9 @( }) r l" [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ W8 C6 X2 Q8 s3 F: PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + }, r: D3 [# N3 W+ M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: u6 D$ b! L' }/ [# x& i, t H# N6 O
0x00, 0xFF);; G. k* @9 w5 Q. U
3 b) a% J8 ` y/ z6 I" W6 k7 I* j/* Enable synchronization of RX and TX sections */
% g3 y6 Y3 ?% V) O% kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 k5 v$ o' \4 w7 p% I. D1 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% O+ [8 \& Q5 ], d+ ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 A0 @$ A9 J9 E7 G** Set the serializers, Currently only one serializer is set as
) n: ^* O9 Z5 {3 P' g6 _** transmitter and one serializer as receiver.
$ C0 P; U( _; ?% V*/
9 p$ `9 e# g1 |: K7 Z( e7 J1 @0 C0 [- JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# q" T& Z) d- @+ _( ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 ?3 @; o _ d$ o' f& M* C
** Configure the McASP pins 6 L5 j6 p* N o0 b& X Q
** Input - Frame Sync, Clock and Serializer Rx5 _" f$ |: p$ v7 P7 D% O" r
** Output - Serializer Tx is connected to the input of the codec
- L& B; j: f" l, Q" l*/
# M& M' f! h/ j* o0 K5 k# ? }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* ]/ x3 v9 u) V5 U3 `6 U8 DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 b* ^! j$ {' K q. h3 Q. DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 n0 [! h K! }0 [/ O| MCASP_PIN_ACLKX
8 t$ B1 z% ?. s( K* n% I* g% B$ j| MCASP_PIN_AHCLKX" R' C: r0 G ?/ I2 d S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, p6 n8 ~4 u% U+ B; iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 Q, C. e( K K# @9 ?4 z9 || MCASP_TX_CLKFAIL % \9 Q: D1 ]8 |1 c9 ~7 p" Z# E
| MCASP_TX_SYNCERROR/ e3 e e+ Z8 i# o9 }: ~$ M- G+ ^) s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ w4 e1 \8 n! ]9 Z, u7 m( |1 J# n| MCASP_RX_CLKFAIL. ]8 L- I8 D. T+ C
| MCASP_RX_SYNCERROR / }, m. S4 w$ o5 d$ L
| MCASP_RX_OVERRUN);6 h3 Z, }6 a- |! D& x
} static void I2SDataTxRxActivate(void), B6 w3 O( @6 \, u
{
# \% W4 P: ` V9 U$ z* ~( b" o! |/* Start the clocks */
7 P7 K: H6 X0 N! y+ `) u' _: rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 o5 N5 S: C0 {9 I0 p; J4 NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) V5 ~) @6 X" j5 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: ]0 C$ f0 u$ EEDMA3_TRIG_MODE_EVENT);
O: H# Z/ s V' B( Q; a9 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - j; i2 R0 ?1 t) q3 o9 @8 G* z& M% i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) j6 n4 a& U6 j* }' MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- t9 `' S+ q4 Y- `/ ]: l- i; MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 h! P2 A( ~' [) h' I9 M0 z6 |* ?' `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: |2 _/ s! R% F& E0 a9 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 b. @9 v# u- |8 M; H+ ^! DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! y. m1 O- |0 i}
4 l( g7 c P( @' y0 G4 q, {8 E0 L, g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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