|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 h4 |0 w0 f3 ~7 i5 k: q$ X
input mcasp_ahclkx,
+ C8 G) F$ w' T% Einput mcasp_aclkx, x/ r/ T2 ]0 j2 p
input axr0,
# b, r" S4 n5 f; j1 }& ?" z1 v3 z
$ E) t) l" U8 b0 }5 ]! C ?) h5 G7 boutput mcasp_afsr,
0 g% N% r3 }- ^1 m2 }. I5 xoutput mcasp_ahclkr,( G2 o% `7 b$ |4 H) F
output mcasp_aclkr,8 H$ P4 H g) g
output axr1,
' f3 f C8 B A, t% V' [+ l assign mcasp_afsr = mcasp_afsx;
7 J8 l Z% L8 e: R+ g V7 }assign mcasp_aclkr = mcasp_aclkx;
8 ~ \$ K3 l8 \! S; Y) y* I5 d2 wassign mcasp_ahclkr = mcasp_ahclkx;% z ]% ^7 f" ~) ^; c
assign axr1 = axr0; ) P) q" ~/ }# H4 x# N/ `
) ]' r3 B5 P7 V$ H6 S" M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . o9 l8 S' C- g6 Z2 ]/ `
static void McASPI2SConfigure(void)
. N. G5 g6 v4 r l% y0 q{
7 P9 w# J& z/ i6 L. yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ |) i2 Q0 X( k/ @# I* wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
F8 R2 a/ `, _% @/ y0 a: \8 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 }7 z7 d0 a% o5 \+ B. E1 U6 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ g! a) q/ U* Q7 T9 g$ Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ ?3 x( b5 U0 y
MCASP_RX_MODE_DMA);+ h* q) [8 I ?- d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) a: l- k. I9 l$ q" D+ [$ B- aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% r) R6 ^' U) p f8 w9 E; A0 vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- m+ A4 l8 d7 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' q. z# l7 ~% a' ^# H4 `# ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ g! ]9 H: x* D, _3 {8 ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( ?* S: V; f1 q) F3 m! k4 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) y* M7 N, Z' Y$ Q: AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " o9 @# ?; W9 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 z8 x. T2 r. L* ], d( \* g
0x00, 0xFF); /* configure the clock for transmitter */
0 T( I0 ~% z1 q; CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! f3 ~: i+ w9 l- A4 ~8 ^3 R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 n& @8 \7 [2 b0 j; J7 H% R" R* H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. F, z9 H6 I7 P' {
0x00, 0xFF);
* I u0 `/ r, g
5 F: R% t& g3 n' m3 K0 V/* Enable synchronization of RX and TX sections */ % X, O b# @ `5 b8 p+ o' R7 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 c: D- b( V8 |' b- Z( S" tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 n$ q& c; a, L& i( q) g" t T4 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ A+ p ?/ m; s$ ]** Set the serializers, Currently only one serializer is set as/ `, `, a3 I; t Z7 M, e& d
** transmitter and one serializer as receiver.
$ Y7 ?' T, P: x) b*/" x2 ^; }8 l J" Z6 U6 w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 o# O. |. z9 t5 q. O2 h/ D2 p/ E; }# QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 w6 b& N& C# d! O0 l# ~; }2 \** Configure the McASP pins % l- l, d x4 N j9 y
** Input - Frame Sync, Clock and Serializer Rx
) X1 @! N0 K, n7 \: @* Q** Output - Serializer Tx is connected to the input of the codec
7 v$ k+ M/ @* a% B# G8 M) A*/
6 E' |8 G6 A8 C u( I* r! _" yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ _) p/ i6 M8 ]8 Z9 U, a& `& s% H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& b! v, A- \) g( c K: a h5 T, GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 K8 K" L1 L# C
| MCASP_PIN_ACLKX
. n g0 E1 _- _0 \ o| MCASP_PIN_AHCLKX
' N' z5 h7 }; h3 K, ]4 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ p" F4 e' u& x3 n, r% W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 o% i8 J' b6 f& e
| MCASP_TX_CLKFAIL
' x& z5 v" e- H' _1 z0 }| MCASP_TX_SYNCERROR
( y- e4 J: r+ {. i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 n: B2 c. |7 O8 F+ C. i$ u) q$ ^$ r
| MCASP_RX_CLKFAIL6 P5 C( X3 I: c- i, c
| MCASP_RX_SYNCERROR
0 P* p& |0 }/ y. K| MCASP_RX_OVERRUN);
, Y U2 f5 s! [) j, v* s} static void I2SDataTxRxActivate(void)
) S" z6 i& @& B/ v/ N{
! X. e+ B% y3 F6 Q0 l0 q/* Start the clocks */
6 E, e, b9 K; R% x4 f' X4 r% dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. q* J& h- J- @4 G3 h& fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% k* ]' x% d7 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% u- }1 D" ^; C) S$ FEDMA3_TRIG_MODE_EVENT);
6 @, e' {5 H, n2 I" d- zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % P1 l& \' l% W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 {1 Z4 V& {/ P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ _ ^( F& \! i- n; s+ O( y( q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// D5 m/ O( O( U: }* U p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* H8 [6 o( s V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% W: g3 Q/ ]! d$ MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 M/ V+ ]; H1 v) U+ T
}
% C) {& c* H6 [9 m; O) L2 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 ]( x. n) p d. J9 a8 P) W
|