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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 P: k8 g' U) |% {! Oinput mcasp_ahclkx,
( Y+ f3 E' C; y H& ainput mcasp_aclkx,
* [. w' N- P7 E2 }input axr0,# ^+ y) Y* s6 Y) |6 P' ?5 A
, q1 n& f0 e8 D/ Xoutput mcasp_afsr,% l# d. }6 E: h+ I. I& n7 _# W
output mcasp_ahclkr,. _+ N9 v1 e+ C- w1 z! o
output mcasp_aclkr,
! M& O1 m1 x* V5 }; s- V$ poutput axr1,8 O( [1 O) @9 j9 b' \
assign mcasp_afsr = mcasp_afsx; O6 {3 D z, {( B
assign mcasp_aclkr = mcasp_aclkx;" o P; W) N. u3 H
assign mcasp_ahclkr = mcasp_ahclkx;& c0 {; r6 k; B$ D( E5 q
assign axr1 = axr0; f: U' Z+ l! r. `- R+ D
. w3 H6 F( Y5 @/ r: `) s) V- }+ Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 @2 Y* p( c. ?
static void McASPI2SConfigure(void)
7 ]& @- t8 C! j/ v{
3 F5 B" f" @0 Y6 tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. {+ z% S+ o( X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' G( g8 Z+ n! S+ C+ Q7 t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( h& o+ z# N. UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 ~* h- m2 Y5 g( G* JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ]' ~. o* O# B, d; m- F' W
MCASP_RX_MODE_DMA);
/ g- m. f; }0 Z' X9 |4 i1 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 q1 H# a/ S1 s( xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( H3 a8 Q2 Z4 c2 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( v5 ~4 K J' W6 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( ^ Z1 @' @3 z, J! d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # s5 Y" c, z+ H, _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" X( ^" n2 ~' B- B4 z& B, g4 I0 p/ rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 z3 g0 B4 [% i& uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 i8 Z9 A3 S5 \* a2 [ O5 A- [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 u9 x/ v. Z6 j5 f' n
0x00, 0xFF); /* configure the clock for transmitter */6 V8 Q# v+ J% h5 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); s) w. i! w: T; n# U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 G8 k1 x9 E* v' `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% K) Q% M2 T2 e0x00, 0xFF);' z! b5 I. K0 q, G
( r Y' s5 x7 F% I$ `0 R% L. i
/* Enable synchronization of RX and TX sections */ / ]- ]' I) \ \, C+ \ y n, i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* r4 `; m5 S! Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 y% c' K4 H7 i2 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" \: i; ?8 ?$ l** Set the serializers, Currently only one serializer is set as
/ c6 {- J4 d/ {0 Q: d6 e5 F+ g5 G** transmitter and one serializer as receiver.' Z7 t+ J- U% _" p- |' J
*/
- Y/ c0 O7 Y! ^# f) ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; L- {2 H" e2 w( Q3 p1 B: ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, J! j' H6 D8 i9 d# m
** Configure the McASP pins
: }! z& `5 k( {** Input - Frame Sync, Clock and Serializer Rx' d* K5 v6 W) v0 |3 @# k4 u
** Output - Serializer Tx is connected to the input of the codec
4 M, e/ n( x' `; I! H: P*/
0 ]/ f6 M9 i% a& H+ iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 ]; z, J- \8 \& W2 {. OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- ^! ~; c9 `! _0 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( _3 A: |* Z, W3 Q, _
| MCASP_PIN_ACLKX+ r( A% s4 H6 v* U
| MCASP_PIN_AHCLKX
; F! Y6 X' u2 v" B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" l7 y) j' j6 t8 X* C S4 W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" K8 m/ P+ i1 f1 z| MCASP_TX_CLKFAIL
( E4 C" |2 J9 Z9 M7 ^| MCASP_TX_SYNCERROR
1 }4 L5 D+ Y7 _( @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 i9 ~1 E1 N- J8 H& u' [' }: \- t
| MCASP_RX_CLKFAIL% e8 y% z. v3 W( g
| MCASP_RX_SYNCERROR
: S! c- y, n3 F9 S| MCASP_RX_OVERRUN);
" b4 m! [9 B4 @# k+ M4 D# N} static void I2SDataTxRxActivate(void)
5 K! B; j# c, E! e{5 W7 }0 |+ X4 f! f+ r& a0 _5 H7 o! t
/* Start the clocks */7 v4 [4 I( q3 d/ i, n. d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! r! ^1 ~' {. X l7 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; Q% x0 r/ C* ~" h3 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ R& C- |5 a+ e* F% dEDMA3_TRIG_MODE_EVENT);
- j# `0 }, Y5 ~* i8 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 S+ f4 i) G( G9 k/ F3 s QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ z7 d; }4 D# t7 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% {: u+ _+ T% {) n" QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 x" N7 G: A' h& P4 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, X9 P& g& P% F8 ~! YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ a* s2 G* Q' e" A$ cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ u0 n! Y! H/ H& x4 x} % j2 {7 B. S- `$ _# F; N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( e: d0 n' O& {( Y' h
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