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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, ?2 J: F& d& B6 W `8 ainput mcasp_ahclkx,# l- _3 C9 A; D# V' h
input mcasp_aclkx," M' @9 w* Z9 |! C
input axr0,9 B/ Z% Z. M5 P
" D3 l0 ~0 u* ~0 {8 m3 P
output mcasp_afsr,
* x/ D8 [" n1 _9 z" C2 H3 V( r5 ?output mcasp_ahclkr,1 y1 |" o5 D% t; D0 B+ `
output mcasp_aclkr,
4 y' | R5 `8 Eoutput axr1,- R E' a$ D, [' ^- o
assign mcasp_afsr = mcasp_afsx;5 B0 N0 l% S3 K: n! B3 {
assign mcasp_aclkr = mcasp_aclkx;
. w9 f0 @1 C* I7 ^+ zassign mcasp_ahclkr = mcasp_ahclkx;
) z4 }, q4 b% x! v8 g4 bassign axr1 = axr0;
9 k; ?, s4 U/ d2 h1 V+ y. G/ |
. q5 i3 A0 G* X) v4 c* L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , m5 O: `4 i7 U, Q0 \4 v/ v
static void McASPI2SConfigure(void)
# Q6 ]4 u1 {$ u1 R, s0 @{
; H* r+ i! ?2 x1 @' M q. Q SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- Y. f$ g6 z9 O- [ ? _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) m0 P6 t F3 u4 m5 W$ N$ }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; k9 Q. T A! z2 U8 N9 mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 N2 j5 J: P; }7 X% G9 t$ P" f/ G) ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 b: t' Y% M7 F+ h4 s) L2 n2 ~: D1 [
MCASP_RX_MODE_DMA);
1 R3 o/ s7 a) |$ u4 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& `- j3 i% ~+ yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 p: d: r! i; y& j. L7 TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) v' `6 B9 |1 O0 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ Y- m3 Q7 [. u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 G/ x2 ^6 d+ |7 z( l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 \4 `% n6 Q! c- fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 z. O/ K) D9 o9 BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 c0 W9 y! ~! R: D/ E% |# @2 D2 bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& }6 J [; @7 e1 K; ]0x00, 0xFF); /* configure the clock for transmitter */
; d( M/ u! t* \ ?8 s/ r+ YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& `+ o. w1 d: F6 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 g# z8 A9 q6 I2 z& K* W/ J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 A0 L, L- r; s, m) V6 ]
0x00, 0xFF);8 R# u+ E' z# U: a
+ H9 x4 i3 k& a2 u/* Enable synchronization of RX and TX sections */
8 |0 f) t& K# xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 H8 i R$ p. `7 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ G& d3 U# n- ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; S) {" s. X ~: N+ O$ D! M
** Set the serializers, Currently only one serializer is set as3 x% a: @2 a7 d. e3 B5 m3 A
** transmitter and one serializer as receiver.
' J8 W( |5 g5 {6 S# e8 T4 L& C*/3 i- W" Q" o7 `" h: |& j& F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 u* | }8 w8 `4 {! N5 B- i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" h0 ?; F: y9 ]8 Z& l G- O** Configure the McASP pins 0 {, a+ e& [5 l5 Z' I) W. v
** Input - Frame Sync, Clock and Serializer Rx
6 s4 L$ l2 a4 W8 d: k** Output - Serializer Tx is connected to the input of the codec * x L y8 X3 y/ l# [# O2 J
*/
' t$ w9 d3 ^) s9 I1 y- k7 G T3 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 i. q& R2 |* X4 E* X: B7 f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% x, ]7 N- g, Z- `! jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% [. s4 U) e9 X& @
| MCASP_PIN_ACLKX7 l, a& M* |& O8 u: X7 s
| MCASP_PIN_AHCLKX
$ y% Q9 ^& \5 R* B! Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 f8 M" ^) T- }. M% z' QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ~, ^- Y- l3 v" W# ], b7 Z
| MCASP_TX_CLKFAIL - r9 u, Q. y7 [- h" H" `2 D) v
| MCASP_TX_SYNCERROR
- Y, \( X s" L: N8 A( N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 M% u4 t: b: G" s1 o4 \( c0 s+ r| MCASP_RX_CLKFAIL
% L r. H' |% J2 ~3 e| MCASP_RX_SYNCERROR . [9 o% B3 a9 Z ^( w& o8 h5 @
| MCASP_RX_OVERRUN);' B; d; i" x) z$ u. C
} static void I2SDataTxRxActivate(void)( ?+ R4 D0 ?* {* v6 L
{
) c' z' Y- ]8 [/ o4 A! e# P9 E! J/* Start the clocks */* K+ c/ S9 ?0 J7 @5 D& I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 Q9 f, I3 s) H7 T! p* w ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& H e; T) {6 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 h6 ?' i, A0 L* hEDMA3_TRIG_MODE_EVENT);
! V$ G: O. {7 D/ i# `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 [8 X0 S) k6 i: K( @1 ?# s2 V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- J' t% f- n" l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 S4 S3 b; s8 _7 F) o7 [- w T4 HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 D& Y% K8 m8 |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! h4 h+ N B; T) j$ W2 e; R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 [3 D2 k8 {) _* I# t1 \) Z: IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* @% A( T5 N6 x5 t' x
}
5 p: G- H; c! R" C2 P/ _, ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 d! L! \! s- o2 u
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