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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 t( K: z4 q$ p5 f1 ~2 o" x
input mcasp_ahclkx,, U, [: \ x$ ^ h$ ]$ L' T! L
input mcasp_aclkx,, i* s2 S- i/ |' G L( ^
input axr0," E( V/ `* m3 m2 _
0 [; N' @; I& a. E( [$ Boutput mcasp_afsr,
# B) ^' u; D+ C: V6 Coutput mcasp_ahclkr,' S* o k' y+ d0 o; a8 ^
output mcasp_aclkr,% L6 u3 Q# g9 `) ]/ V* a. G. D, d
output axr1,# c* Q; _. }; H, ? L5 J
assign mcasp_afsr = mcasp_afsx;7 r( h3 j* Y+ ~# u3 s
assign mcasp_aclkr = mcasp_aclkx;
2 v. y+ R G8 I% K* n9 Z0 L( Bassign mcasp_ahclkr = mcasp_ahclkx;
$ f1 n( `! k* v+ U! X W s6 \assign axr1 = axr0;
- s0 @6 l1 E5 K! g- I) X; o
) n; D2 H/ }4 i U5 l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( t6 T1 W' d6 ]" R) K7 ^7 V9 `
static void McASPI2SConfigure(void)
" O; n5 h2 H, t{
# l" |. w, u2 y+ q; x# ^+ m3 `- IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" H' L/ }" m0 T* T4 U+ w& j& fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 I+ v0 B: |% X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. N) b1 q( l* v0 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( K* W# D( A+ x5 f) q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# [+ ]3 h/ N4 w. t7 @MCASP_RX_MODE_DMA);
. {4 R1 u0 U$ ?5 `& C+ m0 u% P' EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; N+ f+ c4 J) J8 r8 j7 @6 j9 p6 u6 dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ Q5 E" E3 Y( h/ Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + _9 J) z2 F2 X* I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* M8 h: U4 ], n1 o R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* v. D9 l: S" R# k/ f& U( \ eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: y+ v7 \. \( a; w# n) J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 b5 @* i* V/ j7 |, tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ d- w3 k) q7 t5 h/ K- P" DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, R( j" ?4 G/ @4 y! |) ]
0x00, 0xFF); /* configure the clock for transmitter */1 f; n6 c. V% Z' Y/ d3 F, D1 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" Y! I) H+ k) l* e" W$ HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + M5 u! A0 F" p3 j/ O! F8 I4 z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 {7 ], }- r# N* V% F0 {6 T
0x00, 0xFF);; U* m3 S* c; M
0 n& f) b# \0 _2 {1 T/* Enable synchronization of RX and TX sections */ $ E2 q! v' M/ e- J' u4 ^$ `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: S' }" U- ^4 `2 M) r/ ?% p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 ^" |. @! a$ E$ R- P+ FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, w8 U5 r p" ^
** Set the serializers, Currently only one serializer is set as5 Y- x* h- \; w0 L% Z
** transmitter and one serializer as receiver.
% L5 o/ o+ H6 y/ M/ s5 ~*/
- X( o- ~6 O( U Z2 ?( w3 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; j4 @0 |: R- t6 z! e# i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; r- b% C; m6 q& _
** Configure the McASP pins 8 `# p8 K3 \2 }) S; e/ L
** Input - Frame Sync, Clock and Serializer Rx
! Z' Z$ E6 O5 c! u) f. r3 Y( w0 a, d** Output - Serializer Tx is connected to the input of the codec
$ p( ^% e/ Q4 ^; e" s" G, V; N*/
9 c1 r4 s( a+ j$ _2 TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' q8 I% N& _9 P# pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 B. R' P+ }3 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ U6 I' E3 F0 f; G3 ~
| MCASP_PIN_ACLKX
- J6 P/ [" u' c7 Y" {# o| MCASP_PIN_AHCLKX5 @9 G7 b; S* e& ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ Q5 u- d. o) p4 Y* W! z/ q6 a% q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! |8 @% n3 ]7 @ B: f9 |& ]. l| MCASP_TX_CLKFAIL
4 y" T+ I4 |9 c5 U4 { Z9 V* o| MCASP_TX_SYNCERROR
# C9 @6 \ D* u% [6 M0 k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 y9 c5 _, L# t2 P8 `% P. b
| MCASP_RX_CLKFAIL- i" |; `+ Q5 X
| MCASP_RX_SYNCERROR ; z: d6 }4 s. _# `
| MCASP_RX_OVERRUN);; @0 O& @ {9 w% x; D/ D
} static void I2SDataTxRxActivate(void)
8 x7 E C: E& V7 U2 O T{
! G+ J+ T% f1 X. ?" H/* Start the clocks */) C# A( i* A' J; G3 s2 y' I w- A) s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, j2 O3 I2 G7 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' I, m. }1 o4 J+ xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, E& n& O& M F& X7 V. l
EDMA3_TRIG_MODE_EVENT);" o2 B' e, A0 q7 [' Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) @/ w; r2 L" C6 A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ B, a' {/ q: nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* K; k6 q# j; a! |3 I- F9 X2 T1 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ {) a' E6 E# V# Z9 Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% h/ g* R/ d! ^; U' ]; v' {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 u; \' L2 {4 z" l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( @: y/ C {+ {$ ~; A& h2 f7 m
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