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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& f: I4 N3 i" x$ h
input mcasp_ahclkx,; Q) v% q& H6 N- S V+ h% j4 @5 x
input mcasp_aclkx,( Q7 \2 |9 u$ M* f. c% o
input axr0," v; R% C4 f; d
" m3 N7 _, `! I: G K: b( Poutput mcasp_afsr,
7 K# [( D; J4 k7 ~+ ]' _output mcasp_ahclkr,+ E' @: ]1 {5 e( T+ D$ P% D
output mcasp_aclkr,
, @/ v7 y% Z. i$ \$ [$ X# Zoutput axr1,) y: u$ S2 v, m3 B# e7 l, v
assign mcasp_afsr = mcasp_afsx;6 u8 m, n _4 y+ E
assign mcasp_aclkr = mcasp_aclkx;5 m; Q; ]9 }" ]
assign mcasp_ahclkr = mcasp_ahclkx;
/ [4 o' W" _+ T! G- Massign axr1 = axr0;
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! m1 B# A- l; U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & O* |1 h. R1 X+ x, F, d* K
static void McASPI2SConfigure(void)" v; R# N3 q& U7 f; [
{* @% l; i- i+ \: F+ E. P1 W& q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. e ?) r& j2 `5 @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 F6 Y P. U9 j dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 k" Q" q: N1 f) @. d$ r# K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, E+ V6 j* P$ }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; j1 T4 v% [$ w+ w% l* N
MCASP_RX_MODE_DMA); z( T# Y- N7 J9 Z" o3 E: w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ a, o' i0 l- A4 o+ m" V9 U" hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 r4 O( |% f; y R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ P ^$ k: r6 x9 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* v+ j" e/ { U1 X1 Y |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! ~" n# x0 X2 f3 b7 t9 j' g+ o8 j# MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, x, c) Y. k) }: \* f) {% l1 x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 G0 T% \, {# R* V" Y) ]+ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 l- t+ _: E/ Q( E* a" c. ?- E2 Q" k) X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 ?+ x$ A0 p0 d/ e6 l5 ]0x00, 0xFF); /* configure the clock for transmitter */7 z7 U. {) F8 ^, w, F, x# W+ p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" @: m5 q& P" A2 @3 h+ L, G) t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ ?/ r# h$ {3 l& |. n5 t$ Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ c, A3 _+ F4 \; H2 M8 G
0x00, 0xFF);0 m) ?4 `4 V( C9 o, u
# b$ @3 _9 e& K/ U: K
/* Enable synchronization of RX and TX sections */ w" r9 Y! C$ y9 U# q- l2 N @9 ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# @+ M0 I- F& [( `9 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) m+ B8 I7 O0 l! |( d& h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 H/ O3 k* N$ r6 d# y* c** Set the serializers, Currently only one serializer is set as
+ n; b# b" _: }+ {; Z** transmitter and one serializer as receiver.
* l3 N. z' V: q' d2 t8 E) b& t( X4 ^*/
# O' |7 p- ?0 |6 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, G4 c5 T( E1 W3 ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* Z2 c2 z) `) S/ I/ k
** Configure the McASP pins
V* p- }! s8 c! L& @4 h6 P** Input - Frame Sync, Clock and Serializer Rx# w+ \, Z7 W- q" m5 \* j# A7 T
** Output - Serializer Tx is connected to the input of the codec
& r( i0 D2 T' s3 h; P*/
( D* `; ~! c Y) X" G) `5 n/ k! mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. W4 E* n" S; m4 m$ y# l6 L, J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; `7 I! L; t2 N! [7 e( J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* n7 A, n6 g4 e: `% \| MCASP_PIN_ACLKX' Y& X% O0 q! R h* K9 ]
| MCASP_PIN_AHCLKX/ @: \" x1 e' Z: s, p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 m. ^% r) h8 g/ b9 f6 R5 A, s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR l! d5 G* N. V
| MCASP_TX_CLKFAIL 0 b c# }: ^2 \" R7 |
| MCASP_TX_SYNCERROR7 S9 u. H0 c; x/ Z% F( `) W- |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" f0 F' k0 A' s8 f7 I, ?| MCASP_RX_CLKFAIL# ], F. I2 `! L/ v
| MCASP_RX_SYNCERROR
) E+ ] S4 Q- ]* t) q4 d# _( {| MCASP_RX_OVERRUN);1 Q6 G: B% ]* b+ b
} static void I2SDataTxRxActivate(void)
3 w8 L& W$ F1 i+ D6 A; K% e{. h. W8 {' u( N, x6 ^: i' u1 k
/* Start the clocks */
6 k1 j+ H, @, R) p$ s @# @6 EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 E( E/ }* A/ e6 y$ l; M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 M. j4 M9 K1 d3 N( V+ A }' c! }+ |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 P9 l/ ^3 t- y, g; {( X9 AEDMA3_TRIG_MODE_EVENT);
, P8 j; y3 t- Z% N) _7 w( FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& W% j6 s$ Y! k/ |$ K* PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 |" p I/ ^; X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 ~1 K/ i6 _. z1 GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- J S) M q- z) A) R" b7 A0 Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 F& W6 Y$ w; y' J4 `: X4 N5 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 ?. C9 e% G! v% h8 s( T5 f8 `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( ~6 J" E1 N' i" L2 W) o+ ~
}
! `- C7 E0 h* _. c" p; V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + M* L( E/ A- s! A! ]
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