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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 B* |2 v$ X, a" y
input mcasp_ahclkx,3 o' j; z& y; \: T0 F' ?
input mcasp_aclkx,
' Y" j( U9 k& z4 @- z% P3 }2 dinput axr0," D! \6 }& d* P, l( z" t) X8 Z
; K) Z8 V. Y' woutput mcasp_afsr,
2 @! N0 O* z( C4 @6 l6 S5 p: Zoutput mcasp_ahclkr,; E/ E2 Y9 |5 W [1 k1 m
output mcasp_aclkr,
9 C8 o N1 R6 noutput axr1,; @ y0 |+ u( \' V& o/ [! X
assign mcasp_afsr = mcasp_afsx;( E' o, B* b) I7 i" W9 L3 {
assign mcasp_aclkr = mcasp_aclkx;
: d- n, ]7 ]+ C! Wassign mcasp_ahclkr = mcasp_ahclkx;' }% v/ ^/ A- H1 k1 |2 u
assign axr1 = axr0;
8 c9 R/ D" ~7 x, b1 M: T0 u
/ \3 Z# U; `. N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 a+ ~( g9 D1 v; ^
static void McASPI2SConfigure(void)# e# `( @; X$ I4 @6 f7 J
{
" J7 ?* v* U4 i$ D$ t& ?! \/ KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: [" o9 S8 b6 g3 P% Y( W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, C v8 F3 @3 J6 Q! k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, G( y2 E9 ?- j* d' c3 g; Y4 O6 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 l9 X8 @2 Q1 X4 ?9 S( r" cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 J" @7 O; f7 v3 n! dMCASP_RX_MODE_DMA);
6 |4 I9 h" @1 X3 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: H' s- r' p% h; Y5 m( P3 [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) h( C3 ~' K' m1 [% S* [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & w2 ~& S3 u6 e5 Q, S7 a6 T @; j4 F; g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# |, N! e9 J+ z0 L! x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 [1 a- _* N% a8 C" aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 n" ?/ T" L# p, A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 N$ S* ?' D" v' a+ h: S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 O/ O, N( m, O7 c3 [0 p. _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ w6 l8 N$ K0 e8 M0x00, 0xFF); /* configure the clock for transmitter */7 R: K, D( g. c( S0 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 r9 Y0 `& l% lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! y+ u* v1 O, Q' U, e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 I0 e0 c" K3 n/ W7 F5 r" C0x00, 0xFF);4 N( l7 y% B, G4 k N7 C) s6 ?
" k* |; E3 j# I/ K1 P3 H3 e
/* Enable synchronization of RX and TX sections */ 5 k" T" e o( q: F7 z5 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 K* m* K+ m" a: x$ } P( o) k1 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. ?9 {0 k1 G* q7 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; `( l+ `: D2 F** Set the serializers, Currently only one serializer is set as
' v0 t& v) ^; d& f** transmitter and one serializer as receiver.
9 Y! I% c7 S2 X+ D$ ]# R*/
4 o3 y, t3 d3 \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: ~! p: L) l! u$ h* d& A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* h" ?! N* p! ?' |' N1 F
** Configure the McASP pins + U' Y' ]2 ?1 e; f, f% Y
** Input - Frame Sync, Clock and Serializer Rx7 A% M+ c: V" k. C( F
** Output - Serializer Tx is connected to the input of the codec 6 Q% e; F6 O( C; m& u1 q
*/
+ R w$ I, p5 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) U9 d; ? o, ^' [ _9 d; A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" c! i3 F# b! S9 l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( c0 a( _7 d/ e- ~# B/ F1 l: W" y| MCASP_PIN_ACLKX
5 Q# ]% D7 L: s, p/ ~$ m| MCASP_PIN_AHCLKX
0 r L) L+ v& k7 w0 c D1 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 \6 h2 u6 o; Q# \1 K) YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & S/ V. g3 o4 l" U
| MCASP_TX_CLKFAIL : \* U2 F; ^. g5 |1 [4 ]0 r, z
| MCASP_TX_SYNCERROR
( V2 r$ w. I4 w# P1 M; b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 |& e& A% ~( s8 b9 W2 \2 a
| MCASP_RX_CLKFAIL7 W1 ]: @* H# p B
| MCASP_RX_SYNCERROR " S/ V! [% J/ ?1 P, T
| MCASP_RX_OVERRUN);
* e% Y) J" }! }) n} static void I2SDataTxRxActivate(void)
+ t5 a+ ^8 s) q) V{
( k6 A9 N9 x& k! c: J# _/* Start the clocks */
, ?6 x1 z& {6 u ?4 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& ]& y1 [! I% F# `& I' mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# ^8 }8 P6 z% O' ^) I" O" [5 D! [- jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# H G- k) n# V" {/ ~
EDMA3_TRIG_MODE_EVENT);
5 ?% [' X* X1 {% T7 C! v) HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . i& u/ u9 }& m" \' k8 D, C. F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 x5 b, G' G2 c& L/ s! ]* NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, d1 e* B8 [+ R! o7 t- A, B9 y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- c" Y) o( p2 h! ]0 i+ _0 R9 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 W+ f( y/ _/ Q5 \) H0 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' n( t, d" s+ ~' X# `3 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ I( ]$ L8 P5 R! t
}
* y. v$ s: `0 I Y+ Z$ W- c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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