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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 z5 @% A2 n6 ninput mcasp_ahclkx,9 q- ~: e& ]9 L9 p2 Z
input mcasp_aclkx,
6 z4 N: K: _! c2 Einput axr0,
5 V' k: F' X6 i# p
/ X" u+ o, O( l% Moutput mcasp_afsr,& x: x; J m" _( v0 c( q
output mcasp_ahclkr,7 k) S8 P2 Z: }' e
output mcasp_aclkr,
& a( A( C$ @1 E5 j! U' coutput axr1,
{+ ]1 k, T$ A assign mcasp_afsr = mcasp_afsx;0 i. @7 t; z" E) V1 j1 u+ a
assign mcasp_aclkr = mcasp_aclkx;4 W3 _+ E' O- y$ o+ Q
assign mcasp_ahclkr = mcasp_ahclkx;; X0 u/ X- n5 }8 B# x. _
assign axr1 = axr0;
" ~0 K% P% h& F' H' Y
/ _1 O. t$ m R$ K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; x8 i4 ]" S6 n
static void McASPI2SConfigure(void)
1 v( C+ T6 s |2 ^: A{3 Y: N$ Q- D, H$ ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, Z6 v/ D. G9 }+ U4 X" k8 e9 f; F+ RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ K" }+ c8 t, F n( M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 k2 ^( }) m% j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* l' ?- R# @1 u( A$ A) p, AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: v: M: h8 d4 K9 h9 `! ]
MCASP_RX_MODE_DMA);
/ @9 K1 m/ ~& u; P7 N }5 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& S& l. `8 J# a* h2 z6 ~4 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 H+ I0 _+ v+ R, iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( W3 c$ L% l* z8 h" Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 ?) v( r! I1 x. T; F9 R! c# b3 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( X2 d: w: ~' K9 s3 t$ d# ^/ Q" SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. [3 P' Z, s4 b% H! y4 F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) P* }) d0 k( dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# b N# z# y \1 R+ gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: l# i' f7 Z: y
0x00, 0xFF); /* configure the clock for transmitter */
, v# r d; z2 E" fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 g. d! a% H( y! N" ~0 i1 Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 H" k% O8 f8 D7 B* j' Y* S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 o" x8 @) Y6 s# ^0x00, 0xFF);
9 m7 s) }% h5 w1 d$ q, v, ]. ]/ T" h1 b7 [" v
/* Enable synchronization of RX and TX sections */
, ~ f2 } ^4 z+ nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 Y1 c9 @5 [8 V1 a$ PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& `+ ]2 M% x, zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 ?( ~) g4 f( k& o" ~0 b! E
** Set the serializers, Currently only one serializer is set as: Y# S* h8 B' J* c: c4 _& x% g
** transmitter and one serializer as receiver.* N3 H$ s( z2 y3 A" @
*/
6 B) a# H T) C% K0 ]8 j- ?- _+ B QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 D. Y9 T0 X& m+ g6 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 D& V ~- S \) _
** Configure the McASP pins & e2 Q# T e' f
** Input - Frame Sync, Clock and Serializer Rx
5 K9 t2 x- K( s6 B" Y** Output - Serializer Tx is connected to the input of the codec E! P+ `' x. q; W0 ^
*/' T/ A: \ n# R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 m' [9 i: f3 u. L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" {) {& t# l5 m) r0 Z& n u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 L `6 b% p% k( t# s) m; t| MCASP_PIN_ACLKX3 @8 x! k, k/ I$ j# E2 i0 T
| MCASP_PIN_AHCLKX
0 G v$ A$ D" K' L* g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 u( |+ l3 m- l( M: VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" w9 n2 U. \" b( j, l| MCASP_TX_CLKFAIL
9 H, S% g7 N+ K$ Y& V) z| MCASP_TX_SYNCERROR; Z4 g# a* i$ K: h+ g/ q% @/ ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ I. p ^- E, j- k3 f$ s| MCASP_RX_CLKFAIL: Y2 j9 i1 E3 @: l# R+ L N& {
| MCASP_RX_SYNCERROR
) @' X" f3 d% E6 |5 u. S$ Z| MCASP_RX_OVERRUN);
/ M! a( d5 _$ t2 l6 b$ s# P) V} static void I2SDataTxRxActivate(void)6 \) U$ L) g. Y
{( j5 Z7 ?/ P/ Q" J! z) ]
/* Start the clocks */
0 [& x4 m5 t; U2 l; \0 {; ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 b7 z" e$ [! w3 t$ x) [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 X5 |4 P8 w! V# ^& `( l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 X% d: B. @ Q
EDMA3_TRIG_MODE_EVENT);
- Z8 @2 z/ `3 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; z% D9 j3 h) Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 |) N# w6 w" V( ]$ R+ ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* U# j8 Z# D! _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 n. ~5 i7 [& ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) @. Q1 D6 P9 C+ MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* \% Z. {4 Q3 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% b8 ~, X5 e1 u* f% @# _! V
}
. n) {9 g- m7 z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 z) r6 \0 N" D3 p* m
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