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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 j; c5 K$ X. k2 Xinput mcasp_ahclkx,
# M2 C$ _1 b N7 _' tinput mcasp_aclkx,% N4 K! y/ h' s H2 p: q" e
input axr0,
1 Q9 N# u6 B5 { T% |' b i- M" O
* D: E* Q6 @- a8 K( A8 }, E A" V, Moutput mcasp_afsr,
: o, f) H3 i' {& ?! b- G- uoutput mcasp_ahclkr, p) p% T/ Q6 k X* l
output mcasp_aclkr,
* ?6 |, [/ @( F koutput axr1,
4 j0 P" f% g* X: P' | assign mcasp_afsr = mcasp_afsx;
: l4 ~7 T8 j) ]6 G' Kassign mcasp_aclkr = mcasp_aclkx;/ {* I5 l2 R6 ~
assign mcasp_ahclkr = mcasp_ahclkx;
$ p& W0 g3 n1 Eassign axr1 = axr0; 7 O3 E- `7 d7 r4 t% D
$ u1 c- o0 Y J' d" t7 s e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 D8 A7 ~- V; M
static void McASPI2SConfigure(void)
& e- q4 ^* R) h% i$ L{
1 r$ ?7 _9 G& i p% q9 ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);" C! V6 d, Z$ U( ?5 m5 ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" y4 i2 O o6 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; v* D) |! @) R" K! G8 A6 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 A, o [5 ]! t# F4 c/ \& B& ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 J! e' O1 Y" F. V3 L$ `$ hMCASP_RX_MODE_DMA);* Q: l, }& w8 h( G" ^% X0 z8 S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 a- ~, m" _) R8 v' TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- v7 [% j. _1 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . H J4 U% t O8 [6 |; m( O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, _2 O Z$ ~- }5 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: J* b6 K/ X2 v( a o$ U& {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# x! S7 b, e$ u/ I T3 D7 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% l3 N- b3 p2 R8 i+ l( [9 n/ t8 t: o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & k" E/ k$ D$ o" f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 f9 h- X$ U; S, W
0x00, 0xFF); /* configure the clock for transmitter */
& l! {* G9 g6 G: X: F, pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) ^8 P4 p- m% O# ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 Q* S) R" \$ i2 OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ @' Y/ @5 _% @* o0x00, 0xFF);
# r7 X8 f2 q& ]8 m3 g2 o, ]0 x
8 {1 t3 d2 s3 ^6 t- P0 O9 Y/* Enable synchronization of RX and TX sections */
2 n( n* d2 I: o0 TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ K2 Q, L8 p6 V: y) Q+ xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. `" F2 x8 ~$ m/ Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ s2 w' s+ g- R! ^
** Set the serializers, Currently only one serializer is set as
% _4 I4 J7 t9 n: c** transmitter and one serializer as receiver.
/ N& `/ ^' B7 h8 c/ p! u, k+ B: M*/9 L8 C7 U O; M! k: b# H5 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. T7 l2 v/ i+ h3 E$ b+ `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 s# a! G9 R$ V9 p7 H: M
** Configure the McASP pins ; W0 V% r& J4 u$ ]" d; e
** Input - Frame Sync, Clock and Serializer Rx* O* Y! Z0 z" ^$ [! A6 ^0 z1 e$ B
** Output - Serializer Tx is connected to the input of the codec
" K- h- n4 ^! H1 k& q1 d" {8 Z*/
! V/ } ~: e5 P8 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( i d+ z1 [4 e0 a( O: r7 {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ T3 k1 G1 k4 F, @$ O0 T( w6 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. E; t0 I' q' N( ]5 _/ \ \. ]| MCASP_PIN_ACLKX" c3 ?, ]- V8 Y
| MCASP_PIN_AHCLKX0 C8 K4 S* j$ q+ S; |# b0 {/ t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 `( b9 R$ h5 _4 ^ [; Q5 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# C* u9 k7 ~/ s9 F| MCASP_TX_CLKFAIL / v; K7 P n1 A1 d/ P0 R+ @, D
| MCASP_TX_SYNCERROR
. D, R1 p6 w+ M9 U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 R/ g% o9 L; l; p6 ?0 j& @| MCASP_RX_CLKFAIL) N8 u0 K; Z. ^; X v& }
| MCASP_RX_SYNCERROR + l3 A8 Y! e6 H F) ~. z
| MCASP_RX_OVERRUN);
, ^$ h6 x7 `" X$ u+ X8 L} static void I2SDataTxRxActivate(void)
6 S1 t- ?8 u% Z- k{
8 H& G5 Z8 j7 i9 X; t/* Start the clocks */) a$ Z; n/ n- n" n. d# v- k4 J6 q( m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% ?0 u" ]9 b* MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 D+ d8 h1 U, YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 j1 T" V4 b0 }- p8 X. j
EDMA3_TRIG_MODE_EVENT);8 |. |2 l! l* V: v9 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) y6 H+ f0 O; O' MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ S c' W' @( v; n3 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 w. U, Z# r$ J6 E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 Z7 u" r5 `9 C- Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 M$ ]& a& C# J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 V' w) ~) ~' R1 i0 X- C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& [) L: W% A! H0 q: N; S} $ ]* m/ H# y9 l! @. [! p- z8 z( r/ Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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