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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ {, m* H5 ~( c. z# X. Y
input mcasp_ahclkx,
* \0 e0 R3 t" y2 _; einput mcasp_aclkx,4 ^" l1 h* Y" f
input axr0,, W Z }9 X3 M0 M6 F
@& U5 t# v) doutput mcasp_afsr,4 i( o1 K9 C: q. R/ T
output mcasp_ahclkr,
9 W% ]5 M+ d% E# |0 l. Q2 D& Eoutput mcasp_aclkr,2 {/ i4 s% ^& A% m
output axr1,
7 {) Z$ U/ b p1 Q assign mcasp_afsr = mcasp_afsx;/ i1 T# F7 _) q3 n: t
assign mcasp_aclkr = mcasp_aclkx;" D5 j+ N/ m* G9 j7 {' D) \
assign mcasp_ahclkr = mcasp_ahclkx;0 u- p8 C+ q2 {
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 X- i4 R) _9 C
static void McASPI2SConfigure(void)
& ?, ?3 `( ^. A+ U+ i{
: C6 ^/ Z7 C! B* i" K7 w6 FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, F, Q5 J A9 e+ l; K( c2 LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! r3 s9 M/ {6 l- Q( H/ XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 C5 w# z3 { @3 W4 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) T$ R. p u6 s4 s* z; Y6 @( x$ DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% g$ e, Q+ h, S+ f: Y' K' K7 O
MCASP_RX_MODE_DMA);
o; M: z. K/ Q8 c" _$ W5 i5 lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- y# I" p! X3 rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* U: P0 j, V) t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" R1 a, w( J5 r: pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 P5 m$ D% P* `5 y' e3 u* {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, S- |& d4 S* S, F3 {2 E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( l$ ^9 F, y7 z1 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 a/ p6 N) D L3 n, Y: ]( q" b2 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( I4 \: l8 R7 d ?$ M) W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& z; n O+ [- B( e/ f1 m8 A
0x00, 0xFF); /* configure the clock for transmitter */- @3 M, I7 m: G7 g* u3 l; c! r5 G' E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 R3 n4 b1 Q+ ^3 a! D$ d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % y% b4 Y2 z: H9 c4 K1 z/ [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) `3 b* x# Z; r4 `6 L1 W$ X/ ]0x00, 0xFF);
( d! X! i: Q$ d0 ^3 c0 \
* S2 E0 [( z" Q. q2 E) v$ ~! `* V/* Enable synchronization of RX and TX sections */ 2 @; c H# I3 C) s, j3 x* {2 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ Y" m, o* m7 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 h. L' e t; `+ y1 P5 B0 ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# B: }6 F6 J+ h/ I1 |' h
** Set the serializers, Currently only one serializer is set as
' n3 p+ N- K4 `/ |& T! o** transmitter and one serializer as receiver.
) a( _0 m3 u \2 r! h' q*/, ?1 J% a. D1 a, a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 T$ B7 \8 j+ ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ S9 O# ?% T5 o9 c** Configure the McASP pins
% Q8 [# W9 {; ~% e/ t2 h0 K** Input - Frame Sync, Clock and Serializer Rx
. { |8 n* c! y+ a) m** Output - Serializer Tx is connected to the input of the codec 0 {; D4 q. g2 r6 u# P
*/
' N& Z# {, _3 x4 T/ z' ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; v8 d3 d$ D! g6 B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 k2 w% W& f- V2 TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: Q6 c0 A" T3 k4 R$ @* z! Y0 v: C2 x1 E8 }| MCASP_PIN_ACLKX& Z2 e2 t, t- n+ t
| MCASP_PIN_AHCLKX
% G: V/ |9 W, h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( j) [- h" F# ~$ c: u. y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # R' ^# h& |# H& J5 k" f6 _
| MCASP_TX_CLKFAIL " b, s6 v' O8 ^# t- O8 s- u
| MCASP_TX_SYNCERROR
9 c$ g, f" C/ T) u- ?# c+ o' t: f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 l2 x& V& j C. J
| MCASP_RX_CLKFAIL; E1 I8 D5 k3 j* X# N2 k, G) W! Z
| MCASP_RX_SYNCERROR
/ ?0 R1 k8 h# y! v& J1 e0 f* Z p| MCASP_RX_OVERRUN);
" T% R% @" I. I} static void I2SDataTxRxActivate(void)4 V7 X3 D$ W/ i2 j: v: k
{- ]4 W( h) ~& Q4 V
/* Start the clocks */
9 H/ h( N9 K6 w, C5 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 P6 Q. V% k7 a" _6 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) n, d/ c. u1 o' k+ W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 u5 \; w' C& \% `0 F+ L5 aEDMA3_TRIG_MODE_EVENT);# N6 ?, x+ `3 a2 i0 P5 O. T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - A0 K4 s) J; S( I3 s ]' Y; E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. P; O0 E; h' k$ f# X9 I: n4 H# c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 Z- n+ x2 l' `( F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# l' H1 c- y2 C2 U/ V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 o/ D1 F2 G ^+ q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); l6 r! j, y8 k2 o6 K7 a9 X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- H$ H. |0 e( f; s
}
; V$ L% J3 T3 a& g: ?. j& J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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