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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 {+ z/ H& u: ~4 \5 Y1 g+ ?input mcasp_ahclkx,
9 J( V2 u: X. Q+ j( L finput mcasp_aclkx,7 ?; w9 A4 k' @
input axr0,
9 A% Q$ P/ T/ P) F* }" Q
* \' C" J1 D% s. Moutput mcasp_afsr,& s( m8 R' L) t) l9 O# n
output mcasp_ahclkr,
# V: _, U8 I% i' E+ Loutput mcasp_aclkr,- k- k1 _; ]5 j& Z B V( @* m
output axr1,
! D! L4 v) o4 K+ @ assign mcasp_afsr = mcasp_afsx;
- D* _4 |* A" E/ J) d; B A Kassign mcasp_aclkr = mcasp_aclkx;- n8 }2 X# q/ b" T- H! G
assign mcasp_ahclkr = mcasp_ahclkx;
# t- {/ b$ X. ] [ qassign axr1 = axr0;
) H6 G# x" r0 i- N- Z* Y# u# U, i4 N- d$ g4 e$ C; D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 i" W0 k G2 ]# ~static void McASPI2SConfigure(void)/ ~$ W$ U7 o9 ], @
{+ C' x8 } ]4 r! @2 i, V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 e1 H& h4 [) XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ {1 U! ^2 \6 p& V0 |$ }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 J, Q' ^& F+ u2 y- f- d/ b: MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 n7 C# t; t' ~* sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 D4 O. o; q6 Z, f' P- G* p: D9 }MCASP_RX_MODE_DMA);4 R) l. D+ _8 l3 J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, f3 _8 j8 I L C: \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ B3 X; V. P- w& M& y" g$ yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 h. V' a' ~' n' a4 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); k0 T8 I% Z: S% m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 T s. s1 f) i ^ g0 H. ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! d" ~3 u" v4 ?: y$ GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 X; q( J- @5 R) a4 T1 q, x3 ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
b% Y8 W# F/ p- S: |) ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 \$ j: k+ }7 ~" k# V" L
0x00, 0xFF); /* configure the clock for transmitter */
w( c, ]# Z6 K+ O+ PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- c9 l6 U9 c9 f$ j& q1 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' S* ] @1 j2 `' i" D6 z! y6 z# [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* T# w: _9 w2 L- I) R5 B0x00, 0xFF); r/ g" H% a* h1 u9 l3 ]( `
" C# T& f$ z, x9 @( ^6 m: D
/* Enable synchronization of RX and TX sections */
; g% U- O' B5 [' ^! q) IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) m% a w5 C- {% o2 S0 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 O3 N- n n% Q1 V3 x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 s! T) n& i$ _ o1 z: J# s. _
** Set the serializers, Currently only one serializer is set as
: K @" m* a& Z, ~0 V. T** transmitter and one serializer as receiver.
6 r( q: r- y8 r- a*/
3 l5 F+ F. k$ F1 V+ {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 {. X- W" [% q# E' GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- H N7 K5 [* a4 n( b
** Configure the McASP pins
' i3 V& ]. b( B" Z8 J% E% W** Input - Frame Sync, Clock and Serializer Rx! w! C z4 R; \! f8 v5 p% u
** Output - Serializer Tx is connected to the input of the codec ) J6 b, }3 b7 ^9 ]7 W# g3 O
*/) K% Z! d: M; g; }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( ]3 m& E- }! F3 `8 |* b" A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
\! \; r u" d3 ?% W) YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( V+ U3 \& V8 F. D
| MCASP_PIN_ACLKX
$ K. v m N, Y* y) n" f| MCASP_PIN_AHCLKX
& z. A9 k3 a. Y- h: K) G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* ~9 z V$ u. v0 F- z6 H& wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 E+ A" Z3 g6 D2 w/ Z| MCASP_TX_CLKFAIL
/ c0 m0 H2 |4 O/ U| MCASP_TX_SYNCERROR
: m/ k2 w$ Y$ s/ }7 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 S" S$ U1 v7 j
| MCASP_RX_CLKFAIL
9 ?, O% M+ r1 v5 {( W6 G| MCASP_RX_SYNCERROR 4 Q5 L9 B- X+ E! m" P" ]
| MCASP_RX_OVERRUN);
# a5 }% L: N& ~, z! R} static void I2SDataTxRxActivate(void)
. c& N( c* ~6 z" f+ k{
. m3 o* a5 t! r# `) F# I: C/* Start the clocks */
3 k. m- k8 w$ l5 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 t$ X4 N0 p5 L7 l% ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; h: ~6 ~; @) D I Q& tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: r7 V9 D! j' e+ i* DEDMA3_TRIG_MODE_EVENT);
9 t$ l7 A4 W+ `7 |6 R f FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 N# q/ q7 m0 S! A$ j$ U6 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 {8 J6 X( M. t; B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# }" @0 u* @& H1 C+ `: Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& C: r7 \( ~5 X6 H' X% Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 a! N9 Q: [5 s/ M! m% o: \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 W$ ^+ W) C: z. J- ~1 m: I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) O* y7 ?7 O* [; O; r5 S
}
; M2 P. }6 G1 s: o: p j+ h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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