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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," F7 U; `( Q2 {: V
input mcasp_ahclkx,2 O2 ~7 s+ l& g' {
input mcasp_aclkx,
- G. W& X5 |5 A4 p+ @input axr0,
' h5 n. @5 p6 x1 r' m
5 ^* T2 j3 \: m2 I soutput mcasp_afsr,0 n6 ]2 T4 O9 }/ ^8 v& J! \
output mcasp_ahclkr,
' }6 t9 f6 j& H* joutput mcasp_aclkr,
- R: m, v% {5 M# ?/ `output axr1,
6 R6 ]; k z2 M5 C: x5 X, T% _" y assign mcasp_afsr = mcasp_afsx;" A5 b7 [$ p+ A
assign mcasp_aclkr = mcasp_aclkx;+ R& f1 s7 ?# g! z6 u8 T: J
assign mcasp_ahclkr = mcasp_ahclkx;- R- }* b6 Y5 D# Z7 N3 c
assign axr1 = axr0; - U' A; h& K; e& g. S
; u4 B* V/ P1 d( l5 q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 f0 U2 ]/ W: c2 p! Y
static void McASPI2SConfigure(void)
4 J1 i- e0 L1 c4 a{
: n4 w& b5 s5 P, r" u- yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 ?% E3 Z) N; a, _3 J9 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 R/ X; `1 p8 w7 |4 T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& Y+ y) {/ ]% u& y7 o+ IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 p6 ?* N, D) }5 xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 n4 Q7 k* s f6 z& S" o
MCASP_RX_MODE_DMA);
5 Z" u$ x* ] r6 E) rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 v/ v8 F+ A1 C) i; ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 r4 j0 ~, z1 u8 F$ R: Q# mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. c5 m, x; R7 ~& O% r- @7 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ I; h. A2 V' u6 kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) j4 d0 t& }; V) O3 H2 m" H! x% aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 q, n t+ v' Y5 T/ q. G, h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 i) P% s; a: H: A& l$ M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ A* c& Z8 K( Q- S7 b! lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( l3 ^2 K H- P+ Y8 L6 G
0x00, 0xFF); /* configure the clock for transmitter */3 j% U g" j# l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" ?' `, u. c: a& y! p3 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! q1 O- X5 X# a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 M! w5 Z0 B% u* V0x00, 0xFF);7 t, j! V4 v5 U2 | T) V+ m8 K
" l& D4 L4 A- r" A# O. y8 n
/* Enable synchronization of RX and TX sections */
/ k' C0 g5 d8 O$ I+ u7 ]$ jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! U O( E2 k- h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 h) _ W* L6 `; j! q5 S2 e4 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 m- K; U! l R" f/ C** Set the serializers, Currently only one serializer is set as; x w I- O0 m8 ?: n1 K: ]
** transmitter and one serializer as receiver.
" p& L2 o R2 o4 p+ x*/& x: v* w' c0 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% F1 }5 {1 | d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. b4 J) c# ?1 {/ @- o** Configure the McASP pins 9 P9 I- Y2 I& m3 H5 F/ Q
** Input - Frame Sync, Clock and Serializer Rx
2 R. F8 @; D2 C5 y** Output - Serializer Tx is connected to the input of the codec , u4 v% h) T% P/ m4 u
*/
' ] J5 Z+ |$ e) r- h2 C5 JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; i4 g# ?' b1 q! Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 f& d( H4 c& k$ R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" C" ^/ k+ i9 [( x) C. }
| MCASP_PIN_ACLKX
2 S8 }( f- d y, i5 S, n5 T| MCASP_PIN_AHCLKX8 M9 E, x8 }9 W5 c, y D% N7 Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* b! Y- N- O# C3 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! k3 C+ A8 a6 O. ~| MCASP_TX_CLKFAIL
- n# }' ^# y3 [) r" t* W% O4 x| MCASP_TX_SYNCERROR; U. f8 g5 w& A; I( ~# ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" p: l6 \! u* M0 j| MCASP_RX_CLKFAIL
6 V" q v4 j! ~/ ]0 W- T7 a| MCASP_RX_SYNCERROR
9 y5 I$ X9 C; P Y% v| MCASP_RX_OVERRUN);
1 ?# W6 I/ n, Q3 g% l} static void I2SDataTxRxActivate(void)
# ~6 o: a9 G% V8 }" l% _1 N, j{
t; Q p3 W$ J" c/* Start the clocks */+ k8 v- N# o9 d( ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 P4 u( h. i! B* `. a7 i. K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' e0 O' E' ?4 E: H) mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* S/ J/ Y# |8 h6 i! ]* R
EDMA3_TRIG_MODE_EVENT);
$ q. J: w. D6 D' V) i4 h& e8 gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / K1 ]6 p+ A, {, n& [) c( R* l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. Z$ u0 E( S+ c: }' V" `' c9 ~# a3 g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' n8 o0 V; w# H) z( k6 C+ E3 CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 |( w0 ~# ~9 R/ r% D. y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 t* h ~8 m9 x: N: T/ `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% V2 ]0 I) _( p/ q$ J* y( OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# D$ C3 }/ p% e( Q
}
4 x0 B7 M# \" D& g; }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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