|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& w1 B" Z8 U4 ginput mcasp_ahclkx,1 Z( q* M! e' c2 i; J5 Q9 o0 z( ^, g
input mcasp_aclkx,7 p6 Y/ L2 V: b3 R& x
input axr0,
! }7 }/ ^# K! E9 o. t3 d9 {' s1 t0 ~! `1 n
output mcasp_afsr,
& T# W6 H" r( S3 f; h/ M1 L% _output mcasp_ahclkr,+ }( L, `& P% W8 L6 X$ A
output mcasp_aclkr,2 |- d, l% ]) u3 `* d
output axr1,4 G3 `& ?3 \1 x0 R( }" f! w
assign mcasp_afsr = mcasp_afsx;
. C: w5 T. U* Z& o% Rassign mcasp_aclkr = mcasp_aclkx;
+ w& ^3 b$ ]. |9 x x+ }8 M% Tassign mcasp_ahclkr = mcasp_ahclkx;
* d6 o# F5 t# y x; M$ ^8 K! massign axr1 = axr0; 4 K X y& ~% M3 d8 P, A4 X$ u
5 W f1 k' v7 q( Q3 c3 f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " q' f: h; r; N: t
static void McASPI2SConfigure(void)5 Q/ p& k: [8 y' q
{
6 s+ O8 M& c0 C1 l( z9 O& uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ M4 g/ l- u: {1 S' P4 B/ q7 ~( V" gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: Y& v1 A6 Y; j$ I2 V/ y* k4 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" Q1 E6 X# S1 V5 u4 \7 V3 `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& W6 g% `6 i, g9 ~& _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) `/ H) B+ q N& z
MCASP_RX_MODE_DMA);$ G7 G. O, x7 z$ ]9 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. g8 J! Y$ K, m+ Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 V" R- C9 y1 j2 `) g$ n" {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 E) G; u5 ?8 l/ U# a5 o, u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: {% z3 ^/ o1 T* F) @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 q- v, Q h) C8 HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' z9 T7 Y1 H% T. }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% Y# t' K# D+ z! B: w( J# P: P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 Z7 R+ Z2 v' H. Y5 |! u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 U* I0 L' c! d' \; K0x00, 0xFF); /* configure the clock for transmitter */* Y: ]9 L. Y1 Z( j( Q* y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 d) k: f. `' w2 X+ F0 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( `9 l3 I. x3 P) yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 y2 {7 G$ ~$ z8 {- b0x00, 0xFF);1 b% T# K$ C, w8 F4 K' k% c* @3 M
" P% ^+ q' z# W
/* Enable synchronization of RX and TX sections */ 1 ^- e% f+ p4 {& j7 u f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! b' E! Y, {$ Z7 |: m# A' OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' {- n# d4 @3 w& C: }! j+ E& sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! X) m0 A& s- l9 K' m5 n
** Set the serializers, Currently only one serializer is set as
. R9 @# ^% m$ E" z" K** transmitter and one serializer as receiver.6 h$ D4 }$ `' i- T
*/; S! x& ^9 I( ^0 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! S; T6 W! G DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 O8 X, v+ A( ~7 G% C4 @% [: X3 l/ D** Configure the McASP pins - Z3 j% p j8 E+ \0 g
** Input - Frame Sync, Clock and Serializer Rx
( o' b1 m8 v1 R% U** Output - Serializer Tx is connected to the input of the codec
+ q- h+ P+ n9 j% l% e*/
2 s% E! F6 i8 { i+ A9 P, nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% p/ e+ P- s; w- v' D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ }: \7 Z6 Z$ y; AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 v0 P* N& G+ [! K1 {; v| MCASP_PIN_ACLKX: p' r5 [5 x& f5 w. H
| MCASP_PIN_AHCLKX+ U7 D0 }- _' w o4 \% m9 N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, n& j' t/ A2 s2 t+ {* W" [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( J0 X* j7 I% D0 |( l( _| MCASP_TX_CLKFAIL
6 F& d8 {9 e' d# j5 i, v4 q| MCASP_TX_SYNCERROR% E b7 t# r- e$ ?+ W$ v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 L/ t. C' D$ H- B| MCASP_RX_CLKFAIL4 z y/ }3 e7 ~* r+ p$ M
| MCASP_RX_SYNCERROR 1 Q2 j! q5 J9 U: B8 j D; r- E
| MCASP_RX_OVERRUN); W9 B* f! D- d/ \( R, A# f+ i
} static void I2SDataTxRxActivate(void)
# _( B) f8 p1 F) b* \6 Y E{
* w0 h9 |' Q( m5 y& a5 ~4 p/* Start the clocks */1 t4 w% C8 _& h! r/ R6 _! d% P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- s6 v+ S: u! d$ JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) u+ I2 t3 f0 L* s: ?/ [/ {) j3 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! {4 |# J. ~4 a+ [! k
EDMA3_TRIG_MODE_EVENT);3 @0 D6 N5 M& `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 S# ~2 Y3 _+ W6 K/ }& h' M1 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 \9 i* p( E2 t; t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# W9 a, V/ B$ X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! q% ]. `5 v8 E# @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- ?4 i1 S( J! N$ N3 A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 o% h6 S1 M' t* E4 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 Z6 @) M4 I& [8 n! J9 V$ L
}
6 R+ M; V/ O) q& E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ C# ? O9 i; t" i
|