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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. F: ^9 W! n& J2 F& Q, p: d
input mcasp_ahclkx,
- M7 @- D; Q3 G1 O( z# t, kinput mcasp_aclkx,
8 N: g8 u% d: h, O8 ~input axr0,- L3 P- B$ U) j
4 y% O. ~5 s1 a* {( poutput mcasp_afsr,
* X6 u% i0 b2 `" aoutput mcasp_ahclkr,+ J6 g# V1 N6 K9 [4 c
output mcasp_aclkr,
# M, ^6 j6 b9 E0 g: j5 o5 Z' youtput axr1,7 [% K7 C. v* a ~! e0 I- I$ h
assign mcasp_afsr = mcasp_afsx;# R2 n1 t1 m/ i/ |/ X
assign mcasp_aclkr = mcasp_aclkx;
4 [3 D, T5 S. C9 Nassign mcasp_ahclkr = mcasp_ahclkx;
3 Q: n- T8 _; Z/ fassign axr1 = axr0;
7 |: p- c1 c5 f7 S* X* k V8 O5 R8 O, Y S( u4 K5 V9 A& X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 P% S# v- p7 H
static void McASPI2SConfigure(void)
# z& Z6 T6 A- u% f9 l$ e, X+ l$ `' J' m6 r{8 |7 K d: d. J; D& B* _7 G5 z4 |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 u" j5 Q5 J5 @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ v5 q6 ^0 A. A3 Y: V5 T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! y+ x8 w) P& n2 ]. \0 M* OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 }' z/ y6 ^" A# A' U$ E( {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# X; x3 f: q, z( k) f; `; yMCASP_RX_MODE_DMA);, T( `& ? X& k+ m3 M5 m: x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 P& t- e# x2 {( T. O+ y& u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ T N# d6 @/ Y8 ^9 g& _% Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 r3 s$ s9 f5 E" i3 E+ ?, B& [, qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ ?, |" L6 t/ m) ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 P2 ~' N# v# @& S9 ?0 f, J" l6 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: U8 c5 w- v2 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 A% E- ]: n" \$ n* a* o5 |. [: OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 w/ e/ p' V# Z* QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ F) \5 D n# A7 q* S9 b2 s0x00, 0xFF); /* configure the clock for transmitter */
" i: G; _3 x+ D# gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 }6 z$ ^: T' F4 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . K8 _* M6 M9 s6 F: o6 W; n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 t% F, [8 n3 @! R% U; w6 p0x00, 0xFF);
/ p- |9 Z! N& a! l, |1 w6 m6 d
, O3 i$ Y) `0 e/* Enable synchronization of RX and TX sections */
1 n3 t5 t& B, y9 s0 k- m2 bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 i" Y# r9 d) i3 x5 z0 ?" gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, q: W# ~( X6 n# i" t: L# C3 }* ~" FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. I* l9 V* j; e4 X# \0 N
** Set the serializers, Currently only one serializer is set as
: a; L. f: A+ K( K' c** transmitter and one serializer as receiver.% p8 O/ V' K; S+ L3 h3 @$ a
*/
7 j9 Q) `1 {! N4 J2 z( j [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ O6 x) k( q9 c0 E8 G" _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 V9 [& U4 p# P! j
** Configure the McASP pins : K# A' k$ {3 P1 \5 T, t
** Input - Frame Sync, Clock and Serializer Rx+ |* j6 y/ V# {
** Output - Serializer Tx is connected to the input of the codec
* D, y- Z. ~4 o9 T! l4 H+ g*/
5 `$ K( t+ z O9 g3 p0 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; i3 Z1 j4 V3 A! dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) v9 M5 n7 I8 v, R( H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, [5 h& u5 G q# H" V, E
| MCASP_PIN_ACLKX
9 F# ]6 \) x& s/ B# j* a, r7 K| MCASP_PIN_AHCLKX- A) o9 K* x( f2 g! b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 l5 H/ E' Q/ M5 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - J( k Q, ~& V2 B8 |
| MCASP_TX_CLKFAIL
9 I/ ]) q3 L+ ]; T| MCASP_TX_SYNCERROR
9 s8 D |# r% [" M$ y+ U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& \- u# s" g- @1 a& \7 Y| MCASP_RX_CLKFAIL" B' I; s/ U3 q. o
| MCASP_RX_SYNCERROR
5 ~; ^* T& L5 Z! q6 b| MCASP_RX_OVERRUN);; L" u2 b/ b# @5 D0 i
} static void I2SDataTxRxActivate(void)
5 J! e; m" X$ ]3 U6 T( h ~" ~{9 K. u6 p A* r. S1 [) y9 I) @ S
/* Start the clocks */6 h; s1 z) O3 r0 S1 r- W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- n9 X* w, ~" I: a1 h; {" O" wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
E1 g$ X( ?# }6 K6 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 A* {" F2 i8 X& V
EDMA3_TRIG_MODE_EVENT);* Y5 g9 i( w7 q- Z' x% V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # V( s8 e# P; o5 G$ N/ K- m: I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 K: y6 T6 V4 Y; Z- O ^! gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) w9 n8 t5 B1 D" C0 w g* gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 k* L( H4 u) c5 m& V3 P) U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, `) h- x2 [4 VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 a/ g: W# h$ _% b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& e' x3 a# r/ ~; j# P} . t" K, B x5 H$ g, U, e9 b8 F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( Y+ a6 j& k Y4 p
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