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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( [6 `& O' P) z! v9 H- R+ ^
input mcasp_ahclkx,7 T% Z9 j0 _$ W" Y' \+ q* L
input mcasp_aclkx,$ o( e* X3 D& _/ [9 v( y
input axr0,; O( m( { X: I* R- K8 X
9 H. e+ ^! U6 L6 P6 _+ V, ^0 Z
output mcasp_afsr,$ }! W" c1 r$ u9 g! T
output mcasp_ahclkr,
# x4 r" A8 x; z: q! L9 g1 koutput mcasp_aclkr,5 a/ t# Y9 Z# s+ ?0 {0 n
output axr1,4 s4 q6 [: }& O/ L
assign mcasp_afsr = mcasp_afsx;
P5 r2 S" i& {: a# [* dassign mcasp_aclkr = mcasp_aclkx;
; Z3 ~6 u4 w! N3 r5 d6 bassign mcasp_ahclkr = mcasp_ahclkx;
* L: r4 n- b5 u: Q; t& Passign axr1 = axr0;
" ~) n$ F& @0 @ a
# ~" c4 z: _ G/ @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) o% k; V* D! X- i7 q! i+ ystatic void McASPI2SConfigure(void)2 `9 P# t, ~$ ~: I! ^
{
: ^0 }. c1 [- n, E7 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) B# X! u" p# ^. u7 M; U2 B% c( A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 r ?; a3 R" |* x3 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& F4 ?# C' f* H. o+ t: OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, a ]( \: M# w. b$ {4 J8 b+ q3 A! WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. i9 N' w- C5 N' W/ W
MCASP_RX_MODE_DMA);1 q) }. H$ `! R5 v( R3 Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 }. I: T$ ?/ k3 M- W6 Z/ ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 |0 y8 k( I* x1 J# ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 g" [% \; b! @2 C0 r# u' [' U4 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" T# p& F) L: _, R, g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* ~1 \( Z6 y6 D/ |6 E- ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. n* J# O- c. O( D" ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 s' d1 v5 q; _7 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) V' @2 Y V& y( F" k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; F. C" | b( e" s& ?4 Z2 J( o0x00, 0xFF); /* configure the clock for transmitter */2 K% Y8 m+ t/ ^) B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! C8 O' S {! F! ]: UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ l* C; Q% N" O5 E" T( B- S! `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: N' X8 J" I2 E" E5 c& \0x00, 0xFF);) f) u- V5 z) o' e" F% ~, U3 L
; O- x/ r9 C1 w+ {' ^; r# V$ d! Z
/* Enable synchronization of RX and TX sections */ + c8 |0 E$ j$ o" }0 m& S7 Z3 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 F1 I; [' P# ~% ~; hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# j- M+ j1 [, n1 _* p5 |5 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 b4 q9 V U. m% r( q; Q2 n** Set the serializers, Currently only one serializer is set as0 M. d% o. V7 }7 i
** transmitter and one serializer as receiver. A6 g x; D: m5 E# s7 t
*/
& H9 [# V4 R- h) \# GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( w5 Y% V$ J0 I- Z" f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 ^! m. a% k& @* a1 s. C** Configure the McASP pins
% c k1 X5 M. F; O9 {# _: q. ]** Input - Frame Sync, Clock and Serializer Rx4 T9 u: C$ N( o' t& `9 Q; p
** Output - Serializer Tx is connected to the input of the codec 4 b( s% y4 O( X* \- N! x. J8 P
*/0 C8 S2 E4 t2 e5 v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 r+ \) g( M( p) d0 o6 L, mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 i3 t' I3 C- M5 ?. JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# x) z( ?- x/ }( U& P0 Q2 p
| MCASP_PIN_ACLKX( K/ F2 X6 ]9 ?! \" y: F9 x) J2 |4 e
| MCASP_PIN_AHCLKX8 A% [3 |0 Z/ x. h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% Y. G: m8 A/ h& R0 U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 S; r; V/ A, n6 Q
| MCASP_TX_CLKFAIL
m; h2 m$ z9 b! L `| MCASP_TX_SYNCERROR; g9 R/ w5 T' {. u0 [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 a r. g' ?' _| MCASP_RX_CLKFAIL
( E- h( S6 k6 x/ G9 p/ u# k; ?| MCASP_RX_SYNCERROR % \2 x8 c5 z+ D; K0 F+ |; q! f6 U
| MCASP_RX_OVERRUN);9 F( {/ K+ `, U
} static void I2SDataTxRxActivate(void)
2 W4 |( ?; B6 Z( |7 J{
# r6 g7 x' R m: N! c& E5 V2 q. ]/* Start the clocks */
" n, I* x+ ^0 p& v% G4 h( o; CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! }) l' g# B$ v* z' v3 Z/ AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 c5 v5 f; T! AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; c) b* \3 ?' K' m5 q2 {, dEDMA3_TRIG_MODE_EVENT);
# O! W1 c5 x2 j4 C: G/ E, i/ k2 Q. d! bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + f, t: N" Q$ ?' l# _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 \, H! E! b; K$ j6 sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 O' M \! h* r C1 Z; x$ S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( n: j5 v5 z1 b: C0 f* ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! w, N& ]3 M$ H% Y' |4 r, \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# u5 T" E9 [" r! ]# T6 LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 }4 [6 i% e0 U8 R: E$ [, a}
6 t; U* W/ ~: m$ z% ^* y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & i- n( g4 o4 Y$ ]; d
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