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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," b5 Y. u/ i7 [6 a! Y1 S2 l
input mcasp_ahclkx,
8 X: o7 p" O& S, s3 }! Q& P. Q! xinput mcasp_aclkx,0 D' [) v7 @+ ~( p( B+ q6 W
input axr0,9 T. @% S. _4 A7 Z; z
2 f' }$ u1 g8 W6 q N
output mcasp_afsr,
+ t+ S1 x* c* @6 c( Soutput mcasp_ahclkr,# A& H7 P# ?/ o7 V! Q
output mcasp_aclkr,2 R- l* o g) a* m U M- l
output axr1,
& n8 {* b" b; T assign mcasp_afsr = mcasp_afsx;
' Z7 f% `3 w0 Q3 Xassign mcasp_aclkr = mcasp_aclkx;
) F8 T+ _# S. ` D q# p) I, o8 Bassign mcasp_ahclkr = mcasp_ahclkx;
6 `2 _( r$ B2 iassign axr1 = axr0;
/ c1 d, I2 n# X1 b; w2 w
5 r' ]# e8 `9 p, s+ V" o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- t; d. y, p* s2 {/ wstatic void McASPI2SConfigure(void)% P5 @5 M0 I+ |2 G7 l3 \/ ?
{8 x! V+ k4 e9 Q2 M3 Z% u, f! O5 V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 S$ j# f4 h- X. i8 a9 o" |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& g, w" U8 }0 A4 [! k, J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ R+ z9 F3 ]( I" ^8 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 I) i' J7 H/ R; B$ i; c) gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ x$ t4 T5 ^4 W. P, aMCASP_RX_MODE_DMA);
+ N9 i j: B" P# P, E$ nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ x7 ^, T, e# u5 P4 ^5 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: h# t5 }3 \0 A8 [5 h' nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; r) L$ ~! U7 T( _2 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, B4 ]( H3 o. J! J m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 V1 S, F' _& g7 b6 ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 k1 y+ X6 u1 {# Z0 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; c4 w0 x+ m! @( `, x Z K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; ]2 P6 V( J5 E7 u. k3 a' TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: _5 A7 J7 w" K' l" z7 P
0x00, 0xFF); /* configure the clock for transmitter */
j9 e/ I3 Z. Q; E5 ?* m f* G5 q MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( }! P6 Y& k8 o# F4 g6 F `; f1 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # `4 x6 \" a7 J1 f% v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, P% o* l' W- U5 q Q1 p( Z2 U0x00, 0xFF);, M3 }: s7 l/ V J% V. K
7 {8 j5 G& l) B8 B0 P/* Enable synchronization of RX and TX sections */
" f G5 o% q9 J2 v% W6 B7 @9 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 ?! ]0 g" q+ ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 W% o- s8 I9 g. N1 F) Q' nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) R2 V* S$ q, w7 @5 o, Q' [, y
** Set the serializers, Currently only one serializer is set as8 q5 {. T" l# _7 `2 O9 k
** transmitter and one serializer as receiver.
: G ?* k2 K: y6 N, Z% v, P5 m. P*/( d% Q& G8 {% ]$ r" g% ~9 @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; E! a$ E+ v, y. ^- x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 }. P9 [ Z! ^! n. D* P7 y S** Configure the McASP pins 5 y& Z$ l# V$ V
** Input - Frame Sync, Clock and Serializer Rx
" U- j6 P5 ~" r2 l+ u U** Output - Serializer Tx is connected to the input of the codec ( C2 ^# O# b' E; D. O O
*/
; ?! ^( o) Y2 |9 l' M* b. vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- U' m7 S: i6 ]1 Y( LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 b+ V; g- O; l$ V! E* N3 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ I" S1 j# T; ?8 e9 { l
| MCASP_PIN_ACLKX7 y. ^2 [+ C$ I" ^7 e( {
| MCASP_PIN_AHCLKX
# Q% [- u$ M" o$ H- q% || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 J' }. n- x5 v/ x- N3 S- q- zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' S) D$ \$ x1 {' o( m- k
| MCASP_TX_CLKFAIL
0 K7 D2 u6 f- f8 C+ v4 s| MCASP_TX_SYNCERROR1 d' G8 D& g1 e% w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * E% j% T8 E, x- L* r6 ^
| MCASP_RX_CLKFAIL) ~5 g0 d1 e2 T
| MCASP_RX_SYNCERROR d3 e4 ~! V! A, }1 G2 D
| MCASP_RX_OVERRUN);
- ^. q& h2 B2 P$ u} static void I2SDataTxRxActivate(void)( y& m' y3 a1 Z; |5 n9 `
{
& q) c- D) Q+ A: p- z9 n8 @8 q- f/* Start the clocks */
1 `! [( ~- m3 }6 ?+ e' q" l& BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& ?7 R4 `% c& {. |) g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ ~% x% A( s- v) B/ ^+ f4 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 Y, j* o2 x9 z! A" N: |0 \EDMA3_TRIG_MODE_EVENT);7 E4 B1 I# x5 j: c1 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / g% T6 g! P: S9 a) y! S* a! a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 j( @+ U2 u4 `( e' g1 w6 x& A+ K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 m# `" o5 u6 E' N( H( f S, ]8 l3 uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 R% |2 {' E, r: M, M Z5 A/ L" b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. H0 g$ y# r* n0 N& p6 cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' E% s" w4 I# g# ~( \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! J2 b% N( N) Z+ J9 X& I9 x Y9 e J} . k$ T4 u8 p5 w) k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! r+ V7 _" j4 r$ ~8 F
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