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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' ?: K& S/ v7 t; o6 ^
input mcasp_ahclkx,( ?+ \, X$ N& e. x: {3 j. M' B
input mcasp_aclkx,
( @! ]. q1 K* K, S! d0 [; }input axr0,
4 ]$ F3 ^3 V5 }6 w4 a9 T; n5 t6 p+ Q. o+ n1 ~
output mcasp_afsr,
+ y' Q' a! Q+ R1 Routput mcasp_ahclkr,
* P$ a! m6 j8 ]- ?( w, Koutput mcasp_aclkr,
1 q! ~; Y; K: J# s: t' ^" Eoutput axr1,
- ~3 t( B* n9 R' L+ | assign mcasp_afsr = mcasp_afsx;. y- ?. q' y0 v3 E2 E% D1 x
assign mcasp_aclkr = mcasp_aclkx;
. |5 |! r3 Q) b0 [assign mcasp_ahclkr = mcasp_ahclkx;
% ^, E$ v# z: h* Fassign axr1 = axr0; 2 Q a" B% k1 |1 [9 A; T
# f5 E) K$ P, R; j& R. U) j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - A( ~5 f- G8 x9 Y, m3 U
static void McASPI2SConfigure(void)
4 C/ i) A, J* i! }) p{) o/ Q/ K" F$ y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" Z5 E0 I# B3 [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// O' U4 |2 O% u/ M/ l% F1 V# [: G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% Z+ t9 L+ w% x; r. g3 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 ~; W' K( [+ ]0 I4 L- g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, y0 T/ |7 J* V! p8 EMCASP_RX_MODE_DMA);) o- c. u" m: n) a5 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 D9 l* m# {- t) g8 eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: ]7 D% P8 R9 @+ x2 }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 B# R# l" }# N, E) j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- b* m3 z* U: f3 m# @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! ]6 O1 [+ y7 v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& b3 Q& a7 ]' V# K- S0 \+ p3 @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- S7 s4 f" z/ c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / I& p9 R. q+ p" S" g; r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 ~8 [) B4 O1 f, s: w/ m4 ?) Y
0x00, 0xFF); /* configure the clock for transmitter *// @. ^5 C2 p( G4 ^8 P0 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 \: v9 [; l6 f/ H6 g8 D hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 t( n; l; f" x0 nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" Z/ L# F5 V' H( v6 k0x00, 0xFF);
% ?6 A: f2 I# G& T( ^& e
! d6 Y. b+ O" @8 s! E8 x/* Enable synchronization of RX and TX sections */ % v1 V7 a+ y6 a4 T' P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& T% _% R2 d. M6 f" d$ g+ p3 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 D0 t& G5 Q% A1 }( A9 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 k9 f! V( ]: l: c4 m# B** Set the serializers, Currently only one serializer is set as
& O' h9 G5 @6 O: k** transmitter and one serializer as receiver.% }! U m9 @. @) a6 N3 C
*// i0 D( t6 ^: G9 E# Y' n \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 U; X& O+ v$ n6 `5 f6 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 p) t4 ?; e4 M- B! W+ {# G
** Configure the McASP pins ; j3 k2 Y; U& h I ^
** Input - Frame Sync, Clock and Serializer Rx
6 {3 p: N. \/ n** Output - Serializer Tx is connected to the input of the codec & Q6 n% {( p2 i3 V( }1 @! W) g9 r
*/
* ]: y0 Q: `' m Y7 x) E: AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' m; m% G. {( PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' i$ Z1 d, u% I2 T5 N, ^8 q# EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* b# g8 O: V. V: E* i| MCASP_PIN_ACLKX0 P) k: |1 w) {5 G: [9 `
| MCASP_PIN_AHCLKX
* l1 e* Z0 g+ T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( z' T- D" c6 C" E4 w$ ?& n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) Z+ {2 L; y7 ^5 S! ^| MCASP_TX_CLKFAIL % s8 y/ i: w- i6 s& ?% F# w
| MCASP_TX_SYNCERROR
. q. r5 G H1 X2 `5 v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 V) Z5 c: Q, ^| MCASP_RX_CLKFAIL6 I7 f: e# Y, f7 W# P
| MCASP_RX_SYNCERROR
$ R$ k- a5 S6 `- V1 G/ s- G| MCASP_RX_OVERRUN);
0 W8 H; r8 G& W$ A9 q} static void I2SDataTxRxActivate(void)
4 N+ z3 ]0 J: H# y{
, l5 Y9 z4 F6 w% C4 m/* Start the clocks */
/ F3 ^; h5 u: e" h0 N" PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! {4 I ?& Q* g# t. A. WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: C: d" b7 X5 v' _# ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, Q5 E4 s; o$ ? \" v" |
EDMA3_TRIG_MODE_EVENT);5 o0 X6 }" a$ V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' X$ m* N4 z1 h- g- F) AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 j3 @' [: k1 f6 v! R( I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# G, D/ W' i9 d) WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 U- D/ Y9 S3 R! g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ i+ S6 Q3 K( a; q; U8 OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 Z+ k+ c' {- rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) b1 O6 i4 w: R }+ h9 F} 4 D3 M' D, U8 t8 H1 ^2 _6 Z" F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; S+ k t- S# a4 |. \" f6 x% ~) \
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