|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 f0 ^* ] H0 N* ~4 N% Z0 oinput mcasp_ahclkx,
6 n; m8 r7 ?6 k$ Qinput mcasp_aclkx,4 W& d" [; F0 W0 [& q' Q) j# Y
input axr0,0 ] d. Z+ M8 |; a, e
! F: f) N0 z7 c) H& \/ soutput mcasp_afsr,
; _: F% Y; P& S* \) ^( uoutput mcasp_ahclkr,. p; Z0 ^- A& @
output mcasp_aclkr,0 I9 g% ?* A( ?
output axr1,
, I, ^6 D9 Z8 t B' y! o assign mcasp_afsr = mcasp_afsx;% i0 ? I1 r1 i- ~2 h1 o
assign mcasp_aclkr = mcasp_aclkx;- N8 T1 S- `7 J7 s0 L
assign mcasp_ahclkr = mcasp_ahclkx;
* t/ e4 A5 S0 A3 |assign axr1 = axr0;
; P7 I! a m: g3 e4 S2 g6 }3 _6 A* V' w( Z# T0 R% Y, _% O8 A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - }! j; l3 w2 N9 i8 P% H. F
static void McASPI2SConfigure(void)
; y$ ]& U. s# ]# A4 J4 Y" _. N% A; d! G{
2 A2 T5 h( Q; ^1 f6 ^. U6 EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) ^0 Q8 O$ k& x o" r1 ^" MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" c9 t1 Q3 T: H! p8 Z* _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& G8 a" N& G9 W7 AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- y' N; j2 p2 y4 L6 ]6 w5 y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 d# O8 ]7 K* g$ m3 nMCASP_RX_MODE_DMA);2 Z$ V ^ A( a; u0 T( D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% V; n& P2 x1 K0 P+ t bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 ^+ A& n! F: V- X. U; N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 q8 D3 l& I. {+ P6 J. _- ^: u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 {; [: d, j( p& ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; y, W- K4 z/ c4 U4 A$ z* HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 c& `: @0 j" D6 {( X3 ^ E, s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 m I9 A* n3 p: N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, d% l2 Y* F$ i; [. b8 YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# ?/ x; e |* U2 j% [# c0x00, 0xFF); /* configure the clock for transmitter */; C5 n1 u7 ^3 {4 e9 c# t; U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ G9 h4 Q* P4 }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ n4 ^2 {% F- h8 D! VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" c& f& z9 @& t0 n" b3 Y0x00, 0xFF);4 D2 X7 {0 c) s+ e
& s0 h) @0 [% a/ p3 m, K3 B" D
/* Enable synchronization of RX and TX sections */ 7 o) |) Q+ B4 x: |3 t( G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. t) ~( U9 v' ^0 Z; O* E+ \* y. GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- X& E4 p) `* f( m E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 u1 J9 H8 U2 K6 Z, w' X
** Set the serializers, Currently only one serializer is set as
/ D. a2 x3 v" |9 v) Y4 ]% a8 {** transmitter and one serializer as receiver. A- s3 ]4 \. z4 \1 s9 i) w
*/
! }" Z! K( Q9 k5 Z9 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% w7 |) ~7 W+ ^" K: o' c9 a4 O* Q/ FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. B/ Q; K5 Y/ `. J# W8 v** Configure the McASP pins 3 d2 z4 n: ]& w
** Input - Frame Sync, Clock and Serializer Rx5 O6 ?, D5 P' n
** Output - Serializer Tx is connected to the input of the codec
& z: V: o' H9 Y; n*/
0 E" }- I7 {7 _$ x" c+ x JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 i9 Y# @; i& c. I6 t( sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 ~" g" i' c* w$ S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* P0 m9 N' B/ H/ Z& U5 }$ `0 y
| MCASP_PIN_ACLKX
) D) x* [2 n2 @! J7 z| MCASP_PIN_AHCLKX
) d/ d& T9 l9 x3 ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( f4 ^5 I. t) e/ Q7 b+ RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 W6 ^- x. O/ M) b# K7 N
| MCASP_TX_CLKFAIL
( a: q8 S+ |# ^6 F/ |( i| MCASP_TX_SYNCERROR6 v0 `0 h; c6 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( @1 `- R+ P" i: K6 A9 V; ?; y| MCASP_RX_CLKFAIL8 y! F3 c) ?9 B% K/ a' X( `4 g! U
| MCASP_RX_SYNCERROR , |- ~7 K! R+ q# U* `& {; v
| MCASP_RX_OVERRUN);
. ~1 l- x$ D Y: t' ?. \+ j1 T} static void I2SDataTxRxActivate(void)
2 ]/ u- G' D3 z- L( r# `{4 p0 I6 w: N W6 R0 X
/* Start the clocks */! f* @9 I6 m {$ Q$ D6 B/ X) B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 A, S4 B# t/ N2 G/ f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ |! P- X7 ^" g# Q; E& WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% M# d. c% y3 S3 n, h. l" C
EDMA3_TRIG_MODE_EVENT);
3 X/ g$ ^5 F5 g4 k2 ?% _% W6 y. KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 \3 `3 ]8 \/ d1 O5 J8 ^3 e% u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ D; G2 ^* w, `& d: ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
M8 f% ~" I B0 y9 n* X* EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( E& U& M2 V$ v; n1 {1 z- K/ s' Z! v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: Y0 ^# U$ {% ?! }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 f( T3 f7 p1 A- @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( A9 q- g6 |6 C' K1 ?: F9 p" @} / B, d: [& L9 p5 k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! B- W( p' `" E f3 J |