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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( c! c1 J$ v6 S/ Ginput mcasp_ahclkx,
8 a+ c: g! q* o. p- v( o4 ginput mcasp_aclkx,
- p) S6 S, k9 M A( S4 _ pinput axr0,
- r- ^8 j, q6 r2 ?$ u* ^ C
* | q, H5 r4 voutput mcasp_afsr,
# l+ l3 x$ `% R/ p. ?8 u2 Routput mcasp_ahclkr,
5 z$ |6 n" L! B9 poutput mcasp_aclkr,
" J* S4 O) B" O% U# coutput axr1,( R) h9 J9 e. ?5 V5 d- C
assign mcasp_afsr = mcasp_afsx;
% K& J+ K. O2 J- Y: ^; tassign mcasp_aclkr = mcasp_aclkx; G# M# J h3 F' }: W& x/ H; J8 U2 X: z
assign mcasp_ahclkr = mcasp_ahclkx;( ]% `) q1 r5 e% B( n: _8 q
assign axr1 = axr0;
; A6 b! m, E9 h- l
]" s+ K8 L; H1 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( L+ |3 z1 J2 [5 }
static void McASPI2SConfigure(void) k* E8 O w/ G2 L7 g. _" d
{+ V2 S# Y% m( f) z3 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 Z: ~3 ?. B7 R$ m& J3 J/ F# g; O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 g9 r, D' w' c2 E4 F @- PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# b- ]# s$ p1 s# M+ o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; R, i- I- i6 \; u5 x) U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 ^' t& V$ S; R- P+ L( h
MCASP_RX_MODE_DMA);
$ {8 }- c3 c5 D* z I: ?" ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 }2 b1 k5 L u' u- G0 a3 RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( e2 t6 U, U& j- r* o6 {! V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 D/ I/ K! d. {# F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 r/ `8 ~4 X. i5 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 V6 A- r/ l6 r- b) k$ h3 t( [& NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! p/ V& Z- |7 p5 Z' m( P) u KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 `4 e! e4 `; L+ F S8 q0 G, jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 l8 I. c- I% S1 k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, R# M9 G7 ~+ s
0x00, 0xFF); /* configure the clock for transmitter */+ J: d* s. Z" s1 t) r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" [, s _4 V6 U! v+ m" `$ l) ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * B& Q3 Z6 L- V# \" R$ R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& A3 w( D3 Q. g& }0 {# G3 K0x00, 0xFF);4 w# o2 B3 m6 w. @& Y9 H! R
9 u# V3 m+ e9 \5 z
/* Enable synchronization of RX and TX sections */
8 u5 ]% F" a: X6 M* l5 l3 ?5 [, iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 ~! u" r) f3 r- z9 h2 R2 T( [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. X" A: Z& P6 T! m- e% E+ f' |# o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' c2 M' U1 L2 T! j- A0 H6 h** Set the serializers, Currently only one serializer is set as4 Q7 U$ J9 m; g; i7 Y2 Q3 Z* g
** transmitter and one serializer as receiver.
: [3 L" i, N) ?, A*/$ T+ x% }' U1 p! o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 w) O8 \+ x- A. \4 l+ ]0 D" N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# K& V; a+ c! Q+ x! _** Configure the McASP pins ' _0 s3 a/ K+ X# x, @3 w5 k2 ~- f: X5 A
** Input - Frame Sync, Clock and Serializer Rx, i3 _- _4 V! o- h: z# d: X! d7 W7 \
** Output - Serializer Tx is connected to the input of the codec
7 I+ K; H( V$ V3 x4 ]*/
) P+ d' N, e1 @2 k5 J" h( H& W2 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ a$ E1 ]" _# `2 k/ r0 J- ^& c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! Q, L0 C3 H6 x2 e2 _! b9 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
y, ` |, K+ i% W0 ]. J; D| MCASP_PIN_ACLKX
5 T3 `- r1 }. b' N| MCASP_PIN_AHCLKX
+ _3 `# Z# ], G0 p( c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ^* b. K7 S' hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ i# _$ ?0 H/ T: G) h7 h8 k
| MCASP_TX_CLKFAIL
8 \& o8 J& q6 n) W0 L| MCASP_TX_SYNCERROR; N/ n$ \4 f' u" G( S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( R+ F$ [, l. N9 S: N/ Q, X8 c0 O6 d" R
| MCASP_RX_CLKFAIL& C3 {+ d4 }4 u. n( v0 _6 v# x
| MCASP_RX_SYNCERROR
7 a6 K7 c- g) u# n0 x& `) U| MCASP_RX_OVERRUN);9 K, a/ s4 n# h- e- E4 b9 _7 K1 N
} static void I2SDataTxRxActivate(void)
3 H8 r5 F% h: V; O7 C" k{
# F: ?6 d ^- G# {) M- q/* Start the clocks */
; \" a' }, J" p( ~8 @/ ~& DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 w @, ]$ F+ |; BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, y+ V& O9 w: t7 ~) ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 d9 c5 ~, U5 EEDMA3_TRIG_MODE_EVENT);
4 N. F! E: M1 v+ _! p1 q5 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& y" v1 `8 i: H3 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* t# i* i1 o0 O* _' ]6 ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# \" r2 j# l6 Q% h& N/ i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 ~! [9 H" b& W: A4 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ G5 Q/ Q% A7 Y6 LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ S+ ^6 x, M$ _% H# Z2 H% vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 y7 Z; G7 d* S& k/ D6 n: ~5 Q
}
( |) @# N3 X x' B) I& ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( ~, G7 \! u& @# H# n8 p8 H R
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