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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& p, \. l0 ~* G" e0 R3 ^# E
input mcasp_ahclkx,
' {6 b& O2 h8 X9 G1 p' linput mcasp_aclkx,
' p* ?6 B# ~% Ninput axr0,
* I; u5 u& Q: ]% e; ?1 I, K5 o8 o1 U) S, @3 R: E
output mcasp_afsr,
+ e! b: y% U0 O& T# F* Youtput mcasp_ahclkr,
) _1 y0 r& u7 V4 C1 X8 goutput mcasp_aclkr,* q+ u7 T" a2 W, B7 V4 a! j* f: E; c
output axr1,+ J4 e0 `5 U* ?/ ^1 A: P; f
assign mcasp_afsr = mcasp_afsx;; Y% v' I2 P# V6 w% P6 V
assign mcasp_aclkr = mcasp_aclkx;" |4 \# q5 X2 e8 W1 Y5 a$ m
assign mcasp_ahclkr = mcasp_ahclkx;
8 a& P8 l, }3 Bassign axr1 = axr0; * H# W2 z* G5 M8 J
( z5 O. R: @) m) ]: O" f3 C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . H: e: f$ B z" e, O4 y7 s
static void McASPI2SConfigure(void)
: p. X t# J" J6 a% N4 w' b2 {+ |{
; A. P' F4 ~. A4 SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 ~ \' E: h# v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// d8 C; d9 A0 \4 W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 |/ `1 b! F; g. l! \0 h) a2 \6 yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' o+ ^6 n x: l iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 C( }' G# R$ ^5 \, Z& b
MCASP_RX_MODE_DMA);: N5 ^ C- P, _+ p9 L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, {0 d W$ n, S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 Q3 s- c& ] \: u9 S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. W- S# L L* h6 e( z5 fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ D+ m- f% z! UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! b$ K6 ^$ o z; e a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 {! V) `4 L8 v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' J* a4 W' i Z, A/ y& k/ {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) V6 X' }% G( D# C7 [& r# O3 N& o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& J9 X7 d2 x2 P1 i2 g* J0 S- [
0x00, 0xFF); /* configure the clock for transmitter */
& [7 _9 x# c* h% M) M GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: y. r0 C3 f7 v9 a+ E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 S. j2 l3 ?8 x8 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( h8 [8 y1 q9 R" V. t5 k/ I0x00, 0xFF);& d# c z( B- P' P+ d! h
6 M _% s& N3 o
/* Enable synchronization of RX and TX sections */
0 n8 Q8 D. j2 }9 \& a" tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: L( s3 o6 q z7 j' V$ gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 c6 } b! k! d/ aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! x" k1 O% G; L+ \8 }** Set the serializers, Currently only one serializer is set as
6 }8 [4 Y- x4 {, f** transmitter and one serializer as receiver.
5 X4 c& A T" R*/8 |( K" B: b/ H' ~8 |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, W! a, [) l2 o6 p6 [$ w6 U% d* _: DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) U0 z4 L6 K! i1 o
** Configure the McASP pins
' f; f# Q& v8 r4 j7 _' ~, \** Input - Frame Sync, Clock and Serializer Rx, J9 K* E3 b' e4 ?# D) t
** Output - Serializer Tx is connected to the input of the codec
0 e$ w- K' O8 y4 K) c*/! R- V8 m( {* m4 [$ u3 A, B9 h3 ?$ ~/ B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 |& g8 K, Y* Q5 T9 E' ]; nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 x3 i% d" H1 p8 ]: r' JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ v3 s8 _$ \5 m| MCASP_PIN_ACLKX4 A; I8 h0 L' g1 h& F" C+ r
| MCASP_PIN_AHCLKX# A1 G5 @& F3 c# T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ a; e8 s$ {. _. S9 O$ F! b! w. o jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: V; y* o5 v8 S| MCASP_TX_CLKFAIL % `" j# i6 k* S2 m) N
| MCASP_TX_SYNCERROR+ z' H" t" P$ d/ [- ?7 ^$ ~1 N0 p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: ~$ A. Y& q9 r% L) t# }1 |+ i# m| MCASP_RX_CLKFAIL
9 F; q& m% u; a A/ h4 D/ {| MCASP_RX_SYNCERROR " {4 l c( e( e% O0 N- Y* J
| MCASP_RX_OVERRUN);$ Y: `$ j2 O/ @/ M
} static void I2SDataTxRxActivate(void)" y- A: Y: q9 S- D; ]; f8 w' Q$ Q
{: r3 }4 t/ b+ w/ w0 C% t* L# n
/* Start the clocks */) Y8 o/ a1 q; n/ M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 B! {8 a ~( j: T; j" }; xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: ?' o$ l& {( s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 B& w' o+ R! x# H! { k( M, VEDMA3_TRIG_MODE_EVENT);
- H; D0 A! [# H7 P a- T! W. fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 }9 j2 {: _/ N4 e+ h b( G! _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 v, t+ M" V. s" F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 J: E4 N9 |7 U6 I( I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& B2 P @! ?- S; ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 J; j: X. n6 D0 m+ N/ ]% @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ i8 N* u) Y) S& I( \5 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 D; w4 P3 }* N+ X5 |1 J}
/ r: a3 n2 Y* d0 j& s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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