|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 o2 g/ u& G1 m) ?7 d
input mcasp_ahclkx,; | q! f; u2 P* i; G
input mcasp_aclkx,
) j v) G% b# B4 n2 }input axr0,
& }1 b( L' u4 W7 @& \6 g6 t% R; U3 |8 c
output mcasp_afsr,
& D# j l; u8 Y% K7 j7 zoutput mcasp_ahclkr,
, A$ N+ x3 |1 h6 b0 Zoutput mcasp_aclkr,
, O# i) I* Z r% d7 j+ B; x: Routput axr1,8 h9 A, Y! m9 I* t
assign mcasp_afsr = mcasp_afsx;
" ^" x6 P# j. [! n# i/ w* xassign mcasp_aclkr = mcasp_aclkx;
: h- ?8 j. X! Y5 Sassign mcasp_ahclkr = mcasp_ahclkx;
7 f, G A" h% f. X' W1 z# I" Lassign axr1 = axr0; 3 f4 s; Q4 [+ |& s5 R9 C! D
9 g2 ]' v; F! | S+ S! Q8 K& n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 X& E% R Z4 g9 y
static void McASPI2SConfigure(void)
( C2 j2 r1 C% [8 W5 E: R{ L, ]/ L, Z- ]" r7 Q8 Z! x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 a" v0 v: s' }5 w" w* A. xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 o4 N7 y' ^8 g; l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* M8 H+ V4 ~- |: |6 V2 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' Z# i1 O5 ~6 C4 ?5 e! B z" X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: @. z$ S# T, C7 I; n8 ^MCASP_RX_MODE_DMA);" ~8 q7 ~3 @! I$ P0 u5 r! C' o8 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' g; P/ R$ U) d$ N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 Z ?7 X$ z7 U9 P9 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , B# t$ ]1 r6 P3 m/ F0 R v8 o6 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 s0 [& ?( `# i; bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ H q; e. O U& G( g& P3 {% G" E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 P( e& ]' m3 _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 l$ e: O" O/ d7 Y" n( r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& I( i& E0 W0 D3 J0 C! RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 N2 {/ D% M* o: E
0x00, 0xFF); /* configure the clock for transmitter */
/ i# V, X3 Q( F& T ~1 zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 a$ l3 Y/ k7 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% W( V& f# w! H( \1 E* }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. ]& a5 \' L9 r# i
0x00, 0xFF);# P& |, f# ?% m. L
. E$ |: d ], ~/ e/* Enable synchronization of RX and TX sections */ ) e+ w! J, X: Z% M, d( z5 `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! f0 B( Y0 ^" F* HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- z/ z* N* ]1 `2 A/ O. UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 K+ k6 C0 W) `0 e/ o** Set the serializers, Currently only one serializer is set as6 h F2 A1 A+ G$ `. I
** transmitter and one serializer as receiver.1 O* Z( c4 Q) @0 ^
*/. a$ x. M1 K) Y/ G1 h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 K. {0 e3 ?. i' ~- n( m QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% ~1 _2 a1 y$ s) N. A; @
** Configure the McASP pins ' Z7 s& I% M. G
** Input - Frame Sync, Clock and Serializer Rx, a3 C; D* ~3 \- Q. w: c' l8 F6 p
** Output - Serializer Tx is connected to the input of the codec
6 B& Q- h0 }* G& y# J- V*/
* l7 a0 D$ F4 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 h$ A! e Y% @& ^8 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 B+ O! ~+ X: e M* j7 v! bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ U: ?7 u! G1 E+ e3 b6 G9 m
| MCASP_PIN_ACLKX
0 a$ A, z; d& o, t$ D( I| MCASP_PIN_AHCLKX) [7 }* A5 p( h$ l, p. @- A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 {% X2 z# S1 m% O5 N7 \- c/ vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) }+ x+ b! i$ K. X! Q5 U' `
| MCASP_TX_CLKFAIL . `1 | [7 Z& U; _* V
| MCASP_TX_SYNCERROR/ F F8 y; x2 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# N [ p& f: h! P1 B2 }| MCASP_RX_CLKFAIL
4 D" ]7 F& o8 H' o( [. z( r) X| MCASP_RX_SYNCERROR
" r0 L2 N1 H6 ?: t; V- J, D| MCASP_RX_OVERRUN);) E0 Q+ H Y' c7 B2 n" d
} static void I2SDataTxRxActivate(void): A: J! H" ]% V4 {/ n, m
{
* Q; \! W% O& R$ Z w0 u/* Start the clocks */
3 S2 L/ B* w; e* N0 l/ u' _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: a* U5 ^# y& _# c! D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 [3 ^. x4 g! Y. z5 S6 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 j0 Y) M1 K5 T) G6 ^
EDMA3_TRIG_MODE_EVENT);
& [6 @/ \! a1 I& g: p& eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( M0 Z T) C" iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' z d+ @& g/ i' s4 fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 n/ J. b" L0 ~0 P1 F8 j/ c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% U" [5 N4 t1 V/ D- fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 F" i9 U; M& N8 x+ eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 @1 D" ^8 ^" X. Z' N4 x2 @6 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 N+ S. u" Z3 k! I2 ^) i/ o2 y
} 8 n4 |. [% e- u+ K" ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + e- y5 y) Q9 ~, u/ o
|