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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 o2 Q! r% R" I% H( x8 i/ \input mcasp_ahclkx,- |) Q% q4 {: @8 `) o
input mcasp_aclkx,! m# ]3 S$ q( `" m9 M
input axr0,
0 ^% ?' V+ H- p X4 m s
$ _% h5 g! ^( C% p6 ]% `output mcasp_afsr,
4 A! B" K5 {; p- H% Ioutput mcasp_ahclkr,
2 Y2 ], E7 S4 Boutput mcasp_aclkr,6 |! J0 L6 b1 S8 R$ e
output axr1,
+ G. P, W( |1 n assign mcasp_afsr = mcasp_afsx;; ]8 j" ]' B& X4 A0 |; D5 J& U+ s' k7 F
assign mcasp_aclkr = mcasp_aclkx;
/ q- k$ e- d: y+ ]) Z! e. gassign mcasp_ahclkr = mcasp_ahclkx;
0 c$ n8 o" ^+ Eassign axr1 = axr0;
! `7 L% P5 X. P4 M5 H. r/ k5 Q, a1 ?6 I, y
! ^8 k. }% K, q' I8 t% O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 c* c# O/ O8 p) y
static void McASPI2SConfigure(void)! a* @$ r c/ {" B. k
{
7 _1 }) r) f+ {' e0 Y% E' s- [9 ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);) A! i$ R; r9 Z/ L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) I* f) e5 x M, m& {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" l$ W K; q3 R. n) Z3 @( C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 _* z1 H5 Q' J& z: {5 m. n* A7 w; S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 t! T# |! L# Q
MCASP_RX_MODE_DMA);$ @# e9 V* [6 y- y0 Q0 q! ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 I6 n$ T4 `/ J6 d H# JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 r% s9 \. ]: }) N! [/ ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ O! T+ s4 u' `9 }/ p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 Q0 E4 H; j2 B; B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ _1 f, q7 |6 c6 r% C8 j$ a& Y5 x: s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- R9 }' }* _% ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 Q5 [0 q- f( Q/ a+ ]! C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); j, n- `- E. H% G, v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; j- H7 M# ^! j: w/ Q- ^0x00, 0xFF); /* configure the clock for transmitter */
2 u5 u: }0 _* W$ Y% gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ K* T8 W! Z% u2 }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 J8 ~* K* _4 v9 `/ h; E: l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 @9 U7 p* a* ]0 r: T E
0x00, 0xFF);: ?2 p6 }0 D2 E
7 o i/ r; U, {3 C/* Enable synchronization of RX and TX sections */
) t" Z/ K0 O; g3 `2 DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 d2 E% H- g4 }1 q2 C4 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& F- K4 `+ l; L( }, IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( v$ W9 g/ H; h- [! F- z( k
** Set the serializers, Currently only one serializer is set as7 B" _2 N4 b( ^+ @7 X4 W4 H
** transmitter and one serializer as receiver.
8 W5 T7 k$ |9 g' D2 Q; w' i% b$ i*/' k7 {+ b# P8 G7 P# I8 P$ j: h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 e) y& y7 x1 Z" P7 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 o; z$ K; o/ ^* P% k** Configure the McASP pins
8 e0 b) o3 r* _- E** Input - Frame Sync, Clock and Serializer Rx( w, K- [% |' |% u% n4 P9 ~
** Output - Serializer Tx is connected to the input of the codec
+ \, u" U. }/ a( [* C*/" c3 t1 H6 v# ^ i2 y) c$ g, @- E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' b. G; u$ C! k4 O9 z2 z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" |7 q1 f8 N( b( E5 g. @! kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, Q0 V$ i, U: w1 P, D s
| MCASP_PIN_ACLKX8 q o2 o8 T4 |3 T: {) j/ V: Z! S
| MCASP_PIN_AHCLKX
0 F: R5 q" w2 r4 @7 f: k. t i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, \" Z' _$ L; Q- n4 S5 a& L+ fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 K" }2 v$ D k+ K8 f, W| MCASP_TX_CLKFAIL
3 K% Y9 V8 a+ E, T| MCASP_TX_SYNCERROR) q- X: p+ u0 O* }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% y* H( r1 r9 K& z5 ^" ?| MCASP_RX_CLKFAIL
* Y$ ?- P" t4 _) i| MCASP_RX_SYNCERROR 8 R/ q# a3 `8 \- h {9 u5 f W
| MCASP_RX_OVERRUN);4 w, h3 u; S" o# |2 U) y
} static void I2SDataTxRxActivate(void)
' V4 J+ q8 |: O! m{
! Q& a. s0 ?9 b) u$ W6 F. Y$ [* b/ z/* Start the clocks */
4 W2 i: W2 [0 c( Y+ i1 K- uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 X* O+ Z/ @ U$ ]/ b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' f a2 L& r' {' ]. ]6 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) Z) X/ e# Z9 z* U9 o+ U2 Z# k7 TEDMA3_TRIG_MODE_EVENT);
" A) C) Q+ |, j" ~) L9 m; Y% SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- ~0 s0 K7 j6 @9 k) h( x4 H1 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 ?2 H) h& Y+ l& JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, \' l5 C3 W2 j' c, ~, I) D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& |2 j6 t2 V& z1 ]3 dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) z& ]- t( G$ h# GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 `5 R2 L: n5 l* T5 s' w/ wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 I1 j+ J; a5 @7 C% A& {} ; d: E4 k0 A$ u8 b/ A( o5 N: z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 u9 k9 R4 f, V
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