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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," |; r3 e v M1 V
input mcasp_ahclkx," V; c4 V8 w9 W3 `8 G( A0 O
input mcasp_aclkx,/ D& M7 R( ?, k6 T. d% v( A9 ~. L
input axr0,. V, a; e; t( A3 E7 A( T+ Q
6 N' B( t R7 q
output mcasp_afsr,
6 P/ F& ~+ w2 B$ v/ L# Woutput mcasp_ahclkr,
- X) Q5 [: v) x$ ` p/ F5 p5 B0 Y8 Uoutput mcasp_aclkr,
- G& ~: v* I/ _8 r, U* goutput axr1,
6 q) s' o& p+ `1 v6 t# O+ a+ j' U assign mcasp_afsr = mcasp_afsx; l9 \# A) [( A( H
assign mcasp_aclkr = mcasp_aclkx;/ H: F' I3 s) W5 n
assign mcasp_ahclkr = mcasp_ahclkx;" V; ? U) T0 A4 k( v& }. o
assign axr1 = axr0; + l% s' F- F8 ^
. G! V4 n; K7 K+ W1 B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 a0 [' d7 C/ G$ H5 ` G, h
static void McASPI2SConfigure(void)
& d/ `! J* F" Q- ~* y; V4 p6 B{- a0 ~, |3 j/ I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ | c3 Y3 ]8 O/ l" `4 y( ~, MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; @ H. D) U S9 |9 I0 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 z0 r5 n {# |, Q' z& Z3 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 n) d2 T1 _# i/ n LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, k9 k7 ^2 {4 _ U. F: l8 o. aMCASP_RX_MODE_DMA);2 X/ f" i# f8 X% `% [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ q( u4 ^; F- M, _3 _9 X' ~! fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! D0 f) `/ Y( Z' U: C1 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; @% R- K) [/ [: i* t5 I" T1 H8 S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 `( v u+ J. E, h. ?- _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! O5 z! ^2 _. K2 d0 l8 \: b% ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( e- H, q) q3 u4 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 s. e; j: m H% O/ n; ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- w; V2 ~. ~: \" u- t+ ~9 z+ XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* N7 Z+ h% [8 N- S4 Q, `7 O- h0x00, 0xFF); /* configure the clock for transmitter */- q) d$ e" D& a+ l( ~; E) w# o4 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% \6 k e, w+ L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. k. m2 k; S$ s3 k' z+ Q* C. Y1 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* Y1 L! S! d1 O4 _' f0 T% [
0x00, 0xFF);
5 r% G% g9 I) g% R) r ?0 ~. U+ @
1 b6 u- N8 c9 n* Q9 Y" M# F% i/* Enable synchronization of RX and TX sections */ 0 r5 D4 w3 E/ V5 [+ Y! d' w* [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// e' b7 s% E* U4 h2 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( N& i7 B4 N' n- [- ~8 d: l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: \7 \2 ^) e- D/ X" B2 N) i) ]* Z** Set the serializers, Currently only one serializer is set as/ [5 k; V3 i4 J! j3 ?: p
** transmitter and one serializer as receiver.
% S: N; H5 R5 R: M*/
; ]( M& K+ o* qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. @- b7 U, X- w. j8 H6 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; L4 n8 b# w8 q0 k6 H& Q9 x** Configure the McASP pins
7 b/ u" D% S2 V; Y% E$ I9 w6 m** Input - Frame Sync, Clock and Serializer Rx2 R* _+ I! ]) {" p A
** Output - Serializer Tx is connected to the input of the codec
- ?# W9 @* n5 r; y/ ^' q*/1 |* G) o; k3 p# n; |% ` C# }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ e6 S( i( p6 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% _ s { g6 f% g9 l% }, bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 B5 {2 C# v3 x| MCASP_PIN_ACLKX
4 y2 j# [- G8 g: ]| MCASP_PIN_AHCLKX& f3 q/ A& V" a. ]' _5 L; w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 p$ ^) B, ]+ d% F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 A) r8 F, j0 l
| MCASP_TX_CLKFAIL ) ]3 G$ _$ \1 Z" M( N0 L0 T
| MCASP_TX_SYNCERROR
' W0 g+ J) ?, j- H8 _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; ]) F3 \) x* f# p" @4 `| MCASP_RX_CLKFAIL
9 W4 ?# s5 w+ O2 Z7 U| MCASP_RX_SYNCERROR
5 R. i9 t, ]3 `" ]( c; e# y/ T| MCASP_RX_OVERRUN);/ c; ?1 J4 j* R0 B/ r3 H, c
} static void I2SDataTxRxActivate(void)
7 ?1 _+ e% d2 C Q4 `{
& H) C# ~' z% C0 ^ w1 ?% y/* Start the clocks */
0 `8 V3 {8 @* t9 ~2 t; l' w* w: KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# U/ A& I" s7 B$ ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 ]" A3 @5 [; n0 R2 e/ d/ ]. D2 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* ]; `0 ^9 ~: P) N6 c# z% a; mEDMA3_TRIG_MODE_EVENT);: I# Q* j5 N. B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 o' }& e. F* g S) I* q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 b4 w# W+ i. e" H* L/ f, f& t" y: vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 d& c" J6 U4 v5 ~$ k( A# BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. v) [3 W& y- `- S( t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. {. Q. B( J. {) b- B) k& hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ B* n% L/ K, O7 P& KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 _: F- W' R1 w+ d
}
" t2 p. h# R" L+ w8 F! u: q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ N8 k* s+ d" {* K) O
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