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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ H* B* @2 |% ^/ d* X9 P! xinput mcasp_ahclkx,) N" o+ F/ Z4 A0 s# A* Q& X2 Q
input mcasp_aclkx,
1 ]* y* f5 w c, yinput axr0,
7 M m' o3 u' \# f; U) X9 x1 P8 \5 l8 N; O/ U
output mcasp_afsr,( l9 b# S$ T. O- u' @4 O2 G" h& E; g4 g
output mcasp_ahclkr,
1 w8 Q5 M6 W+ T- c: A- o# Ioutput mcasp_aclkr,
* C; R, T: O: c: J( ]5 noutput axr1,. f) y: Z4 T( r2 @; v
assign mcasp_afsr = mcasp_afsx;
1 r2 r4 y9 P% p% A2 Nassign mcasp_aclkr = mcasp_aclkx;3 h8 p7 t7 H+ W" e: v" t3 m- V
assign mcasp_ahclkr = mcasp_ahclkx;
* ?8 _( T* O8 ~3 _" kassign axr1 = axr0; % k/ w$ `. c; F& T! U: ^
9 ^5 g& I$ o8 k3 Z0 j! G W5 @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! `- ], R% ]' y3 e ?
static void McASPI2SConfigure(void)
3 u8 ?1 @2 ]1 @{% }% U( E6 x- q0 j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 v: a3 D7 ^8 M9 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# Q) v; l6 E' J& O/ ~$ zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# r4 e: e6 i/ F3 @6 x- EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 N+ T- T O+ E- gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' r$ X$ s6 g3 k6 w8 F9 g2 J! aMCASP_RX_MODE_DMA);$ U$ m1 r3 J+ v" s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 M' Q0 ~2 x- VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, A9 ^5 s+ T; c. k5 ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 M5 {$ {$ T6 i& k Z* X- ?9 L' ]8 ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 S6 l3 I8 {0 M2 }1 \) [, |' X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 W( D, ]1 _: A4 `4 K \% I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' C: e8 s1 t7 p9 g! d5 @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% B+ s9 R1 H+ W8 k% A# C( D1 r0 \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); T* E7 s/ \$ X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* o$ J# F# P: Q) f5 a' h# x: g, N$ x/ y4 ^
0x00, 0xFF); /* configure the clock for transmitter */' L1 V2 E2 e) I1 G0 V- w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' Z4 B: a- E8 B( y6 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 o4 G/ Y5 K i6 {9 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 ?+ J) O4 J$ c& F6 B8 }0 }0x00, 0xFF);& x- r6 M; [( E/ m* K
/ ~2 a9 U0 x$ a
/* Enable synchronization of RX and TX sections */
: M+ E! y- p, V% i! W4 F5 Z5 OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( u, z0 ? m/ y: o4 j3 XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 S1 F6 L2 Z$ V( ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 \5 ]; [3 H0 b9 }/ u7 V: ?** Set the serializers, Currently only one serializer is set as
$ n$ o- {1 y! I8 w* j2 w' C5 D) Q** transmitter and one serializer as receiver." R4 C. ~4 \, m# k
*/% X& `+ A1 C9 }% Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 D5 M* Y9 ]. ]- m/ f: L; a0 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" }( p/ L- I& L/ {" B. h6 T** Configure the McASP pins 9 L' `) ~* p% ^( [0 P$ q; h
** Input - Frame Sync, Clock and Serializer Rx( n) a, O8 s& U6 f
** Output - Serializer Tx is connected to the input of the codec
$ _" m3 L7 {+ K4 E7 k2 I*/, `/ J: o! w8 O% h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ Y" k" f3 m9 O# n1 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. E R3 a7 o( a* ]) T) A) |6 N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* M2 H5 W( i5 K% [. N| MCASP_PIN_ACLKX4 w) l; b, S7 [7 m: Y5 D/ {
| MCASP_PIN_AHCLKX8 |$ I$ @1 q5 ]" a4 _7 F- ~% T" Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% ]4 l/ G' P0 g2 [; x- jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' T- c, i1 o; u4 B% N
| MCASP_TX_CLKFAIL
! J% c" n; ?' }5 G( A) R, d| MCASP_TX_SYNCERROR
( Y4 l2 o, i7 s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 j1 d5 o( i/ \! T" u| MCASP_RX_CLKFAIL
$ W% ?- O) Y: S# O( k| MCASP_RX_SYNCERROR
* e% ^0 O! e0 s8 Z* d4 ^| MCASP_RX_OVERRUN);
- F# o. Q% a9 P, B} static void I2SDataTxRxActivate(void)
3 A' P( g/ c7 j; l+ z+ w; b5 n{
2 n( _9 X' ]2 v w) I0 T/* Start the clocks */- o# [' Y# ]: U3 l+ u0 e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 A% Q( I; d9 BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! N l% A1 ~6 |$ R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' \6 X ]8 }% Z* }2 U ^6 k4 j. vEDMA3_TRIG_MODE_EVENT);3 @) c6 P& Y7 J+ n$ M! g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 m1 ?- G) m6 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 Y y- b4 `; t+ }: W+ g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- Q* H) ^ R- rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ U" X6 C& x$ \, N4 w! `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 d0 N# E! q* h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' E4 n& Z1 ~% B- {* j& t) P( X2 d) EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' R9 ^2 Q, D% Y- N+ [
} 4 K% I. ?# N( o/ Z1 v; `% b: J$ o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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