|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ _4 h+ ^% g E% u" j/ ?# c( e# P
input mcasp_ahclkx,# |* T4 e8 D9 `0 y) F
input mcasp_aclkx,
5 B) G% ]: _" C) I# oinput axr0,
" z/ i: R/ B5 F
* l# U" T( A, D) ^9 P8 [output mcasp_afsr,
) J8 I6 q6 N! [; aoutput mcasp_ahclkr,
+ Q+ ?5 V; |: n- j( Voutput mcasp_aclkr,
# P3 h$ _+ b6 Q1 ?" K y& x; moutput axr1,$ a$ j" q* c8 C" Y3 f; u! b% C
assign mcasp_afsr = mcasp_afsx;$ m/ s* A0 B" H
assign mcasp_aclkr = mcasp_aclkx;
9 L; |7 M6 |& R0 y0 Dassign mcasp_ahclkr = mcasp_ahclkx;
9 y8 T7 [* u- V7 b! H5 S; v; i" `assign axr1 = axr0; 9 E1 Y% I1 ]6 M& S& V, d; H
3 y/ @2 A% H/ S) L& t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ K. U I& r. Qstatic void McASPI2SConfigure(void)
3 G& s6 E7 v: P- Z) u+ S C{
& o% ~5 f7 Y3 O+ ^$ P; ]2 ~( LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& q: R) d* n3 X: ~: M3 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 r* R' R( v1 j2 ^. f) u ]2 j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% n! J9 k8 h6 T7 w; _5 s9 @5 Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 A* Z0 A0 h- z2 d- N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% V- `) t+ d% ^" R9 U2 W, N3 `MCASP_RX_MODE_DMA);0 r* \. {) c) T' f3 x# T! n$ C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 c# o' }. x9 F- [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. V O# b& p- Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 \( Q3 k& `$ r( y8 ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% v4 h3 {/ X: U2 S9 j. s I6 W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 p0 s# m+ }) E5 E8 ^. K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" l! C! g! N0 e# ]& yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 v1 N5 o- x6 T( I+ V7 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 Q& J+ g3 U2 | ?' y/ Q+ sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ N4 ]* ?6 L9 x% W
0x00, 0xFF); /* configure the clock for transmitter */
6 E8 _$ Q. d' Y! W$ Y' sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- ^7 l }: ]) ]4 z- l9 ?, `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & ^4 T' d7 o O0 \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) P. w& K3 w& A* v9 m
0x00, 0xFF);; f' i$ t, A2 c! n$ @* P+ |, L
1 M1 A- c% Q! A" o
/* Enable synchronization of RX and TX sections */ " y) m) { E: n$ e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" S7 e: o: z; {' [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# R$ W9 U: r$ U9 v' q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: l; h# w. U" L9 g( A** Set the serializers, Currently only one serializer is set as! A" X- o6 p2 L; Y
** transmitter and one serializer as receiver.
! ]8 J4 |3 N! b* v9 ]*/
- o9 P9 }6 H( ] _1 \, A4 LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 N0 m( F8 [1 z7 v% l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** B1 p+ _ f! I: z S
** Configure the McASP pins
& q+ Z% c& r) j% c1 |** Input - Frame Sync, Clock and Serializer Rx
$ W+ c+ R7 ]+ H$ e** Output - Serializer Tx is connected to the input of the codec ! i5 D+ G& V. I
*/
3 U, W: }3 e$ B- D) s, o kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 ]" S2 l$ _! v" a2 o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* V: `( ~8 |' ]' E* ]: j, {$ x+ DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, M4 O1 U* k% f1 X# Y3 a| MCASP_PIN_ACLKX
: |, |; w! C+ P8 I- m; ?7 |# [; c| MCASP_PIN_AHCLKX2 Q& ~/ M3 G$ K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- s% T+ J. \3 {7 J9 [$ J& K+ ]- Q. PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . G4 m( X8 I8 @! a$ l
| MCASP_TX_CLKFAIL
6 \3 u7 F% p7 p+ h| MCASP_TX_SYNCERROR
7 b, h% ]# b( V( W( @' t: a' [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 t C) b. n1 T
| MCASP_RX_CLKFAIL
2 u! W2 R4 G8 }+ g' f* |; a| MCASP_RX_SYNCERROR
K/ N2 }7 Y6 }1 J$ D3 _, X3 h| MCASP_RX_OVERRUN);
# {7 r N) M! z) ?; t} static void I2SDataTxRxActivate(void)
1 J% g+ e; ^, o# o3 r{. y6 V, a: x) k- {/ h% R
/* Start the clocks */% r; o+ r5 D( t6 C% L# [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) T7 m8 v. P1 Q# P8 R* r; VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" R, \. N) Q* |3 _& b4 j$ OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- S9 I. m3 p4 c
EDMA3_TRIG_MODE_EVENT);
* c# ]1 h( n% J* A3 P/ q; @# K8 N) iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 L- q N+ E' f- H0 s6 }4 h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 {5 e8 ?/ N; _" ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- }/ [2 Z; y |7 U7 _% G1 ]/ D+ lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ ?: B5 Z9 u" u: P2 e* ?1 @# h/ |3 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ z% j# F m! D( v( Z6 B, H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: ?+ m6 K2 Z6 X5 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# x1 v0 u# `' e- b3 s. l5 g} $ S# g. Z0 P+ s) @0 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / A4 u% Y) |, f( A: ~ e- A7 i! G% n
|