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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 o: L, N) x+ B! ^. _ ~, R" K2 ainput mcasp_ahclkx,
# F. Y$ A# b4 Hinput mcasp_aclkx,, { o0 k( i P! k2 V& R4 V- l
input axr0,8 }8 T0 }5 t5 Q5 R) n0 q
2 K/ [5 c# F6 Y2 h* J. zoutput mcasp_afsr,' \, b1 s! _0 Z# u) j0 g. J0 T
output mcasp_ahclkr,
7 Q/ t( K: @! \& soutput mcasp_aclkr,
# r4 _- c8 m1 B# _output axr1,# u1 O3 [; s' y" ~2 s
assign mcasp_afsr = mcasp_afsx;
" I/ P& c, `- o) Wassign mcasp_aclkr = mcasp_aclkx;
- F! U4 f0 V% a' w2 _& v! uassign mcasp_ahclkr = mcasp_ahclkx;9 T$ \* x) U7 E1 ]. e
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % Z+ ~* L d! i7 U
static void McASPI2SConfigure(void)4 u/ s9 W. e B, ~. B% v/ n% t
{
' a1 H# u$ E% M A1 p$ h: a2 A% vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: v0 B$ l0 j Z! d0 F' M, nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- W! T" c# W z0 s, e& P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 ]0 W" t" e; ~9 M8 TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 m) C* _ j% c* ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, {7 }% k( I2 ~9 i' |
MCASP_RX_MODE_DMA);
& Q4 B+ G& p' VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* t7 Y& T" o' Z, MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% G9 Y7 b, ]0 Q& J& n1 _, }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 R) y u# g5 Y. P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- c0 o T. Q' {( @0 p& U! G# kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 R" [' n) z0 s# V3 z+ aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 ^: X% \ `! ^/ X% s: T3 i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. E3 j6 f. R6 T1 U* C, H. X P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 g1 i1 w: A) \6 u' ~" cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ e' Q0 V' _2 P" Z, ^: L0x00, 0xFF); /* configure the clock for transmitter */
' z5 j1 F: l) X& AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 u2 F9 g/ [ J% D# X: {: wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : t3 Y% A6 t/ v) b% a y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 ]: U$ h: v2 g. N6 i
0x00, 0xFF);' V' y% L I: [4 F
5 \7 f# t! Z. z' S; ^% _; I. M
/* Enable synchronization of RX and TX sections */
8 l; w' V( G- b6 F( N+ z( HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 k4 f; g4 d& a1 BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ X2 m, i; F3 Q$ t4 p$ Y9 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ X" S- \* D) O2 u6 e3 K
** Set the serializers, Currently only one serializer is set as
8 G. g8 c* z3 t9 V** transmitter and one serializer as receiver.. P: l. Q+ R3 a% l! H
*/# p, }6 Z# I- M1 K) [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 ~) _2 D( J- v7 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! `* K0 s7 a3 o4 W/ |* d
** Configure the McASP pins
# h' ?: `' R" i( ^4 k** Input - Frame Sync, Clock and Serializer Rx; |9 B; O( ?8 v; X# C
** Output - Serializer Tx is connected to the input of the codec # y7 y1 G6 }: _3 q
*// a X3 H1 w/ w2 `: i7 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' A6 _7 `5 B, D4 x. I' F6 G$ Q e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 l$ D! f; \/ y' D0 [8 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; X5 C: k) l# v; N1 h7 u| MCASP_PIN_ACLKX8 O, f, v9 ^( D- n. Q
| MCASP_PIN_AHCLKX+ o5 m0 j% K0 I9 w' w m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 |/ E/ l; x7 d, H3 AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) m& X; {1 ]4 M4 f, L
| MCASP_TX_CLKFAIL
* `( t. T9 }& v9 b| MCASP_TX_SYNCERROR5 a7 Q. t9 P- C ]$ H3 q8 M# r5 v& O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " ?$ w5 o% H2 _0 r J" S% s
| MCASP_RX_CLKFAIL
+ R4 x6 u% |/ L| MCASP_RX_SYNCERROR
8 U& k1 W8 }( k6 q| MCASP_RX_OVERRUN);
) A' _. V8 j% M0 ]3 W* i, y( s} static void I2SDataTxRxActivate(void)- v+ C, ?* y( F8 b0 h& M' T
{
8 E) t1 O, }8 [$ E3 _+ ~5 j. x0 c5 x/* Start the clocks */' N- E' x3 i& k) ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! a0 n. T9 y4 W$ c8 e* z6 aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% `( f2 l, p1 C* l# B- i, ?% n" SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, r7 c: \( D8 `9 h$ T
EDMA3_TRIG_MODE_EVENT);
% j/ a+ `0 ^/ P, N4 r l5 l VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ `/ J V2 v8 Z c* qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. g& s9 ?( B0 C: v: B( \* E7 O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 s. X, h( A7 s% B8 X" p5 q* LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 m2 M5 o2 i, x$ x' g$ q$ T( K) N& M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 h3 M6 } \: u) r( _+ Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 T) V$ y% U# m" n- BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" z8 T, F. c" {/ q0 z
}
# c" P0 f: I3 t3 G* B, ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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