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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 B |+ r. d7 |6 T$ pinput mcasp_ahclkx,) m# E% z* T3 T' L; J
input mcasp_aclkx,
: X% _& a& w9 E cinput axr0,
8 M: [# X& g9 V1 L' z$ S& B) g; y0 x7 s! X) v% y0 C
output mcasp_afsr,* \1 k* s8 f) f0 V0 q
output mcasp_ahclkr," L. @) z' [7 Q7 L' m
output mcasp_aclkr,
A0 W) \+ N# Koutput axr1,0 g% l6 e0 d- C
assign mcasp_afsr = mcasp_afsx;
, ?6 \( E! }& @5 m6 xassign mcasp_aclkr = mcasp_aclkx;' x4 R @3 D0 W6 ]% q* O$ [
assign mcasp_ahclkr = mcasp_ahclkx;
- r" Y+ d B! j5 F; B. X1 }assign axr1 = axr0;
: Q9 R5 ?/ A( Y/ _. L4 W
7 N3 j2 t/ q3 s1 E# d9 J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 B2 D- G. E% w! Qstatic void McASPI2SConfigure(void)
/ a0 K* G% }- w! N* R0 [2 v{$ \) D& _% [6 l2 S ~+ \. o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ T" u8 n$ |5 E1 XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: @* P; d# ^# ]( k/ V. N6 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 t. l( k9 b; k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 a. r( Z; f" c v+ j" w7 O! A6 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 G8 [+ S: ^7 j' y# M: aMCASP_RX_MODE_DMA);
8 E, u4 c) R+ E0 x% `, b4 L2 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 X% z, @3 D) F' J8 C) Y& \* I! }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 k3 w! {6 ^9 N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, t% Z; ^6 r8 p) D5 _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% r- B% w* K) R$ n) ?6 p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 T+ Z1 c" w% q6 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ ?1 c$ A0 l1 S- X) E* s9 ^; S& HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 B. E$ O4 l( W- [6 n/ m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . r% a9 y4 `- k. f5 r1 R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 y# K' I( ~3 ^0x00, 0xFF); /* configure the clock for transmitter */
( F( @* L( _4 ?( |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); g; `! @ w! ~# Q5 l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & C5 M9 A1 f# s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 Y3 X' Z' j& D8 A5 R0x00, 0xFF);; Q% L1 `7 N+ i5 D2 q& w: b
5 a" `& p/ Q# [7 X! m& v" F
/* Enable synchronization of RX and TX sections */ ! x/ k8 q, `6 L7 ?) {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
J5 k5 [5 I# i3 n; KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 i; W2 K5 m' [- K5 z0 f( W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 P \! C+ Y, X9 H. [- A6 k
** Set the serializers, Currently only one serializer is set as7 c# M) \' ?4 A: m( s' _, w
** transmitter and one serializer as receiver.) f* ^4 _/ e/ I, ^2 A
*/
& z8 [- { Y' M* iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 V# J- N% {' J9 F- o% x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ w/ Z' k+ _7 j0 _9 _
** Configure the McASP pins 8 b$ c! M7 K1 ^3 _' k: Z- K; _
** Input - Frame Sync, Clock and Serializer Rx
8 C( M4 i \! C7 K3 U7 V** Output - Serializer Tx is connected to the input of the codec ( f4 r4 ?- r- K" q
*/6 L2 V7 a0 [+ M5 A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, t% B- R o* J! pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 |2 [( ^' N/ n ?. ~) KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) I5 v9 i5 s1 g$ \) ?% `8 I# Z8 ?
| MCASP_PIN_ACLKX4 @ @/ L4 n; Q! J' U% @. `
| MCASP_PIN_AHCLKX
; d4 u5 Y0 R4 _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 [0 p8 @$ [$ h/ \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 Q' l1 _( c5 R7 \| MCASP_TX_CLKFAIL & F# ^& i' }! }9 G
| MCASP_TX_SYNCERROR
. b; l8 Y2 i/ R% m. t( ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: V* J! }) k% q| MCASP_RX_CLKFAIL3 I/ z7 V7 E5 {2 d8 @; G" _( {- M
| MCASP_RX_SYNCERROR 1 I; n# u0 z4 |7 a
| MCASP_RX_OVERRUN);
7 g6 i, ?; `8 M6 q2 Q} static void I2SDataTxRxActivate(void)
' X: ~1 Q, E* M" F+ S# l9 A{
x! z& I* w/ w# v X/* Start the clocks */
0 x! w( n1 p4 `* WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) ?# Q! ^1 A, x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: t: P+ e* T2 x& e9 C% F8 r& F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 }9 V; F4 I. a6 M3 z* a& b' e" ]
EDMA3_TRIG_MODE_EVENT);) n5 k$ z+ P' V3 p! h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( u# K- h* j; j/ f( n/ l; @' w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 t. `7 k8 x( |) D- O6 g! g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 I5 l! Z, R: p% zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ O! T# t" Q1 ^ ~) f, Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 ]7 e7 _5 L) ?6 e- w; xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& {1 E- Q$ O$ Q3 J4 f- j2 E1 k5 u1 C2 nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) D9 O# s* r) a( b}
4 l' C, j, Q5 W% v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 l% ~% {' k7 l8 u) v. U( A
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