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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ j5 S' \' I) @& m ?2 f+ Winput mcasp_ahclkx,
( I" K8 P2 p6 N5 v) V( sinput mcasp_aclkx,6 A9 G$ ]- S4 q+ V! \
input axr0,$ O, F. E8 w8 ]/ u1 M2 |% U$ o
5 [2 P4 p9 k9 M0 s# r; \
output mcasp_afsr,2 Z+ T ~+ P% |. a
output mcasp_ahclkr,
: c9 l5 k# P. @: c* P# _' poutput mcasp_aclkr,( N& m- D+ j' ^
output axr1,
. k) e l& `' P ]7 D assign mcasp_afsr = mcasp_afsx;
6 L3 N8 I, |# q$ K+ J4 [/ Massign mcasp_aclkr = mcasp_aclkx;7 f: x) g# [0 b5 a+ p- r
assign mcasp_ahclkr = mcasp_ahclkx;0 o7 d* k) |1 Y( P0 {' G& z8 E% W
assign axr1 = axr0;
7 g- H$ ]& S% I0 `- N X" x( W& \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 h) ^' h9 X4 s8 w3 A, }: g
static void McASPI2SConfigure(void)& H- R: Z( d# _7 ]0 p" v
{
+ f' x$ Z9 c4 x4 {McASPRxReset(SOC_MCASP_0_CTRL_REGS);* C% f+ ^+ n* u4 ]/ z5 M% B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 W5 x6 y$ X7 A4 N) y% pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ i2 l$ Y9 u1 y! P, A( D3 ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- o8 { F% a9 d8 P$ A) X0 L! [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) \$ ~' Y' m% ~3 K6 j3 b
MCASP_RX_MODE_DMA);
( L% D/ F& l$ GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% x& H8 T( z) ?4 }: _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: R/ z/ I0 N! Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + g/ X1 t0 o$ e/ s; g/ e, ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 l2 C# p K& C0 k0 q, nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ V1 Y- l4 A2 l& x1 H/ b D- |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" V7 g7 u7 z. u9 ^/ F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: o9 q: H4 I2 d9 m. ?- K, z) g$ x/ PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : j2 Y; c; b7 N& x5 }( B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. H( ^. {8 u* W4 }! ?; Q# i0x00, 0xFF); /* configure the clock for transmitter */
) H. K; D7 k' e2 a h7 }* VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% h4 W6 V# S, z: @) E+ K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( y( `" a D/ ~# wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 N3 u& ]+ s% K3 i0x00, 0xFF);' o* ^6 w* v3 r* R+ [' m; j; P4 I$ r4 H
* b/ Y9 b+ h. ?- b( n/* Enable synchronization of RX and TX sections */
3 {) M6 G1 d/ M6 K( iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: N6 n, z' p9 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% M$ w; h) a( W- m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; a. s x. v( C! B) K2 L. d** Set the serializers, Currently only one serializer is set as
4 c! @: l: c# I& n# z* q w** transmitter and one serializer as receiver.4 Q( @& t {* a F: H* W2 N3 O( x
*/
# q% |7 U4 G( o/ dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) b9 K( b! ^5 Q1 [0 y: |; ]1 d0 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 Q* K, C1 ^+ k, R" g3 w5 n** Configure the McASP pins
1 k( f( e5 C1 D& d) f** Input - Frame Sync, Clock and Serializer Rx/ ] g; Q2 K" R- ^7 R5 O" M
** Output - Serializer Tx is connected to the input of the codec
$ X% a8 m# t$ T! ]' Z# }( w3 w*/8 f$ Z8 x1 i7 Z, F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 ^ k* q( C/ A4 L# N' F7 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ J6 g( U& o; @$ D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, T P2 {: z! p3 [ I3 `. U| MCASP_PIN_ACLKX. p7 y+ s; ^+ Q' o3 @7 @4 h' }
| MCASP_PIN_AHCLKX
( d) z& O9 P5 o. G+ f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) q, v" O N I/ u GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * J: |+ L, e, T
| MCASP_TX_CLKFAIL
2 c+ v. p; _. O$ ~/ a% \7 J| MCASP_TX_SYNCERROR
) t; I. t# T, t, \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * J! e( N3 x( C* ~# }6 A$ P9 f
| MCASP_RX_CLKFAIL( S. S3 T2 x( A9 u
| MCASP_RX_SYNCERROR * |# D+ A' n3 |. s8 q9 |0 L5 R4 ~
| MCASP_RX_OVERRUN);
/ r2 r: K( V1 M+ J' W$ {} static void I2SDataTxRxActivate(void)
9 s7 a3 `4 M+ Q+ o1 Q; m{% C" J8 S! W4 r
/* Start the clocks */' @2 M" Z& D$ q. z3 X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 m' M+ J; Y( e8 \0 M/ LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 E4 E0 q+ q; v( G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: N# |# {1 @6 jEDMA3_TRIG_MODE_EVENT);" [! Y( I6 J2 j @7 \( @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 g: r# Y6 e4 A7 J; X4 ^8 r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 ?' E9 s& ]7 O+ _' z# |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' h! J' e- o. E8 R+ }1 b# KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. N j4 Y4 E* f# awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 _ m5 N2 |) \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 Y' c3 _4 c# S; s: P& i. h6 A( b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" ~, I- f$ O& m
}
/ r: M9 d1 J+ T+ U4 b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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