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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 k/ B t$ W* y8 ]% u* z2 y
input mcasp_ahclkx,/ u7 F5 o! [5 Y V
input mcasp_aclkx,
1 M% i' O2 c+ T& P0 ]input axr0,2 B2 k0 P: ~: U4 t
6 y7 \' a1 t: V; ?6 koutput mcasp_afsr,' i& G" [/ i* q& d8 J
output mcasp_ahclkr,# {) F! `0 n- W1 A$ @# e. Z+ V1 c
output mcasp_aclkr,2 {( n0 K8 r. z/ I6 K2 d5 a/ T
output axr1,
2 l* r: H. B% p5 z: @8 s assign mcasp_afsr = mcasp_afsx;* S& j! x* j9 h' h
assign mcasp_aclkr = mcasp_aclkx;
8 E; s0 k# N; V8 v" {7 C* R4 iassign mcasp_ahclkr = mcasp_ahclkx;
# [7 U) I8 u# m7 M& T4 b$ s- vassign axr1 = axr0;
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+ O* Y" M* w3 B3 J6 D; N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 E! @( I& S' k
static void McASPI2SConfigure(void)
1 B z; i! p! D5 x, E4 ~, N{4 q5 _" v( d* u2 d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% E- v. ?! R& }' \: ~( _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 R+ E8 P" L/ X% a( h8 u; w0 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' B! m- t% G X! o f" a7 [& kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# I" L( S! s' ^. y1 \) n' l) H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 \& {. K- e) g' B8 C3 B, D2 O
MCASP_RX_MODE_DMA);
; j' d- t0 s N0 e2 x2 b5 {' @; ~: k. BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 d* l; n8 ?! G7 o4 h t kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! P) q/ Z" r6 e( w) ~3 @- c( I& h# f5 d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) b+ q; y) W7 q" l& HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& w! V% |, y, I& B* ~- ]4 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 n1 i) o! ^$ ?" {! i# _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 r5 G- p3 u: U/ M% ?( E0 U4 u6 v: D. hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 ]" i8 O& P% y! y$ E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; J. q) G6 ^) x" i& EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( u/ \; Q% u! a4 C8 a
0x00, 0xFF); /* configure the clock for transmitter */
# n3 M0 p+ J" \! Z: ~( Q; IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. N: x$ I) z1 `/ u( z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* b* E1 p+ W- @5 ^# eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," A6 c7 z6 O, K+ A* P' A( b. A6 e2 e6 H" [
0x00, 0xFF);/ i6 |/ D* x9 Q- H5 j9 q; |7 |
* p& f( j+ j% }8 T$ N$ R/* Enable synchronization of RX and TX sections */ % b+ m4 Y% z/ C' P# u0 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 u; C1 |5 H8 AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* i* C. M( n9 z0 W4 j. S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! _) K. E# V* I
** Set the serializers, Currently only one serializer is set as! b2 m. X6 A& b1 c% n: a- x2 c* X* s
** transmitter and one serializer as receiver.
1 [" @" J6 C) B*/
2 X% o2 q O5 k, {9 ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ x) _( n; u- N2 J* U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: R; _ ~: S/ ]. N* r0 t: F4 s/ E
** Configure the McASP pins
j$ F9 v2 R% Z1 Y8 {( e** Input - Frame Sync, Clock and Serializer Rx) p1 w; w% H% f+ P. a
** Output - Serializer Tx is connected to the input of the codec
I/ f9 x" G* \+ M. } e8 `+ R*/
# D9 s2 Q r/ y. l6 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 K9 [8 b: P* Q5 }7 RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 z6 W: D- P1 i# A4 l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) o0 J. w5 g. H. o9 A! _
| MCASP_PIN_ACLKX
( ~& k9 s3 h: q. n| MCASP_PIN_AHCLKX9 m" [( k) c" V1 A+ {- a$ }/ s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" P8 ~( J, d5 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : v* w( N3 \& D% o1 F
| MCASP_TX_CLKFAIL 9 O% m, k1 |) P8 y, x/ j. Q
| MCASP_TX_SYNCERROR
H4 {* Q7 d+ Z' N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % G0 N2 O: S6 d0 f$ F* K/ K
| MCASP_RX_CLKFAIL- C; ^- d$ D/ O8 X9 f
| MCASP_RX_SYNCERROR
8 l8 `! Q% C' o Y| MCASP_RX_OVERRUN);8 j- d! R& H0 [1 A; _# [
} static void I2SDataTxRxActivate(void)
8 Q8 V: |1 Q4 u y7 a+ m, m' `' a{
' H9 w. X- R( u/ V. a/* Start the clocks */+ J4 e/ i# L8 X- _; j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' C* [2 z, w9 R8 v7 I2 M: I4 b# dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ \3 ~5 h" ^" {; X% L, x" }" u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
K) A4 E2 T5 p* H* g1 Z) E' pEDMA3_TRIG_MODE_EVENT);
7 _% C1 q# N6 @: B% ?) N V; X6 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' s1 W# `' W3 ?, h: @# PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" u1 n5 D' C/ D U" u+ T IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; z, v; R: }$ d$ \" n! t+ XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! ]0 Y& h. j8 Z+ U( d" Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 Y% Y# h H1 s7 ^, GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 h5 Y: p" z1 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& t6 H4 q+ G0 c
}
' k( O) j. r7 l" C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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