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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& r# d/ y, `* F" ?- M* ?% \# p
input mcasp_ahclkx,
. r2 `, M4 P# A" W* finput mcasp_aclkx,
. p& a- b, x$ ?0 w0 c# y& ~; V% y' ~input axr0,
( O' `. ~( F) }/ ~9 v4 Q* q1 D9 U: m/ c& }! E; f9 K
output mcasp_afsr,) f0 [% H( [) b0 X, z
output mcasp_ahclkr,
$ P7 Y2 z# g$ R" B2 |output mcasp_aclkr,
1 H1 F" z ?% p; w' U7 Zoutput axr1,
' A6 f$ Y: V! P assign mcasp_afsr = mcasp_afsx;1 \7 p9 G, U1 H/ o
assign mcasp_aclkr = mcasp_aclkx;
6 H b+ H; F" B qassign mcasp_ahclkr = mcasp_ahclkx;+ V6 k6 p% R$ M9 s( M: a! C
assign axr1 = axr0; ! n' @: F! C/ j. ~$ p
3 \9 E( W6 ?% e/ z4 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 K! J& T! [2 l( B: c
static void McASPI2SConfigure(void)% ]5 R; d: K3 S
{+ J6 { [5 E1 a% i4 V" g% }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" Z$ T% N" T- Y2 Q% n0 _ |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 w$ F! m4 k% b( D/ Z; w, YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ j8 i/ z8 C1 d w- O2 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! u' S# N# _% M- YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 u% w4 x8 t! V; u: U4 g+ {. v, kMCASP_RX_MODE_DMA);
# d$ d+ N( |$ d* v) JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, M5 W4 B z+ u' w4 G, ^) iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: M$ w9 a8 T0 N. ~, M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 e) ^5 z' j# z/ m" n. }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" j3 E2 J& a% F+ Z+ f, v! H2 q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- k5 v* X3 o) x$ B8 c, i- pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 Y4 ]1 \2 R8 F( Q9 {6 E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" f! J1 S( n1 m9 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& N) x/ {) ^; m( _# g2 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ ~2 ], ]7 Y% f: s: s! \$ Q8 q
0x00, 0xFF); /* configure the clock for transmitter */
. V; x' t2 S T7 f% RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' H: ]0 b+ J. d, i, Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 B) `0 J( j% Q Y$ T8 P, H/ PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 N& G' u7 ]& m$ x, i0x00, 0xFF);
& U3 x0 G1 |7 }) v4 }8 L: U0 p
/* Enable synchronization of RX and TX sections */
/ m# a4 k7 I4 sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! ^0 l# d) L6 K$ I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# a2 V0 V3 @" b0 ?3 A. zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ N- ?5 x+ c( ?1 ~: [6 B6 ~
** Set the serializers, Currently only one serializer is set as
1 m N' k- l, {) q: {0 j** transmitter and one serializer as receiver.% q$ C9 C5 V* y! l, o$ U0 N
*// M" {1 e+ Z0 I \/ [. W0 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& H9 v% t3 J1 ~9 x, y+ t; Z; ^$ _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 P8 }1 Q9 v9 k0 u+ h+ k** Configure the McASP pins
4 h( ^4 h- \9 I0 `** Input - Frame Sync, Clock and Serializer Rx. E. {: y- `! k7 B) ~( Y, D7 n- J% C
** Output - Serializer Tx is connected to the input of the codec * L4 r* Z2 d% U: d+ ~+ ?3 W8 k
*/' ^3 v/ ]5 [8 d- K/ f- x; {, w% e6 z! \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, }4 }$ x/ Z( B) l% H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) i' A% P6 T4 [$ m# x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; I6 ~5 Z2 I5 d1 ^, i; ?3 [6 y
| MCASP_PIN_ACLKX/ }# y5 N: n8 y8 r4 H
| MCASP_PIN_AHCLKX" Y" \5 W+ C* W f4 z1 r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) ?" \* Q" f& D8 O0 ^3 @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' t) }; `1 O+ [: l3 F
| MCASP_TX_CLKFAIL
4 z) G% H+ l$ h" V$ ~2 I( i| MCASP_TX_SYNCERROR- O) _0 P- o) g6 J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: Z% ^9 D' b; q4 @. D| MCASP_RX_CLKFAIL- }3 \3 [* d* `) H) W2 F
| MCASP_RX_SYNCERROR
. h# c ]' t6 T6 z9 u P; b6 ?: a$ j8 R| MCASP_RX_OVERRUN);
. q: i5 l% Q0 R ^, J4 A& ^} static void I2SDataTxRxActivate(void)) e( |4 c5 _0 q6 G' o' g$ E" S: c; j+ K
{
, {+ d" f$ w ?* |) u3 ?/* Start the clocks */4 P! s2 f" l5 z/ M6 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 ~ R: c0 U" N) O' ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 l: k' S2 k0 q9 F) ~- n% OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; j2 i8 d+ |( D) h/ y3 f5 YEDMA3_TRIG_MODE_EVENT);, L2 O& g& K0 f! m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " L8 M# c( a) A# \; [; D) D! T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* p& D- j0 ^# m/ r+ ?, vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 m& H+ C; }- \* {9 a; m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! x& _4 S3 H6 b/ n3 R7 K8 s5 \# J9 l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% n+ ^% i7 m. j$ U1 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. |& h" C0 s' r9 w0 h8 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 ?5 T M- m& k# q1 Y} 2 g- ?% C) P4 {: }& Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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