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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 b$ v$ q" g5 w: T8 F# {
input mcasp_ahclkx,
) r* P! [; I: P3 _% @& t7 n( Jinput mcasp_aclkx,8 @+ y3 x2 @9 N$ F( R/ _9 N
input axr0,) t. m: z5 y& z8 U. j2 }4 E/ ^! f
& F8 `% p# t1 i( R9 l8 T
output mcasp_afsr,! s1 E/ ?+ I3 J! w* p* h, l
output mcasp_ahclkr,' J1 L( |3 f! s
output mcasp_aclkr,
6 i6 l! r1 |! r. Uoutput axr1,! t# m6 p, o: ^, G
assign mcasp_afsr = mcasp_afsx;
( }, ^/ Y% q. p5 ]assign mcasp_aclkr = mcasp_aclkx;
2 L4 M( n, k$ a. d/ n& [assign mcasp_ahclkr = mcasp_ahclkx;
@: K' L6 f# h( Yassign axr1 = axr0;
! ~+ c$ A( G4 M9 q+ s8 x
/ K4 N3 J9 U: k( b8 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / [& J2 o2 f, N* o; B% z; E, q
static void McASPI2SConfigure(void)
( @1 n3 Q/ ], V' U; Y. R' Z{+ f6 V/ X" Q+ Q5 d) u. n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 v+ ]: C3 q0 I4 Y! e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 O; a' E2 |5 x4 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 `+ J' `' n. D$ \/ b& C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 T; k I9 b' Y x5 H8 F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' u" `, w4 w! @* n! c
MCASP_RX_MODE_DMA);6 X6 R6 m' Z- P0 j3 x- X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 K! V& g2 \! C1 ~8 {5 YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 l# b+ D7 C3 D: P( B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! t9 s( f- s0 H8 Y$ J, O; W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 Q5 D$ P0 d/ {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 F2 z+ l' K8 I! n. [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# X( f" ?! D* L; U$ F0 y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% I. T4 w$ Y3 l6 ]7 b' HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; p7 a$ G7 I: z4 Y6 z6 b$ GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- n5 x. `) O- D& p* a* g
0x00, 0xFF); /* configure the clock for transmitter */
1 C0 T$ W7 e# a: K; CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& Q* @$ H7 Q, V6 j8 G0 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 O( k& a0 K0 c) ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 y+ H! f( o* j1 w8 n
0x00, 0xFF);5 m0 T. E- X8 H, R8 X/ B
( x: O4 J( C5 ^8 ^ y B/* Enable synchronization of RX and TX sections */ $ z9 u0 V- A& q1 n: X* U4 L( h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- h* P3 N5 S: YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 b1 l- U& k/ V- g9 Q; bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ f r i9 H# p9 R, M; N% t& R** Set the serializers, Currently only one serializer is set as
8 O/ x; w& r1 X) y% F** transmitter and one serializer as receiver.+ T b+ `4 p7 o: E' s
*/
3 w5 U, t+ f) eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* _: i# p1 a6 `: d7 u/ C% r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 E& l: H1 g9 `, H& W
** Configure the McASP pins & J6 h" D- R# T
** Input - Frame Sync, Clock and Serializer Rx
0 y/ e" g7 {) N* z) H** Output - Serializer Tx is connected to the input of the codec
{. j- s6 }& ^9 ?4 J% w. v+ Z*/
3 a4 q9 S; i+ \5 O' A- a- QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, M& E9 i. f$ A/ K% Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ O' c z! K `# g; e+ WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 J$ G' z0 g% e$ z1 M| MCASP_PIN_ACLKX& b/ ], F$ I8 \9 T3 T" n
| MCASP_PIN_AHCLKX4 P, e2 _/ [8 Q: G$ b) d$ q4 G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# {% K9 [/ i; F; @+ eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 n, ]3 O2 e4 H- n| MCASP_TX_CLKFAIL
. u* A' D5 E6 ]+ F* V| MCASP_TX_SYNCERROR; ^( y2 p+ `$ I. ]# l4 u9 N. z2 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 S4 O0 R8 I9 B' B
| MCASP_RX_CLKFAIL
0 u D7 P8 i" y; t) z' Q4 I| MCASP_RX_SYNCERROR
# _8 A5 x% C9 _, x5 H k! X3 Y( x| MCASP_RX_OVERRUN);# a% }' Y: `, I# W( U. |& D3 U, P
} static void I2SDataTxRxActivate(void)( V' a1 o6 ?+ V' V: [
{
3 z0 }! ]8 ~% S( \8 N" h2 H# K: j' M/* Start the clocks */8 h9 M# Z& F3 G9 l4 S2 D: N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, L6 m, a. M0 O! K, Z: Y; D, `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# k5 }! s, S1 [! X3 ^$ W6 J9 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 a5 H! S" F2 j/ M4 XEDMA3_TRIG_MODE_EVENT);
9 h1 F' x; m, d( m" A' k1 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & r8 _! {) Y- t# T8 p/ H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: @0 b& O; c, l' CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" y& w' Y1 Q, a5 C- ?& a' L. m! _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. \5 M! A4 E6 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 `1 J( O2 M1 X" p1 zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ T/ V6 Q% D* S6 u* [# F: c. T$ ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" f* n$ K( g4 C2 Q/ u} 6 S2 Y7 A; V/ k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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