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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 C8 g6 A, K7 |$ Q% i cinput mcasp_ahclkx,
" {* V+ p8 u' J) |2 }" {input mcasp_aclkx,
6 {& J! a7 Q$ sinput axr0,9 L% k: q4 y; p; L- d2 Q4 ?
( e5 A h- H* V" ]
output mcasp_afsr,
( v# S# U. m4 A7 {0 v2 ^output mcasp_ahclkr,
9 \# l* ~% K6 Q6 Q) x& Koutput mcasp_aclkr,4 ^5 y# v- b6 ^, I9 b% J$ j1 R
output axr1,
v o( n1 ^. J4 z1 k4 z( ]3 V assign mcasp_afsr = mcasp_afsx;
! G( T3 p9 N Jassign mcasp_aclkr = mcasp_aclkx;
$ d% d( M: [* I- U! C# Nassign mcasp_ahclkr = mcasp_ahclkx;- {' f7 h. r5 J4 c5 o
assign axr1 = axr0; & Q! e' l$ T# ?; r( c8 l& Q- g
! e# n. m9 _' d: I' v. y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! y }3 t* N8 `: l; j9 M' O0 Q
static void McASPI2SConfigure(void)) W& d. M2 d+ V g/ F& L
{
7 e3 h. o/ b9 C: ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 {( I* G8 h; J' i8 ] O1 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 }1 |) N$ @ t0 U- oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* u2 Y; |8 p: C0 J8 h& D% g6 H- ?# fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 p8 b! c3 Z" R4 C. x* _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, Y! f% h3 w. e: s \MCASP_RX_MODE_DMA);7 t& t4 h2 C, o' X' s: A* z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* X- T6 U, {, |4 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( R! n& l/ A4 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 }& U3 j ^$ w8 U: B# J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" W5 t ]7 P& P) v5 k! H- w6 @' |" Q( SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 D" B3 y, Z, n0 q3 g" ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ N0 a/ D6 t$ x# u7 ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" |! Q6 O' s7 k1 _4 V2 e6 wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 _7 o4 s4 T( y; S G( J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ C, @" [; d6 P/ @0x00, 0xFF); /* configure the clock for transmitter */4 k0 V% q& i- ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! u7 N/ X; b/ r( r9 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 p! v6 Y+ K+ P# ^/ ^) Z1 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 b. ` `* q: u. E& q; b* C" j" ]0x00, 0xFF);2 v$ p+ K, t2 Z1 o# b2 [ V
1 T+ R% I5 ~' @- _2 w4 Y2 A
/* Enable synchronization of RX and TX sections */ , n! H4 d) ^- G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 X6 b1 [& y- F$ f( A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ?. @( Q6 {( l" y. AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! |, ?0 G. o5 F% i9 k0 c** Set the serializers, Currently only one serializer is set as
1 x/ w$ }% R# k' x. \** transmitter and one serializer as receiver.
: ~8 |; k8 J! i! N+ D! d- X*/7 z* C9 |/ I7 K3 R% ~2 j* }# L/ }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 K! |! N7 D6 v- x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: X3 ^, X$ U& k- v& t+ J2 m* L" N** Configure the McASP pins
: J& h/ x# `0 [% i Y5 A' T** Input - Frame Sync, Clock and Serializer Rx( V: k9 G6 V! a' _* M/ X
** Output - Serializer Tx is connected to the input of the codec
& v# f" a/ r$ | O% G% c. ?5 D*/$ h* W d0 Y+ `4 z( z" E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 J" L/ A; H& Z. |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! }) Y5 O% J/ \2 F B) z6 tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- p" m2 z* S& ?; s
| MCASP_PIN_ACLKX
# k1 q4 z$ j6 C$ C- c" ^| MCASP_PIN_AHCLKX5 n% v. e: f5 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! v- v9 t/ E! A4 p% rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - `: }( R5 E* S8 L, O5 P
| MCASP_TX_CLKFAIL
" N& f Y# C6 ^" k) A| MCASP_TX_SYNCERROR1 A k# J8 E. s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & J% W' W7 u0 J0 N7 d
| MCASP_RX_CLKFAIL
7 Z- ?" D+ g/ p U2 _| MCASP_RX_SYNCERROR
& d2 q. q S) `' s5 c* Y| MCASP_RX_OVERRUN);$ V, e. B5 z% J
} static void I2SDataTxRxActivate(void). I+ a. Q# }7 F1 d @, l
{- ?3 h- Q+ b" W, ^/ X
/* Start the clocks */( q7 G n' M" ^6 W Y% L' Z* l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: x/ Y( e+ s. F; UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% Q* {) o& v# ^% tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ M- Q4 Z$ N X: Q
EDMA3_TRIG_MODE_EVENT);/ r6 Z, D9 V6 F! ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% F$ O6 T4 e3 [( g" C2 BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 [# ` ^# Y- }' yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) T' C! K1 s( l+ K' f1 L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. F1 c: o/ J* Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 J/ c0 R& S+ y4 {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& _$ m3 |+ M4 s. gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: e( [) |+ p, Y/ v2 r {8 {
}
8 @% g4 _6 R) h6 B' P7 `. O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 ?+ | K3 H/ X
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