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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. K4 L; S4 o) g: R9 @; Cinput mcasp_ahclkx,
1 _+ p2 i, Q, g3 @4 X8 c# a; J S8 winput mcasp_aclkx,2 s4 Y. N4 S) q' c% [
input axr0,5 o& l, O3 m8 Y0 Q9 ^& ]% N
- H3 r, }1 m: p
output mcasp_afsr,5 A7 q: J- y& u8 ?1 F% [1 s0 S; r
output mcasp_ahclkr," |% J. ~9 k: q/ d
output mcasp_aclkr,
/ W% ^6 f# q' f, [3 u9 uoutput axr1,( n* E& I, y) @, J
assign mcasp_afsr = mcasp_afsx;' X: N7 Q5 ?( Z5 c8 ?5 }. K/ C( H
assign mcasp_aclkr = mcasp_aclkx;
5 a+ J7 M( @8 i p- ~+ Bassign mcasp_ahclkr = mcasp_ahclkx;4 N6 N; Q& F; f! _4 V' \6 B
assign axr1 = axr0; + I4 ~# T$ [% O: M6 @1 T6 u; y. t
2 N( j) T* u) b& H" N% k9 [6 h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% p1 N& J# r5 _& P/ _: J( ^* `static void McASPI2SConfigure(void)
6 j: f- [. o. X F{# H/ U/ n* T0 E7 g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" I) F1 E: x( m7 P3 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* f V3 d. T Y4 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; w( e3 z& ]9 p: X) O: S1 y" r* u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ s8 F( s3 q; s# nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ S" m6 |3 X, j& D% QMCASP_RX_MODE_DMA);& V# D; f q1 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 o. o$ o8 d$ I& _- c6 z6 WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ l9 N, N1 E# a. TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. O5 i1 f! z7 [& J. l& B8 kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& L" i9 Z# w- u J: ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" o+ d; m' Q e4 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% W1 _0 R1 x2 x1 ]9 L& e* N& yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 v; t6 s6 a' u) gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 L8 U( L! W6 a! S5 N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- ]% C+ {! p* I8 V0x00, 0xFF); /* configure the clock for transmitter */
. q" f) C! }/ W2 |; G: U% w6 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ @0 t; m( H7 f' W2 h0 d/ H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . p+ n9 Y3 x2 ^& ?* R7 A7 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' g& e" ?5 t* v3 D7 a+ z3 u- D$ m0x00, 0xFF);
& Q2 r2 f$ G+ }( Z$ r/ j F( W; h3 Q0 e2 {) c- T, z
/* Enable synchronization of RX and TX sections */ $ G7 @/ B$ b/ l2 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* s9 d" F% `0 [. A+ [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: N" l0 V( W5 ^- i4 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 l; u4 X2 Q2 j, b
** Set the serializers, Currently only one serializer is set as
9 l6 s$ e4 J' V; r* s$ D** transmitter and one serializer as receiver.
+ s7 ]5 L. }- w9 s6 o*/( \! V( Y/ B% n* g- v2 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) P+ Z5 \' ^7 Z. W7 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, I1 q+ g% o* K. F2 O, H: @
** Configure the McASP pins
! B" t! }) J+ B' M4 T+ Y0 p** Input - Frame Sync, Clock and Serializer Rx
H' W6 M5 w. h9 a' h6 T** Output - Serializer Tx is connected to the input of the codec
4 f) A* @# j7 Z& h) S*/
8 s% O3 _1 ^+ h& kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 c) Z+ x; X( _4 \) K( d1 H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# L# C- Z8 S ?0 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 m( i7 K h- e# `' G5 }. p| MCASP_PIN_ACLKX5 l" ?0 P6 h: k) B; L+ }1 o
| MCASP_PIN_AHCLKX" M- l4 J K9 h7 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' D0 J7 \# W; q) e- I7 A! k) W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) j, G# h; v5 P [1 S' Y4 O
| MCASP_TX_CLKFAIL 6 O8 {% B8 H5 E: l4 F3 h
| MCASP_TX_SYNCERROR$ _7 S4 T) d. v \6 S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( z# O! k! w" L& G| MCASP_RX_CLKFAIL
4 x; y+ S; a* A* t8 U| MCASP_RX_SYNCERROR 1 X! Q. }. A# z& |, h* {5 O
| MCASP_RX_OVERRUN);
( n3 \/ i _5 x' o5 s2 D} static void I2SDataTxRxActivate(void)
5 ?: U! C+ { g/ Z8 `{. T9 k' g4 j' z. N) y0 b* T
/* Start the clocks */
# A3 r1 k7 \* I6 S6 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# i8 D$ X F3 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) l5 }' P4 Z( l( N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; T9 f9 A$ ^0 q( u; M3 d
EDMA3_TRIG_MODE_EVENT);
( u, _" j: G% H. Y$ PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" Z' F; I2 l, E; q0 O6 Q$ Y/ mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 k* D3 i2 I, F/ U; ~' b7 [( A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
Y9 ~. ^+ N& v4 B# j# Y$ J fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 d7 j: D/ f4 t& ~8 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, p" L) |- [ @. }: r. l! _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. m5 _) o% L- n2 V. n" A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# i1 d/ s8 e0 D- f0 ~5 y3 O}
, v* K" L6 a& [, L I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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