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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ |$ d- H* ^, y% s+ o+ c
input mcasp_ahclkx,1 k3 I4 u: m8 O- S& w) z* }) P
input mcasp_aclkx, R6 T4 O/ j( [5 v6 d9 n( V! I
input axr0,
% |; A& `8 H9 ?$ w W4 z# }9 L) V5 e F; G. V0 R4 Z/ ?3 q
output mcasp_afsr,
, ]( _7 |) [) E' houtput mcasp_ahclkr,; Z! n2 z$ T9 W
output mcasp_aclkr,& ^+ K* I X) m* z! K
output axr1,
/ W3 k' v/ R1 h1 T* J/ E assign mcasp_afsr = mcasp_afsx;
; O. [6 `8 _0 G/ k2 Z! `3 v. Sassign mcasp_aclkr = mcasp_aclkx;
3 n6 E8 C) X+ Yassign mcasp_ahclkr = mcasp_ahclkx;& w$ e5 w5 k* f7 H5 s* f2 ^
assign axr1 = axr0; - g3 r1 G* P- L: c
5 F) S$ B! |9 a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! ?8 v3 O5 @1 b: ]: S. R! \
static void McASPI2SConfigure(void)( Y* [/ z2 Y0 A: a A7 d* O
{
2 e1 h4 q; C* e0 @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( N; h1 A- E Q' GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ c3 X$ Q9 `. zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ u9 ?7 {1 Y$ I; \2 \3 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ ^1 o# R* R0 S; X0 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, H7 ~$ ]- o, j, |9 g3 f1 a
MCASP_RX_MODE_DMA);
R3 x! }/ s. pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' h3 V8 C1 i% B% X' L1 f4 W& R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- @; k* H# g& ^# }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' f& H0 w* k) s* H% ?2 I9 ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% ` o d: p# y0 `% S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 r/ g8 W, t; v4 d, j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. l# [* y, n6 M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ w6 w3 {1 u# d. w2 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ D( B, E( d3 M m5 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; `5 V' _. M, u7 j6 J8 F0x00, 0xFF); /* configure the clock for transmitter */7 b" ~ X6 g: F) d" t9 Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; p8 c; z# B. F# H) r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # {! {6 Z6 G. g$ u+ Y8 Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; B% C* R7 K5 ]4 t) R9 e0 ~
0x00, 0xFF);
1 p! j, m( ~% h( p; I- c6 r) S$ H5 I( x6 b2 ]4 g, h `1 i
/* Enable synchronization of RX and TX sections */
7 L- l' a3 C2 m4 KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! J! H A$ i) p2 I3 h* q1 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* c5 G, {9 N0 U8 a) f }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; B! H! O6 w# b5 N, ^1 |** Set the serializers, Currently only one serializer is set as; {# o( ^4 Y! s" f! T
** transmitter and one serializer as receiver.# i6 j# |) _5 Q6 P( Y
*/
3 a1 T: I7 c7 e% r, KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 p& l" }* E' e5 B2 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) b) O/ N; ] L/ Y; l. i/ J
** Configure the McASP pins
# \6 _6 R# I; Z$ \; ?** Input - Frame Sync, Clock and Serializer Rx
6 }9 j4 N( n( L; y7 L** Output - Serializer Tx is connected to the input of the codec + q( R; g6 C: f( n. i
*/9 {) V; g. o& m0 J3 m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. I/ ^. h+ o' f$ e6 a7 P' p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" s" R/ y, ]) jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 R" [+ ~. O1 [. t4 K6 f3 l
| MCASP_PIN_ACLKX
0 n5 x7 ~( q3 W# y+ m0 d1 M+ W0 B n% C| MCASP_PIN_AHCLKX
+ e' s$ I7 u; ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 h) D4 I& e% Q! B3 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 c) @5 L2 i. k' R
| MCASP_TX_CLKFAIL
* _# y) t+ P7 X7 k. r1 G| MCASP_TX_SYNCERROR
* j! c. A, q2 D* v$ }) N# Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. a4 E0 N6 Q( g5 d: M| MCASP_RX_CLKFAIL* p: Z1 M- p R8 v; x/ r, V/ _
| MCASP_RX_SYNCERROR
2 B* X6 t! |4 R. r! ?2 i| MCASP_RX_OVERRUN);% ~ B6 g/ v6 L6 l! c
} static void I2SDataTxRxActivate(void) \' o# w* F% b
{
, _; G6 ?) h2 }! [/* Start the clocks */
4 ?( D1 F6 e( R3 N1 X- T4 m1 m3 f5 pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ \9 |# P6 x% g, P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 C% M! x5 z. w0 P, v4 ~3 gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 ^* L3 X- n) W9 ]EDMA3_TRIG_MODE_EVENT);
) ~' ` y* k3 S% h1 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + m' R! w- Y' Q% j+ r2 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ v; H) O' [5 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% j0 j$ ?7 W! HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 U- `' T& ], r* f- g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! Q( l" n" m/ s7 W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 r6 A# Y- u1 x$ }% C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% X, D+ f: Q7 W0 r; P; {0 v) L
}
I$ D/ O" {* n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % ~$ s8 v7 y+ c- Y. W/ W
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