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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) K# K6 [; a# t
input mcasp_ahclkx,
0 a# A( b8 |2 \input mcasp_aclkx,9 B- U: U- n3 I: u7 B. J; V: y
input axr0,
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output mcasp_afsr,
/ K3 b1 p8 k: `* e) m+ b) W8 zoutput mcasp_ahclkr,
: B! F+ Y2 w( R* N( |3 ]output mcasp_aclkr,
- T7 X0 \1 A' E. J8 O, |output axr1,( l( |- n3 s$ X/ [6 S. K
assign mcasp_afsr = mcasp_afsx;: i8 C; {! f/ V
assign mcasp_aclkr = mcasp_aclkx;/ J8 v0 Y* P7 {# M. {2 t5 y ~
assign mcasp_ahclkr = mcasp_ahclkx;3 r" B0 g3 B/ |- P1 q
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( T* |# p4 z9 I/ u+ P9 Q& E5 Xstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% p2 b- D( n0 }/ PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 d& y4 T _4 e0 V/ O5 ]2 D3 U% }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 d7 J! U# a1 e* pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) [& X$ @4 U$ U4 s; m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* j4 p O' d0 s8 X zMCASP_RX_MODE_DMA);' H. m+ Q% _) X& K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 Z8 C9 C9 m. bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 X. N% v: w+ T8 V5 }' SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + q1 ^! l/ P- i8 F. d1 }* h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ d& h% ]3 t5 x+ SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ k- C' v9 Z" i6 x. GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- C% P: {+ o$ ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 s& O/ O2 D- f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% K* Y6 a M7 k; B0 {7 tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 ^ h$ x) L$ g( b; s( a1 @0x00, 0xFF); /* configure the clock for transmitter */
+ b1 F% x% \0 \) r7 c+ U! t$ Z" AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! \- o' u( G( v) J/ E# iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% {3 m8 I& d1 T! v7 N9 P# e* TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," E. W6 J( c g# D. }8 ~! X) p
0x00, 0xFF);
4 z1 T% F5 g$ n! V" K5 l) x
4 m" P( m. x, X, h6 L3 b: U/* Enable synchronization of RX and TX sections */ 6 a2 ]8 z0 K8 n6 ?3 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# _, p$ l; K# }, \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 i6 q' j: D5 b2 E+ ^3 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, |7 _7 v' }, b7 e3 s7 }** Set the serializers, Currently only one serializer is set as
) P8 T4 m9 a7 W/ n3 I** transmitter and one serializer as receiver.
) @+ U7 |8 ]. w9 u*/- A+ d7 [6 H j$ @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 q+ Z Y% z/ | Z2 h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) v( J3 U7 l- n7 B2 t, s: G2 S6 N
** Configure the McASP pins ; }$ e+ ~8 I5 N k% A# T8 p
** Input - Frame Sync, Clock and Serializer Rx2 [! F% S% H h' e3 I8 c
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 Q3 f& }6 O( Y4 C; F$ Y4 ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 z8 j. v6 D. h \' H2 {. d9 BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ \- E$ k8 a: U! m
| MCASP_PIN_ACLKX+ B& }3 z$ X7 k8 o1 R! @1 ?* o
| MCASP_PIN_AHCLKX+ D- G1 V0 G$ W; R5 q6 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 a, c8 H" s8 }* N" U, P% j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - ^' C: g. t' J' \
| MCASP_TX_CLKFAIL
% j0 f$ d* F4 z4 x| MCASP_TX_SYNCERROR: }: f2 P2 a1 e& R0 F9 x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 C! e( t3 h( Q: g* p
| MCASP_RX_CLKFAIL
6 g- C7 x7 Y: s. U- p" l| MCASP_RX_SYNCERROR
+ C6 g M( Q$ W2 X0 {| MCASP_RX_OVERRUN);
, S# T: ^: @$ M( `, p& {$ \} static void I2SDataTxRxActivate(void)
1 W; C$ _8 \( }: b: ]{
1 t& H s! r/ W q' p/* Start the clocks */
) H- S- j) g$ J. ]2 ?* p; XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# h0 e2 P6 G, u' k, e( P, r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' B6 z( m5 @+ H+ j% P+ L% X- n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 P% W! H; l, v' yEDMA3_TRIG_MODE_EVENT);
/ X* p! ~' f, q" H/ j5 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! Y# T Q! K8 {9 b, v) {0 `' s( HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 D0 h/ }& V0 d$ ]4 v. U0 gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, _' N( ]7 q* V* M6 E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 ?# U K+ M: ~7 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 ^( Z' b7 _) y- n* M$ G4 |- }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) N9 L& |. Z7 b+ U# qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 j8 \, K- l2 h5 e
}
* R' v% p/ J( a; t/ L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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