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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 N, t r$ g* Z- z3 s
input mcasp_ahclkx,4 b$ H }: l9 q0 f( D4 c+ Q" m( Y
input mcasp_aclkx,' Q# p5 Q& w0 R. ~0 i" ?
input axr0,
+ x+ ?6 e; N5 u+ ~, s, n
" I3 L7 _% ]; U, E, routput mcasp_afsr,; x& z7 |# ^$ z
output mcasp_ahclkr,
3 {" R" ]3 D4 C$ poutput mcasp_aclkr," _9 v" R# J" f! }$ k: Z7 H
output axr1,6 e2 K5 m6 _# @- V+ W
assign mcasp_afsr = mcasp_afsx;
/ D5 ~! F& `% S$ Vassign mcasp_aclkr = mcasp_aclkx;
3 Z, P' i# K- Z6 {assign mcasp_ahclkr = mcasp_ahclkx;: C2 Q4 ^$ k3 r7 |9 Z# r; U- p
assign axr1 = axr0; 5 F+ A5 R* C$ S- O6 F
0 U+ X" n7 `1 A2 {0 W& A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 {5 V# R7 ^3 Y: h! L% F, \* m5 Mstatic void McASPI2SConfigure(void)
6 r% V$ E4 Y: k{
6 X5 j( E$ W# f' W) LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 o- x" T7 I- W4 q/ c3 W4 w( M7 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, r: }+ ?2 Q# r& E( t! hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; d2 h+ d) n9 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 e' z" n& f5 M- J! y/ {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! m" O4 o' u3 ~. O% i+ `8 LMCASP_RX_MODE_DMA);3 {5 _5 A) t; n; W! l' L, |4 O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, ]3 b, V$ f6 Q, o: n6 U( c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, j( O& ]! _! K; q# `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 |7 N1 x" C$ ?$ OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. f$ \" W( w. l9 g" R0 k2 S& x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 R6 t# I2 q5 K$ F. S0 J+ vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 ~* l9 K/ f& p+ p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& O5 k% V4 {6 c7 n, ~. Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 n1 j4 r7 _3 n3 D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 }/ O6 k( N( b' ~
0x00, 0xFF); /* configure the clock for transmitter */1 _( h! \; l7 T7 u" [! H0 |# m5 {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% Y& n8 i% K9 j& D& U5 g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. I' f# f# ^2 b% s% b9 L2 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& L7 T( J7 Q- k) d0x00, 0xFF);0 _% R( z. e* _, z# a G, r) V
, k' O5 a2 R, q% k( }# i7 i
/* Enable synchronization of RX and TX sections */
+ x3 r. a" \7 ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* o/ n: J' j9 v0 [2 L" Z4 Q8 K1 t; \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 c% N) c7 E* d! u% w; v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 I9 c5 k4 Q4 v, E0 H' o** Set the serializers, Currently only one serializer is set as
" T t3 _' T: [** transmitter and one serializer as receiver.
- W- O( f h ?! Y*/8 a& |6 K- A: U2 b6 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: ^, V) H. G. J7 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% w' C: U2 @( t& R! y n9 m) j2 c
** Configure the McASP pins
& [. m* F0 S& ~' {+ i** Input - Frame Sync, Clock and Serializer Rx" B7 J* S% \0 X$ I9 f: m' G# \
** Output - Serializer Tx is connected to the input of the codec 2 G) b% z5 \5 r/ P6 P( I) ~2 D
*/5 t' l4 j; I& `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 p4 M7 c8 y; a: W0 u3 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! d# a0 [- L% \( {* Q" c+ X; {$ L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* Q) R' J7 X/ W& V- y$ b% A- r4 `
| MCASP_PIN_ACLKX# L" {; f; I9 m
| MCASP_PIN_AHCLKX
3 ~; w' l+ F, [: U0 F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ~! a z6 B/ O0 R; e, T0 tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR M% q1 k+ C8 i( k# b) s, F
| MCASP_TX_CLKFAIL
# Q P1 r4 @3 a: u5 Z* V$ W| MCASP_TX_SYNCERROR
H3 K( ~# V' }) Y A3 E3 F$ @) C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ q Y1 f; g9 \# l! a: ^+ e| MCASP_RX_CLKFAIL
3 F) u* E9 v% O; \| MCASP_RX_SYNCERROR 5 O7 ?: N; j% ?5 x: V* I5 G2 o
| MCASP_RX_OVERRUN);8 U2 ~9 C: p) [
} static void I2SDataTxRxActivate(void)
1 m+ B. L. v' P) C; ]{
8 G( G. a$ C3 G5 D. Z) M/* Start the clocks */7 S+ `1 b1 ?; k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- _1 K$ M/ K! J: j3 L+ J4 r [4 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* ] r3 z& m9 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 ]3 w# h. [, I. p7 j* fEDMA3_TRIG_MODE_EVENT);
. a- i$ {, p. S( k' TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 S1 N+ U" [/ e9 T7 YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
F' w) h" f- l6 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 U0 n& I# _( @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 x' H' T2 s9 b; `8 t X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- k: a1 y- \) r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 g$ N2 U# R' z% Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* Y9 I/ ~; N6 [9 {7 B3 G
}
( i5 A0 u6 T% P% x, y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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