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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 C% H" t. ?4 @0 ?) r( C9 u$ V
input mcasp_ahclkx,
/ |4 u7 X' W* N2 h. e" tinput mcasp_aclkx,& a) z, ~/ t; \* O8 p5 \" k8 _
input axr0,
- P1 o( q: ~1 \7 b1 w7 G+ ?! U3 x+ W$ ~! P( U" A
output mcasp_afsr,
9 N. x& e2 |0 d2 Boutput mcasp_ahclkr,% v% A) C" W4 ~8 \' {( b
output mcasp_aclkr,
. v9 i% x9 s1 {/ r5 ^- C2 h$ [output axr1,
: v6 c; r) \3 l; e assign mcasp_afsr = mcasp_afsx;
4 A# [/ E+ i5 g" ^% Yassign mcasp_aclkr = mcasp_aclkx;* k) `2 Y& P+ V
assign mcasp_ahclkr = mcasp_ahclkx;
$ e; B3 m5 ]5 U q4 n4 |assign axr1 = axr0; " a* e. R# a6 |* q
) i2 n9 y, O9 @( R7 _0 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / J, ?) |0 `! o0 I6 q: X" a. W3 o
static void McASPI2SConfigure(void)" q% L" i+ ]; b
{
" `2 n; R* r2 t. yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, l) S+ d0 q' [+ H9 v% {$ U8 Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 U% X$ I" B/ B1 @7 [. DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ F- h4 E ?2 x' V( k' `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* z8 ?7 _ `" X% E2 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 E( k2 k. r- S0 N" }# s: uMCASP_RX_MODE_DMA);/ B+ W: M6 b( |- z0 v. [0 `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* t8 C n( r! J+ o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# X6 D# f9 J+ VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, B9 ~; _1 ^" u2 x2 X! J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! r# h# Y; I( h9 q/ e; v/ M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 k9 n; e1 [* `+ t3 \" R! \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% X( s/ y+ N7 F9 b. q, q7 J* OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 M6 z( z$ O' k+ w0 |- I( h0 Q4 ^: }0 Y/ e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; ]1 k3 s* z4 M+ E- |6 b) F9 S( fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 h, z, L( n2 W7 v3 `" P5 R: n; m5 ]
0x00, 0xFF); /* configure the clock for transmitter */
* J" l5 M8 a6 T0 w6 [& i$ @3 K4 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); W7 G0 l# Z- b$ C$ {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 U* B6 q5 ^2 c3 u9 H* w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; V- w5 m( J; u3 r9 j0x00, 0xFF);) D* \/ t% }7 \* H: x# P6 R
. r$ m* H# L$ L+ v) G- U1 p- J1 p
/* Enable synchronization of RX and TX sections */
+ C1 T1 ]( O v1 u( B: `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# N) F2 c" k3 B" P1 h" P: t$ Y8 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 W3 {8 T( c$ s7 S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
t6 z/ Q+ E- ~. d' B- b** Set the serializers, Currently only one serializer is set as
: {+ @* @. X- P** transmitter and one serializer as receiver.- A5 O* q4 j6 F" r" ], q9 z
*/8 C7 V/ ?& J3 j% K5 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. X+ ]& Z; y3 y% H$ E! E1 B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 E5 ~2 `$ ?7 O6 m% Z$ F** Configure the McASP pins
1 J2 B% O) m9 Z, @% _** Input - Frame Sync, Clock and Serializer Rx: m$ ~% u; ^7 ?6 o& E
** Output - Serializer Tx is connected to the input of the codec ( e$ f% S* i+ h- Q5 x3 l
*/
' I6 I( O. @' ]$ `: j& c# IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 t' ~6 s3 i: t' i) O+ D) z4 i3 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 ^% w1 D1 N5 E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 J3 e5 U/ [2 p. e
| MCASP_PIN_ACLKX
; V# u8 [6 n! H+ F4 v7 Q3 V T: P% o1 T| MCASP_PIN_AHCLKX' a6 D4 s1 l& O/ a5 Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- ?4 J2 T( H. {: P3 p# f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 `5 s1 N! {# ]7 \0 T2 X| MCASP_TX_CLKFAIL
+ [+ M9 W' t; R: C+ ]8 c# e/ N| MCASP_TX_SYNCERROR
$ H+ n5 L# _2 f6 b/ Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * N# H9 \& o: P& r
| MCASP_RX_CLKFAIL
# D. w: o8 ~- x) }| MCASP_RX_SYNCERROR a4 b/ H) q7 ?' k- r
| MCASP_RX_OVERRUN);3 ?% y- L5 j: A6 b. M8 L: @2 H
} static void I2SDataTxRxActivate(void)+ q2 g. N& L9 p3 m6 n
{8 y- T7 A8 K5 X2 @: Z
/* Start the clocks */
( O4 V% M/ i0 a5 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 C+ G; T9 ]; g/ t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 e6 e5 u, Y+ i/ b! `; t! _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ S' Q& f( w' d; L/ u7 A! M
EDMA3_TRIG_MODE_EVENT);
+ f6 b; T4 B9 d0 w' P: ^7 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 V V& E! W1 f. eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 u! k3 f7 \' }, T9 g9 ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; o) C, E! J0 ?! pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. b( n) U! U6 N* ^1 G5 S4 vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ U0 ^3 t+ m8 ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 I) T6 Y# I% H! J& \1 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 r6 r# ^/ O6 U7 H}
7 z. N( U1 E3 S" \3 u& ^" b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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