|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 m; c3 |# K% n' O; e, Y* H; m1 cinput mcasp_ahclkx,
3 f* r* q# o7 N" H5 Iinput mcasp_aclkx,
' I$ b/ l/ J9 w0 [ B. kinput axr0," B N2 b: Y8 O' [# L
+ q- U/ G. d; [3 O. P/ w9 Joutput mcasp_afsr,' y; }0 g1 `( \# K
output mcasp_ahclkr,
) N+ |8 s: v% W6 }; J5 Ooutput mcasp_aclkr,
$ W, F1 p# W+ f8 }9 U* ?1 E# ~output axr1,( {5 l# N+ I. w5 d' D! g/ g, h# Y
assign mcasp_afsr = mcasp_afsx;" q5 N2 ^9 g) J
assign mcasp_aclkr = mcasp_aclkx;9 h, l2 q) |: d6 \3 i- x2 V, W, w
assign mcasp_ahclkr = mcasp_ahclkx;
- w! @" A# }: @; _. k9 t3 nassign axr1 = axr0; ! R/ l! I! } P3 m
% ?; d, E0 I8 _6 A' P/ T3 m0 z4 U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 Z/ a1 a" {; h
static void McASPI2SConfigure(void)
, ]4 c$ w: U5 g/ k! |, v{
% G3 v# W6 j0 N; L7 T& QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 C% x* I8 A+ [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 p7 `2 p8 v$ \7 E" z2 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); D$ `( q2 P0 y: Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ g+ ?9 M" O- J" y! MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 n% Y* ]9 t0 b# ]" uMCASP_RX_MODE_DMA);
! r4 K$ x0 V1 J0 Y$ h/ MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 p9 C2 x2 u& Q hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: z" @% t% c. T; f4 ^' I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 ?, j' T' x( \9 M; y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 M. F1 G( k2 f: u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ z3 g' u/ i0 s* F; Z4 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 y% u& a0 v4 {7 |, Y( u1 ]% N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) R* N8 _/ k8 m- X* l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
V& ^6 ?4 R+ Z0 y" K9 tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ o; s; j4 w9 o& n0x00, 0xFF); /* configure the clock for transmitter */
7 a* X7 G% T4 OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- {( N$ P' V5 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 o4 C- V, S$ Z% T( CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) b: `, d- }/ h; T% u8 V
0x00, 0xFF);7 a9 S Q7 X" c1 S
- H) c2 u: D9 [- x* Z% D0 V7 \, N
/* Enable synchronization of RX and TX sections */ # N9 Y' u2 J& F4 k& V, ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! h2 `/ x/ }- g" ^( a. k% {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ _& g% d, d) b8 S; c3 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% i a0 j2 p$ v, u- t1 C. J** Set the serializers, Currently only one serializer is set as
% e; e0 `8 x, h! O! L8 P" r** transmitter and one serializer as receiver.
8 F6 _: g, B2 y+ z' s6 y*/
; @: U+ }# N. X/ W- v( N' OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. P1 a5 H. t: G) ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 [0 ]0 r& | F# A5 F ]. M** Configure the McASP pins
5 f+ K! E& T9 R3 D& R7 A** Input - Frame Sync, Clock and Serializer Rx7 D2 Z, p* o3 D- K' H- Y* O
** Output - Serializer Tx is connected to the input of the codec $ e3 y' \5 T# x q i
*/
% g( M6 d/ o/ z3 V! ~+ y$ f# B; OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" Q* E" v; t# p& B% f( e8 Y- iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' y/ J' v# s& P: v7 w L0 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; `3 F1 x) ^# U1 G| MCASP_PIN_ACLKX i2 S1 q- U1 { K
| MCASP_PIN_AHCLKX+ J9 I p$ q5 c9 B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, ?# o+ K# w/ v2 g; m7 i; U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* r$ R; l6 X6 O3 A$ O4 @& {3 w| MCASP_TX_CLKFAIL 6 f$ H- L3 ^8 n; H, b% l
| MCASP_TX_SYNCERROR
# `% P v O) d$ p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , A5 T0 y" i0 D4 j4 D3 w
| MCASP_RX_CLKFAIL! }( H& D3 v% g. Z+ `& V# J
| MCASP_RX_SYNCERROR
7 B9 w% s6 r3 o' N, K7 z; W4 H| MCASP_RX_OVERRUN);- v7 \( @$ w6 j
} static void I2SDataTxRxActivate(void)( B( O8 g# _4 Z" G) x" }3 l
{
. o7 S+ v) H% u; g* S/* Start the clocks */3 Q' y8 o4 W& p( Z0 ?7 [& T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: H" n; p& h" [6 ?% s; aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 b, l, `% I: A! y% D2 y r* I( cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
l6 Y/ F/ \ {' {! z3 ~/ J/ v8 g+ ~EDMA3_TRIG_MODE_EVENT);7 K5 B- D, w+ r3 T$ ]8 v. O. l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: j5 J. j) F- i& WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% A" _( n# ?( a/ f$ b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( `; N9 i# y/ {8 f+ l8 u% FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; y9 K# A4 T4 a2 u" [0 S: F$ k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 y9 r- E# c) HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ J9 W+ G- [+ o/ _9 |! g, v( Z1 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% F2 S" C: h6 H) ~# b
} & ?! C9 F- K x% U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
& K( r# F6 V4 L: Y$ C0 s |