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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, X2 N5 e9 \$ Y$ t4 pinput mcasp_ahclkx,
5 m" ?. p' a, `' u# }input mcasp_aclkx,6 H9 S; q! [0 A+ u3 {
input axr0,
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5 o% I% c0 ?5 g/ ]output mcasp_afsr,
3 s+ {. G: d1 Uoutput mcasp_ahclkr, W- J0 Z7 r3 A5 K" h
output mcasp_aclkr,
! ~; B) {1 v) n' Aoutput axr1,
% `8 s# P8 m! G assign mcasp_afsr = mcasp_afsx;/ u) j. a( { y" c4 S+ z. c+ Q
assign mcasp_aclkr = mcasp_aclkx;( f, Q9 y& n# s4 Y6 I+ ?
assign mcasp_ahclkr = mcasp_ahclkx; T4 S2 J2 G( ]7 t
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 f6 [$ T6 X2 b. Z# i2 _$ r5 a+ f0 `static void McASPI2SConfigure(void)
$ [( s( w4 I1 ~9 ~* f{
% h+ X$ k) c$ _7 TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, \: O% n: J: p" B9 S' |8 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- I; P$ g8 ?0 P- D' ?. t9 C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( g0 Y! k) C/ z6 z3 e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! I3 f+ l( ?" ~& q7 \" `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) A* ]0 u- g" n4 {' j4 Z
MCASP_RX_MODE_DMA);7 E" ]2 b+ D3 B; k- n2 u: C0 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 H' Z0 |5 m+ V& B4 [5 R1 m9 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 b! q5 E( @. P1 U' j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + G) J6 j& g% T- D [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 m- X& J# x0 z6 I( _1 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 P) w5 B/ d+ v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ `9 L* K* ?8 RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" x& h) P7 h# \+ i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 b" v; g8 h+ N& {6 T$ M3 p8 Z/ ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; t# x/ I- ~+ L% K( {; _! G
0x00, 0xFF); /* configure the clock for transmitter */* Q @ p" [$ _- A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 p9 g' u8 w$ ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 \& U! R% y& ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 h1 ~! t! m5 [3 v) T
0x00, 0xFF);& K- j1 ^. X3 O' W
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/* Enable synchronization of RX and TX sections */ 0 C* E3 m% C% Q, Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ ]# ^( A0 K6 _* q bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ ]- Z8 e2 }- E- _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 i4 D% e; J \
** Set the serializers, Currently only one serializer is set as
& ~$ b1 L) ~! j* f4 N: J9 |** transmitter and one serializer as receiver.
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' Y7 m5 Q3 K% z. BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) i) H9 J) j. `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 D1 g# J4 V r& t; e6 Z
** Configure the McASP pins # y5 i5 @+ v7 U/ p6 t) k
** Input - Frame Sync, Clock and Serializer Rx: I- Q' \5 ~% ^6 a; P- w# R$ W
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
j. b3 F: k# R8 q+ QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# ?) r( Z) x6 C; Q- b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 n( T! d/ c/ H( a) H/ X| MCASP_PIN_ACLKX
1 h9 @* z( D5 d) z/ R$ }' T5 N) U0 E| MCASP_PIN_AHCLKX
# U; e Z3 U, |/ f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; T C6 b& b7 W" }4 w; B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % n# r5 h% E* m* j
| MCASP_TX_CLKFAIL " M; C1 |- Q8 D: k- l2 m/ q
| MCASP_TX_SYNCERROR# A* z+ w5 Q& H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 |" r/ U" T1 S8 x5 X| MCASP_RX_CLKFAIL
" n) M7 _. g0 ^: M+ |) h| MCASP_RX_SYNCERROR
. c' a* g6 q1 Z! {| MCASP_RX_OVERRUN);
7 N2 n Y2 z: `' ], z+ z} static void I2SDataTxRxActivate(void)8 g1 k* K( {& F9 {" L
{
. G' @% D% ~( l/* Start the clocks */) a) z% G }- b, ^8 u6 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 ]5 U" P0 L% N1 }, aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( N" Q0 F1 }# T% m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 t* _# ~; T( f8 Q; s" l6 d
EDMA3_TRIG_MODE_EVENT);9 x5 P9 P- x. _4 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 m* w4 f* ?6 k& f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 p+ }, D6 d' n/ E3 p( z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. I6 D. ^6 g6 y/ v" a# E Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 Y% {( z0 q5 f% w( @" g+ W8 M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 }) A8 Q, N9 w5 B, X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* N$ n, I: B' S D, X& W; O! JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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8 J% J- W' d2 L2 U) m U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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