MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
6 G* W3 v# C" l$ \9 Ginput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
, {0 L8 e' b6 q! w) `& ]- w
" V1 D1 b; I  V. y9 m1 A( C3 Moutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
6 q; P) R; R. Z. E, _

assign mcasp_afsr = mcasp_afsx;
& `2 a8 _" }6 k9 hassign mcasp_aclkr = mcasp_aclkx;
  ~. J$ P- r4 e) n6 f- l, }& E8 sassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

7 z& ^0 r$ x# N6 O4 [9 e

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

9 h+ {$ Y" ~6 j# l

static void McASPI2SConfigure(void)
% C9 e( n+ g# u* ^' n; y. a% L{
  U$ S* O8 i0 M6 a$ ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# A9 u0 Q2 X* x0 l1 q. i" NMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
2 S0 e2 i/ b; t0 z  xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 T4 o! I% F2 u* D1 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
  S% }. d/ _) d" KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 f1 u8 s: S+ o- s, j, y, [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ r4 p" g  c! jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& K% A8 @* j3 e7 qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ z8 n" u  s& r% F5 I8 kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- j, A( ?5 D  N; r6 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

: {, o3 d3 w2 N* c/ q# V/ J5 m/* Enable synchronization of RX and TX sections */
% }. l* k  y6 H) T% y% |  LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 A- Y2 u/ e/ q& F$ j0 NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
- _% k" V3 t0 E+ w2 ]) m6 g** transmitter and one serializer as receiver.
" O  d. ~( X; `% `$ i+ ?# r4 u*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
7 B. X3 |+ g0 {** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
7 g1 J1 ?0 z3 {** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ Z& F2 y% Z/ Z( h- Z, }4 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: m- t# p: o% E| MCASP_PIN_ACLKX
* B' S9 z0 X6 X| MCASP_PIN_AHCLKX
; @* p4 d, |- u0 y| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 `- b9 s  W! K  g" t- i. u| MCASP_TX_CLKFAIL
$ T4 o8 [' g' q) G& J$ O3 j. {| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
. i" n6 e, t' x{
/* Start the clocks */
8 z4 J1 O6 v: U" m* |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
* A( w, v0 R/ T3 I5 _4 E- NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, y+ s4 N& V% HEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
5 G& ]' w6 q, k& r% {2 L* Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
& h+ N" I) J+ l1 U/ wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
  c( n6 L: H* w$ WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; _) `/ C, C9 L# j7 z}

+ ~' N9 \6 B3 r- W0 Q2 \8 H6 N( h

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.