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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 y* r- \, P" j" Q' Winput mcasp_ahclkx,
9 C$ D _6 X1 w( I6 Tinput mcasp_aclkx,# X2 O. b5 ^3 }/ `( o/ y. b8 v3 g
input axr0,- d9 L8 L$ z8 x4 I5 ]/ O6 n
) n) o) U% Z4 @
output mcasp_afsr,7 \' B u$ Q2 T/ J4 N3 I
output mcasp_ahclkr,3 ~7 n) G( A1 @; R
output mcasp_aclkr,
. A. e! E7 ^8 Ioutput axr1,! a! p* s h: c' U
assign mcasp_afsr = mcasp_afsx;
, |5 Y3 R4 @/ Z5 Vassign mcasp_aclkr = mcasp_aclkx;
, h7 E1 p% |0 @8 Y, Oassign mcasp_ahclkr = mcasp_ahclkx;
% G- n1 i! r; b; t% [9 ^- |$ passign axr1 = axr0; 8 g3 u: r' `1 m, f
; n# @2 _8 N) H) P: u' Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' T" M' |* q' R% Y7 }" tstatic void McASPI2SConfigure(void)
* ~; D5 e. j( v, Z{
- x4 x. U K# C; \ l) T% Q) WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- T! w6 `* J/ k" `" D- E; r6 o' x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 `2 w( M( s( h" X( O8 d1 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 U/ u8 F5 x" ^8 ]& MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 X: ?" l$ U7 D# ^. j1 u( K( L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ I; k2 W( k$ [; {MCASP_RX_MODE_DMA);
7 ? Y- `5 o3 F5 O0 x- J$ \( MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 m n& p2 J) I: Q7 L4 l- P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 B8 r5 k( o. z9 R- e, F' s" z0 D7 [' _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 G) }3 l+ }( \: U- {8 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ ]8 l0 L: \! M+ p) WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" ` f& ^" l+ q$ B* |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 M) T' N# B/ N. a( h; ?/ E5 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ v7 ]' J8 |3 H9 e+ W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & ~- [- x$ o- ]1 l+ r6 ^! v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 b3 t. k: I. p- X B9 q
0x00, 0xFF); /* configure the clock for transmitter */* c+ m/ p( ^+ N0 Q0 J5 r* y& u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ K6 E- i6 g7 k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ p/ |0 n" [, {; q& `+ \+ ^# A: OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 o2 t8 y: g5 \0 M0x00, 0xFF);
0 |; I8 u Q; A% j6 b0 C. t f1 h; l4 \
/* Enable synchronization of RX and TX sections */ " j5 m; O0 i9 q) f7 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 r7 h. L0 \+ k5 C0 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 s% V6 ~) o( U2 w' U6 G" f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
z& g' W7 v0 k+ A1 W. n** Set the serializers, Currently only one serializer is set as
* `$ v8 O) Y2 U5 r& k, v2 p** transmitter and one serializer as receiver.' f) @$ ~0 ~! K7 ?) X' {
*/! [ u5 {8 s" h0 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 f3 ?, ]$ t+ o8 b& fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 ?% j5 l1 j. L$ Y( h3 L** Configure the McASP pins
& T, A: F2 k/ ^& z, l& `, U** Input - Frame Sync, Clock and Serializer Rx
+ v# k4 {1 [) e/ l2 x% Z0 H& {4 ]7 T** Output - Serializer Tx is connected to the input of the codec 4 F9 k4 d" b) V. b
*/
7 T1 A( R' ^4 ~! k4 RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* |/ G( R/ Q6 [& `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ q" @: P, a6 d' J6 }1 ^# k( kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% Z' |* n' a1 c4 C6 C| MCASP_PIN_ACLKX
( C% A* ~ G% u/ T6 F' f| MCASP_PIN_AHCLKX
3 r! i6 T4 [* ?' n' s) A9 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! O: ?9 e7 B% v* ^% u2 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ `" G7 O, ^2 y) ~; N+ h| MCASP_TX_CLKFAIL - E( i$ j7 m& Y/ ?8 X5 C
| MCASP_TX_SYNCERROR4 l7 S. ?+ U, r6 `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ q: C s* B2 g7 e9 e9 X
| MCASP_RX_CLKFAIL
4 {" T' {. n9 n1 L9 F| MCASP_RX_SYNCERROR * D$ H+ l# I+ g) C
| MCASP_RX_OVERRUN);
0 L; b' | o4 o L} static void I2SDataTxRxActivate(void)
4 p2 L2 _3 P( T B" P8 k, ?{
" }* z7 j) s7 W( [" G/* Start the clocks *// d3 I6 t5 w: q. @. v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' D4 O& U3 b' d1 D; mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 ^- ]1 G# D8 D0 M! I! V p M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# A( d1 K" r+ K7 T; a f8 z
EDMA3_TRIG_MODE_EVENT);& ]. [* ?4 M/ }% T: @1 V% c# o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ w |' z. n6 q$ w% c# z3 qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* G( {. ]; w$ e2 F5 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 O1 ^, Q5 ^+ K" s, j% b. QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ y- O' |; C8 Q% Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 r. M4 s8 f* L* K; d$ u5 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; _9 f1 S5 b7 R" ?6 J, U9 n/ [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& O5 T: o/ w* p% E* T; I
} ! g: |8 W' e* N8 i5 Q0 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / i/ a* G: p9 c! B0 z
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