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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' p; \; b7 A' J/ C% ?; d5 Tinput mcasp_ahclkx,
# U" ^6 r2 g$ {. C$ x7 Y# \6 ^$ L: ]input mcasp_aclkx,/ Z0 p- b; l1 G. N: q: U
input axr0,
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$ P/ n- h4 b4 f* b4 ]output mcasp_afsr,, j/ z& F& x0 q* j5 g6 O7 Y" j
output mcasp_ahclkr,
$ y2 [1 B; v+ B4 M% w' G7 o. w( p9 Routput mcasp_aclkr,: b5 h, x" P* F
output axr1,9 o7 j4 P6 R! j, y' _" L! Z# j0 b
assign mcasp_afsr = mcasp_afsx;1 H; S) n7 _$ |# h" a0 x7 R0 o
assign mcasp_aclkr = mcasp_aclkx;
6 s: I w. I3 P' passign mcasp_ahclkr = mcasp_ahclkx;& U- N2 o8 z3 F; B5 @9 O
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: s" q3 j1 z( E2 z$ x# Dstatic void McASPI2SConfigure(void)
" Y, N+ F' ]. h4 I" \9 H; F{* A7 n! Y0 x5 m `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* w% G; F# u6 o- N/ t' U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 k: J. W& ~2 H; `) ~+ a/ Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ x6 f1 d! N/ U% b! `* c6 u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, z2 l% t% b5 {2 y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; V3 t& P5 ]! T# L
MCASP_RX_MODE_DMA);: A& [( V! N, m3 G q9 x& @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 w+ S u& g+ _3 _4 _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- ^' J9 s9 ]) C z QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 k- V/ F( N% D! h! Z) D7 b$ N/ \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ n+ Y8 ]1 |, f0 x3 B& I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) B% u0 V& o1 C4 T7 _& k0 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 _( S9 G5 g( m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 j+ N1 M) J8 r$ r. {, \: YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- w9 ~) f1 s p% T$ t% I% VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ w2 A& y3 {: F# |' ~
0x00, 0xFF); /* configure the clock for transmitter */! j4 c+ |" p9 C& ]3 c* G- i4 b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
n$ L$ o. @6 f+ L* B2 W( EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * v m7 G9 L; W5 R. l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- x1 E2 l p: a" X4 F+ j$ z
0x00, 0xFF);: T8 p4 _3 }& `1 w$ \: ~
9 g/ w+ A) C) O" [. R/* Enable synchronization of RX and TX sections */
/ u' [# \; }% TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ Q' P+ r& _* S; `1 z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
V4 J) `" t/ ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% f0 @' R5 l; f. Q
** Set the serializers, Currently only one serializer is set as
# \' `9 K' M% s# n# Z; n** transmitter and one serializer as receiver.: Z( T2 ]3 k, |( x4 A
*/
3 k. c: E1 L: _, J& E, y8 Z; T& IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' W$ p! R* `' ~$ V jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 Q' b1 R6 b0 T6 {& i) I** Configure the McASP pins
+ D% F& F3 K b! V% o# j$ O** Input - Frame Sync, Clock and Serializer Rx
/ R7 W/ x% R$ A# s$ O** Output - Serializer Tx is connected to the input of the codec
* V8 Z; |; i9 c" i*/9 D: }8 N0 N" @+ S: P" r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# ~ M* S4 J9 A, F O3 p( TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); T4 {' X+ H+ I G2 W! s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 m4 v7 {! p0 ~1 H| MCASP_PIN_ACLKX( _, U6 [" J; r9 C2 [; F5 e* B) K
| MCASP_PIN_AHCLKX7 T9 Y6 r+ G- Y- }' S: c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" J/ T* b8 S% o9 ?' m4 v" H! D6 h- sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 |; G2 }- J+ P! R0 o| MCASP_TX_CLKFAIL
4 _& b' Q1 }1 `2 |, v) T3 m! J| MCASP_TX_SYNCERROR( y# }5 @( a; V* K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% j' r" h! t/ k# V) b; U| MCASP_RX_CLKFAIL
6 Q* c% J& W8 h9 N# R- ^| MCASP_RX_SYNCERROR ; E' M# ~0 w7 I! Y% m9 W$ B
| MCASP_RX_OVERRUN);
; P- b: J( i* P* v; Y* L; }+ U} static void I2SDataTxRxActivate(void)
! p5 w$ c. h- C( z* A4 y{0 v' j/ ~# F% s! l" x, \4 ?
/* Start the clocks */5 j8 m$ ~: j: Q9 w) v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ a' F: N Z/ ?, M% h# X6 [5 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- m/ f+ M, |: z- a& S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ \. ]1 ?! r y, ]4 M( kEDMA3_TRIG_MODE_EVENT);: z O) f5 m% F! P0 ?9 s4 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 K' X& ^( y. s. V& w KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) B+ Z3 ^( F H2 g% r RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 [5 L7 c( r# x- SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& ?6 R+ T% z8 @: t/ B# rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 {, j8 @) F, ] J( R. L" D! t, O; |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! Y4 ^$ Z+ D# Z2 q5 K8 N! h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 {0 \; S' v) G. Q/ f5 {$ p* E
}
& g- W9 @5 Z) r! _3 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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