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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# a- g5 `* ?. ~# z3 d
input mcasp_ahclkx,; j' {5 t' Z0 ~0 {; ?
input mcasp_aclkx,
/ K& O+ x, X$ @input axr0,
; G2 z) V7 d! G) o, @" _: }2 b2 d1 T0 c, E( [2 }$ S+ r
output mcasp_afsr,' I1 L9 v2 I. j6 p* }# ]/ \
output mcasp_ahclkr,
4 } H1 u( a6 M" @output mcasp_aclkr,
( g) l, `7 y8 x3 aoutput axr1,
% C; t: E7 h9 w y3 m1 J assign mcasp_afsr = mcasp_afsx;9 ~; k3 q. C4 G* F Q
assign mcasp_aclkr = mcasp_aclkx;
- x. F6 J) M1 N1 T" i7 e+ massign mcasp_ahclkr = mcasp_ahclkx;. q6 E0 {) N# F7 K0 \
assign axr1 = axr0; * p/ v2 O0 F# z" G7 I- ^' U
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . u, P$ N9 t! k0 C5 Y+ x
static void McASPI2SConfigure(void)8 n" r! p0 |5 y+ w% L% Q* S" }2 D
{
1 i% r' F. P |* @! sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
L7 K# S! V4 H+ n1 O7 M: ]4 NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& q6 r2 M# Z* i5 A5 {' G( u3 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' o4 G, C& w7 V0 ?* `! u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" N1 `. j5 ?$ O: m1 k" rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 U+ L( _+ b' U
MCASP_RX_MODE_DMA);. r# A9 c3 V) q7 W9 v) Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& ^/ L* O+ Z4 _: w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 T% [# b& x: w* A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# | \0 s- R. ]$ G8 ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 m4 g- d! t, d2 @ w! YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 N/ G7 l/ o1 O7 A7 y4 `0 @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 t2 I: u9 c" t# Q2 T/ M8 h; n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 L& r8 L# P* U2 e9 B& H4 _8 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 {' c1 U( s3 |# jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 {5 t0 v- x. r" G% z9 S
0x00, 0xFF); /* configure the clock for transmitter */% X. R# P* ?' w& a9 L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; {8 O0 L, H" r7 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& V% O" Y" w: c+ q' m/ P5 k l4 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; s" m. N2 @% @) N/ e0x00, 0xFF);6 k$ H: E6 r+ `8 Y
. s7 {* O! d4 X+ `1 X/* Enable synchronization of RX and TX sections */
; r* i1 W( S3 L/ F! z3 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! u$ o* o8 D o# }, |; Z/ XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& d% A' @- n" A. E# a- Y I ~7 d$ lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 S" z/ \; a' i& T
** Set the serializers, Currently only one serializer is set as' T, J v6 v* }7 C+ O
** transmitter and one serializer as receiver.# J H! v, c6 u8 a" M
*/
- {! {- U2 t3 u3 K% J) ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* ~7 @- y9 p, r8 D; b3 tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ e% K+ b' O- B** Configure the McASP pins
6 C& V2 V0 w5 y) V# M2 }** Input - Frame Sync, Clock and Serializer Rx: F( r+ Q5 k6 k( a4 d( D
** Output - Serializer Tx is connected to the input of the codec
7 t. k$ ~, r& u) N*/
r4 ` p$ u/ N4 e" R5 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" I' M' \/ z: c! e! }# h% zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) o- ?" K( E8 A" b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ B& g* k# }6 r# F1 l
| MCASP_PIN_ACLKX
, E" q5 B3 T! n5 H5 x/ V1 H! T6 n| MCASP_PIN_AHCLKX
3 J$ Y) E% D$ ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! u' G3 V8 y V( B9 R8 Q0 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" r$ F1 ?+ I+ G" q& \| MCASP_TX_CLKFAIL 1 ^+ n/ Z8 L0 s% i3 B2 ?
| MCASP_TX_SYNCERROR2 R9 e4 C; G* ^' |; |+ y$ T9 X/ G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * y' Z) Q, Y$ v8 q+ g% X3 d2 J
| MCASP_RX_CLKFAIL
. @6 y. I" }# U1 n6 r| MCASP_RX_SYNCERROR
- ~: @! J$ _" z& } m| MCASP_RX_OVERRUN);
; y5 G- i$ S, r1 P' |} static void I2SDataTxRxActivate(void); k& U6 L- W& g! S/ p, j+ }( ~
{
& Z, p- `* `) P- L7 I/* Start the clocks */8 B; ]( ^, z( s% t% D2 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 y& \+ w5 J+ ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 a% J5 L# M' k( D; N; I5 {5 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) f6 n q) J/ A' S% Q
EDMA3_TRIG_MODE_EVENT);0 V4 G2 M2 Q) l- ^7 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ x f, ~/ E9 y. a4 @. k; kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 W; X; C& Y' H8 D* `# R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ W3 A- c" s/ f2 F4 ]" C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- m% n, D$ V5 L3 T: [2 _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ u0 u- ~) @: ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 R N5 r- M3 D9 V6 Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( s* a4 L5 m* j: O }" Y7 G} ) Z- @% K, X, \' ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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