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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 w+ `7 B! V8 _+ e& d+ ^7 ~! Q) finput mcasp_ahclkx,8 X0 p2 F( k: Y4 Y
input mcasp_aclkx,5 b) g# w+ [7 X& |* D- J
input axr0,0 ?, e4 L8 [0 p
+ z' t. E) [/ [0 T3 X* _output mcasp_afsr,8 c- \) c0 M" B% N# g
output mcasp_ahclkr,& O. V3 q; ~. O2 a: X8 k
output mcasp_aclkr,3 V0 s9 l7 X) L! r9 }0 Q, I
output axr1,; z# I) e5 _+ b
assign mcasp_afsr = mcasp_afsx;4 ]6 N$ R, p: u( @/ R, z% {) Y* x
assign mcasp_aclkr = mcasp_aclkx;
& p- l6 i7 y; O% _2 gassign mcasp_ahclkr = mcasp_ahclkx;! U! q5 `, `( O; T7 T
assign axr1 = axr0;
# i1 m S! K6 k2 Y p w' c" n7 X0 |% l* [2 q% X' O3 d6 _# K2 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' D8 a& M$ w+ m/ k3 ~( @+ P5 u
static void McASPI2SConfigure(void) _" r1 a8 `$ g4 p' j
{
8 D* r8 N) h( R: P$ R: W/ xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! v$ a2 E6 x9 z3 ?. n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* |3 `$ M j: i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 \1 ^: _2 b0 N8 f" nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 {4 d* _+ q9 }8 y" j* ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# P& k7 Q3 S5 F9 @
MCASP_RX_MODE_DMA);3 D& a- t1 ^4 e) e, u# U6 \6 h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) x: S E. G2 g2 e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- \6 P" l+ j/ { d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 v1 ^/ @7 ]- V; k- HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
[8 T7 p: r; I1 d- O! gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- U) z- P8 ^3 J' L* k3 q- rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 y8 l' f# U/ }& F/ ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# P1 L T1 @" C; A) l3 F! {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! A7 Z; }8 W# f% P8 M% s8 Z7 W' y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& w) F S( _7 \3 k5 r
0x00, 0xFF); /* configure the clock for transmitter */
8 K! `/ V7 t1 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: t+ |0 X% X& p' G8 o2 ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; Z, v, W# t. C/ R, \5 e- ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, e. ]% c9 D7 R! a$ i# N% {
0x00, 0xFF);9 ]& t7 N3 E4 R* ]- O0 z
! D$ G/ ]- O" l: _) v9 o1 x2 n* t* s
/* Enable synchronization of RX and TX sections */ 1 t; p5 ]9 R* F1 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 R: g! }3 b2 O0 x, j2 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# v# \/ D$ p/ L6 J0 I. Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; s- r5 b0 H% Y# Y9 z l** Set the serializers, Currently only one serializer is set as
( F5 F9 Z- L: M3 w( K9 P7 f; ?% l** transmitter and one serializer as receiver., Y% u* p+ m4 g5 }' @- c
*/
, d6 K, h6 P2 H6 S# K z2 D' m+ M* CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ e$ D5 O* A3 N7 e% A( kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% p' K# U- O4 v0 Z9 F% Z" m3 J& w
** Configure the McASP pins
8 V- B& _6 a- u2 R& `0 B) e! G2 w; Y! {** Input - Frame Sync, Clock and Serializer Rx' T0 b& Y5 P# y4 P# P( ^, Y0 |# l
** Output - Serializer Tx is connected to the input of the codec 7 B$ j2 r; t9 p" ^
*/2 H2 U/ w# D$ E, o" ]. ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 k* F" b, K2 n l8 R$ wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 Z3 x# x' p, E5 {4 c6 G2 p* s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 P. ^' A8 h. c" s
| MCASP_PIN_ACLKX
% h" k: e4 g, U# l# N| MCASP_PIN_AHCLKX' M8 ?) e0 M8 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; R' M" c* l0 y/ w% }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" [) D6 T6 n. N+ _% u: ~2 t| MCASP_TX_CLKFAIL
; {& J |7 S4 u. g$ J2 B5 B% J| MCASP_TX_SYNCERROR
3 g7 y; U4 a6 T$ e! g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - S: _, n+ [, x
| MCASP_RX_CLKFAIL
1 {' W( ^+ Z: C, e| MCASP_RX_SYNCERROR $ ^. `* I; G0 m8 [
| MCASP_RX_OVERRUN);1 ?5 h5 P$ s$ U; ?4 W+ {
} static void I2SDataTxRxActivate(void)
' j) M* v- A" R3 Q3 Y6 `! s4 ^$ F{5 U2 g0 R$ K; m5 I
/* Start the clocks */
5 X M5 F5 F, s9 Y. [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" h$ s5 m8 S- N% f [4 E. Z; x) @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; Q% ?6 p: f& o' n0 _ z+ k; b/ i6 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. R- ~" r' U; |; q: R
EDMA3_TRIG_MODE_EVENT); w" c$ _% N# M" g* W8 Q4 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 n& z6 \" t9 B- s: q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; [! R5 j0 B6 W1 U6 `( T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); z. o) Z. x+ ^4 W0 `+ y5 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 M2 ?9 o9 ^7 g& k9 D6 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 g1 c7 Y8 s: j5 X/ d6 ^ s% pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 [6 v; [& e, Q2 b. z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! S# h9 {9 f X; z3 v d
} 7 c) U# `% `5 j( F% V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* P' W& Z% q3 j* [( x |