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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ u* k3 w; o; x8 k, ]- v
input mcasp_ahclkx,) k" h" {; X7 q. g
input mcasp_aclkx,8 F% d8 `7 O3 v4 i4 D1 u
input axr0,
E3 ~' r: P3 N C" e! O
- F2 M) T; M; h$ Houtput mcasp_afsr,# [( E0 Q9 B2 p. j" S# Z; v5 Q
output mcasp_ahclkr,
5 S R! m/ T8 q/ moutput mcasp_aclkr,
! g: D: V8 |" goutput axr1,( e" G0 G# h& f( P4 L
assign mcasp_afsr = mcasp_afsx;( J9 k1 f6 E/ i* d6 T
assign mcasp_aclkr = mcasp_aclkx;- ]8 v, U3 H' @1 @2 N) p* {
assign mcasp_ahclkr = mcasp_ahclkx;) I" l; r* K% `, A2 s5 j
assign axr1 = axr0; 2 x1 _5 M, ^' z8 `
7 H. e; o1 v z7 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, v$ b, C* I) @; E0 J; h0 s3 n% Ystatic void McASPI2SConfigure(void)! _3 g) e7 v) D4 L
{
. D2 w' z1 q, Z6 oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 Y( f' }7 Y j9 S$ e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ ^, T, a/ l8 Z3 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 e/ ?1 f: ?" D OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 m% z( v2 `8 E! b% cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 S$ p' o- _" n7 j$ NMCASP_RX_MODE_DMA);5 C8 ^0 ]6 T5 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ @/ v# `- X* A& d2 N5 E7 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 K) C- V1 \5 t% Y+ z% D3 n4 n3 j3 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% `% f' A- n( u! C3 w7 c" FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" P2 W% j1 \5 ]% k1 X6 H$ W' G# KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 K/ n" q0 L+ J- v6 H, S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 q* n% Y, }) @% R; ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 r; P1 H' k f5 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 X& F# W& Z4 k" h7 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* O) v' a+ r/ y1 c8 E
0x00, 0xFF); /* configure the clock for transmitter */9 T% Y4 g8 ?9 z6 M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ |7 S; q7 H3 p: E& @2 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 i3 D& C5 I3 F9 F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& L: o# P# p/ N: q7 n5 H2 T
0x00, 0xFF);
. ]" p# _$ l# U W: k& {3 a4 J: R/ @( J! f# s6 {& s, N$ g
/* Enable synchronization of RX and TX sections */ 0 P0 D" [& h5 s" `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* u9 S4 Z2 e+ K# J" z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( J4 S" S0 _ |; o' Y9 @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 b6 _4 j; J% J: m& W( m- n
** Set the serializers, Currently only one serializer is set as, L7 ~0 T" l! j2 t% U5 j
** transmitter and one serializer as receiver.
# g3 v7 b7 Z! u*/
) u8 P$ Y n3 m0 J, MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 ^8 i, s- I8 J! [) D1 H Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" `, k9 U+ A1 k! R, o$ ]: A" Z
** Configure the McASP pins
2 f6 L( @. s" B2 {! |** Input - Frame Sync, Clock and Serializer Rx. m, M" W' n2 A& s/ W1 G
** Output - Serializer Tx is connected to the input of the codec & s, h& n# y$ e8 T/ a6 N/ Q
*/
7 ^2 n3 p- s: R9 `3 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ I/ z' U" W4 d/ ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" x' C, u# h0 j2 y. M5 k, B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' I$ k$ U! l& ]1 @2 _; r- |
| MCASP_PIN_ACLKX0 l( H' _9 Y2 d+ P! o+ v! f7 Z
| MCASP_PIN_AHCLKX
$ D# x9 `9 Z+ |9 n! r+ Y6 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 E: q5 W" G+ o2 w* t$ W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 n% j3 R. K; M% ]3 _8 E| MCASP_TX_CLKFAIL
+ t- @8 ?7 |3 Q- w* \( p& m| MCASP_TX_SYNCERROR
; [ J$ @8 X. [3 o! G/ D+ K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, r. V! X1 v! J L| MCASP_RX_CLKFAIL
" Z0 O- ]- f' T$ c! z| MCASP_RX_SYNCERROR
* B/ A' {0 `+ U9 U& V; N2 |! q1 T| MCASP_RX_OVERRUN);
& z, m2 _3 A7 h/ q. m} static void I2SDataTxRxActivate(void)- J6 i5 Y8 Q& w' |. l( k9 T
{6 V" E7 `( `/ ?: f& s4 B1 }
/* Start the clocks */ j ?& F" D) T6 ]* Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; K$ }: m+ l6 QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) D. |9 K( n0 D0 t0 Z; F6 b1 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) w1 f" o( d Y3 f& M
EDMA3_TRIG_MODE_EVENT);0 g7 [& D; B/ Y. r$ J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 C N [+ I( l9 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( Q( V; v) v: a4 qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 l5 o0 n+ J* i: K! w; G) ?/ ~: UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ t& B4 T; ]2 ]; T2 U8 @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# c+ {- g. t1 L; c( F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" G( S* { V3 `$ E8 \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& O& I; u( L/ G( |) K} / w( s. ?& r+ o# L m" h4 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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