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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 [( S! [6 H! [" P7 ~
input mcasp_ahclkx,
2 B" i Y- K1 n# v! ^: B2 Vinput mcasp_aclkx,' e# w" M: k8 o/ b
input axr0,1 d1 k, k+ `( L4 n9 ~; n1 Y* h
`, {! V/ m5 ^8 B/ c# ?6 L
output mcasp_afsr,
" m7 x( Q3 z1 I0 C w7 U+ m( S( Doutput mcasp_ahclkr,
% Q& h0 c! K0 H- w8 `' _7 U: E9 @output mcasp_aclkr,
* z% {3 x2 L; y& j9 Zoutput axr1,
5 v0 f9 w7 i0 W( v6 I7 U0 x% E2 } assign mcasp_afsr = mcasp_afsx;- o% H0 r1 |& K. T$ u: c" O
assign mcasp_aclkr = mcasp_aclkx;
- g# Y' Y# i7 } `assign mcasp_ahclkr = mcasp_ahclkx;
3 [( H$ F/ d" p5 l9 v' O7 Hassign axr1 = axr0; 7 u2 f c3 c$ b6 m. ^% e' \
) U6 K# a! \; r" @8 V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' ?3 k, b( ~* f; Astatic void McASPI2SConfigure(void)' ]& |/ |3 T; l3 L! k" c5 C' y/ o! ~
{
9 S1 F9 K! E3 e1 x% VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ F1 P! a6 n% VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 N& g8 O4 [2 x$ r# c: H; _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 ? c# ]. S* R; \6 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" j& ^* o3 p8 x* z+ i9 VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 y2 g$ k; ~! _9 p) i8 r
MCASP_RX_MODE_DMA);
( _9 |2 B" O+ i- [. m& ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" O- H+ g3 t' Y1 [% q; t ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" }$ ]" w& B) A5 t( l. u" x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 \$ U# `& I) p% ?8 a- w G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 W8 v- ?6 n$ x( \) @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. g. `& e7 x' X p$ ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, ~! L$ d3 w- G* a& s) R1 Q# J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
\- m0 K$ \, G: HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( O/ Z% X5 Q* c3 a( pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& l+ n; E0 [+ P5 P7 ` l1 }# I
0x00, 0xFF); /* configure the clock for transmitter */
0 a8 x& w2 ?8 {5 k' n) X5 OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); k4 i4 `, P: S% L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 z! Q7 i' c/ M+ r X) d8 C* s4 I: z" g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# ?' k- t/ t0 l% `2 s/ z* P1 W' p0x00, 0xFF);- h; f& K# T9 U5 S$ ^- t
: _: Q- ^: \- _8 s
/* Enable synchronization of RX and TX sections */ 0 K/ i& \* |( B" l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) O2 \( \/ E7 K& Z$ L$ X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: H% F. ~( x$ p" ?; ^" h- U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ O0 f/ i# [+ m& G8 ] d' G** Set the serializers, Currently only one serializer is set as
# H& U; O* `. O1 y** transmitter and one serializer as receiver.
& a6 A: {: f5 X*/! m8 I. ?5 C6 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& T' \4 q& F/ a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% b2 c, B( _0 e7 p! Q3 d** Configure the McASP pins $ L; O: v1 N+ k1 W3 o
** Input - Frame Sync, Clock and Serializer Rx
7 {& k, b. A" G: B& T7 r; ]0 P0 }** Output - Serializer Tx is connected to the input of the codec
7 V `: ]9 J/ p9 m9 U*/
; t. B" D( q+ p4 C# mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 r% _5 a: b- @2 m( C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, [/ z5 M& T) g! ?, t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 f& x' H, n5 q4 j. G. w6 J
| MCASP_PIN_ACLKX" q4 J3 C. W; B& h' s$ H, B
| MCASP_PIN_AHCLKX6 o3 z H) D: f+ c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 P9 ~) _! ?* h2 q1 ?* O' E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 r. f. [4 I6 ~& ~/ k8 K. p
| MCASP_TX_CLKFAIL 9 G2 u% }4 U4 ^ d# U, \
| MCASP_TX_SYNCERROR
; Z4 ~% n, U% ]& g1 s# n/ y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ ]8 R# L& R1 I" \3 \( X! S* w7 B- N| MCASP_RX_CLKFAIL4 T: T: s! P) F( j6 P4 A0 q
| MCASP_RX_SYNCERROR / `7 `& ]" H/ u t7 i, O
| MCASP_RX_OVERRUN);9 G. J" f, ^- J4 `2 `
} static void I2SDataTxRxActivate(void)
/ N. K/ C) ?4 s" [+ @1 y{+ `) H& X, ?6 i( f
/* Start the clocks */3 M* J, x( n' \0 W4 z6 T; s9 n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) ?, K2 o: q! N( U% WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; q9 ?0 d7 E9 v8 u7 J6 N& w; e" p. uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% y2 c2 X2 a. S) R/ ?- o3 c
EDMA3_TRIG_MODE_EVENT);0 ^: V6 g% {# N7 ^/ h0 ]* j/ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " G. u6 }& l3 J1 N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ b$ _" O+ ]8 p: d. c: h, z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# o, {& p- u, `2 _, }: eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 ~! N6 p* u8 P. E; \7 v* p! n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" R! V& D. I2 u. v5 V& l- m+ T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 Q8 J: ?# s) o0 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 \! R& U4 H2 s2 @# t+ p
}
+ e$ u/ k+ U/ z) L$ Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) [) @7 O. \7 q! v! D. ~
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