MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

3 u7 |" \8 v0 }9 [4 |output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
5 j$ n; F) K- U+ M; q# C9 Soutput axr1,

assign mcasp_afsr = mcasp_afsx;
- K2 ?. J8 [/ R6 H  [0 \assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

" c; {4 ~' O9 x" l
8 t/ Y3 t8 a7 _! e

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
' V+ f  Z, M8 C  R) X* cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; d6 l8 \' f& m$ E) i5 q& nMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
8 _: u0 U" C9 F% MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" c! Z* C; ~( A; S$ `8 V# {0 p2 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# B) F5 s! z+ ^2 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
  ~% e; z9 ~( t! p$ TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- N7 z4 b$ [4 ]: OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- {+ U) s4 g! X& M$ v" t+ SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* [- v+ n  ^8 J* }/ b0x00, 0xFF);

/* configure the clock for transmitter */
# U/ G  Y; w! u# C3 O( E& AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# E9 x* {' \4 U2 \6 O: R" b0x00, 0xFF);
, g( e% w& T% `7 Q: Q) ^  }
/* Enable synchronization of RX and TX sections */
* }0 z+ h0 R3 m2 _% ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
. D5 d9 J2 Q3 Y# M' ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
7 L" R; V5 L' F" C; n: K+ m** transmitter and one serializer as receiver.
9 M! u7 z: P6 B: l*/
, r7 ]5 H2 Y) s) F2 \; Q" ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 q: }' R/ a, k" qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
2 U4 y% |$ H# q6 v3 I/ c- d** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
) l% U7 U4 V6 K/ i9 ^$ O*/
" Y9 M& M) u& M. @# b# u8 z0 XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" O+ }: t2 ]) ~; Z2 O0 J8 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
* a8 O( o. C2 s3 Q4 u- |) X: f| MCASP_PIN_AHCLKX
: n& Z, A+ r% r8 S' y| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
" s5 k2 {+ N) |0 o# J5 @1 N6 x| MCASP_RX_SYNCERROR
! ]6 }* ^) |. d  k$ R9 s| MCASP_RX_OVERRUN);
, _8 d% g0 t" Y9 V4 k}

static void I2SDataTxRxActivate(void)
- x/ o6 C1 k) p( h, y{
! C: a% [* c, A5 ~) M) F; L/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
4 A  r" h" I' Z) }" GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 P1 L7 J5 u: nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 r0 ?- `6 _2 D  }/ zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; L' p5 `) }( a! y, K: K5 I# _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) t9 U2 B- n3 S9 b, |}

0 h+ s+ w$ L1 x6 r4 t8 F7 q. @

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.