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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' v F8 v1 ]1 }# L! F: l# C+ j
input mcasp_ahclkx,
" R/ s# P* S1 z/ F; |8 B$ \input mcasp_aclkx,% p: L3 S* P, u! \% {. i6 L% J
input axr0,
8 U9 g( t) C D/ t3 I+ ?
) G, ^: ~& A% E+ Z) V' ` moutput mcasp_afsr,
* m1 e$ T i, T1 m" |5 Eoutput mcasp_ahclkr,, l1 d h+ q$ r4 ^ N
output mcasp_aclkr,
: j% k( `( U8 Q9 C; n8 ^output axr1,
( H; p) _6 X& o assign mcasp_afsr = mcasp_afsx;
+ }# O5 d! g% ]" n5 tassign mcasp_aclkr = mcasp_aclkx;
( ?/ p, E# T9 f: X6 ^' N4 jassign mcasp_ahclkr = mcasp_ahclkx;
1 s$ b& T- z0 D3 ^assign axr1 = axr0; ; P, s J+ H0 v" X6 E
* s* M3 H& U( h0 [* i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 b" I: v% Z2 {1 a7 Ustatic void McASPI2SConfigure(void)! l) K/ y0 u! ]: h7 m1 o: C
{
: p5 N0 w3 N7 uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 L7 R! q( P2 t; E# X/ ]7 F3 [0 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 f3 @4 ~1 y0 ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. _8 I4 [$ q8 A' P \3 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 @3 z' M& h: [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% V" \& |8 V2 m) H8 j8 z' D
MCASP_RX_MODE_DMA);
: p: {* e/ m7 n7 ^4 ^ GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 Q$ @! r4 m$ O! l4 V3 z- qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ M0 a6 ]' a2 O9 NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( o0 o d' D* z) E* [" ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); O( ^4 j5 x3 ~" |& {6 C( C" d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" v. ?0 e% r& ^: R& D6 d8 n7 u" d/ v% cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' A2 [8 N* P- y0 z: |/ ]$ E ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; B' [( W8 [& ]% I- D+ [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ Z. p M) H6 x/ v% ~- oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# @! z" j5 ]5 w( }/ o# n
0x00, 0xFF); /* configure the clock for transmitter */+ _* @ ~6 G5 f8 ?2 c4 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, k: P0 x5 G t' {1 I, K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( M# X4 i: d; u; d) G. t! j# X% R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( I. B: g6 p# a2 A( ^
0x00, 0xFF);
, u; v. L9 L7 C- E
' n( [+ d, B( v& s8 W. a- E/ y/* Enable synchronization of RX and TX sections */ ) W' {, \5 J$ E" e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- [2 W7 Y! X+ H. y* }9 }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, E0 y# _5 ]2 l- ]+ X3 W+ DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 d! S& z) N5 `2 G @2 u; Q- A** Set the serializers, Currently only one serializer is set as* s, q' H' z* v. @* \0 _( o
** transmitter and one serializer as receiver.
8 f5 w7 \- S3 G2 U; _*/* x. }7 W+ {% h: w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 j! {. `( S+ k, E1 O* {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" ^& T D& I6 g# r** Configure the McASP pins
* ]& c$ b- Q H$ I** Input - Frame Sync, Clock and Serializer Rx
* x: N, c b+ p* K3 W. j7 I3 u** Output - Serializer Tx is connected to the input of the codec / X/ S7 m& I5 w5 V
*/8 ?0 v( e& `& v- D# x( w" t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 J" ?# a7 ]: t0 u* l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* v+ Z3 [' F. p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 R' e) }, H0 n' a, F
| MCASP_PIN_ACLKX3 v2 `' X. ?" u e: A
| MCASP_PIN_AHCLKX
( k* B9 d. y2 L# f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" j' u# j) i; Y- n. W& oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) f& ~8 E# @, E7 K( |& F& E| MCASP_TX_CLKFAIL
9 [/ b9 h8 j; h9 H( S| MCASP_TX_SYNCERROR8 |0 A- @' P# I2 d3 k, w7 r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . G3 R9 [0 S: y/ j
| MCASP_RX_CLKFAIL0 D/ m9 d, A9 }
| MCASP_RX_SYNCERROR 1 w2 p3 r/ n5 D6 Y, v
| MCASP_RX_OVERRUN);
* f* e: y3 S& O* j0 y. f7 H5 V} static void I2SDataTxRxActivate(void)( j% M* x' [$ Q, M( \# {& C
{
$ }' g$ w: l& R7 T; z6 N3 Y3 I/* Start the clocks */
3 V" m9 I1 p; i- ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" k/ L2 Q* D$ o+ y5 @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& H k' Y" m i; o. q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 H' M- P3 M) F
EDMA3_TRIG_MODE_EVENT);6 P. b0 q6 E. I& U7 {6 F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 U6 w( L& B( CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 T7 _& E" }% j {( z: y: J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& Z3 A% n# O' F) g9 X% X0 v* V# HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 `7 g3 h' T- J I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 ~9 \) a; J& g5 H |7 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! p$ @. L$ u# p5 A2 z! o0 e- T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% _9 b8 ~ L8 y |+ T}
- s" O3 p P% J: _* W6 r1 ]# u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 U/ h1 P4 k5 k. {
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