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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 T, l3 S- K8 ?0 Z$ w1 L
input mcasp_ahclkx,( I( {/ V {* m0 s# I
input mcasp_aclkx,9 B l' N! b8 s9 t# R0 `4 M% H/ o
input axr0,/ C" u: E- G( w
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output mcasp_afsr,/ e* Q* }5 F( J. X) D" o! q6 t1 }
output mcasp_ahclkr,7 P) @, S7 T9 h4 V
output mcasp_aclkr,
0 X4 r* L8 |: X8 Y7 xoutput axr1,) i5 V0 {; o/ l) i" R
assign mcasp_afsr = mcasp_afsx;1 H# y1 {# a' V) \: T6 Y' F" @
assign mcasp_aclkr = mcasp_aclkx;
" l2 y' b2 Z+ P9 M5 k. {6 I7 Lassign mcasp_ahclkr = mcasp_ahclkx;
) I$ i$ K5 M6 ?: n1 u! Q0 Aassign axr1 = axr0; 3 F! x; d: u4 L' I4 o$ ^/ u
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- v1 y, y9 I8 Cstatic void McASPI2SConfigure(void)
; z( B: L2 M. S) u4 g0 G# w{* W7 u3 S/ q& n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 j" Z) E7 S+ R2 T" _9 M6 j. L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- Y% X# N% A/ }6 A# sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- N1 L/ e( c' `5 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. q8 h5 B' O1 ?0 q7 Q% H- bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 ~3 d; M! i' h! e4 x
MCASP_RX_MODE_DMA);3 ?9 E& d, U9 U: w& I) ~$ \# G0 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# w! b, {0 I. E5 ]' a1 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 w7 @. H. K% vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + t7 s1 }' b# K: K: O1 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 d6 q- s* _/ @# X/ E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / q. W9 V2 m5 h/ `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% F% m/ ], `! ]- P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 D: f. Z: X" ^2 T0 W7 HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 H4 t4 M7 a; i* D& O3 d1 \8 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 E( ?, K3 v' j* z
0x00, 0xFF); /* configure the clock for transmitter */
( q. \0 y/ f# h) IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& C* w( q( `+ l( w2 m# o& o+ }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + G+ ?1 n- ]( m i6 K G1 C5 _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 O8 z" D* o. D& J4 ?0 G
0x00, 0xFF);+ C% z5 M7 K; q4 Q; o5 i% R' S# E
6 }9 U$ |2 T; o! d/* Enable synchronization of RX and TX sections */
9 i9 T% |) ? d( U3 N' M5 A; jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- H. l) Z3 q( B) r# P8 f0 C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- |2 c$ [ k) a$ [5 k/ e5 m! n2 X5 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, f2 \% n2 Q* ^0 J* b
** Set the serializers, Currently only one serializer is set as3 } W2 v' _, ~2 Q/ e! b1 r
** transmitter and one serializer as receiver.4 m3 D+ C* j2 O- V2 ]; [
*/
) |$ Y& `2 Z, QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ Z N3 \4 \/ e: Y$ b/ P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ s2 Q$ T# m0 Y' _! L6 z** Configure the McASP pins
* z! e& U- N( ^& [$ Y** Input - Frame Sync, Clock and Serializer Rx& ~3 `1 z% i! C# g" @! ]- q& E
** Output - Serializer Tx is connected to the input of the codec
' v! f8 Z+ o+ L$ |. B6 f& c*/
, n: {1 j5 u, ^5 n! r- oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; c0 D7 N, y& l& D2 w. B# N8 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 L$ Q, N$ M& c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX Z& H% D5 B, O- I' }" n" v2 ~, ]
| MCASP_PIN_ACLKX
5 \0 P+ p1 M) s7 J- a| MCASP_PIN_AHCLKX3 f9 B% h4 T- U2 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ F9 F* m1 Q6 e6 i2 Q: lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) M) G, s" ]# \1 ~: m$ |- I7 j& t
| MCASP_TX_CLKFAIL
3 r' b5 t5 H3 b7 t: [7 y| MCASP_TX_SYNCERROR
' j2 \* C/ o( Z6 x2 B( c& s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 ^9 R1 C G3 m$ Z1 S
| MCASP_RX_CLKFAIL
0 P3 M5 `2 d8 }& h3 t- I/ S| MCASP_RX_SYNCERROR
4 ~: @$ j2 g6 n- t. P| MCASP_RX_OVERRUN);* S( u. R0 a# R+ D. A
} static void I2SDataTxRxActivate(void)
) m5 x/ h3 Y* s- g6 Z' D( g{: o2 U, m& n4 [- }
/* Start the clocks */
6 v5 ~' m7 [! T2 m7 W* HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 d- Z7 d/ z/ L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' t* j. w5 m% J( s) i9 M; W0 M) j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
H. g. i+ g: R7 W$ H. o" w/ i1 `" ~9 [EDMA3_TRIG_MODE_EVENT);
K. z4 a; ~+ eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 U2 e1 i) g) L2 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 ]& T9 f+ \+ y$ Z8 O5 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 a5 e2 m6 _2 [2 {* KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) @' q) Q+ F8 [' u& A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ P1 x$ a! y7 A* Z* X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) g) n$ `( |4 V& \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, V f% W" l9 U% `) T3 t
}
' ~) c) O; }; a# d u, l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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