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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- E# ^/ o9 Q7 l8 `- W
input mcasp_ahclkx,! N; D: }6 @; |: L
input mcasp_aclkx,
; }" c) N2 b6 I2 y" j, P& K; A. |6 O0 kinput axr0,
8 h5 l6 k! a1 e$ i1 g$ W- g- ] C5 x M0 s, C/ p9 [
output mcasp_afsr,
- _6 X( y' t9 L, c! ]output mcasp_ahclkr," @: j" E& e/ ?8 [
output mcasp_aclkr,$ O; J; ?+ h$ d d1 j9 \ q* \
output axr1,
4 Y; I# N' |- U1 W assign mcasp_afsr = mcasp_afsx;
6 r+ ~6 p7 s% n6 A* ^0 hassign mcasp_aclkr = mcasp_aclkx;
* ^6 U m4 A x9 b' \: G% `. ?0 vassign mcasp_ahclkr = mcasp_ahclkx;
- Y/ }$ g; W! p6 w- ?7 Gassign axr1 = axr0; 2 W2 G d( Z, Q' I) i8 B
1 E9 m; A" R) _. S% T1 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ W+ z! I) S& v4 U: U
static void McASPI2SConfigure(void)1 ]; [' y5 k3 l. ]" u0 L# Z: C
{! M$ }1 U4 o: q: `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! x1 \; [1 C6 t5 C3 M) P, QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" c+ w) b8 ]7 @- oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" N7 _! ~8 D' D) G8 `# j u* {4 AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# q& {" Z/ ]# X5 c4 ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; |1 O% V( `" b2 H- _) G1 bMCASP_RX_MODE_DMA);
+ \2 i# G0 T4 h% l: S# Z+ V5 G8 B1 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' ~1 o( z# }7 V5 k8 k/ c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 v4 K; ]( S" ]. }8 M4 F3 l1 V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' W f {/ e% G/ J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 T! w/ E6 q" T+ ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 m7 g" R: H5 i) n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. I% M! f0 y8 R* S& g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ U' b+ @4 x" J8 w O8 u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' b" q1 b* r9 s. B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 O4 j7 X0 k0 G$ {# |
0x00, 0xFF); /* configure the clock for transmitter */
, y* U- F d& e4 U& X2 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, y3 ^7 |! d1 n* \; s7 t ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! L9 _- r1 I( n g$ sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 R- v! O5 Z. {1 T2 c, m
0x00, 0xFF);! n# R' b9 b% e, p8 C
( A+ R: j; z2 @3 e
/* Enable synchronization of RX and TX sections */
4 I- Q5 @3 B) M5 JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# v. I: G5 m, R: _ P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, I( ^! U ]3 e( {: U9 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 a$ i) ]% X7 G) i$ k
** Set the serializers, Currently only one serializer is set as$ B/ [7 Q4 R" {/ q) u
** transmitter and one serializer as receiver.+ a5 H% y: _% w
*/
$ o' S ~' `0 z; h. QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- |# c3 @$ E/ q9 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, F. y @, u/ ~# Z/ B8 D" Y** Configure the McASP pins n7 l" ?( r# |4 W/ F
** Input - Frame Sync, Clock and Serializer Rx/ w" l5 G6 l+ g5 X' F- w
** Output - Serializer Tx is connected to the input of the codec 3 C* ^ V1 L2 o1 ]$ B& K; S$ n
*/
0 R" @) p u* ?' `5 ^) gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 a; b3 B3 E4 m2 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); ?8 T' o$ \: t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, f: D/ j- T% _: k7 Z
| MCASP_PIN_ACLKX4 h3 }: Y0 V8 L5 p3 v
| MCASP_PIN_AHCLKX
1 `6 t' |( q; u4 D! c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 ~5 g) Z5 x0 P7 X2 e/ P. @& _7 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : c/ Y4 k+ O4 t# z3 U
| MCASP_TX_CLKFAIL 6 }* N5 Y' F. [" Y. Y# R$ v
| MCASP_TX_SYNCERROR& s" \0 V1 m' E4 a, o2 S, Y1 }* q& k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' b/ M2 L5 l" ]% a' ]( v- ]& J
| MCASP_RX_CLKFAIL
9 S6 _, R8 y, `' J# ~| MCASP_RX_SYNCERROR & T4 `5 W; q3 r/ j1 y/ X! o3 o
| MCASP_RX_OVERRUN);
3 h9 v- u" x9 [) p6 F0 R} static void I2SDataTxRxActivate(void)( w% B& R% m. Y3 ^% b
{+ W! @- T, Y/ M
/* Start the clocks */; i9 N# W4 p& ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 e0 F9 D( d. ?- Y4 bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ [# n) p% r6 ^" @2 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 y# R" C$ {4 A) WEDMA3_TRIG_MODE_EVENT);
4 @) p3 Q5 b7 f; I- p+ y2 |% hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 S/ z( j' v5 E, |$ g9 x( |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: t0 p# b# B" X" {- S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% Y7 K3 G7 J/ y1 o0 j7 W, V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% Z4 T% P, F: d, b: A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 D& [, Y; o" m2 }2 h2 gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 ]7 Q/ ?0 M( F. L7 A1 X$ ^6 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- h# u1 _8 U: R1 z2 z d9 Z B
}
3 Y6 H/ d3 x. B# q8 l1 J K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( J! K2 ^& H" J# M2 ^
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