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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 o% p. e$ U6 ~) P# W2 A
input mcasp_ahclkx,
, [& N* f$ C6 N+ R0 s# L" Iinput mcasp_aclkx,& @7 a* B! n" j$ c* v" g
input axr0,1 |$ Z0 e% w V; C
6 s( @; l! N' H! Y6 ^5 t. b+ Poutput mcasp_afsr,9 C% Z; u! b. _) ~5 b6 c
output mcasp_ahclkr,) h4 Y4 j7 [9 u1 [2 G6 t) T1 I) {
output mcasp_aclkr,3 o5 q, L2 y W8 c
output axr1,
% \" Q. Z: m8 J$ ?" r- O: R) i assign mcasp_afsr = mcasp_afsx;
* G' ^! @; R! p2 f% x' _' sassign mcasp_aclkr = mcasp_aclkx;
4 T$ `& M" H' O- _* r5 V6 p* Cassign mcasp_ahclkr = mcasp_ahclkx;/ H9 v% d: ], x6 y2 X& r: x
assign axr1 = axr0;
8 w" \0 \5 L) r- C+ f0 h. a& {% w0 _! `1 f. ]8 a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 q) O( x1 W9 w' Y8 G
static void McASPI2SConfigure(void)' Z/ @# N6 w( i! p2 v: h
{
% \9 ^0 s" c1 \1 S3 K" hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* Q3 y, b2 @5 v6 O. R8 U( F4 D( Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 _7 G k& r7 g- i" D* h4 j7 ~; w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% I1 W- E, C$ q5 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) x! m0 i$ S0 |, o8 z$ Q: R* @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# q, E4 f r c1 Z' v8 _MCASP_RX_MODE_DMA);
" B) M( n5 N) t) c" k( T$ l' s+ {; @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' n) N$ P0 _/ G3 b- k' B' |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 j5 S1 f( I$ ^: UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + X- \! ~; |! B) R4 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 F/ u. N+ G/ \4 q7 n, h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! A+ E/ X1 _: k$ W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. e J" `, A: VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 a. c" }/ [7 A" o+ O0 @9 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + A9 [' N$ V! T I9 }/ \9 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ |% V) Q: c% J l
0x00, 0xFF); /* configure the clock for transmitter */
# @4 V+ f5 Q3 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ d- A" L! m1 w$ G9 t) XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) |- h8 d+ O$ f( w; |7 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 ]5 r/ r% m O( c d" N6 V: q
0x00, 0xFF); n# X( b5 K' y- l. L
% S% ^8 z$ K( r3 M1 H' S; q/ R% L/* Enable synchronization of RX and TX sections */ ( O$ A; u1 [8 I. T _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* ^& T0 a- \% N% ?0 C1 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# f; l: _" W! I0 K$ I1 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& G: O2 u7 Y2 |" ]1 G
** Set the serializers, Currently only one serializer is set as2 _* H3 d7 P/ H% E
** transmitter and one serializer as receiver.1 z2 Y" A7 n& K6 d: ^
*/
4 Q- Q. B: v+ a6 M. b2 ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. j' P" {: f- y' c- o5 h6 X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ }* i! U5 h3 o4 B! r8 [3 P; b** Configure the McASP pins * J: H7 m" m% E, c! H
** Input - Frame Sync, Clock and Serializer Rx
" c" d# w) M9 R& ~7 W9 P** Output - Serializer Tx is connected to the input of the codec
I( \7 X: M5 G; @: n% p7 m*/
4 h* u2 V" \$ I2 S# L0 @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' ~# K; v$ G6 `6 \. {5 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; i7 Q. ~) z2 P! K& o u) AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
[$ Z) p9 {! W: Q6 z6 j| MCASP_PIN_ACLKX6 P. j3 ]! j0 h4 p
| MCASP_PIN_AHCLKX
5 S; G+ r0 A/ T$ c( {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* D; T- V) H8 ^8 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % S, q8 K+ y4 G" ?& n8 f
| MCASP_TX_CLKFAIL
3 m- {6 v) T: M| MCASP_TX_SYNCERROR6 ^, `( ?' u+ q( e- ]4 R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; ]0 W! e7 @) ]/ ]6 R| MCASP_RX_CLKFAIL
3 W+ M% C* ]/ t3 I3 T| MCASP_RX_SYNCERROR
' n- M7 k% r+ c4 x- R A9 M4 G0 Z| MCASP_RX_OVERRUN);* t8 H' }3 W ~8 s6 T( P
} static void I2SDataTxRxActivate(void)2 z* {; O+ u, U+ w" e1 P7 x
{+ H5 v: |/ J& t3 y$ |) R+ m
/* Start the clocks */4 J& l, e, L8 @" ^: H' U9 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 [- H$ t( J' _- ~# A( e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 Z: C9 q+ D& N: h0 k9 W$ A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) _2 Q* {0 k0 ~0 ^2 s/ l
EDMA3_TRIG_MODE_EVENT);
5 |4 [* n# Y7 \7 N9 B$ rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# c; Y; w& N2 Y8 K% d nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# w6 M5 C" |! {" {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 z4 h6 o" |4 q, ~8 X) lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' b: N7 }" z2 F: b3 Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' \! U. F; V* L$ Z8 J1 b! vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, y3 O6 X9 Z# V( [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, i2 O8 E; m ]( F3 j
} # e7 R" d, ?& J+ `# |3 n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 S" S8 ?, {- `. r/ C% \$ q2 A
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