|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 I3 z+ ]! n; g3 xinput mcasp_ahclkx,0 [$ @& n9 X" f& r' z3 m7 b
input mcasp_aclkx,& i' v+ B8 C5 _/ [
input axr0,- M, o* G Q: U+ ~* X# k$ C0 J
, X4 t7 C' z) J0 E, k
output mcasp_afsr,
0 Y ^" {; S+ A8 @- Houtput mcasp_ahclkr,
) D! O/ G( A* W- w. [! e# u% Loutput mcasp_aclkr,5 ]8 y4 U s+ h2 c. ^. I, ^
output axr1,
& Z/ L; c3 o6 H" }. N- V assign mcasp_afsr = mcasp_afsx;
7 R; W. Z8 E: o* x' t; k/ E$ H6 uassign mcasp_aclkr = mcasp_aclkx;
) u9 f, p3 H7 zassign mcasp_ahclkr = mcasp_ahclkx;* T; y: Y. ~: J; s* r- F4 q
assign axr1 = axr0; * _0 |/ K( Q. A" Z* P$ l: V
9 R' F9 }& ]/ N0 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 Y) K! J8 ?, L7 v3 lstatic void McASPI2SConfigure(void), Z ~* D2 [7 z; [6 [% Q O
{
; u* [1 C4 ~6 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
p# J: L% g9 }% m l# bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& m1 ]) \( K( U' G! q3 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 b" ]4 d4 R! HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 j# A! h) J$ G4 |6 F9 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 l, z; c, E$ ^- s7 j) k1 }; K
MCASP_RX_MODE_DMA);4 y# E% _% n8 I( N- J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 Q b2 ? r b) PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 h7 T" H; e. Z7 `; I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " N7 ~: Q: }: u" e; f# n$ y5 A/ _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: d0 o* a8 w% P! tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . i* p3 h( g: ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' [8 A: Y3 M) U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 l/ p2 b/ y/ E. W) g3 C* p$ R+ ?' u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + b" m- h& `# W+ C; j$ o/ v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 F: C/ A5 F" b
0x00, 0xFF); /* configure the clock for transmitter */
1 Q/ r; U2 ~3 [2 `: Z) g. nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& X. x' O" |! S7 U$ oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! i; V# Q. A: H/ n) r' O9 jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* w( P7 |1 q' |9 a1 O, [0x00, 0xFF);+ R4 x# F2 ^* V4 Z
" T" D8 D0 S3 ?4 L w* p
/* Enable synchronization of RX and TX sections */
d/ }; q6 |8 ]/ DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- x. M4 r1 z# n5 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 \5 p* A; I4 ^' [# Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! H( t" A0 U5 J) c* c8 o$ o- c** Set the serializers, Currently only one serializer is set as6 @/ l; O4 ~, ?/ V: J; ~$ O
** transmitter and one serializer as receiver.
( @% a+ G3 L8 P*/: h) \/ `( m8 Z7 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; v- K3 L. p! i0 C1 j" \! H. zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 Q# e3 F5 z" q. A8 l3 B% G** Configure the McASP pins 2 ~) P# u P' |4 } T9 `
** Input - Frame Sync, Clock and Serializer Rx( x/ j) M: ?2 P* N# @
** Output - Serializer Tx is connected to the input of the codec " |, ?; A5 c1 e1 ~6 ]) ?/ u
*/
+ ?" d$ C' {/ ~& x2 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# R I+ W1 M, a9 ^, b4 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* V8 A0 E7 Z' n+ w7 w _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX P# N1 q2 x: ?0 }0 z! y! c$ j
| MCASP_PIN_ACLKX
1 n- W0 Q. ^, N/ W+ C| MCASP_PIN_AHCLKX* A: Q1 O6 Y% ]" W r- t2 C e3 P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) s, H1 B0 y4 \3 C# LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% {* T( |# K& M) s6 e7 W" m| MCASP_TX_CLKFAIL 3 m$ E! h9 F! Z+ W h/ Y
| MCASP_TX_SYNCERROR
3 L5 W+ @ b& L/ C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / s! v9 q* S# f7 G+ x5 b- E2 C
| MCASP_RX_CLKFAIL
5 j6 \! W8 c. z% ]" E| MCASP_RX_SYNCERROR 5 |6 W, R0 ?$ N4 A
| MCASP_RX_OVERRUN);
* w! n0 a; r. W3 \# R} static void I2SDataTxRxActivate(void)
; T% X2 b) [% p9 c$ `, D{8 ~0 k- I; Z+ s2 ?: w* I, ?6 b
/* Start the clocks */
0 r7 ]: o# ]! mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ C/ X" N6 a) j6 M# u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! B: C4 W0 L& S- x" Z2 k) c) B" REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% L6 m7 c/ d4 H8 WEDMA3_TRIG_MODE_EVENT);
1 y( R" Y! f1 H% MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; U+ ]3 R6 B" j4 L4 f, g; b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 b- e' H4 w6 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- R# o9 T F5 Z6 xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 g' P% r5 W1 t7 y0 h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& n2 E2 L3 @+ x; q7 A+ @; J3 u% @' h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* ]* ]" p& N- }3 r- P+ OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' c3 i' t& I5 a: n& q0 g
} 6 t! f, L: \$ ?$ O5 ]4 r( p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; v, l V; Q3 y' u
|