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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 g0 `; h$ |* w3 G6 `3 dinput mcasp_ahclkx," |1 R' e. U/ E! T2 [) N
input mcasp_aclkx,5 O( R1 |4 F5 p; J, K3 C4 P
input axr0,
8 r/ h0 g- ?. ?! A: p. Q
$ L8 s: ]8 }( g1 i. j' G l Eoutput mcasp_afsr,
& b7 B* U' W$ Y" d% \output mcasp_ahclkr,# I7 @' o& Y4 m- x2 F- K/ D
output mcasp_aclkr,
+ F7 f$ J2 E9 Joutput axr1,( c; x7 M( e& g% P! u& m
assign mcasp_afsr = mcasp_afsx;8 ~. g# i# L6 }% v; B8 \
assign mcasp_aclkr = mcasp_aclkx;% Q: {" z h/ F4 ]& @
assign mcasp_ahclkr = mcasp_ahclkx;
7 Y/ u/ U+ Y/ J( O! j% I3 e. Cassign axr1 = axr0;
* P' @# r: G+ T- [; {' o; \9 \3 \& a$ B1 q3 q% P% O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " R# L/ k+ v8 p6 R" ^7 z: G) ~
static void McASPI2SConfigure(void)
) G' H: _& m+ ]) |+ q, J# X{
n/ Y% r/ a2 K5 ~. _# D9 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 E$ u+ O; t B! K4 ~$ fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) D: l5 w2 A* s, C y$ QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# n- x5 T/ j1 _/ y3 ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 J$ M* v- N1 I' o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 e5 g: l" ~( [+ J \9 g9 w
MCASP_RX_MODE_DMA); B4 c9 ^1 _; q1 u- ^, m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 e( k2 B T+ Z Z; z0 J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 Y" ~8 {" O6 J8 b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 ?' I2 I/ ]0 b1 _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. @5 r9 U& a, o" X D, m- G! eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! f- q0 R' `5 O2 { }: S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 q3 X4 o9 c! o: y. ^% A$ s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 S: h1 o+ ~! x: s6 [( [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * X+ d3 t- w$ I" Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ m4 @$ H3 i3 c4 [
0x00, 0xFF); /* configure the clock for transmitter */
8 m/ p8 {6 z- z8 nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 h" L0 n! S( u/ F' ~* A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& [% r8 P- O7 S) O3 V+ ]! {+ pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," {0 e8 s+ [/ M
0x00, 0xFF);
# E7 L! ^6 a Y( \2 D
* m! ^! H9 [" v% @/* Enable synchronization of RX and TX sections */
5 t8 Q2 _3 H* j* a5 C( iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 k; m9 g R# P1 V4 k: [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' [6 k+ `/ ?$ n7 Y( \; eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# s S* Z1 j1 R# H4 r
** Set the serializers, Currently only one serializer is set as
- b0 m/ v+ c- o' J3 e** transmitter and one serializer as receiver./ }- X, q/ `3 {5 r
*/. m: J9 d$ q2 I, t! M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& Q4 K- {1 y5 K' u* QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( Q5 C# [. g+ q7 q$ o/ D( [% M {** Configure the McASP pins
8 m- q+ n( f! E/ n1 ~: T** Input - Frame Sync, Clock and Serializer Rx( d2 |. Z% _' Y8 S4 M5 {- A5 C
** Output - Serializer Tx is connected to the input of the codec
6 _, d" b, ]; i: S- f$ T5 t, n*/
! v( d2 u5 s) n8 g, O* R# O5 s' ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 A* ?" e( e3 }+ X" H$ M: j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( ?6 m- \9 T, J4 ^1 a6 x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
H. H7 P- U" w# B| MCASP_PIN_ACLKX
# {; |+ U% ~& Y: t+ U, X+ g) D. D& V| MCASP_PIN_AHCLKX) H1 W7 h) x M0 I5 \, I. E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 Z7 y2 A3 N) [: _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 D: j$ E! V8 A# A: U| MCASP_TX_CLKFAIL 6 S7 W3 l, r2 w/ m3 L" i$ n
| MCASP_TX_SYNCERROR. }% [! o5 Q) d; @, k; n* m3 z0 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 f/ U9 J; X% y7 |: D/ ^4 w
| MCASP_RX_CLKFAIL
6 W5 B1 w& a, B6 ~| MCASP_RX_SYNCERROR
. x& I8 g( R. \1 @) ^. O| MCASP_RX_OVERRUN);7 V7 N, D E, D* w
} static void I2SDataTxRxActivate(void)
3 e, b& s4 O6 K: V' I/ h0 f{
# X2 C$ Z- M7 |/* Start the clocks */+ t( z% I/ m# R* h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 J/ P9 D9 J g/ Y4 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 G& E$ ^: W! M9 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" _0 I0 r) `) B8 p7 E6 ~EDMA3_TRIG_MODE_EVENT);; k/ T7 B5 j6 B# ?) Z1 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: P& y& t R2 V/ P! l0 f, aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 g4 k: y6 Z" I) }7 a( D E' r# ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 \% \2 A3 a- K4 K' ]+ X6 M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ H" s6 C @# B Z @5 Q2 B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) l1 S3 R: k7 M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( R! V7 c* ?3 `: X, J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 F L* R( W7 t6 o6 m2 h; y: n! c
}
1 p1 R# h p0 h% t! T! |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + v% J5 N- ^8 z3 C7 `
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