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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) S2 `4 M f5 k( I5 u" Y3 finput mcasp_ahclkx,6 |; x, Z" O9 c1 X% Q/ h) \: G7 l' L/ p
input mcasp_aclkx,
; H0 s& R) Z1 U5 _. ?5 ~$ hinput axr0,, E/ e9 o1 m9 N: R3 n7 e
: q/ l& e6 b! j/ I/ t2 uoutput mcasp_afsr,
) Q& v; X4 D7 F" i9 ~) foutput mcasp_ahclkr,; P# x2 u- m+ S4 H( P# ^- ~( [! Y# {
output mcasp_aclkr, T8 U- i5 ?4 S# \8 ~
output axr1,1 ^) ^* m. ]* s- S1 R) B
assign mcasp_afsr = mcasp_afsx;! j" C- v' {! i/ J( E$ H8 G5 j* N
assign mcasp_aclkr = mcasp_aclkx;
/ |9 P2 Z$ m0 H0 ~3 C/ E) tassign mcasp_ahclkr = mcasp_ahclkx;9 d8 v' m" u4 i/ r1 _
assign axr1 = axr0; / E- e; {1 {6 [) K u1 k
- U4 l+ M, d5 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 X9 d6 {# [+ \* kstatic void McASPI2SConfigure(void)
( W) _; e( f8 f. \: A( c2 A# Q{3 @3 m6 ?0 D! L, ^: Q, Q9 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' h# w2 |) a5 K: b/ V9 ^& C+ E! eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 e4 z! A4 Z9 _6 q- j" w0 E( K" @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) m6 W. \* C: g( v+ k) {% i! ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 j' T0 [- d: \) E5 j! t" sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) l, v( J- i# ?$ R# XMCASP_RX_MODE_DMA);
# ~+ B# b& t% y7 s, z- u4 c+ Y7 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 R% k( T. {, m% m0 P0 C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 n2 _/ O& l& P" mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 D) P7 [9 @5 m- H1 ^$ \7 `: ~9 M8 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 w$ G2 O5 J7 h4 u' `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) \# v8 f5 H8 ~% D! i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) G5 z Z& e" v9 ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ y0 }* U7 z2 h- w7 L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 H- v5 I# i' qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ L; E7 v; T: M& A ]! K" q! h8 e) `0x00, 0xFF); /* configure the clock for transmitter */
" P; Q |: x$ P- uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 g5 ?: ?. Q0 T% |/ UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 B* c/ @. d7 e5 k4 n/ V0 z+ QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 l' w" r+ R9 j4 P( f' N+ c- W K0x00, 0xFF);* Q) r6 G2 e; h3 s
) H& _- T6 s; m8 d& j0 Y/ ^, }
/* Enable synchronization of RX and TX sections */
l0 i0 Y* \% ^% t' G" XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% Q9 G' U5 o* p6 m7 s" vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* g, ]& t$ Y1 x9 ?6 b) ?7 S6 L ^) ^% ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# {0 j4 Q5 Y' {9 C' H- A/ }" X
** Set the serializers, Currently only one serializer is set as) j; h( P. _& ?5 t/ k1 ^
** transmitter and one serializer as receiver.
$ _# f+ m9 y9 r) a*/9 M' c# \& A6 {- [' _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* x4 W N- N9 c) |8 T9 C5 h! RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( S% z2 ~# _7 V3 w4 j/ x! I1 }
** Configure the McASP pins
0 v& V* C* G: j+ T; \** Input - Frame Sync, Clock and Serializer Rx
* d: S* h. {- p" W** Output - Serializer Tx is connected to the input of the codec
" D, M- m! y1 K D5 R1 j `: M! H*/1 I" [' C( _, X4 p* n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 u# R" @! N! W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, c3 c& _" M" |& N" XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 h- Q2 o- U+ x4 q7 B6 t7 C| MCASP_PIN_ACLKX
8 u0 y$ ^) x' x& x/ y( c( j| MCASP_PIN_AHCLKX- _" J' B* O) r9 d4 S1 a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 F8 n: \) X9 j: L/ l8 {* `, VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# M+ m8 r# i1 \0 B| MCASP_TX_CLKFAIL
* \2 ~( S& l `| MCASP_TX_SYNCERROR% }: p# A/ L6 y) m0 r4 n+ s( W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 n7 N. ?3 k F' z" b| MCASP_RX_CLKFAIL$ m) V! _; k& T9 B. L+ Y# t9 Z' Y& d; V
| MCASP_RX_SYNCERROR % O0 l# }- g# g/ ~* E
| MCASP_RX_OVERRUN);
& {3 F9 y' b7 Z; {' T' }( u0 n} static void I2SDataTxRxActivate(void)
! X( x# L$ K3 A$ @% O# a{
8 N+ A" N5 P8 U. D+ @7 d/* Start the clocks */
- g V8 w; w* `9 ]( T. NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: ^( |& K( m- m7 P/ e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 R/ [: h0 g. m0 m9 r0 c; u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, G2 G3 ~# F0 a
EDMA3_TRIG_MODE_EVENT);' I( D4 ]; T/ ]5 Q$ g0 J" X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . }# G7 n: Q# y' v6 X# W7 t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) J' n6 i( {8 x/ M: ]' X3 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 ]2 u" s5 Z5 c2 m s2 T5 s/ P) i- |3 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% H! r/ C1 e- H0 M* o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! X1 S7 r1 i$ I" \6 U" zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* Z' A3 w7 V# K3 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" M$ j# o* h0 F2 g0 i}
; D7 `* _( a& e0 R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " G; a$ O( u5 a- t x& B9 p
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