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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ c \% E" Y5 n9 I( R
input mcasp_ahclkx,
; I" I1 b& V1 a) ?5 Tinput mcasp_aclkx,! ^! z- ^( L$ r f4 W
input axr0,5 B0 G# f$ z8 x& x6 o
4 Q0 _5 F9 T: P6 O! j; noutput mcasp_afsr,( }, s; U8 c5 Q3 X! V- r
output mcasp_ahclkr," ^: y1 Y+ e- f' \$ y! A
output mcasp_aclkr,
' n1 k! l6 \+ R) Eoutput axr1,& P% e& \* ~4 W* } m0 A
assign mcasp_afsr = mcasp_afsx;2 _; ^$ e k% i# O: O& o- U
assign mcasp_aclkr = mcasp_aclkx;( U( J' n w9 N
assign mcasp_ahclkr = mcasp_ahclkx;/ n8 J- z* O7 E; ~% [& l m7 p
assign axr1 = axr0; 7 ]& u, o, g; C( w5 \ ]
3 m2 }6 ] ?& R0 }9 x$ m3 D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - w' I0 [" l4 a1 g, Z. F( y8 f
static void McASPI2SConfigure(void)% D2 w9 M, _+ {9 p7 b- e& z0 k. f
{
. D2 o- D+ H7 |McASPRxReset(SOC_MCASP_0_CTRL_REGS);& R3 T2 X5 d9 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 C" @1 w6 O* h, I7 t# _. K$ |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" W2 S6 v9 V" l! ?$ |0 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& M$ @2 S, y5 X1 w% f) cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ i' t4 z& t9 k, @4 i6 ^! fMCASP_RX_MODE_DMA);
( c1 d) N/ ?$ ?1 m7 |, u0 J" {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ ]% {% a; M4 M! S: V qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! z* Q7 u. a1 ]1 q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + ~' M5 N: f( q3 ]" A5 @$ F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 u9 C2 H) ?, x" v2 r4 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 `7 N+ w0 A) r1 ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- _. d) J* g' l( v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. O% a+ T- s6 B/ E, x! s H, xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) m" O9 W6 e2 p+ c* S$ c! m4 eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 V2 l9 A! \! q3 G, Q
0x00, 0xFF); /* configure the clock for transmitter */+ p. u" z9 Q0 W; n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* [9 ]: L* t9 S$ K& j/ h) R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 @! H5 [6 y) D0 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 Q# Y/ ?3 h& X6 C9 w0 E# t/ S
0x00, 0xFF);
$ u* S8 Q! f% V% v- d" f& k$ P4 O3 y8 g% e" B1 ^$ X
/* Enable synchronization of RX and TX sections */ 5 ~- K- {6 U4 |/ V* [0 m$ p. A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) ?$ T; w- y C9 l- n# gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 A6 d7 m3 J8 Z# E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" t L" i+ u2 U6 i** Set the serializers, Currently only one serializer is set as
: r0 x7 P+ H( n& d2 r* D# _** transmitter and one serializer as receiver.8 R7 V- L+ k& R, [# j& p
*/
; D* J, A: @0 ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: F$ p7 A2 ~ d% e) eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 M! n: G1 s- d( E% |6 F, x5 ^) p+ P
** Configure the McASP pins 4 K0 ~6 Y) V7 x' u* d8 Z
** Input - Frame Sync, Clock and Serializer Rx; |9 _6 u& H- L
** Output - Serializer Tx is connected to the input of the codec
7 h8 c$ I6 V. V*/
2 J5 d4 B' i) C& D4 |- d: NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
Q7 ^$ M+ I3 F8 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 r- s, P0 }% t& C) @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 o: E$ B f/ G0 N E
| MCASP_PIN_ACLKX
2 h5 p% a+ c2 c/ `# ~& V: w| MCASP_PIN_AHCLKX2 a' q. R9 g$ n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, {" P7 e$ O! F" D( xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 B: L% s7 W; U. F+ U* j| MCASP_TX_CLKFAIL
* ^1 G& b1 N! o- B| MCASP_TX_SYNCERROR
' d, g: ^% I. L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 M6 J) |& S7 d4 C" g
| MCASP_RX_CLKFAIL$ c) j; B3 G) N3 g( @7 n. |3 L
| MCASP_RX_SYNCERROR
+ Z: N4 M" N# @) v( M+ v7 o3 G) A' }| MCASP_RX_OVERRUN);
. t, E2 N* D. s) w' U, _} static void I2SDataTxRxActivate(void), ]0 H' b" Q! T# V- u! N
{
5 m; ]2 {' w1 G7 }# e* i2 O% S6 Q/* Start the clocks */. v6 X# }) j3 r( h8 ]9 [, M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, m2 P4 f$ V! Q3 d' @! X& WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- |8 m5 Q. |0 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 ?( ^. c9 ?- q* U! l% ? _% R2 REDMA3_TRIG_MODE_EVENT);
1 r7 k- k2 z' e, s; ^% LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , T% T0 x! Z2 Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: G7 @; K, f4 ]$ w8 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- d+ a! E/ T! H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& d( X% v0 v# X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; B, R: M6 X5 N+ ~- HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' j" b. S. O& L4 ~) @3 c V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 O) w/ ~7 T: |# M1 P& N7 O& D4 X} / l9 Y; L; H! V4 |- |- r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 x' B9 S; i1 s/ a
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