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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 O* K1 r+ j8 e( H& w2 j' F! ~
input mcasp_ahclkx,
8 ]$ |1 S' d; ]3 f0 E" H D0 hinput mcasp_aclkx,
/ `3 T& f1 V" Q( d9 ainput axr0,. f+ T) w& k: H, D( [0 g& f
0 E; ]' _$ u" @6 f Poutput mcasp_afsr,1 Q$ X* A, H; M6 `1 g3 d# f
output mcasp_ahclkr,. c" H/ g6 H( r6 }/ k
output mcasp_aclkr,
; U- W. h* w$ r; N: q4 soutput axr1,
9 S+ Z! R' g- l0 ~* f5 I% X assign mcasp_afsr = mcasp_afsx;& i8 g4 g* Z& h( B, Z' z- F+ c( q
assign mcasp_aclkr = mcasp_aclkx;
- h0 |7 \6 v8 l! R W; U$ rassign mcasp_ahclkr = mcasp_ahclkx;
' ?. f- k, q7 j( u" gassign axr1 = axr0; 5 n7 C% N) n* M5 u* ]6 l% {1 E
$ M- x* a6 n9 o* a. ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 x9 `+ ^& |2 e. m# a
static void McASPI2SConfigure(void)
, K; S( O- s- p: F9 G( I, o( X{4 |. n+ F8 K% V4 p0 w1 Y& {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) F% _! \) N6 p7 b& r3 ~. X4 B+ R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 w3 b0 t3 e9 g" h' `/ f* L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; L! f$ n8 B! M, @% r5 ` B8 u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ e; j }* `0 X F6 `' X: m# v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! w% m. z6 _! T! [7 q# f& L% l& q
MCASP_RX_MODE_DMA);6 \1 g& C) F7 j1 a8 u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
R4 y! _0 f, g5 H( x: y% J( k2 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( Z7 L/ L* J' [: G# F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( V& V/ M( ?% P/ f( V! g3 ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* {7 |7 y& Y6 s5 T" M: @7 XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - x q4 Z$ t# J3 ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; D I, q8 t! t2 D6 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 I- E1 r1 m* A( pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 z! n3 H- Z0 r! z2 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% I, i$ k' a7 x0x00, 0xFF); /* configure the clock for transmitter */
* s" F* [' m' WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* ~/ i% `! \ N( _7 M6 nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 s& G3 k) ~8 m" M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* }# d+ G7 K) |! ?. M* ~0x00, 0xFF);
- o5 A% _$ |% _
2 a# a0 s; @8 k% u. Y+ I/* Enable synchronization of RX and TX sections */ / S" V8 ~7 b* n) J7 p$ S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 q& E- N7 ]) J2 J0 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& e, {+ [0 L+ D& _/ {1 G2 GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 q! _9 u0 H! R( z. p6 q1 {
** Set the serializers, Currently only one serializer is set as
5 d& Q1 e+ j, f# e, Z5 r( I+ y** transmitter and one serializer as receiver.
9 }- A4 i% b& M: C8 l4 t4 l+ Z& p*/
8 O: v: {% p" {% qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: E# S7 }# x3 _ I0 D$ {& i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 P; S+ c6 N' ?1 z; S# K* ~# v
** Configure the McASP pins
4 c- l# j, ]5 s+ @** Input - Frame Sync, Clock and Serializer Rx
0 J, M4 }1 F) H; |! G** Output - Serializer Tx is connected to the input of the codec
+ X2 j- e* S A* G6 j; h/ t* l*/
6 n5 p( W# W, S/ \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" [2 ` x7 P% ]4 v$ p' N, z9 M5 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! i. ?/ k$ u; T; ^1 n, N( E8 |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 z' f& _ R9 \9 R
| MCASP_PIN_ACLKX
2 ?3 D' i% X$ y7 F. @5 v4 w| MCASP_PIN_AHCLKX" V* M: m g3 b& \* w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
W) @ Y+ N, K- Q% c$ ]4 D. yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 [8 x; S, P2 S* y0 A8 W
| MCASP_TX_CLKFAIL
0 J l6 K2 g& h( B; z: d| MCASP_TX_SYNCERROR
3 V1 Y( V: Q6 ?* ?( P/ Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + r' F2 n; G% ^" S; u
| MCASP_RX_CLKFAIL9 N+ G) K. i7 E9 D m" _3 C
| MCASP_RX_SYNCERROR
1 G$ W- t7 u( g! ~| MCASP_RX_OVERRUN);
) T) F" `$ _) s3 K g8 \} static void I2SDataTxRxActivate(void)1 F0 R( G# A* [; v0 O0 _
{% L5 H+ B! r s$ {" d2 F8 T9 o
/* Start the clocks */
/ m% o, q6 I& z$ o, `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 S6 e/ O9 E. `* y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 B/ F) ^2 p: w! e/ Q1 _9 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! d) X. e! ?2 j* e( aEDMA3_TRIG_MODE_EVENT);
8 S {/ f% X* }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 U: M+ ~/ r5 C: X' zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; [! A) D" ]9 ] ~% S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 O. \# t8 L5 V |3 F0 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' f. L9 H$ t% T: i9 x* l8 E- t( Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( J1 B+ K) \/ r8 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. z: _( h1 U, \9 e; U }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
W4 E) L( y4 z5 P8 c! {! l. _$ ^; y}
9 v" p& t5 o% i. h, c( e0 _$ L6 i8 x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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