|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* Q0 m+ a/ [5 b" |$ U- ~1 O
input mcasp_ahclkx,
% s/ S$ ?# b$ v3 K5 {% d6 e6 Tinput mcasp_aclkx,
0 S+ D6 M" R$ Y4 Q8 `) V" ninput axr0,
* G5 F& d3 ` `) \ [
" F* _* S& t- A( {" c. o3 l( foutput mcasp_afsr,' Y2 [( A0 ~* ^
output mcasp_ahclkr,
! F- K. u$ @" o, { F' G5 V4 boutput mcasp_aclkr,: x5 v8 ^4 Y: e/ C# i
output axr1,
$ g: J3 m/ `8 n; s assign mcasp_afsr = mcasp_afsx;0 W' u1 }" f9 }. q
assign mcasp_aclkr = mcasp_aclkx;
% W. u0 J/ R0 H! U9 ?assign mcasp_ahclkr = mcasp_ahclkx;
( R8 B4 Q6 |) P, u9 E1 qassign axr1 = axr0;
/ O) G" P, E }2 O, l# M. M" p, h; g* {5 @, [( ]/ q' x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. g; G+ `4 t! r+ o) C9 jstatic void McASPI2SConfigure(void)
# o/ J! @% V+ e \3 j% S, X{% E+ J! Q+ Y$ `# L% G8 }! l( f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 {$ D5 i8 m0 H' r8 ?% j2 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- B0 l, H! a8 `' d t; AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 G$ G- s$ y( Z* zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* E$ b) A, P6 Z% J& p% P/ o3 ^& DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 y5 y7 s! _& Z4 S/ [1 Q$ Y* Z$ D. B+ OMCASP_RX_MODE_DMA);# l7 B/ q: a# d9 N6 s1 j% {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 n5 F& w* w+ `# H% S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 i7 D" A2 i; j9 }0 {8 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& d+ {" u, C& A! W8 I' p' GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& L ?1 c- Q! C- E- eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ j9 i) h8 H9 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// W9 Y: i* C3 @/ _% x/ W) h0 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); J: N4 d" p' H3 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 o# k& G& e! n; K3 R9 _0 S5 g7 t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; l( v. Y6 ?: ]/ N: r0x00, 0xFF); /* configure the clock for transmitter */
# Q2 c8 o- q/ q( v8 L8 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- ?4 E) k+ z8 OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% M) j4 e; k8 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 J/ B% |% c* M8 Q7 w1 l8 P( z* M0x00, 0xFF);
7 ~' V9 H$ s C# [
' d7 [+ U/ u( q, X" y, Z( b- M/* Enable synchronization of RX and TX sections */ 5 K" M! h7 v4 }$ }. m# t4 N& Y# D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ Q/ \# r' l& T5 p% lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 [. v) R% \0 W$ G5 s. o- Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 Q: B$ g8 ^3 ]. q% ]' t** Set the serializers, Currently only one serializer is set as
; I' c/ V( ?6 V% J! Q* M& i** transmitter and one serializer as receiver.
) h# A+ }* D" \; [. S# F6 K*/0 p v0 d. o" A$ j. w# U2 u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# g' F0 y: L& Z9 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' T# z( O( Z% }* w: l e D: y** Configure the McASP pins 7 c1 ^1 L* E$ u
** Input - Frame Sync, Clock and Serializer Rx* L* @6 F2 _, d0 v5 r
** Output - Serializer Tx is connected to the input of the codec
* x5 X. A+ p$ s* j# K*/
! s9 G9 R7 A8 @- L1 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- T2 [8 X5 z. I5 L6 W& M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ Z& w' s5 L3 xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. b8 u9 r8 ^8 ]9 Y8 }7 j7 x| MCASP_PIN_ACLKX* {+ [# H! I5 @; E
| MCASP_PIN_AHCLKX. A: a! m1 j* i( X3 C$ \! r& v/ }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 W, P$ J/ M0 W0 e# wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ M n7 H/ t% ^) V, `+ [( i| MCASP_TX_CLKFAIL
8 n! {8 \- _# n| MCASP_TX_SYNCERROR* c. ^( y% }" U4 H& M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' ]& ?, [# j! l [& n, G
| MCASP_RX_CLKFAIL
7 u6 W/ a" _5 s G% U5 n" Y| MCASP_RX_SYNCERROR * h; C0 l) z0 X6 U0 J
| MCASP_RX_OVERRUN);" a3 I" V9 R2 a& W8 |: b
} static void I2SDataTxRxActivate(void)9 E1 }/ O$ g; O( Q/ U
{
! o0 P' p+ v p/* Start the clocks */5 }8 v" x6 ~6 [! }' }" `8 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( n5 H2 E% {: M# \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, \5 M5 T7 W/ r6 e: ~' ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! Y3 E! [* W6 }0 gEDMA3_TRIG_MODE_EVENT);
2 M3 `( W; }! S% fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 y2 y# O4 d! b: JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 E6 ?, N' ]0 m$ x! D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
a0 _7 w' {& I5 }+ [6 R) L- j+ gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ Y. a% c2 p8 B8 x5 ` L, Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 o9 o' A- K2 C/ {- E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! [ Q, V% m. x! W+ U4 p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% x- f$ n2 q0 s2 l& _: u: P
}
9 t3 v1 F' U% `8 \& B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
/ b y' a c# ^' n8 u |