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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 ^0 w; U0 P" s6 G \0 i. Xinput mcasp_ahclkx,
9 O* A; t, {! Y2 x& R( ginput mcasp_aclkx,
+ c7 U4 z0 {6 ninput axr0,! z8 k5 O/ \. i B6 _4 H
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output mcasp_afsr,, G% s4 u) d: c2 [2 J
output mcasp_ahclkr,: p. Z. H9 E* D! t; K
output mcasp_aclkr,
# A/ B- K5 L1 f# ?output axr1,; x" F: T" `* h7 y; a+ u; }
assign mcasp_afsr = mcasp_afsx;! h& O! M. B) R. Q. S9 G
assign mcasp_aclkr = mcasp_aclkx;
" W! _, [) t& \- O& i* t- wassign mcasp_ahclkr = mcasp_ahclkx;
$ o/ A1 b8 Y/ g. ?- E6 d, fassign axr1 = axr0; 9 K5 }8 s+ K9 C3 L- K$ @; F! H
, F# }, M2 F) P& K: Z5 m- o& o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( s8 u7 @* ^; b) P" ?0 b) mstatic void McASPI2SConfigure(void)
4 |( _! W1 D( G+ ? s1 c1 x{& t6 O' Q0 L+ W, N8 z' k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% F5 v* v. w' j0 d3 z/ G2 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' }9 N4 W( E3 Y7 dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! ^( `% v% D$ P( o" zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 T- |2 p8 J8 x+ [' _2 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 F2 i. o) E( t1 m; N" s! q
MCASP_RX_MODE_DMA);
2 `, z7 K, X: T2 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( a1 x! J: W% _: d9 W$ r; o* U+ P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, s }. g, o6 a8 W. R; h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( {$ P; o3 L! T$ S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ _1 E) P, R4 ]$ [7 p5 V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 T0 s/ I/ v5 n' L: T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 w* |) ]+ @' |. U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' g1 T$ [% K Y7 K6 \) Q }" G2 k3 pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # H0 \$ E: ?- L5 D7 |6 @- Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) n8 G6 t3 v* O! q! ]6 D% H0x00, 0xFF); /* configure the clock for transmitter */
$ t0 `+ K8 K+ B( U/ qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 K, n K2 _- j O+ O+ CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- q! A# N) W) ]7 o0 b/ b4 s) s3 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 m. w3 M3 x) @5 ?( I0x00, 0xFF);# B9 N, z; b' z' f. X' I7 A. s
, K8 r4 m" R" L/ M i6 x2 ~/* Enable synchronization of RX and TX sections */
, ~; E' `8 o7 n1 x( z# GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: ]: T; B9 W' k" ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' X3 n9 V- |* F% F: S% W* G$ `# I6 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ _. _% ~- I3 u7 z** Set the serializers, Currently only one serializer is set as. w7 S$ l0 C! n% u" W% b* k/ O- X
** transmitter and one serializer as receiver.
5 @9 P8 Y* J8 O+ ?5 {*// r8 Z; C7 Z1 ]0 l6 b; Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 y# U" u# a" _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" i. \1 ]) U" f/ L9 A4 l# o C
** Configure the McASP pins . x( z% K7 q7 B. ~
** Input - Frame Sync, Clock and Serializer Rx
) c1 N l# U6 ~ R' h8 ]** Output - Serializer Tx is connected to the input of the codec * P( V9 U7 ?" z/ N* v/ D
*/4 E6 e, W6 p! H4 _5 r* @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. r) [. k' _0 j x( p2 r6 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& A! j% ~. U$ @ {* ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& T" {" J! {) |# Z1 U| MCASP_PIN_ACLKX
D) K' n2 X5 q* t* f| MCASP_PIN_AHCLKX
D5 r. F0 W$ c1 [1 `% q p8 ]* Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ I! L' [! a! G) R9 @: iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. ^+ a8 q% l& a' ^! @| MCASP_TX_CLKFAIL
; N3 J2 k9 p. V( S- s5 n! H| MCASP_TX_SYNCERROR
2 k9 B5 f! u& E% i' \' x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 @) j8 s9 A9 ^* F( ?" h
| MCASP_RX_CLKFAIL
/ R# t& B ?- H) }- z/ I| MCASP_RX_SYNCERROR 1 Y6 J& s& ^* X; @+ J; I, R
| MCASP_RX_OVERRUN);
) r$ ]# ^' | a9 u; p M} static void I2SDataTxRxActivate(void)% ~& P4 F8 @0 t( G0 e
{
% z! O4 M' X1 k" a* W4 e6 V/* Start the clocks */7 v D- Q$ c0 ^" H& C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: B2 r. a7 E. \- J) e2 W c" LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' X# }! e, G/ \. E Q% Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 O" K: s1 a. ~1 P9 q( [0 _EDMA3_TRIG_MODE_EVENT);
- N, T7 v$ N- H$ cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! [$ @1 {0 T9 G0 B3 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; ^) Z/ F1 G* R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 u3 c9 p* X* A6 d$ K {8 u" XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 G4 {* [& G+ J) [* \$ }$ M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 I6 F' @% _: f, a6 a) tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) E- z" }/ W$ L U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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