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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 o7 h ^8 s: g( v0 uinput mcasp_ahclkx,
6 R6 w8 A6 F- Z" Winput mcasp_aclkx,
3 j: G+ m8 D7 g' Linput axr0,! f* F) X7 |& e1 G9 }- W
e5 g0 w( H" k. B$ V. J0 [7 T
output mcasp_afsr,
& ]% H+ p1 ^/ h" q. g( D7 \output mcasp_ahclkr,% g9 m7 g8 v% P, e9 V" q
output mcasp_aclkr,3 ?! ~3 r; i7 g. S' O
output axr1,
% l5 C5 U2 I$ I/ P assign mcasp_afsr = mcasp_afsx;
6 ~5 J1 r( C) }; R. nassign mcasp_aclkr = mcasp_aclkx;$ q& P" p& ]3 n/ q
assign mcasp_ahclkr = mcasp_ahclkx;
, {/ j3 ^3 ]* Y/ }1 Jassign axr1 = axr0; 6 u$ B& i8 c6 j5 i& |+ x- I
* K' P5 i! d1 e& k# z- [) J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 H* h/ |+ i9 G$ `static void McASPI2SConfigure(void)/ o- H! @5 M k- ?+ T! m3 H
{
8 K7 b q& Q; @1 f- \2 d. G6 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& i9 A' Y4 k% {: _$ a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) a' k& l( R, j4 {" c0 ^% {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* r2 t7 s$ X- B$ I/ MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ G6 T6 _3 p, H: @1 wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
\3 H1 A% H* B: t: GMCASP_RX_MODE_DMA);; g2 u3 |# g" l% e' j6 l% d2 F' M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ m& v4 \- _* sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" c: B! O% [# p# I7 l1 g2 m# K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: M* @" R0 V5 |/ m6 LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' W. L2 i: e; M& b& C. d- n6 cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 k! s5 i9 S3 j; J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" D6 _2 E$ X0 eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! y8 u0 R6 b9 ^7 o- p9 D0 I2 @! h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 ? z1 _. d) u% |+ ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 E0 ~2 b8 [2 J" U6 e p0x00, 0xFF); /* configure the clock for transmitter */
/ G) E8 V7 r2 k7 Y2 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; h1 {/ U2 R0 D$ m& KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 _' ~! F- r6 A H7 f! s, zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 r8 M7 x" I- t5 U0x00, 0xFF);
% @ Z+ ]; v& @' t; [* I' ~6 c& \. \- |/ Q6 P" O) w0 p
/* Enable synchronization of RX and TX sections */
* i) z9 X* b8 D' bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 k* ?, z) b j" h* e$ X+ dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 ~: F. {% e4 [7 _! L, F4 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 v; `1 X2 }' p+ S$ k! ^
** Set the serializers, Currently only one serializer is set as, k7 J$ x3 R& S5 y& K4 M
** transmitter and one serializer as receiver.
% n: V- f6 H3 R: j*/7 Y9 p r: M) h8 m6 t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ H0 I9 X& v( h9 n& i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# P+ `/ M# g/ }+ i. W2 t** Configure the McASP pins 4 j3 Y, o3 z# k! i# `+ R4 l
** Input - Frame Sync, Clock and Serializer Rx
- `% i' n/ D. m8 H( d5 F4 ]! \' Z( D** Output - Serializer Tx is connected to the input of the codec " F, b5 T! @. N/ d* ~
*/9 h% s( r7 Z% A7 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: h5 @9 O/ v& i$ r9 T. { s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# `- h+ W) w) P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 {3 R1 F r1 Q d' R| MCASP_PIN_ACLKX5 O, w0 B7 [! `) p9 V
| MCASP_PIN_AHCLKX; c# `+ L) {4 |8 f+ A7 g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 t; \3 d0 b* V3 p7 L" M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 Q0 n* y! X Q( u, s& ^/ G| MCASP_TX_CLKFAIL
* H& }+ ^0 o8 n| MCASP_TX_SYNCERROR
0 V: N. L" ~. M; L# X6 s% J6 [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 g* H2 ]1 F+ n; R, t9 j| MCASP_RX_CLKFAIL# ]3 u: l7 R. [$ @
| MCASP_RX_SYNCERROR
; e7 P( J# T9 M9 i| MCASP_RX_OVERRUN);
( P1 [: C% Q' z, j) J# S} static void I2SDataTxRxActivate(void)
4 |) r: ~9 x2 f% V1 |{& @( x9 j; c! t: W; P
/* Start the clocks */1 j3 W( A, p! F+ e8 n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& w- B! ^3 n, ]3 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% x8 H, Q2 |* C/ u7 X$ L9 g; UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ p8 V* o2 K, B* p, J6 W
EDMA3_TRIG_MODE_EVENT);: g: L+ g0 b L/ s$ |* \8 F) F+ X L* ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! d; o' e9 _) B& K0 j) QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- Z" p E+ `( j) ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% P1 i" V+ C. {9 E/ s4 }$ h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# @( k- Z" k5 l# E: B$ Q9 U/ {# Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' s: N2 u' D6 H {) P/ c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 `8 `- S- Q: V1 A( {- @( o) _/ C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 C. v9 e' K, M" S5 z/ U} 8 K* W* J7 l, v% K% f3 ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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