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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 m" }# v/ F2 Winput mcasp_ahclkx,
& |4 p/ q0 ~" s1 @" v" Jinput mcasp_aclkx,
1 ~4 q5 \# a6 Y) k0 D3 J7 p4 tinput axr0,9 l5 M0 S: E) K% C
: _% z6 c2 m# l5 Z5 _2 w
output mcasp_afsr,
( s |, H9 I0 ?; u* V4 X4 foutput mcasp_ahclkr,5 S* Y% F2 D3 Z1 z% |3 y
output mcasp_aclkr,
3 w0 R" c! F# w D7 Doutput axr1,/ j7 Z5 X( f2 r9 U6 V5 y, `* p$ f
assign mcasp_afsr = mcasp_afsx;
2 ]" K' A# y' z& s2 O; qassign mcasp_aclkr = mcasp_aclkx;# w! M, k" V9 h$ n
assign mcasp_ahclkr = mcasp_ahclkx;3 s; K& \- P& L- J5 t9 b
assign axr1 = axr0; v; j3 k0 Y! U* ~* D, w8 e$ p9 b
5 b' z! a4 \" l/ }; a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ W3 [$ q2 [. w
static void McASPI2SConfigure(void)
! E5 A" q- K- e& M% B0 f' _+ I{' J' ]" g# N- w8 e) S! N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 b: L$ F2 O1 n& e, IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 p! N- G2 I, Q& m4 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 O7 K! d; g( L i. b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 ~0 S: g! o* {, G3 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) B' P: x4 ~, o5 {8 P7 hMCASP_RX_MODE_DMA);
- z' I' X! E8 q* ] {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 e g: Z& R: o" Q% H, }+ NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 F, m0 K- G/ o. c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* @7 L9 H7 r. z6 p* YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 l/ l: L5 B0 r+ y- D$ S* YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 _" v& v! @4 n, X) u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 L9 E: j6 Q) k' `& j7 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ c! v4 I+ H) ~ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" H" t. C2 n; @; ], }( ]6 pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," v+ H [7 m) E, n, N
0x00, 0xFF); /* configure the clock for transmitter */
+ O/ D3 T$ C9 R$ ~8 x" i7 s: I3 v KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 b$ j! x- P- D; g+ V& n" @+ eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ ?/ [9 t2 m3 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" N! `: L, n& N' ?1 S0x00, 0xFF);* m2 d- Z+ z0 Q& A6 s0 u [
( C8 M# P/ m" n9 ~1 f/* Enable synchronization of RX and TX sections */
4 W T7 x% t: l7 A8 i0 L8 l8 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) f* ]% {* i1 O0 `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 _+ a5 g! ?: ~. o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 n8 d7 x7 q% @
** Set the serializers, Currently only one serializer is set as' Q: D1 `6 D/ ^% j$ m
** transmitter and one serializer as receiver.0 b4 A1 c! A0 _3 G% l
*/1 J/ H% T$ m( ?3 s$ J2 h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 q1 H) y! B( w1 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 A4 O/ C2 w5 w, r7 N5 C** Configure the McASP pins
7 {; s7 B7 o# U. ]% p( H6 _** Input - Frame Sync, Clock and Serializer Rx
8 Y- Y0 ~" `3 h* @ X- M** Output - Serializer Tx is connected to the input of the codec ' B' s+ D+ |1 y* J O4 P) }! i4 u
*/
% y( [7 p/ y" y+ f5 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 T2 ?+ e* g6 U$ q+ E' }. S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 h& }9 @' q" `1 AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& B1 g& N" X7 z Y* o
| MCASP_PIN_ACLKX9 @8 l* s1 }, Y1 q/ H
| MCASP_PIN_AHCLKX
& T m Z' F" i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- e2 b# |% U3 m$ { W) V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " ~- y' G, ]$ M
| MCASP_TX_CLKFAIL 5 _3 s1 | T {; m8 H* Z- E3 _/ l
| MCASP_TX_SYNCERROR" T8 y8 e( j6 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# H/ x6 i/ g2 ]! k5 _2 ^$ I| MCASP_RX_CLKFAIL5 c6 V6 n9 J# O8 J
| MCASP_RX_SYNCERROR
- V g" m2 r5 P( i( E/ n| MCASP_RX_OVERRUN);/ |9 l/ Q1 e0 m
} static void I2SDataTxRxActivate(void)) `! c% _: c Z" }0 \; ?" h1 a
{
( K4 J3 T- v! h/ k8 Y/* Start the clocks */
6 B& q, W" l6 {+ `" NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, r( S; |4 h( R9 r' X; rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: _! O: e4 c: M. g2 Q2 l* XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 O! ?# I, d( w" P+ tEDMA3_TRIG_MODE_EVENT);
) v, N% a1 U5 n# U9 ^) q% |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 L o2 N* e3 w, j1 k( G1 G- t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" g& U, _: u1 Z8 l [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% M" F- U" `, c4 B* `( oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 R5 _# T6 u) g/ R1 z& M# }0 A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: g6 ~/ \5 ?: A# |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, C5 r( M$ W: e' `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ K- Q3 k) a- N' s/ @# o! t} : e5 D+ ^$ n7 @ s: k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : p8 `, a# @2 _# g' K H
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