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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) U, `- @. c. rinput mcasp_ahclkx,
3 f3 k3 h& S9 B: y5 pinput mcasp_aclkx,) E' t$ s( ^ L+ [1 y1 R6 R- Y
input axr0,
7 p9 K3 Z3 ^) Y+ b) G! ?5 ]# P6 h' A6 G' z3 O! v1 N* N2 k
output mcasp_afsr,
7 C- P& L Z7 P) O( Uoutput mcasp_ahclkr,& ?7 b; e( P" |: i+ N* o" d/ H
output mcasp_aclkr,
* D+ O' G5 n1 R3 a/ Q' joutput axr1,
4 e1 a$ G/ [5 l+ c2 }# \: X assign mcasp_afsr = mcasp_afsx;1 U9 A7 }: s8 C& X9 M
assign mcasp_aclkr = mcasp_aclkx;8 v7 i c# e2 P: K7 Y; z: ?
assign mcasp_ahclkr = mcasp_ahclkx;5 Y9 w. Q# x5 O2 _" C5 d! r9 y: w1 v
assign axr1 = axr0;
' T4 ]: {: ]) L" b
2 m8 F+ ^8 x: k( c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " w1 w) |# z `( N
static void McASPI2SConfigure(void)4 Y3 D/ r9 m9 N9 q4 o, y0 K
{
4 S9 y, K1 Q$ n: V ~7 dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% _/ R# D5 e) MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( S, x/ _7 e1 h% Z/ G% L ~0 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ f9 ^: A# f/ m! a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 v7 ]9 N; T" [" e" `3 W7 mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) u6 S( @$ l0 u5 W2 n' yMCASP_RX_MODE_DMA);
/ x% W2 a. k9 j. QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 L6 o1 Z3 v5 E: H- F4 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 {4 a6 _5 n. Y7 ]9 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 A. V z) _0 H, S, \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! [1 p+ M5 h. ]1 b9 v* x! jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 I8 N' H% ?0 v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 t1 h* S2 f; p* r& q+ k) B" y$ q! A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! e9 a" C+ t. b1 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 c: O- A( f& t, V9 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, \" o$ g. Q( K% Q. r5 C4 b
0x00, 0xFF); /* configure the clock for transmitter */4 o9 W! O: ?$ f, D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% l7 U$ A3 r; G- \) n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + P& V3 `+ u3 Z s1 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 p& R/ }3 Q& l
0x00, 0xFF);+ j" l& B; {. x# M9 D7 J S
3 G, Z+ q. O. B% m/* Enable synchronization of RX and TX sections */ 2 p; e! i7 |: [7 d) T+ K% { i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" W; y' ~# O7 n5 \( |0 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# n* W! A9 C- `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
m4 w, A9 Q# [( A7 `** Set the serializers, Currently only one serializer is set as$ R5 W, R' k) ?- u: E! D" L- \6 N
** transmitter and one serializer as receiver./ B7 t- M7 ^% F5 \; A" |+ C
*/
: h* K' Z. @& MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% i, h3 F, D, Z+ i) NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- X6 g. w! o- `/ {
** Configure the McASP pins $ |$ q# n/ b# U6 M
** Input - Frame Sync, Clock and Serializer Rx
9 [+ ]+ F2 `0 B( s; i** Output - Serializer Tx is connected to the input of the codec
1 o6 u. c8 Z$ n% `$ ^% m6 b* H% g*/
- R, W9 ]# \, T7 u( ~! y: o' s6 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 y# {- I" V I7 S/ EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 N, H4 u2 z7 w: `. {7 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( d8 s4 o; v( h4 K! m0 R- w
| MCASP_PIN_ACLKX/ Z' m7 G/ `8 a& T: f
| MCASP_PIN_AHCLKX2 c! N' t) N$ P( h* I2 k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& k/ x" ]+ |+ d7 j) o$ |+ OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " T1 t7 ^7 \. f
| MCASP_TX_CLKFAIL 0 x4 B8 k7 O# v* i
| MCASP_TX_SYNCERROR# U: n8 \( ^6 x7 P+ i7 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ B5 f0 h- w4 w
| MCASP_RX_CLKFAIL2 {* |; K, j) r, ~7 z6 x9 u2 N
| MCASP_RX_SYNCERROR
; q u, K% G$ {& E| MCASP_RX_OVERRUN);5 @" t6 ^& L8 t3 L/ a0 _
} static void I2SDataTxRxActivate(void)
# a9 q8 Z5 [ w1 Z{& B" N9 p* K9 e
/* Start the clocks */
3 X/ ~. }2 f8 Q; N7 C2 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ g3 A, N6 {8 r! N! o4 s$ x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ O3 v" \% W% a' a2 c: QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% I! X+ ?1 U) y Z, r6 o+ b; L
EDMA3_TRIG_MODE_EVENT);
+ f* G- v' J6 v5 O5 V7 J: UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 p. D9 R. W& A) B( iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
]6 e2 N8 t6 h$ l1 C& f7 S; lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( ]0 Q. s; d m. }4 f/ s) ]( l$ H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 K0 G+ ^. g7 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& z3 X- m2 j F0 c5 H6 C0 W; B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, j2 i6 }3 l6 I2 n3 x, o0 nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: N+ k! ?" ~% n, ?3 L7 F} % d* S) S" l9 `& x; |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ Q! o* B- u& V: y' c- Q
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