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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) o" q9 r* I1 ?5 j
input mcasp_ahclkx,4 I# q$ F7 h4 u h8 k, C4 K# j
input mcasp_aclkx,
# z9 l. ^% S% v/ [: z9 v& j1 zinput axr0,
' D/ ?- `1 f" B6 s4 }5 p2 x7 x+ [5 {, _
. \8 W' |8 D' G8 ~ qoutput mcasp_afsr,
; u, T. D: p$ a3 _8 loutput mcasp_ahclkr,6 B" J1 o% e; K
output mcasp_aclkr,
+ ]4 j2 I# z' P) m+ P7 r2 _$ }output axr1," w, r4 t* b2 B2 n& X7 }
assign mcasp_afsr = mcasp_afsx;" u$ c) H* O" g) F4 {$ n3 P
assign mcasp_aclkr = mcasp_aclkx;
- S1 W- N$ o) \5 f% Fassign mcasp_ahclkr = mcasp_ahclkx;0 K. k! g( p) Y( B: N& G6 H/ x
assign axr1 = axr0; 4 u: L& E- M/ m% s3 P
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 Q) x9 M# m' @; b, P& ^
static void McASPI2SConfigure(void)
$ j: T# O. {& p. F/ H/ d; t6 r9 }{' J- ?0 E+ k; n0 S+ d t8 q) U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" r6 i/ W. ~' F5 ^$ U, j7 }( U, |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 o* _7 {# F$ {9 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ V: ~1 B* e& l/ sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ Z1 j/ o! S' y _( e$ a) YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 _, r) S( q% ^8 f: v" f. B' C% q( VMCASP_RX_MODE_DMA);
W' ]' J' q( L( r* H& Q/ gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ~0 t8 X. L( ]4 RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 u; U: F: z6 ~, a6 R7 u3 ]8 [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* V& d Y! Q+ o/ {/ |* bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* ^! _0 u% f6 u( TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . S) j* l- T! A$ E4 ], L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ j. s7 m) G! X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 q+ b Y6 {5 N9 A( PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 v# \7 g r1 B: S* y9 k0 ~1 `* O8 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" R" [. b( W; b/ [. S! [0x00, 0xFF); /* configure the clock for transmitter */
2 \1 x `+ R9 _7 gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 z1 y( ?3 ~" Z" [+ Q' }" c) r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 P8 y& p0 U# a+ X" y- BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 t2 \* Y# H: U$ [; c% n) ^6 D
0x00, 0xFF);
/ r+ @- d9 V. K" e" [+ O0 a3 {8 k2 G% K" K
/* Enable synchronization of RX and TX sections */ 5 M e5 O! y. X0 W8 f; r* a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 Z) @4 ?* @2 n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 ?/ k( \2 u( X9 y' @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' l: W1 G' C* N" t' W9 m8 @** Set the serializers, Currently only one serializer is set as
' g& W3 p$ r7 q** transmitter and one serializer as receiver.2 N) L' U: i! d2 B* U5 V, p0 Q; y9 _
*/
5 V" \1 n/ e( Y- L- b( d7 A( UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& [! T2 } c% ^: Z; _ @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 c, A. U; d/ y# i& I
** Configure the McASP pins
7 Q2 K- D+ a$ y/ d8 Y. l** Input - Frame Sync, Clock and Serializer Rx3 i2 Z; q: ?- _8 Q
** Output - Serializer Tx is connected to the input of the codec 1 v/ {2 C* k" e( B* c% Q5 ~2 E
*/' {; W& T" x0 x# j4 O, h$ l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ B4 x" k; O7 N* Q$ B) DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ d' g/ ^+ i$ p# r2 E# i# [, }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 s# O! P3 p1 P' Q- x, l A% U| MCASP_PIN_ACLKX' A4 J4 C" f9 i0 {
| MCASP_PIN_AHCLKX3 r& |, ~) p6 x; X" a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
\6 o4 E' x' K# c% D& LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# J# x/ k% `4 O* q" a! E| MCASP_TX_CLKFAIL K1 J7 p7 h: D+ X3 y5 d; z
| MCASP_TX_SYNCERROR0 L3 H1 {2 r0 o ~) R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 ?* ?2 ]2 L+ H% x& H& A7 E
| MCASP_RX_CLKFAIL
" V/ r5 [2 b2 || MCASP_RX_SYNCERROR
, E, \3 H% f2 a5 _! z/ d, R| MCASP_RX_OVERRUN);
+ b& w+ {+ D; r} static void I2SDataTxRxActivate(void)' t# `4 y8 O& k8 A5 }* \; l' `# j
{
+ J! d/ x) u% U7 V$ @( M/* Start the clocks */
. l+ Q1 ^+ O6 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 G, Q. K) G8 L+ a) z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 h" R1 N& g8 K9 d2 A# A$ x: F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) n! M7 g6 h/ |0 E& p' k/ |: SEDMA3_TRIG_MODE_EVENT);1 K8 L$ u) N' D+ j3 }9 M/ z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# E' V4 |$ Y n4 E. ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ t, S& g9 r4 D9 X6 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ ~0 T3 y, E: B6 x8 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. J0 V V ? }7 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 I/ v# M: E6 `, P* o0 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# s! d5 A L# M7 S9 ^9 Z! b3 Q- }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% M) w' {% f# ^( p}
# [) |4 c3 o- R+ _) X4 }$ ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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