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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 o# ~- z+ ]( S) k5 Z8 \8 C' s [- v
input mcasp_ahclkx," A3 A& {0 i) |+ R) a7 X4 ^
input mcasp_aclkx,9 V8 h4 k9 F3 B7 J: T0 d
input axr0,
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output mcasp_afsr,- |7 j6 v. X- D* ^' }7 F. I
output mcasp_ahclkr,4 u2 q/ d; U2 N. u. q2 T
output mcasp_aclkr,: M4 R% ~- `; z; i3 R: n
output axr1,; Z# m9 i0 |. U& {* e
assign mcasp_afsr = mcasp_afsx;2 W+ r# ` U# ]+ o+ f
assign mcasp_aclkr = mcasp_aclkx;. c/ h! Q4 w5 m0 g
assign mcasp_ahclkr = mcasp_ahclkx; O* x$ e7 B$ w1 Z, O6 N
assign axr1 = axr0;
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, B% f" F# B4 z1 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 t2 G6 \+ t9 q0 b% g
static void McASPI2SConfigure(void)( Z4 j) [8 V. h$ s t2 K7 x9 P8 E& S
{# G- N% M: l5 a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" G% x% U- y, o3 o/ d, p1 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# h8 Q, j' }3 ?3 K! }) i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* C. T5 S3 }, f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 [: b( s( i8 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ m' m Q3 i ]8 x8 e, Y9 D( iMCASP_RX_MODE_DMA);
' n5 V) B: w# \2 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 X4 ~" _$ X6 Y5 ]2 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, G4 P& q% L$ e5 W+ f+ X0 r/ O6 M: c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # x0 y; S' [0 ?; ?( k" |% J0 t- w* P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 i0 ~$ g6 f3 bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# X8 b. B0 V( hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, G5 k* z- i5 ?3 `: i! g f9 c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, [6 t' R# h, w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( N5 f0 `+ [3 \+ f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ m: h/ k7 d7 W6 R5 d& w5 l o0x00, 0xFF); /* configure the clock for transmitter */
D$ m) y$ X8 E, d& z2 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ i$ t* m* u. M6 e0 i) `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. [0 A) R s* {5 Y: K- ^+ _& \6 u: gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 q! K7 V z: y) f% l% c0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
$ O0 s, ^ h/ M: ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& D! L, \3 B" V( Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( c5 ~" |+ u- z5 c, D; l3 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ F4 l) U# c0 D) x+ G# z) L9 n
** Set the serializers, Currently only one serializer is set as
: z( ]3 k6 r: ^! p' C** transmitter and one serializer as receiver.
1 N; t/ T8 N! Y$ u" z7 {1 P2 G1 \*/" {" [6 g2 m2 ]) u: ~, n, |$ q) O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); Z9 m) O. Q+ A g8 X1 \( b& f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* N! D2 @8 n2 I- h2 V& k3 A** Configure the McASP pins
3 L% x6 s' k, G! d1 N$ Q** Input - Frame Sync, Clock and Serializer Rx
/ r9 y+ L3 G2 Y$ V1 h: G** Output - Serializer Tx is connected to the input of the codec
+ F( E9 K( n; a" b, _*/
; x- S Q7 Q R& D9 X7 FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' s' |" x; I4 \' M" C0 t: N, lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# x5 I8 m8 Y% R! A& p9 ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 \$ z9 ~# h+ s0 s7 R5 b
| MCASP_PIN_ACLKX3 T5 U) m4 c9 C
| MCASP_PIN_AHCLKX) Q: ^& E( }" S! q- j" e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( k. K! K" Y* b% S0 j# {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) X) P) l$ }! ^/ ^| MCASP_TX_CLKFAIL + w" k0 A6 @3 N1 g" f
| MCASP_TX_SYNCERROR6 N: b; D {& H. l: l% r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 V6 S* R0 o/ T! ?! }! p| MCASP_RX_CLKFAIL
7 ~; Z; ^, C5 _| MCASP_RX_SYNCERROR ' }; [3 V5 h- R, s. x
| MCASP_RX_OVERRUN);
. W' d( x' n9 ^! x' b6 O} static void I2SDataTxRxActivate(void)
& ?0 ?7 m! s" u{
3 r$ O4 r6 g, E* `; ?/ [4 `/* Start the clocks */
" V3 [7 _& n, uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 Y& e9 z3 B9 k. O; x! v& `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# b9 b& f8 v$ p9 E* m# c9 L/ J" cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% t5 y. r* ^0 vEDMA3_TRIG_MODE_EVENT);7 o' [2 a- G9 T5 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; e8 H* v6 X7 e# X- I$ l7 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& t/ b5 m/ Z% }) K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* A* F+ A' c6 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 p" M* a+ Q0 B3 E3 E6 Y+ s; N$ m* uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 s7 m) X% s7 m2 n" sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); }0 \% D" v) l. |" C1 b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
{0 V/ ?' t C. F$ d! u} $ q# ^ A1 S4 q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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