|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" M/ X# f7 U0 f4 R# hinput mcasp_ahclkx,% t3 R( `9 V' y& n5 f& {8 z
input mcasp_aclkx,7 S& {6 X# f3 K5 [# O. k( V+ O
input axr0,
* `+ Q$ q9 p# x5 O- S4 z. b- F+ x
% V8 u3 G6 L$ Z' Ooutput mcasp_afsr,
' H2 ^$ Z( v% t6 Zoutput mcasp_ahclkr,
& z, Z$ m: E7 D6 |) B3 L! Y7 doutput mcasp_aclkr,: ~$ s# X. e+ z9 P! O' H& n |$ k
output axr1,
$ j1 n& T$ ]7 J5 I' X, I% q assign mcasp_afsr = mcasp_afsx;
: E* A- M9 C7 O1 Hassign mcasp_aclkr = mcasp_aclkx;
3 e }4 _1 v, |. eassign mcasp_ahclkr = mcasp_ahclkx;. Y0 h6 @: }5 G$ D: Q
assign axr1 = axr0;
, k4 w. D" }, z9 c
- M3 ~; g8 J+ k7 b( H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % f1 G0 i3 V7 u; r2 k1 I/ a
static void McASPI2SConfigure(void)4 r/ D+ N# p- d P9 @" K- j
{0 o x% X' S7 Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- X G' r' _ c A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) M# h$ G- B- B" g1 o3 l$ G, ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; d: z# E6 G! c0 V9 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 ] g S9 B1 J* Z% H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 |4 S, h$ X5 g- mMCASP_RX_MODE_DMA);* P1 a* [6 @3 `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) I) [ m/ g: b5 [0 j; J0 [0 EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) L! \* R+ @8 g0 HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 M! q1 G) K5 _. F2 ^) N+ w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( |0 x# q9 Z, g. D) V$ E. @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 j9 O0 X! k% Z# y0 ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, c$ E) c( {' c$ n& R; Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 D' g7 @7 ~; p. \4 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( C# }/ v! o+ [+ i/ NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ q2 j2 Z C+ h# W% Y# E
0x00, 0xFF); /* configure the clock for transmitter */
2 j4 e9 k& g& V1 l' i9 zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, b: Y/ \# j+ R9 c+ Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ l- D- B$ S4 k7 q+ H9 n. }; lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," _, D' `% D( J$ l" V/ B& d: h
0x00, 0xFF);
. n; E/ i3 I" d
. S, g! _) n3 x1 @/* Enable synchronization of RX and TX sections */
( Y3 z* |6 C5 m8 f9 m0 _7 J9 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: d5 q' E D! qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 R! l) k, D/ N; \% M. H* A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ c: P8 ~: A3 d( l) a$ {** Set the serializers, Currently only one serializer is set as; s8 o* H/ W1 u6 w9 L: \
** transmitter and one serializer as receiver.. t% d$ h2 _+ @8 B- \- f
*/
$ G, t/ Q! l( f7 J6 W5 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) ~( B. ?3 D3 _2 x; L. Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 R3 @8 g; U# r4 V6 ~' r: Y
** Configure the McASP pins
7 x+ R4 i6 A" \2 {4 c& `! C9 Y5 [** Input - Frame Sync, Clock and Serializer Rx. r6 ]- K5 a! P- k) e. {) U) p) f
** Output - Serializer Tx is connected to the input of the codec % j! x, d( w; X* k" l* ]% r
*/) |6 K6 F: G, s6 Q( H; K1 k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& y; F8 j+ @! o8 b. G& |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, e0 s% a+ x9 m) s, o7 ]% S6 O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" T* \6 I0 [! @/ H1 W( e6 A# d
| MCASP_PIN_ACLKX
% w0 H* T) g5 H$ _. @2 l. I8 j| MCASP_PIN_AHCLKX
8 b8 e: c( @! {8 X7 @+ M) B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 k3 @2 I# L' C5 ^- `/ C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 L- L5 i' X K- ^: S& S
| MCASP_TX_CLKFAIL # T- x& a/ [8 c$ l
| MCASP_TX_SYNCERROR4 }/ p% u6 T6 H' m' b v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - X3 K1 U9 k6 k/ p3 p6 S' b
| MCASP_RX_CLKFAIL
. z+ R+ ^8 m9 s$ j M# h0 n# t4 Z+ Z| MCASP_RX_SYNCERROR - E T$ u% l' P
| MCASP_RX_OVERRUN);
; P+ }6 U! R' o( O7 a, b5 Q} static void I2SDataTxRxActivate(void)
2 R/ c6 z, f+ G! u8 i) B{
- @2 m6 [/ ]! K8 q- J. p$ ?/ q7 Z. _/* Start the clocks */( F2 `# h$ }3 @: f- N- g5 V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# r( S/ m) ]% {2 ^" i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% o" @8 s5 W0 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# Y$ m C4 R# Y* |EDMA3_TRIG_MODE_EVENT);+ B0 K& g3 o% h# Y6 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 B+ X2 `; q$ e) y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 }8 Q- q' a3 S. Z1 t- _. tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 {* {4 u c7 |( `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" d! t1 ^* L$ M: J- t. J* z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& {; |7 |( U4 H, K" e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: g* d" v3 C5 | A+ E# ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. a, K# H( Q# c- z8 R}
4 w2 h" ~+ H7 {! n ^5 @$ N7 `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * E. U' ^+ f _( q3 G8 L) A
|