|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, s8 Z% d9 m$ v N# Z$ X0 R
input mcasp_ahclkx,
2 {# j7 d/ V4 b2 k' G/ X% Dinput mcasp_aclkx,
/ m* ]5 J9 @- I6 Minput axr0,7 i" T, }& {. d
* f4 D0 A0 X) Z' toutput mcasp_afsr,
* B: \$ Q* Q( d' Joutput mcasp_ahclkr,) G$ C3 J3 ~1 h3 X+ C
output mcasp_aclkr,
. x+ C, g* T7 `" L: \/ D+ voutput axr1,- N+ v( ?& U( H8 e
assign mcasp_afsr = mcasp_afsx;
- `; E# |- B s. E+ ^% w: Qassign mcasp_aclkr = mcasp_aclkx;
1 v6 z& C: ]. p; iassign mcasp_ahclkr = mcasp_ahclkx;
[; e$ j) E2 X) v$ ?) dassign axr1 = axr0;
4 n" U. L: m7 L
. H" g$ t0 R+ ^7 G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* l# e# g1 R" E6 Mstatic void McASPI2SConfigure(void)" d- \( C7 k9 g9 P. ^' I; p
{! h5 X' L$ P4 V( i1 P! v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- D3 s+ r K5 |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* ^# ~) o. K& jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 F) \5 ~# q& j4 }4 F- c% dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& p) s( I3 P! i# u8 G5 Z9 p, `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ B) L W: p$ Z) R
MCASP_RX_MODE_DMA);
8 y) b, b) Z& B2 @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ |5 [) o1 \& c( b8 m; a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, w! f! _! @0 ~& }4 _- V* g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 f" j) G* T4 I/ ~! Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( }7 O0 q& B7 p7 G& j sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 k+ c! K7 {& d) R8 ]8 RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; e1 O; D+ n$ N" j, q1 D' dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 l( Y7 j! y" V8 ]2 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 _- a# d$ U5 O' O2 G# |& \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ y8 W8 a* o3 ?& C i' c
0x00, 0xFF); /* configure the clock for transmitter */
; u ?5 W6 f" y. @- l! [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: c* ^5 B7 q" T: e) L- B) H3 v5 sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 r! K2 F9 q. k7 g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. Q. ]* j" |) K+ E3 e/ p! Z1 X3 |
0x00, 0xFF);
8 q0 L6 c2 ]9 ^7 l( N _2 r
- r4 ]$ `+ I t& I/* Enable synchronization of RX and TX sections */ ; n! ]- I% \2 x! q( x7 W! g7 d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. \5 @# Y z8 }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* H N" N1 i7 Z2 v$ w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 g! Q% w9 H& W. K& |' l. J
** Set the serializers, Currently only one serializer is set as% A; e6 f! Z: u9 t. K
** transmitter and one serializer as receiver.8 E* K( ?7 X) T; q
*/, A1 T. T G7 C* M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% S' [( j; ^/ ?" I' P0 Z5 U4 I0 p. c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! {; t5 h- s7 R$ k1 y. y: n** Configure the McASP pins
+ w; r0 r- N/ C% y** Input - Frame Sync, Clock and Serializer Rx
) |3 w8 `4 X& ~** Output - Serializer Tx is connected to the input of the codec
. J7 ^& N% v8 [1 @*/5 S9 }$ Q0 n) I. y1 O' r. q3 [$ h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
g: H% y% x. _& M% d0 A- R) KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 I' u& X( a# E* t- u6 |, \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, z: Q x, i! O% A
| MCASP_PIN_ACLKX
+ b# L9 m* r, s% \' N( R$ ^| MCASP_PIN_AHCLKX$ G8 ` B7 g a5 W6 l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, e0 ?+ I2 A+ f8 ?+ j! s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 z: v5 l+ h; v5 S$ e
| MCASP_TX_CLKFAIL
1 [. J7 e: a1 H; m7 q% E& D- u| MCASP_TX_SYNCERROR
7 {% J- Q/ r0 Z4 c9 ~" `2 R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* A1 L, a/ _" X9 w' }( a| MCASP_RX_CLKFAIL5 D9 n. p% V; R4 n. I
| MCASP_RX_SYNCERROR / C( T$ H+ D u/ l( X1 X
| MCASP_RX_OVERRUN); a1 M1 d6 J! {/ K$ `
} static void I2SDataTxRxActivate(void)
& Y9 G- z4 n& \% R! L F2 x{6 K7 |; Y: `* p* ]+ B$ ~
/* Start the clocks */
2 c$ s2 e5 l; V3 \& M$ F" gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( ^, w5 w. g2 m: d; YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* t9 k( j+ I3 w d4 _- z, Y# DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 C d5 ?( v; ~3 K5 r
EDMA3_TRIG_MODE_EVENT);
. b% q; T4 B D5 I/ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) Y- c/ l+ g8 f+ z5 n( IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// e! P! P, h# G0 h3 z4 D o l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 n7 P8 n& q! D3 KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" i" D7 T, W) [0 W5 A* b1 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! A) \- _3 G* r6 H" Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 N& U. H- @' I4 U. @1 f+ y, @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 Q( `. L0 T- ^; ^8 ~5 @
} " c4 r/ O% r+ w2 E- c0 x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & V/ C6 C; k+ z6 E* P; `
|