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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- E8 _1 n6 h2 B* v! y a: {
input mcasp_ahclkx,8 S% J2 Q, U3 X7 H! Y0 A1 E
input mcasp_aclkx,( z- y0 C- K9 Q2 z! k3 {: c% p5 ?
input axr0,
8 ~: d3 N! g$ o! W/ G' i
3 P$ m& P* @* Xoutput mcasp_afsr,0 V( N5 \$ i3 y3 U: {/ }
output mcasp_ahclkr,
" Z/ _( n h Q9 e4 J" n; @output mcasp_aclkr,( H0 d% B" ?- ^0 y" z4 D+ y/ K
output axr1,
0 B( J- h9 N+ a* R, _' V# Y: O assign mcasp_afsr = mcasp_afsx;
) G7 o) r0 e Z& L! \5 fassign mcasp_aclkr = mcasp_aclkx;
0 i' o: ?5 a" b' j$ h" a g9 ^5 S8 Kassign mcasp_ahclkr = mcasp_ahclkx;
m4 M8 C9 h4 l! [% o- xassign axr1 = axr0;
. h6 {9 e$ K, H. j" F) u8 L8 @! A7 i3 _2 {6 B& Q+ ?9 P% P7 P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 m2 d- L# S& H5 n l+ ^+ Qstatic void McASPI2SConfigure(void)2 m" h. Y+ A& W' K
{) c. }. W4 c. u3 k: N0 G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: R \" D( p, qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- p! \( S% {( e0 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ x$ c( `4 \$ z: R0 j: ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; v5 Y2 f0 A$ Y- R) S, FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" I, `" x3 g1 z, `, EMCASP_RX_MODE_DMA);' y( s2 F5 n5 C$ _; L0 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# b8 _- o* I( Y9 q# wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' s4 E' q! g- b c1 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 d; q' u* i+ KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 {$ _0 u" e ~* M" N# A* q5 e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- }# A+ \" G, ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, {2 E, o. Y8 h: tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 U2 H9 e) ?' J( v \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : n9 ?+ V' e) O0 a+ g# L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' O' Q; E- w( f0 m
0x00, 0xFF); /* configure the clock for transmitter */
) }$ ^- m! e( w: t# \ aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# a6 I. p& }$ p! s$ C( wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 S: }5 r9 t! ?8 P2 G8 s, pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 a3 b# H$ B8 G, [0x00, 0xFF);- v5 |* c7 I) }) P+ E6 s( {' R$ Z
& p" ^/ j: l6 i3 ^! G) |4 d1 ]2 p
/* Enable synchronization of RX and TX sections */ + O; ]6 Y/ u9 C4 S; c8 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; h. g( O1 S. B$ u# h9 u" F/ H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- u' _7 J, L2 s) B& N5 S0 m0 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ U7 I3 v2 Q0 R
** Set the serializers, Currently only one serializer is set as
4 O( o. k8 O3 w' |& I0 g* I K! R/ Y% j** transmitter and one serializer as receiver.
/ o" }, U# X6 \7 F7 {# D*/, _/ G0 n; l: e: h9 H$ ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 D7 H4 Z) }7 P4 u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, C" Q0 |5 d. o0 b5 H** Configure the McASP pins 4 a1 k- D" N& ]1 O
** Input - Frame Sync, Clock and Serializer Rx
( i3 H/ N, v0 t9 F/ k** Output - Serializer Tx is connected to the input of the codec 9 E" K# {* Q+ u3 G$ q/ C. U
*/
6 `1 Y, R4 y: gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 s7 O1 Z2 o4 F) xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 c7 x4 l! N, ?0 |/ v# p" w$ b5 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 r' G! C# k! |7 P1 k& s
| MCASP_PIN_ACLKX+ o% [; b" ? x$ b" E* Z
| MCASP_PIN_AHCLKX: o) h7 i& U' u+ y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( J. F M' G- A+ JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 h! L; N- R+ e/ `* |& a* ]' [, P5 R
| MCASP_TX_CLKFAIL
5 ~7 Q- e$ w+ L8 i( g| MCASP_TX_SYNCERROR# _9 k' C D) c. I: I) A. F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 A' C2 R1 L. C7 a" m% O+ @6 o
| MCASP_RX_CLKFAIL
# H' U& v& A% g4 U5 H, s' g/ P' f| MCASP_RX_SYNCERROR / b& K; R# U8 M
| MCASP_RX_OVERRUN);
/ B( B1 I2 i. C4 c: q7 n} static void I2SDataTxRxActivate(void)9 x3 k* w B) f; u8 S
{
9 _' a6 p" J0 K2 E- d# {/* Start the clocks */
6 b; [, R, a/ QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 [; _# J" g7 H& A2 p" L2 Z0 p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. G4 y4 Z# P( pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 [3 N, r! p/ P: g2 d; K
EDMA3_TRIG_MODE_EVENT);
N' U% j @* q3 A+ e( fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# U& t0 \2 H/ g; WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! Z6 z, k2 V3 L$ l0 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) G Q7 [4 p7 @. Z8 j/ P! _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 X* V5 p3 A& v. M* Q/ p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* S: X! c( I8 O7 R$ G t$ V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 f9 l* C3 W6 j8 t7 CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& [( P0 c5 a6 e/ j) P} . D1 {/ \5 J$ S& K/ a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 W I' c9 K3 k7 J: ?! ^& G3 m
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