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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
Y9 K, }9 n4 w8 _4 einput mcasp_ahclkx,4 p6 M+ L1 Q. |6 _
input mcasp_aclkx,
T% C. M. b Tinput axr0,
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output mcasp_afsr,
) U3 a( O6 e m4 b+ Doutput mcasp_ahclkr,: b2 C, ^) w* `2 n/ D2 s- |
output mcasp_aclkr,. K/ L- ~% b1 m) \4 z; ~ Z$ m
output axr1,
4 w, {+ m- s5 s1 H( d! e: j assign mcasp_afsr = mcasp_afsx;% g/ c& S3 j3 b# O, m
assign mcasp_aclkr = mcasp_aclkx;
( L, |- A' A ], T0 r, |assign mcasp_ahclkr = mcasp_ahclkx;
: \+ M9 o% t2 Q! E% H9 L$ Vassign axr1 = axr0;
: q3 ], Z+ R6 I% \. | @% A. E+ z: L% ~3 M+ K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# N. ?% q6 a7 ^' g; c( `static void McASPI2SConfigure(void)- _/ }8 d0 b- [0 L# G
{
2 T# P, y+ p) `7 Z7 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 j3 a2 N/ R; f& ~5 {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 G4 d! u% t& i2 U; B/ DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- Z' P+ p J. m' {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 U5 g& Z) p" `4 S1 ?) W+ [' a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" s& J' J5 y) P3 k! G# l" p3 ZMCASP_RX_MODE_DMA);
- I# k9 u; l7 `/ T& u2 oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
m8 {1 C- |& O4 u4 CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 {! |( [7 l6 N% u& N. G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 _$ l" A Q6 W4 U Y5 A( O( D' NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 Z& D+ @ a6 U8 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / O% G4 J$ c- ?% q% d& H( S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' P O6 _1 e& z+ H$ |- c# P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. o" g2 t0 f, d7 L. l( B8 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ F4 M+ d; b$ I; t' ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. R E2 n* o# v2 w* R5 |6 t7 a3 \, O0x00, 0xFF); /* configure the clock for transmitter */
0 l* a7 Z. D) C5 y X Q* NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 ^0 M! p8 n+ y% |% B% @4 a3 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 i- z. g6 c& l9 V3 n3 jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; u! B4 G+ G( @$ D) [$ e
0x00, 0xFF);& U, r' |6 f& l; |- n6 e6 ~
* r* ]+ z& o& G N* S
/* Enable synchronization of RX and TX sections */ , f8 ^- I. C% z# p9 z8 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' o0 U7 q7 u9 v! i' A, pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ i: ]8 ^, V4 r9 b2 [7 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 Y$ S m3 L1 ~! B; B0 _& v* D** Set the serializers, Currently only one serializer is set as/ l! S7 p& n5 u+ |) @* W/ C
** transmitter and one serializer as receiver.
# O z/ @4 U; M4 [" U*// I3 K w8 |9 ?( k3 T4 [3 W7 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- t9 ?+ L6 I R9 bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, e7 h/ L7 D' i7 I** Configure the McASP pins O) [7 G7 _7 w' o ~: ]
** Input - Frame Sync, Clock and Serializer Rx3 u. J9 L) f5 [& H y. e& z% B4 z, Q
** Output - Serializer Tx is connected to the input of the codec , B9 a5 m7 L+ F; n! E) s
*/
7 ~; \/ [. n) p% {$ yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); [7 e, V+ g0 R0 Y$ X6 h; i$ l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; L* A' E- Q6 o9 H7 ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" I, g4 ^' q7 o# i& V7 J' v| MCASP_PIN_ACLKX [ I$ f" G# n3 I! T
| MCASP_PIN_AHCLKX
% s; s% }8 t# S8 ?3 a& S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ {* H, _% |5 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - J- K' ~( S# L1 R
| MCASP_TX_CLKFAIL - E# }. Y4 ^- S! p9 W; R3 A2 x
| MCASP_TX_SYNCERROR
8 P. L9 W+ a( J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
i. ]( e3 o" U Q$ c/ O! G| MCASP_RX_CLKFAIL
. G4 [) X9 f0 B# n7 L| MCASP_RX_SYNCERROR ( S2 _$ a( B7 {( y9 { O1 ^& j
| MCASP_RX_OVERRUN);0 B' h# x! t3 y- X1 ?
} static void I2SDataTxRxActivate(void)
2 m/ n* Q# b9 e+ ^; A& e( v{& g4 J3 f! b7 k. E' J8 u
/* Start the clocks */
- W! I0 y4 d* w" Y5 p! \, O: G2 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); E/ ]2 l. u. S* k9 z. H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; C* c$ C. O( ^8 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. K0 k$ y6 ?( a6 i. [4 Q) ]2 s: B
EDMA3_TRIG_MODE_EVENT);5 y0 l& M7 d4 f; y3 F% O: l) j* V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' t- \0 x/ b% V/ Y* f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" S2 }/ X {& X1 sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! I& ~% ?/ M* r: o+ |) H5 ]( @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 ] ^) ?& c% W% @. I. ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- v- S2 L }. `% aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 K2 g& q7 g: W$ G9 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- T, ]1 ?$ D/ G0 D0 {# |
}
$ Z2 O6 s" T" S- a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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