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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 @: x7 Y, T. v- ]( T
input mcasp_ahclkx,5 @4 A& f, s6 \* K, l( B1 k- r( F) K
input mcasp_aclkx,
& R7 f3 D- R. w! O% ginput axr0,+ }! z- @3 D# g/ c/ Q& g4 j, a5 x
i+ l" y2 A2 V* d
output mcasp_afsr,4 J( q3 x8 E6 g3 |# g. U% O- R
output mcasp_ahclkr,/ C) x" f3 ^5 @6 N3 m
output mcasp_aclkr,' R9 O6 O; ?8 U; Z0 o, ~
output axr1,+ U8 A5 ?: B- l. ~3 N3 w
assign mcasp_afsr = mcasp_afsx;
9 j' b* ` I: V' gassign mcasp_aclkr = mcasp_aclkx;
' x, J( e% [4 U9 }9 I4 N+ Q( ^assign mcasp_ahclkr = mcasp_ahclkx;
: l3 b3 M2 u% b, U4 t) j5 b) B5 iassign axr1 = axr0;
0 z' k3 k& R# y$ k% v" K6 J
. I+ J# a6 ~/ D# o( H$ n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 p. o; `1 B6 hstatic void McASPI2SConfigure(void)) y1 R, G% B9 b
{# i# ~; \' E( Q, P7 }0 c: D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' d7 T0 T# s2 C9 N( Q6 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; D) w! N$ A% s/ r* k5 j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# w3 \2 w; Q) C# q/ a4 P" c+ D, dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 S! V1 Y0 M1 H- V* D) p* RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. [; W: p( d! Y( ~MCASP_RX_MODE_DMA);
7 k; a+ N" e, f& ^0 r3 u2 n; DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," F5 D9 m7 A1 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 M" E, V+ z) j+ _+ ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' u+ ?3 ]8 a. R. Y5 F% ~: [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 ?; y# N$ M0 DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' y) u) N8 W; ]# ]' y1 r% w8 T( u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 j. b+ e1 N# s; T3 ]8 M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: j5 G/ y) c3 [, x9 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* A2 b0 z7 C( [9 ~/ V5 tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 W3 D8 n. n$ m0x00, 0xFF); /* configure the clock for transmitter */
. U+ I9 g' m1 F# E( h* k$ C& Q1 iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" z% @; m/ M' k" i1 g5 ^( q4 v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / W2 ~* ?) `) ]; p1 F* `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: ^" T) R. ?7 w7 H* C, v, g/ `* {0x00, 0xFF);
, i t! }" b; z
, ~% T* ~6 }( A5 W/* Enable synchronization of RX and TX sections */ + @ ?. x9 n/ g2 ]/ _8 n" {% t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 K G- B% G5 r0 ^# A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) M8 |% V" \2 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 ]; _. ^: y" q( Q, M** Set the serializers, Currently only one serializer is set as8 ?, m; Y, g5 C9 o2 Q
** transmitter and one serializer as receiver.
# u" {- _" z: k+ Q' M. g*/! a$ u% p) t4 O; L. D7 @) S$ N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& G7 N# x- F2 k% i: n& ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 T6 ~! G. C7 p+ n; _ c** Configure the McASP pins
- M2 L; ~. D7 U0 x** Input - Frame Sync, Clock and Serializer Rx2 D: T x, E5 |
** Output - Serializer Tx is connected to the input of the codec
; \% w+ f5 P$ H- g& }: T*/: U! d$ D! N# u2 t' D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! ~# D( `3 e4 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. Q- b. I; q8 [, J. f; _5 [- [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' q$ w& v: z* d" E4 D
| MCASP_PIN_ACLKX
. o, T i# T* R; w| MCASP_PIN_AHCLKX
7 y0 q: i# a' G" Y9 n- b& T3 O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 h8 k* I( c) i, |) X9 V" {: o# zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 P X8 Z$ _1 x6 r2 H0 d- K& E5 H1 b
| MCASP_TX_CLKFAIL
* |* O. q+ Y8 s| MCASP_TX_SYNCERROR
! u% p8 D- f5 t3 y& i& a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- h$ E( z3 g+ I| MCASP_RX_CLKFAIL7 K r7 F) t) V w+ a0 I& J. i
| MCASP_RX_SYNCERROR & \6 H8 S% n4 X3 c3 }0 R o
| MCASP_RX_OVERRUN);
5 t7 C# r- G- [# a6 y, t# w} static void I2SDataTxRxActivate(void)) F/ u+ G8 d9 o8 m+ b% q3 H
{4 T( R" H1 A. K7 A2 D7 x
/* Start the clocks */
2 B* ^2 u1 [) r4 M' jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 D3 ]* O' w( DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% ^2 u) c, t, f, DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ }; C8 q8 N' S6 _6 N9 a+ E5 QEDMA3_TRIG_MODE_EVENT);+ u0 P1 i/ X" X: ^% z' y3 v1 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( q- U2 V- l$ P# L+ k, c( c t6 lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* Q( X4 ~1 h6 k H" n2 L+ LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# Q% H% S# i) m/ A' I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 i4 Y! G3 l, M* v/ D* q% Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' A1 e( V* X; J+ h% }6 W% E: YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# g; C, C: q3 u2 |6 x* PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 s* m8 ~, T* N7 L( ?* T+ w} ) V5 n' r" E* X% y5 f7 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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