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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 c1 s( T0 E$ Q, S1 k) E$ e
input mcasp_ahclkx,' Z. Y- E, }) w$ d9 ]$ G* c
input mcasp_aclkx,; A- o, o: k; V" f2 c5 G" R4 J6 R
input axr0,# G' q3 E% q* P u+ J/ x1 K
, G. `8 l; @, s" @5 goutput mcasp_afsr,
" \9 U* s2 S! b: A* T1 ^8 toutput mcasp_ahclkr,
5 Q8 J( t0 Y! l, j3 Zoutput mcasp_aclkr,. B) X8 _6 B3 ]: [6 x
output axr1,3 ?1 T* b% b& t. i1 @; h/ x
assign mcasp_afsr = mcasp_afsx;, {9 v/ G/ A- e9 F$ C
assign mcasp_aclkr = mcasp_aclkx; n$ A2 L0 z1 r: d. ~( X
assign mcasp_ahclkr = mcasp_ahclkx;* s- p% y6 h7 i2 d
assign axr1 = axr0; $ `+ a& a+ a+ K' o/ z4 a/ [- e
0 d, W/ G$ m5 ?1 f" _8 }8 S& i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 e& E& c0 K% s) C0 Qstatic void McASPI2SConfigure(void)7 o, X- T7 u' m
{! T; a4 H0 l! {; `" U8 w1 U6 `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 n7 `+ [4 h) L; M; e6 ] |/ ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, E9 ], p0 h$ q- [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& y% [5 g" x+ V+ J- bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 z4 R( w% ^. Y7 j: `2 e; [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- A# A( S" r# U7 P: x7 F& d
MCASP_RX_MODE_DMA);5 i* J% ?) k+ @+ ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 j+ t: |$ u- p8 Z0 V3 a# R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 w+ A. @5 g l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * J, j( x4 S% j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, I) t, E7 [$ WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) b( L1 _% Z. @5 s! V' _7 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, w6 {$ X7 g* kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, e' W5 K" P5 \8 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! R* {$ E4 F2 h# p% K! r8 Q+ UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 A0 j1 B: ~5 z' X5 Q) _$ q
0x00, 0xFF); /* configure the clock for transmitter */5 B4 H( _3 k' p- r3 \* {1 b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; s" ?& _# I Z5 MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ c) ?: b o. U( }4 pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) N2 G- g# U4 G: T: Z: H0x00, 0xFF);2 M) l" F" P# e. N. F
$ z X O0 b0 c# w1 U0 N& R
/* Enable synchronization of RX and TX sections */
8 Y$ E0 g6 i9 G& W, _( V1 g" |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( A2 u% ~/ V% y2 j. z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* ]" p8 N9 A. r$ }4 `' ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 A5 W. u% C8 h5 q! R$ S** Set the serializers, Currently only one serializer is set as; V& d: [9 Q M) H8 f1 }
** transmitter and one serializer as receiver.
/ r8 s) {" r5 b$ y D" P+ U( U) a*/
5 C! H+ Q; @. q4 q8 `8 J0 |$ aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! V! a- f0 T7 J% b# z! CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, k5 K- Q& C+ E* s** Configure the McASP pins
2 u: I0 D& r3 h& o** Input - Frame Sync, Clock and Serializer Rx
( t4 m& y& `$ Y" b9 e** Output - Serializer Tx is connected to the input of the codec
( ] g+ x% {0 W* l, D*/* H$ {+ Y5 r' W+ u6 ?1 I6 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, J; J" N* ?/ T) FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, c2 Y: Q2 O7 P. b* xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ R7 P! `; o Q/ R1 w
| MCASP_PIN_ACLKX$ w6 a) s. m7 r2 D2 P
| MCASP_PIN_AHCLKX( g9 B; S/ D* Q" {- k/ v( e+ B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// _) O: I- L+ G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % i& e) T- A1 A, J
| MCASP_TX_CLKFAIL
- E- B8 r9 Q9 ^ ]| MCASP_TX_SYNCERROR$ ~- ~- E/ w+ Y: N& w$ H1 @; {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 A$ j/ N1 |8 e) q
| MCASP_RX_CLKFAIL
3 j- M" v: p* }) c| MCASP_RX_SYNCERROR " w, M/ P+ \6 g$ f) B
| MCASP_RX_OVERRUN);- e; S! y' T* Q' T" ~0 `$ _
} static void I2SDataTxRxActivate(void)' O4 V! a4 k0 S9 D7 S
{& ^+ b; r+ n1 k, W
/* Start the clocks */* q; K5 d U$ j- ]1 T- @) b- f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% C" I0 ? l' nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) j8 r* q9 q- U# s( REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, a6 @ K) d3 M1 O) H' i$ E" FEDMA3_TRIG_MODE_EVENT);+ ^5 M$ y" @8 A. P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 ]) N6 \8 i" M! U* Q4 Q" bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# y( c0 R/ B4 K& }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% b/ F8 Y; H# \/ _$ h, kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 N, n! r: G1 u( M8 A- O- Y, vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- m5 I; \; ^$ U* ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 n/ S3 b$ `6 P. ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 B8 t3 t7 F' r, i& Z, O
} ' h2 |" h2 X5 j; A6 m( Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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