|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! v R/ }: u+ }input mcasp_ahclkx,
7 V* ]& X, s! e' o* `: _9 f! rinput mcasp_aclkx,! A' z2 ]: ?8 o8 x- [
input axr0,( X) H1 X4 V4 P. e% d( I
0 T+ [; L% B" p, x/ N- D
output mcasp_afsr,5 z# v& [3 U' L. A. v' h. w% f
output mcasp_ahclkr,; [5 V* l" l/ d! P+ s1 Q
output mcasp_aclkr,
9 c3 _: y7 I" [( Koutput axr1,' ^( D, S% L& }8 T9 Z$ d; v! I
assign mcasp_afsr = mcasp_afsx;# ^. j. ~" z1 m
assign mcasp_aclkr = mcasp_aclkx;
) J) }& m0 S0 _3 D2 G9 jassign mcasp_ahclkr = mcasp_ahclkx;
7 X0 K0 I3 G" t! @! w3 Passign axr1 = axr0;
2 `8 _' z* E* m% ]1 d) q9 w5 `: \& W/ n1 N- _. F+ W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * N* X/ ?4 ~; k! R
static void McASPI2SConfigure(void)
7 H9 K$ u& A |8 y' ^$ o/ Q{
0 U, f3 i# o8 k8 rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 g X. _& B: f# o- IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& ~" O6 h* _! _ S" e K3 }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 Q. |& |# C$ a( w7 a7 Z" S! XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" ^! T: u0 M9 w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" Z4 }" F5 j2 H( JMCASP_RX_MODE_DMA);
) ]" y2 f9 e/ jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 O1 R: J: \+ ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 ^1 \/ M7 }+ A# j$ _% h/ YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) k! I" J# z0 D4 @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 E$ k H9 n/ t8 W1 o) \: lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * I0 [% V) V0 @' {2 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: X1 f# k. I. a0 @, PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; G4 B# r8 C; R8 \9 c dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 Q; `3 G2 F; x' A* d* @, G. u7 bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 W4 B3 ^* @ S; L, E6 ]3 E6 a, I0x00, 0xFF); /* configure the clock for transmitter *// x8 T# q. k7 O3 H6 L5 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; L1 m w4 Z- c6 _" X' Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); f( A8 {* F' X0 Z6 f$ T! v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% ]4 u0 u0 ~: y+ q$ |3 Y0x00, 0xFF);% a9 K N" E+ t" h7 K
* U" r( P' H# y1 V2 F
/* Enable synchronization of RX and TX sections */
: u0 ^/ R$ w4 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 j: u1 D( \5 S% N9 b7 ^: GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 p$ w/ L& Q/ |- @, X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 n' O5 y! ^" ?& j% \) H* N# w** Set the serializers, Currently only one serializer is set as1 ~3 I: |1 S4 j4 o. Y( w7 Q7 m
** transmitter and one serializer as receiver.5 E( h0 @# w y& z/ {
*/
/ B4 k& P% c# j" TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 [- b: P' H% K2 `& B0 E2 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; k2 H+ w e/ X& M% d$ F+ u5 c
** Configure the McASP pins
3 @5 W0 ]% d8 z* m3 B; [ l. e; S/ w** Input - Frame Sync, Clock and Serializer Rx
; k. M% _0 h7 ?- I, _** Output - Serializer Tx is connected to the input of the codec
9 I7 f8 @8 j5 h4 q*/
: A% j: V( b7 U) FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. ^- E8 a! f: d8 p- ^9 Z( ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ o) S P9 [# ~5 k! l; V& NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: }6 M! o8 J- H9 M& |- |& _1 k. Z6 N
| MCASP_PIN_ACLKX8 x$ |5 O& \4 l5 n3 q- E
| MCASP_PIN_AHCLKX
/ ~+ ^5 s# _/ @7 F" K; D [' Z0 I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& K: @! y, F8 R# S8 V* U' F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 l) M9 |8 @. ?- r7 g1 m _| MCASP_TX_CLKFAIL
7 M. h, ^4 u' e( E| MCASP_TX_SYNCERROR
1 Q$ v$ Z6 {- a+ m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: Q* d& ^, W2 @| MCASP_RX_CLKFAIL
+ f6 F1 P8 e, i$ x& @7 }( Q| MCASP_RX_SYNCERROR
" g1 K2 x) s, Y; n| MCASP_RX_OVERRUN);
% D. o. r$ g6 r* J6 ]7 C} static void I2SDataTxRxActivate(void)/ P) ` y' W% D1 N9 i
{: r5 o) n y; s$ s/ ^
/* Start the clocks */2 E& Q8 J; U6 y: J1 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 X6 s4 u: x' }+ c% Q7 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 @) q6 S) }# U6 ?2 \9 j1 R Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, Q" `2 w' I% q9 @ N: W# S2 q: U- M
EDMA3_TRIG_MODE_EVENT);& u% J8 k! ^9 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 ?6 p/ V! G5 mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 ?% a$ t5 y' a; g; K+ V( _% |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 _: a& }# G4 X% ~# f- k! v0 x% h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: c5 d" K! G3 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 h. G# j( ]2 _, f* g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 n3 I1 O( E( r6 B. K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" h. J" I$ m- Y+ i# I8 R* o} $ f8 v$ c4 b6 [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 w' ?; u6 ]" j' R9 k6 J* x |