|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& G3 K( R) y* V, rinput mcasp_ahclkx,
. U( v" I, m5 F4 W" m uinput mcasp_aclkx,
8 U6 d. @5 v G' _input axr0,
9 C3 G5 C" \# g8 S! [: n2 M g- X2 P5 W! b
output mcasp_afsr,0 R4 r: }# ^) U; R* f
output mcasp_ahclkr,
+ n8 [7 U ^) r3 a0 _/ Koutput mcasp_aclkr,& a. F" O+ K5 W8 l, m
output axr1,
& S( A( S. }# V2 v6 T assign mcasp_afsr = mcasp_afsx;) G+ a2 i3 _- j. y' l
assign mcasp_aclkr = mcasp_aclkx;
, Q# s0 j& i8 k9 e( F9 N' Hassign mcasp_ahclkr = mcasp_ahclkx;
7 f' f9 d% }- w% t a; G. B+ yassign axr1 = axr0; 9 O& G( K# ?9 d9 T5 V; [4 N
/ I' I; F; s& d' s6 t# W4 H3 M) x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 N! ` | Y; G7 {static void McASPI2SConfigure(void)$ d' ?" S" R, |' T
{6 D& @1 C2 V9 F8 i/ ?( b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 S1 y' t1 V- T: ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; W& g& Q Z$ jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 W0 P: v2 @, y' k- `/ C/ AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# h- h; V0 I8 C- z* p9 f) f' e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 q% F% T* w8 u6 s4 o4 G
MCASP_RX_MODE_DMA);
# V& [4 d) k$ P* f! MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- _( c7 T* i# ]1 h( F) l0 I, _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 I( ` Y/ N. ^/ r3 M' }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& B% ?( f# o, C6 i5 s# T% K9 U7 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( X8 u, U# h# l" C) z8 g) T1 kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / e8 X4 n0 \/ j- U! e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 \0 F! m! a! I1 o; o; r8 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% Z" Q4 P+ F, o; T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % i* c% C# p* G$ N7 \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, c4 ^ a; K+ j- t& O7 f0x00, 0xFF); /* configure the clock for transmitter */
5 q* ?$ h9 U9 ~; u0 Y8 zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( I1 _- {) R; {, X6 V# [, W7 m4 b3 [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ l- q# u2 P$ ~; y( C) P' l+ nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 p& x7 h6 A6 S9 _
0x00, 0xFF);
/ E. O! z A& B V- Q$ a. m( P
6 L& j" s8 y3 w, ?9 ~& p: t4 Q# J) b/* Enable synchronization of RX and TX sections */
; t# R4 [9 J7 R e& \5 f9 M. w) G: vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ N* z! f+ O6 \0 ?7 s6 UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); Y8 g5 a7 [8 D& t1 W: L) l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! L: o. B) a( @9 r+ v k** Set the serializers, Currently only one serializer is set as; g6 j9 c- B' L( L# ^7 d
** transmitter and one serializer as receiver.1 c% C& @" i( l
*/$ E6 y) E0 e# B* \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, B- J0 v* [! r6 X- `' D$ F' A- F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, j# U/ T8 @' A: b- x" Z3 v5 ?9 s** Configure the McASP pins # {8 |& G9 @+ Z, I% d; z: e4 A) H( G# |
** Input - Frame Sync, Clock and Serializer Rx. }# E# l* Z$ _* e. h
** Output - Serializer Tx is connected to the input of the codec 7 K1 N6 B0 m4 V j! V% F
*/
& M ?9 L- i D1 e; }) PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, \' `& q/ f O3 e9 ]; _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 ?- J9 e j4 ^0 Y `# v: i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 }% T9 g, d* a# _| MCASP_PIN_ACLKX- q0 [" X: Z& D+ Q2 O5 V2 q3 V
| MCASP_PIN_AHCLKX( Z/ M1 N0 \& d5 G3 i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 P# ~4 K/ M7 G) [( [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) k2 x9 ], _5 [* t* m& z
| MCASP_TX_CLKFAIL
' Z( a$ `$ i h/ x) B| MCASP_TX_SYNCERROR
0 f( R; h- V9 T0 M% h! |: l" o: w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 Z/ L' W. O3 a- a. v8 b( D
| MCASP_RX_CLKFAIL( u% v1 H- ?% e' w+ _
| MCASP_RX_SYNCERROR
- M& c. d6 F {8 {0 q| MCASP_RX_OVERRUN);
& L$ ]" V- J5 k8 @( o' c2 A} static void I2SDataTxRxActivate(void)% E# F8 B# ~, _* l
{
0 |0 a) ~! u7 `9 N; j/* Start the clocks */
' G ?& i1 P5 j! fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 n/ b7 K. d4 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% d ^) h7 w$ M: a6 ?1 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- w! j: P! o# o- |( r
EDMA3_TRIG_MODE_EVENT);5 \7 K, a) S7 l0 t8 L8 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' n& q3 Q/ }3 ^- J) G$ e- Z: wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 O: i" o+ C6 ^8 q0 @% }8 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) e( U4 j! w6 o! x2 C, G+ f: r1 e. f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 O7 g1 M! D4 p6 e3 Y2 mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" S6 O6 V# d& r* P6 |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) {# C0 S. z# _5 [1 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ w1 t; G/ U" n8 ]4 D} , C: H; M+ i6 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; `+ w. s- K5 }2 O" F |