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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% E+ v q2 [4 H' R; ^
input mcasp_ahclkx,
- b* U: O: k- N/ T* _9 Minput mcasp_aclkx,
! i* T, {# l! h# ~# p Oinput axr0,
0 [2 Q$ `5 p* z0 Q9 b) R" ~3 _: S. [3 J2 T- g1 n% j
output mcasp_afsr,6 F h2 W: o. D0 ?, b4 Z, \ R
output mcasp_ahclkr,
* {( r1 P; E1 |6 koutput mcasp_aclkr,
1 J0 E ~1 n7 w9 o) R0 eoutput axr1,
' ^( x: J# V" ^9 Q! S3 ^: H; I assign mcasp_afsr = mcasp_afsx;* {) K8 t2 u& L" [% s# N( v
assign mcasp_aclkr = mcasp_aclkx;3 E5 Y& S. e1 {9 e3 o. p3 f
assign mcasp_ahclkr = mcasp_ahclkx;
4 b' p6 ?* b m4 Y+ H0 \% u+ Lassign axr1 = axr0; . w# E( J- A: q9 Q3 M
0 U& O$ O/ G8 U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 n+ |% b6 \( y# z3 G
static void McASPI2SConfigure(void)
% k7 B4 F/ R0 m3 ]: s' w' r{- J. X/ k7 W* b7 a( {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# ]* y7 W4 F* M, Z# ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 t. T! l+ [2 h5 A% s) r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) m2 J1 g3 y- H3 i8 T' @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 w4 ]& O! I3 m- s e; t4 aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 s. M; n, z& g N& ?: r$ @MCASP_RX_MODE_DMA);: `3 o3 ^; [* F/ u! R4 b5 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" J+ |2 v* b4 a$ R2 q0 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 o& ]2 a- T+ q' i1 O/ gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) a- N3 E- w% U0 o# n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; X" [3 s0 H; {/ g- e3 c! kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 I S8 e' X F$ a. v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# t3 @ d; l+ OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 c( c( S6 n6 L: ?5 E- j6 ?, M9 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 c" r# |& O; V, P/ Q; ?, GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% C0 ]3 u ?+ g; P1 }3 ~0x00, 0xFF); /* configure the clock for transmitter */+ V" o( A& A" E4 Z; K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- r: p, S( T) `& lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& X& W8 d2 l5 K1 b' j7 k% TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! G$ g6 _- s) ^( f0x00, 0xFF);$ e8 h, Y6 ?, Y
+ \. T5 ^9 @$ f
/* Enable synchronization of RX and TX sections */
4 u3 F" y% @, v! ?& o6 r8 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& @2 _% E0 v) {- \8 V Z, QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& e) A$ |6 t* fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& @# O& X" M& C** Set the serializers, Currently only one serializer is set as( G2 f& _+ ?$ M0 v2 R
** transmitter and one serializer as receiver.. {0 a9 c2 C, G; n/ k5 m8 o
*/
7 C' {. _& ?+ a. qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* x# w& |0 A- e- X0 m2 x" ^1 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 E/ O! \4 I9 O9 q; y5 W2 f
** Configure the McASP pins
0 i. C- R+ A+ `5 G. g** Input - Frame Sync, Clock and Serializer Rx6 [$ I0 Z F& u, @5 n" |
** Output - Serializer Tx is connected to the input of the codec
$ ~0 Y( d. b. F0 a a4 u*/( `% o) q( H! r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* i7 }- d9 L- s$ C4 ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
Y- p3 ~% h; ]6 HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 ^7 K" V" |8 C9 [! J2 I& B/ {
| MCASP_PIN_ACLKX
/ }) M6 g* | @: l/ w/ U7 X| MCASP_PIN_AHCLKX
. y, s2 B$ f7 F3 t# C) c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! y, s+ c4 @1 d: ]" Q2 UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; o/ }" l1 u. G7 `
| MCASP_TX_CLKFAIL * w: i$ }. E0 d Y, g
| MCASP_TX_SYNCERROR
# W; z# Z Q; x/ n: @2 F9 a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! f8 m! e+ j0 w6 G6 J2 a| MCASP_RX_CLKFAIL& L/ [! h: R9 P- I9 S
| MCASP_RX_SYNCERROR
5 ~' ^: Y% t3 o; Y, p# O| MCASP_RX_OVERRUN);0 {5 O' l0 e& r9 F& Z1 {! G/ a0 x5 R
} static void I2SDataTxRxActivate(void)+ f: x& a9 W& Z3 A
{
% j$ t9 i/ R2 Z/* Start the clocks */
: l7 V3 e8 f/ d( }& NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) s4 O3 K2 e# y c, Y8 n2 mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' {4 o! ~& m$ m, a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 I8 k8 c P' `" a% [% v( i9 \0 `5 SEDMA3_TRIG_MODE_EVENT);" ^# @0 e$ Z o( G! c- O: j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ N2 A+ ~* Z" Z' tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; W" P1 {6 Y R K3 l- o' ^" {9 }3 VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 M1 p1 C9 y$ P0 ~2 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 z P& \( ]+ c g5 G/ |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 M9 b3 c2 B* RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& U0 S: g! C5 ]5 @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: X! x* Q7 v1 i: `, r
}
7 Z4 {. m0 z9 r0 S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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