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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," `# p; V1 i+ T) |* {* n# G' ?
input mcasp_ahclkx,! v' v; ~* }; c/ G; o% H
input mcasp_aclkx,
$ x( R8 a8 n% x# ~* t; K$ v. qinput axr0,5 t3 j* r, k- i$ R+ G
% T# N% Q, Q, j+ ]3 ^output mcasp_afsr,
3 |2 n* n- `& E0 goutput mcasp_ahclkr,- n7 C6 Y# o$ \! h' f( L
output mcasp_aclkr,1 W$ }; o+ L3 V) ~+ H& r$ L9 |( c
output axr1,
. q# ^2 v4 ~) w1 o9 ~ assign mcasp_afsr = mcasp_afsx;
4 D# w! a+ t" |0 u9 v& D, ?* Zassign mcasp_aclkr = mcasp_aclkx;! ]+ n1 z/ f4 m0 R- u% k
assign mcasp_ahclkr = mcasp_ahclkx;
. a P" l# V G* R. }2 Qassign axr1 = axr0; - ~* C: I9 V2 b7 R
% o; A4 X# [& f6 O: |! S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % [8 Y) c5 p7 m6 x
static void McASPI2SConfigure(void)
! k' I! m; y, Q: R" I! d/ W; }{! c: Q/ x0 J3 B+ p3 u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 e) b J7 m5 N/ |+ r* _7 @, N$ i0 [/ x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* o4 @# p1 N+ p9 E$ o- J$ R i9 J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( ~& {. F1 J; o' j' a ]/ f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! e2 ], N5 l) g! e$ t" `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 Y4 V9 @) E9 L2 FMCASP_RX_MODE_DMA);
* C" r' a3 i3 ?1 x5 Z3 I$ d7 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 |9 h u' \" Y2 l& ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( _5 P9 U3 o* a3 m$ l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 R( m) v: M) c3 b6 N+ G) N. ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" ]8 Z' P' D: o0 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 }, ~ ^3 b2 P8 s6 s7 l; v3 WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ A& _4 M+ |6 c- a) w- p( aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* z6 b8 ], \" q2 t) dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) }8 G% o. K7 i# Z+ l2 ~! g- Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ q( {, t4 I# p, x r& C7 L/ h
0x00, 0xFF); /* configure the clock for transmitter */
- B& c; r" M! Y: D9 b DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 u7 S( e3 S9 |7 Z1 V0 j2 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( p- D7 p1 B0 \& B& r% \8 J/ t% Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) f* Y2 A+ r+ N# b
0x00, 0xFF);
3 K) f/ F/ d& @' k
k2 c6 _3 O1 J" v/* Enable synchronization of RX and TX sections */
~$ @- U# s: T# wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% G& ]0 j* q1 C4 R- t* r- C: aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' i* r3 b, A- p- P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 F1 g6 Y% E1 s5 l% Z k** Set the serializers, Currently only one serializer is set as1 C/ B6 u4 r' w, `) q
** transmitter and one serializer as receiver.% k4 f* m1 _7 E! I2 J) p
*/6 b x0 |: s/ p/ I& T: C2 V9 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 e! c8 L2 Y/ N0 D f) j- T* \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 ~0 h2 u$ M! F" w5 d9 |
** Configure the McASP pins
4 Q- ~8 Q7 B" O7 d" M( \; |0 D# ~** Input - Frame Sync, Clock and Serializer Rx' }& X2 Y1 D$ O8 L* e0 R
** Output - Serializer Tx is connected to the input of the codec
+ h$ Z9 A$ y, @, K- W. R' v*/
% G5 H6 m4 a# l+ H2 R. }0 `8 ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* K$ ^* g+ T8 ^1 Y# N( _/ x& BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! J5 d; v1 W* z! ~8 ?& k1 Q: z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 _( _; ]7 b- O. b% {+ _% x! O* o2 F$ ^4 _| MCASP_PIN_ACLKX k7 ?! w) e& p1 U) \
| MCASP_PIN_AHCLKX1 i* @; t( {0 }; Z$ W% r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 ^: f5 x+ K7 x6 R: \" ]/ L0 g( w+ mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 @! p" y7 C' \; R4 d0 g8 t- O
| MCASP_TX_CLKFAIL
5 }0 W; @. r! o* T7 {" q& e$ O( v| MCASP_TX_SYNCERROR
% u( d5 I- {# X% j- r' l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! D4 @* ` L8 |% n| MCASP_RX_CLKFAIL
/ v% u5 G# u' G) M6 m b| MCASP_RX_SYNCERROR
7 O4 ?$ W% @+ k" w, t| MCASP_RX_OVERRUN);
$ L J# M( ^3 t$ @} static void I2SDataTxRxActivate(void). n/ _' Q$ V- t0 {' C
{1 t- n+ |: W+ N1 @! |
/* Start the clocks */
3 [* p4 ^7 t- {1 [/ b( s, v' `: WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- f- I* Q3 P; ]4 Q: W% HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, S9 i, ]( V& n* k1 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 _. `; f! O; R# c: l$ a
EDMA3_TRIG_MODE_EVENT);/ j |0 c; B6 _! V- t3 |7 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 v( c% r/ B6 ]' P; }! M7 Y5 ~% T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 ]* `7 _$ ^/ z: OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; e2 i: l/ { b; r' ~/ p, bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( X/ |: d7 N, G- y X) I; `, G/ L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 b/ c% ?1 w% ^% [8 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ k" e4 F$ B y: O3 [8 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ T9 l7 N5 ^" h$ N+ @}
9 ?( P; o5 A, ?! P" _7 D8 Y1 `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . b7 l/ ^; |. ]9 y" E' _! @
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