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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# S( V. O6 m9 k' B5 O- T9 H3 ?, ?
input mcasp_ahclkx,/ p/ I% K4 ?' k. s
input mcasp_aclkx,$ b6 Y% ~4 H' v) Y+ W# m( U
input axr0,
: K% W: R! Q' M* [3 Y6 a
- D. @, u6 J; T$ L2 u- zoutput mcasp_afsr,/ j, w: \6 j% y" ^8 c
output mcasp_ahclkr,( z% H0 Q& \, m1 m9 B! T1 z, L& I
output mcasp_aclkr,
6 J( y$ f7 }( f9 z! v4 I3 w$ i. Youtput axr1,4 F" a$ R) ^7 d, M1 ]9 Y* s
assign mcasp_afsr = mcasp_afsx;
. r& S7 ^: k3 o/ x8 |- xassign mcasp_aclkr = mcasp_aclkx;5 M4 Z/ ]3 M# K* {5 ^8 Y
assign mcasp_ahclkr = mcasp_ahclkx;
! B9 u) F$ I/ Cassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 B/ p2 \* l5 n' t2 h- \
static void McASPI2SConfigure(void)
6 u9 h% Y3 t8 u( e1 A) @{
& R. d, [7 ^" I! M6 ~. q4 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 v/ R( C( K( O# B6 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; \# D2 \& z" Z; z& z7 X/ I2 J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
I- Y+ O8 z7 h! R, |* S7 [% tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% @+ Z& D" z6 w, c' L$ `; a, xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 k% s, t0 p R# J0 ZMCASP_RX_MODE_DMA);
2 P8 q* h8 y3 e' jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" X3 S. j1 V6 _3 s D1 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( @( F4 e/ T: b9 u& |; t$ ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 l3 w" f) }8 q9 H5 FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 U3 C; S3 l/ }5 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% ^) L4 x$ m+ ]: h( UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* V" ^; W3 `5 E% @9 O8 p4 _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. r6 j- A; | L6 l- ~9 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + s- j+ D% r1 I. z5 \. p% v! S) K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* D( K$ |8 |3 P& [7 h
0x00, 0xFF); /* configure the clock for transmitter */
6 n! |* D+ Z6 M. j4 S a( dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: _6 N! `. ^* ~# ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - x% c4 O( {9 H% k" e" g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," J4 W3 ^ {8 G& t
0x00, 0xFF);
- c" J! T- ^2 X& [' K
! w7 |5 y* y: O9 F- ?% e' \/* Enable synchronization of RX and TX sections */
' I+ W+ n; { f0 {: p* V, J3 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; b' {( L0 A" h6 N- i/ z' LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 |- i: W) E( a$ H/ L" S# B; CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& N' R8 p5 ?1 ]' B1 Z
** Set the serializers, Currently only one serializer is set as
0 w J' {9 u* O* T** transmitter and one serializer as receiver." G& c. z6 |6 Z# Y) s# I
*/
5 l Z& y+ ^3 t: Y1 i' u" ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( b; H# l5 f8 q& S: v, m4 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. F% L# b" A' V0 Z0 x, D* V9 Q** Configure the McASP pins
2 c; W' t2 y. k* V' q6 r** Input - Frame Sync, Clock and Serializer Rx4 L' m! o9 ^8 q( u: }5 ~1 P
** Output - Serializer Tx is connected to the input of the codec ; U* v1 F6 E; e. }6 ^
*/
0 u* Z3 c# B/ D) VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 F6 A a$ R6 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ @! G! g- Y) Z# F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 a0 K3 \1 [* R. E; c! n \6 R- X _
| MCASP_PIN_ACLKX
" _' w" T( t9 V/ S5 u+ n6 _0 Z| MCASP_PIN_AHCLKX
- G1 l; i& m4 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- X* \0 j+ a& v) n! ]2 D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 [3 G: R1 ~- K, P3 {2 r: r3 ^| MCASP_TX_CLKFAIL
) V& z, s4 h; J$ O| MCASP_TX_SYNCERROR
) V3 i7 E8 p L4 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / J0 ?6 z K4 u" y
| MCASP_RX_CLKFAIL7 }. ^5 i; d- f3 z3 k9 j% ]; ~/ i
| MCASP_RX_SYNCERROR ( {& ]) z2 d- C4 Y; v: j4 L- M
| MCASP_RX_OVERRUN);+ P! A+ _- R; l0 `. H$ n2 U) s
} static void I2SDataTxRxActivate(void)$ L* B; [$ ]4 @: l! R5 ` l
{% }. Z# l" P7 f7 ^
/* Start the clocks */4 r1 v' g- k( F; Y N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" l1 v" R. @$ ^5 ^/ O+ bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 G( O4 X# `. k! b3 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ l6 ]7 E( K5 R0 dEDMA3_TRIG_MODE_EVENT);
1 q/ K4 y/ p$ o1 @% J3 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " P4 j# ]6 ]8 R: D7 G" l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- H0 R6 T0 \5 K ?7 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 a- u6 m' h+ W7 ^, o rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. K1 v2 X5 W. s5 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. Q6 l' K2 I9 T- L1 VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& c* q- i a& M2 w, ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 m$ L6 [, A! O7 d% k8 u7 X
}
, B( o/ q5 e' s% r% A; ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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