|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, d, l5 J. [3 u. \: p. t2 T( T7 Minput mcasp_ahclkx,
3 m0 s% v- @; q; Q) v: b/ K( ginput mcasp_aclkx,' |4 u4 Z, J& v" Z9 q4 g. H* f
input axr0,
) K9 t" q* {1 m. N8 O' H: I
0 u9 o& s" ^ O( u1 S+ B9 `output mcasp_afsr,
2 T' m. w- c+ D# h9 p9 L2 j6 A7 `output mcasp_ahclkr,2 [- ~9 l5 a6 C* P# @( ]% k) u
output mcasp_aclkr,
' d9 }7 c$ n. i. ~% R! m; j! B' Uoutput axr1,0 a: Z" \2 H4 u: ^9 ^
assign mcasp_afsr = mcasp_afsx;
0 e- L! e+ o3 e7 [assign mcasp_aclkr = mcasp_aclkx;
( e4 q! r/ T$ ^: i+ s& Gassign mcasp_ahclkr = mcasp_ahclkx;
( z7 j1 G+ d* u$ P( ` sassign axr1 = axr0;
6 a. P/ A( F S9 e. e, y2 z
) |# j4 {/ H/ ]5 w o- E, @- N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 K; C/ S6 T; B( f+ ^
static void McASPI2SConfigure(void)
3 Z1 I" E* W$ N3 d. M& |{
j0 B% B6 p5 m1 j9 R aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% K& Y' T& f+ G+ R. IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 v, R8 i6 { F( ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' v9 {& `" L g! `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& n8 N# L& Z* f, W, G/ f! zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ d$ B9 [) j2 t- `; vMCASP_RX_MODE_DMA);
2 q) i" Q$ A4 j0 H0 ]5 C9 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 }" s( |: L/ @8 B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 C) E$ ?0 U9 L1 ?( tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , N. n% ?9 J& S) f8 Q6 f+ I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: U; z8 Q' b. K6 E, h; T; D, Y- T3 {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . A% S. S( v4 q9 o+ B- ^% X, h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* F( f! ]" ^8 j1 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: c8 U4 J1 K' o! y; F) X6 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' y% Q7 C! k0 a# u3 E4 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: u9 }4 \. p6 g" @$ Y; C4 Z) {
0x00, 0xFF); /* configure the clock for transmitter */
% |4 g9 _+ U: ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% n( I6 r6 H" a, zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 o" V; b. f/ Y- L2 x$ AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% P# N+ ~( S+ m2 q5 d. V$ ^& Y
0x00, 0xFF);
. f7 J" j4 ]8 ?# L. `/ J; Q% a! T! Q
/* Enable synchronization of RX and TX sections */
/ ]% v' e* P$ \9 sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// |; m- g: N, r% J6 g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: c7 S" M, N8 r5 ?0 a- O0 D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! F l) M+ ~* n+ R6 p9 ?** Set the serializers, Currently only one serializer is set as
: K1 ~' Y/ O% @$ {$ \5 N# ?! Z$ j** transmitter and one serializer as receiver.- W, k0 y% H2 a! H. |
*/' G5 {: S2 |0 F7 v1 W% }. w. T4 a* L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; }; Q: s) X8 K) Q+ SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ W' P* ^ Q' k6 B& ^0 j** Configure the McASP pins
% t% p. |+ ?) G. a/ ~! I+ z** Input - Frame Sync, Clock and Serializer Rx( W8 M" ^ g e9 t, g3 I4 u4 z
** Output - Serializer Tx is connected to the input of the codec
+ h; H/ e: c ~. |*/
% j8 W2 J* c3 r: r0 yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# y; J1 |' |- UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); t" J: M9 Q3 [2 b- U' O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 h7 F1 y0 \! k2 S, l| MCASP_PIN_ACLKX1 s0 B6 G9 s& M8 P; c+ \2 e' r
| MCASP_PIN_AHCLKX
% n) V* h/ R2 T7 Q0 g. g6 u- b( l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 [- l( c T& ]: m% Z" x$ {2 c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * s; l3 {9 Q2 P" g% Q, E
| MCASP_TX_CLKFAIL 0 Q" T" h6 \8 Y
| MCASP_TX_SYNCERROR
% d6 e# S6 g- N: j; S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
Y9 ~3 u q& ~8 E! m: ?| MCASP_RX_CLKFAIL
# R( `% ? H, R/ \| MCASP_RX_SYNCERROR 1 ]7 \: f5 @1 {7 o0 I+ A
| MCASP_RX_OVERRUN);
8 d2 F7 J. l5 F& p# N} static void I2SDataTxRxActivate(void)
1 r0 u$ I1 D3 K7 d1 G9 ^{3 y% ?. F1 i# @5 M4 @4 u9 c
/* Start the clocks */
: t5 p1 b( C9 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: C" [7 v- v1 d4 X3 r; M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 h2 S' l( s7 j) mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 X. v" w4 G, ^; t5 G: |( M
EDMA3_TRIG_MODE_EVENT);
8 I# e4 S3 |1 ^& J6 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* q) ?7 n l1 A' e0 WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& D- D; v+ E" t. CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ L, F" q/ H8 D* {9 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. _1 E& H" o) c6 K) ^$ F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ i, c1 ~, O# m" S+ L C# z7 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% ]) j8 f" C6 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 [% v) S) }/ j
} 1 P; \3 c6 X# V. i% I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - l; k2 v: h( a% X- Z! s0 q/ `
|