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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# Q" d0 ?/ k# R4 J& t
input mcasp_ahclkx,
3 Q: ?" |1 S6 ~8 rinput mcasp_aclkx,& }9 a- p/ j4 i
input axr0,
9 M- B( Q8 {" Q; H( l% C
6 @2 Q/ F/ J. j( m, w6 coutput mcasp_afsr,/ }7 n7 N% z+ Z T- m. z
output mcasp_ahclkr,
+ B# h: A4 Y! b, F2 f6 c3 }9 [output mcasp_aclkr,$ s# w; Q9 h+ p6 H6 W4 `( W: s$ q6 g8 A
output axr1,) q4 c/ P7 O% ^$ r- ~# C
assign mcasp_afsr = mcasp_afsx;3 _8 y" z* ]: p, y- D! G
assign mcasp_aclkr = mcasp_aclkx;4 R G. G3 G$ r" ~( M8 K
assign mcasp_ahclkr = mcasp_ahclkx;
; k; z% q# s- k' B4 Y& E/ Xassign axr1 = axr0; 5 m* I& v3 S b5 M3 h; Q7 o
( n6 r0 f/ U$ P: N+ d& p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 ?( ?, V, j, ?! R
static void McASPI2SConfigure(void)
0 r. m3 @6 I4 u* X8 r) p{
2 t2 `8 s# S: N2 EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ t m* }" `/ RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 M: c8 i0 m2 `: o, f9 D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. k% j3 a. j( z4 p. _" mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 g% B' W9 G% }$ d CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 R3 H8 `8 ?' [; u! a6 VMCASP_RX_MODE_DMA);
1 O N! \+ B E& k6 @6 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 |1 }9 T. T' Y" n+ u- R2 M- F. ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: R5 p# ?4 K1 {& {: [4 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) T" j( R3 C' f7 c' o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# D8 s9 n" H) _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 N- a4 j# [6 w* {& k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- b' `* K6 I7 R2 g* S- x* ^ F8 \0 I6 E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ I, h2 L/ {9 J' s( c; f/ JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : d1 A+ r2 k% S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 V" X# i, v1 E) U' [
0x00, 0xFF); /* configure the clock for transmitter */
, k" K' R* Z& M. {6 I$ A% c- zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, w1 [! o; }, l; p, d5 d2 hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % w9 E9 |- N9 J# w" w$ @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& o; x' _2 \& S# ]
0x00, 0xFF);& S5 c/ a' g0 w/ q% `: R2 x: L9 Z
& B$ `4 B# ~1 U( F/* Enable synchronization of RX and TX sections */
# s5 v" I! {8 F% \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ c" S( ^6 J! h% i) G, LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 V2 t! E. ~8 @+ L7 GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 q1 J$ M( m5 w: h3 }3 B" ~4 B
** Set the serializers, Currently only one serializer is set as
/ j. o5 K/ @; N& {$ g5 I** transmitter and one serializer as receiver.- D5 c H, w1 P3 X6 w
*/; ~# g0 ^: R4 I. T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 m, e- c) y! J) U* Y# K1 V" S8 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% q I( y: W& E; @3 D. A2 c: W
** Configure the McASP pins
; \: \3 s0 \: G: y4 T9 M/ x** Input - Frame Sync, Clock and Serializer Rx) a4 y2 ^8 @3 |6 [6 M& `; ^9 D" K
** Output - Serializer Tx is connected to the input of the codec
4 N3 D# |7 y9 T*/
$ |8 |6 @5 L2 X% l e) RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 J# S, X0 N5 E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 L0 F) J- U: K$ ~5 m' i- j- EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! U! ^8 ^* F0 V7 g
| MCASP_PIN_ACLKX9 O. I3 j A" w
| MCASP_PIN_AHCLKX, }- B, a: q- `/ S$ B; R4 S( Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" g! i+ o- W \2 Q. q! NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 x* t1 A+ f2 i" V1 _: v: \| MCASP_TX_CLKFAIL
1 c2 z) |! k5 ~6 p( q| MCASP_TX_SYNCERROR
2 l/ w! @2 g5 y2 v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 S4 U- q' c+ F/ g( [6 j/ P. Z| MCASP_RX_CLKFAIL
& i5 Q5 \1 s6 N( B| MCASP_RX_SYNCERROR 9 \' y' X1 |# p- X3 \; U7 u7 v
| MCASP_RX_OVERRUN);
& }" x2 U9 n0 C( l} static void I2SDataTxRxActivate(void)
& _+ U) w Y$ |7 z+ C5 x+ @. s{
. i B7 x* A3 E K" b. n; `/* Start the clocks */% |1 w3 y1 i2 e+ D, a& f. i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 J7 }4 p% C/ C0 p2 qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 O8 R; D% ?& j" P# h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; o) h3 H$ Y2 G5 u
EDMA3_TRIG_MODE_EVENT);
+ \& [ u: }! }& O0 Y& A7 U) lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( } ?% Q& I1 W- V( z+ J# `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: H2 f+ E0 y* m( u5 @1 a: UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 R- I5 [% ^/ _9 f! Q4 @7 Q: DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( I' i" p; G) I5 C& E* ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 j. g! H# e$ u7 o5 JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* ^- d! E5 p, f) OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& Y' {: I9 y$ k
}
- ^0 B% r7 T7 x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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