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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ f) J+ N8 k- D8 P
input mcasp_ahclkx,
, G. a5 w5 H0 L4 M. |2 ~- r; Xinput mcasp_aclkx,6 P: N9 | f' j) r
input axr0,/ T8 K0 @' P- Q/ W
( J. p5 @: W, _9 D7 t+ A
output mcasp_afsr,
d1 X0 U9 P# @0 \" x6 T4 _+ Loutput mcasp_ahclkr,
" j# e# x) w5 r* j6 Joutput mcasp_aclkr,
$ ~: }2 ]$ e, ~/ l/ woutput axr1,
: h3 s; k5 m( R( k ^- p2 H9 K( i- C assign mcasp_afsr = mcasp_afsx;, L' Y7 `) L5 A/ i! B f4 [
assign mcasp_aclkr = mcasp_aclkx;
# b4 Y" d( H8 H% U4 a$ W, Cassign mcasp_ahclkr = mcasp_ahclkx;
/ }) ?! e ?, }& t9 Y; @, _( K' ^assign axr1 = axr0; , X& c4 n; g6 y) i
" r, m, Y$ [. Y/ E- O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 _* N! l% C( T8 ]" v
static void McASPI2SConfigure(void)
, {2 K. C, a4 o! t! w* X{$ L( t+ T5 G! ]! J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: w4 C6 ]4 Q8 p" vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ B" ? o" M) y9 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 g& L, z' h3 \: U J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 q9 j: u6 X6 b( n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) {1 n1 b, h7 \
MCASP_RX_MODE_DMA);
0 B& R7 e( g5 B! X2 y& _% iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) p! @ G. U2 k3 {& e7 s t0 cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 |1 v" _7 M' Z; V5 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # }6 N. Z9 r* l; _% ~6 m& \4 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 i4 Q% ^& U' i) E) r& A1 a( `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: B! o! t$ N2 B0 g( O" wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) g+ h! t9 b4 ^! |4 HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 r$ k& W+ w: Q; v5 T3 Q |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 t. [: `. n* l. u. o3 i2 GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, c) p1 H9 U% E% O0x00, 0xFF); /* configure the clock for transmitter */, a; {$ G; M {0 @, R+ D, m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 G- b) T. F/ A5 ]3 r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - L3 o: x- P) l) R/ t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* j% f6 L0 t( b
0x00, 0xFF);
6 v0 g5 a4 q& y; o) l; y
( a' Y H3 V( i/* Enable synchronization of RX and TX sections */ " }# z4 L# q) h9 [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ n& R" H# u g' o, c/ q; b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 L# y5 g. o4 \4 h% t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; d9 C5 l% Q* l1 k1 O) |" {* M
** Set the serializers, Currently only one serializer is set as# J4 K7 n5 ?% h r( E! l! z- r
** transmitter and one serializer as receiver.* v6 L4 H9 T% ~+ U/ y- \0 c
*/6 u% \, g% H1 q7 F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. |! m( @( j% c- i5 \' sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! t& ]1 E& t8 V/ ~$ |
** Configure the McASP pins
u* d) \. ?! }8 X1 V4 a' g4 A** Input - Frame Sync, Clock and Serializer Rx& ^ L6 d7 }) p: F
** Output - Serializer Tx is connected to the input of the codec % F. H% Q0 o, J) r8 H
*/
" X3 d7 q. k- K8 E/ X0 C+ A; K" uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) k# b" @2 U F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( u7 O/ C( ?3 P. L8 O& Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: q" k# p3 Y. q: L
| MCASP_PIN_ACLKX
i, ~; B3 F* C, ~0 a+ ~- c2 p| MCASP_PIN_AHCLKX, ]0 m: P# D! ~8 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ x! h" |) g* u {2 {4 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, |& m' n0 v0 q+ _& W8 Q' U+ W* z| MCASP_TX_CLKFAIL
- K e' i" `7 f9 a# D1 K| MCASP_TX_SYNCERROR' }; ^" U$ F9 b6 b6 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 ~( y; p1 l2 t6 _2 T: J7 a
| MCASP_RX_CLKFAIL
) s. @5 T4 B, u, l| MCASP_RX_SYNCERROR
4 `4 n( H1 Y/ t6 c| MCASP_RX_OVERRUN);
7 K! _- _7 w: R0 O) y4 d* Y} static void I2SDataTxRxActivate(void)
) B8 r6 h- g% x4 J{8 I9 X9 ?! x- I) b' P2 @
/* Start the clocks */
' n4 z) P, o: h. L: A+ {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! Y+ W& A" {0 t( a0 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' D2 T& v3 D) h6 X# b9 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 h% \: r$ X7 q2 S: p! w
EDMA3_TRIG_MODE_EVENT);
6 e6 B9 n/ l/ f7 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # ?) I0 k! P+ t- x( }+ ]# \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 i& X9 O& m* j# ~7 x, u z9 }* M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& v0 K* N% A: w" M" GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- N4 x4 T. @* O0 `3 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 E, q2 [# ]' Z- IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ T5 P9 U' g" dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. L# ]! g: w# O) c3 N% M0 ~: j
}
1 p3 g" Q+ [" a2 N' C# `6 C* |% _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ n1 s3 j9 Q# E0 L) i: D
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