MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
6 x1 u8 O- f0 b% z' c7 f4 Winput axr0,
6 Z" t/ M7 R5 O- H6 G
output mcasp_afsr,
  f$ H1 l, P3 K# I3 N$ Ooutput mcasp_ahclkr,
output mcasp_aclkr,
+ L/ _5 H& H, e2 ?' S6 s! A7 ?& H$ |output axr1,

assign mcasp_afsr = mcasp_afsx;
2 G2 r" Y% w( z- X# r) O. x3 z$ Uassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

3 ?/ W& \2 p7 S9 U; h: R

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
$ o' H2 i9 Z" [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* d4 I! g7 o+ e$ V# [; [! l$ HMCASP_RX_MODE_DMA);
% f+ I, |% ?0 [- F+ Q3 L1 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) B2 F4 f7 ~1 X$ F" e/ n/ G; P' yMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; \0 O# T% b# p8 t( c+ X- SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 t. P. o/ H3 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
6 M% S8 }6 N8 b* z7 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. }" Y+ F6 s  G* S+ n+ RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) o& @) T6 Z. C: C3 _. Q0x00, 0xFF);

/* configure the clock for transmitter */
3 C4 I9 G' D, E+ I* qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- u8 G& u+ D5 ^% |3 B& d0x00, 0xFF);

& u( n% P# Y$ f  a; M8 L* x; Y/ L/* Enable synchronization of RX and TX sections */
& D" V: X& c, Y( zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 y1 T) G+ O; M3 D) t. g5 _& AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
% a+ P, I$ I9 d* Z, A$ \5 e- P/ @** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
. s* E) a! @2 @7 L# [+ S/ Y3 O*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
5 ~3 J' g; }+ K5 x, v& B, a8 FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 a  A$ Z" ]4 z7 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# U! M9 m; ~4 s6 a  o9 j2 vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
3 \7 W" d  o3 Y+ g' O( }| MCASP_PIN_AHCLKX
. e: o: F$ `. X2 H/ Q1 @| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" ]/ x; W4 K2 S| MCASP_RX_CLKFAIL
! _, D+ V9 j2 t0 W: ^7 d% @3 X! ~| MCASP_RX_SYNCERROR
# T& {4 l1 Q: h. w4 e| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
" F7 T# u6 a) Y' _1 E{
7 }% N$ b  i7 p1 O8 t( `/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: W+ m) [: z8 B; N/ ]3 mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
0 s* M5 a4 s+ vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
. H- \& [5 s9 y8 Q) p; I. a+ j' wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 ?$ f0 T6 W7 k& u7 w& B% u& m: wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
: H* W# ]& b  s& {' M5 v$ gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! ~+ `  C; S" o1 E- `3 |3 I/ JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
. U# M2 r! f' QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" o5 L/ \, F2 E1 W% I4 M$ m" c+ IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.