MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
- u: o" K  t3 L8 Linput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

; w$ T- A5 m5 S! \% o* ^2 boutput mcasp_afsr,
output mcasp_ahclkr,
( u9 z: I& \7 M: R( s0 \* uoutput mcasp_aclkr,
" J- D! p& i( I/ ^, `output axr1,
1 j2 U7 j% W3 V

assign mcasp_afsr = mcasp_afsx;
& T7 k$ d& Z0 V4 h  t0 I5 d2 y% Qassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

! p" w3 Q& `+ H) f

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

$ A; N  X- @" h* x- |& k" Y

static void McASPI2SConfigure(void)
' [: ]' w/ Z, L4 Y7 k) O3 T+ Z{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
8 p. L1 l1 W7 h- nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. h+ o6 Q, r. S; Z4 o9 W: s, oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
4 S& c1 X  {: J' S: b% qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 N  A; u5 \( U, O$ W, `' n" O$ _MCASP_RX_MODE_DMA);
- a2 V; {+ C$ _2 f$ \7 eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; X2 I( C& U. E' V+ n# r% o: S! fMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) t& |' w& g! [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 B, Z# g' G* {& _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) ]. I6 D" I8 F$ MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! M) Q) `- B  [) `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 @; ]. F7 [7 F! M9 z" a' ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
0 l) f  P3 u" S5 Z3 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 ]& Y2 w! y/ T2 Z% ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
/ x7 p0 O  E2 E8 ?9 b
* E3 T* A8 i# V/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
" `) }" S& f8 h6 S" ^6 y" s** Set the serializers, Currently only one serializer is set as
& i- ?) y; A+ {. v; m** transmitter and one serializer as receiver.
, A' x/ o" ~" }# d+ u*/
- z6 ^; F, ~& e2 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
  ^$ [; {$ t. yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
" t3 T4 Y7 G; l: Q1 [& I* q& M** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
6 q4 W8 K7 h" t8 c+ ]! Q# D8 s| MCASP_PIN_AHCLKX
* W7 l* g! l- `5 }! E| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) G) {0 ?* h, R+ P- CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
9 Y  s4 V9 h' T| MCASP_TX_SYNCERROR
' J1 t# G, ]3 b- ^- n- y| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
* \+ M; W' _: s0 t& A- d; b* s| MCASP_RX_SYNCERROR
! Z8 I( N; |. A( t1 h| MCASP_RX_OVERRUN);
$ A7 }% U4 W$ m; z% X( U4 |- d, b}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! r- r2 q  j# T& L/ g  IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; [9 N6 V$ l' ~+ K7 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
3 g4 k( S8 \8 W6 t2 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 ^" I7 b, v# v' e& f6 x- e( r}

, ^, c2 r, m8 N  O9 P3 O

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.