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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 Q1 Z! K, C$ o8 L5 Ginput mcasp_ahclkx,
( X: `* L2 E) j( l1 Einput mcasp_aclkx,
& r$ C/ f: I5 K3 O- N% p6 Iinput axr0,$ [* s: W& o" `6 ^/ }% A5 r
- j3 R) v2 O" {6 g; D. Y1 f- y) I2 P8 ~output mcasp_afsr,
& W2 t, H8 e, I: c# soutput mcasp_ahclkr,! X' I8 W. z) {6 L3 Y# }; g# }6 Z P
output mcasp_aclkr,
! x6 ?0 I5 U: e) m! I" qoutput axr1,
( P, {" j8 A: _. _8 ~9 M) B assign mcasp_afsr = mcasp_afsx;
/ i1 N: ?) d0 p5 x; u8 G! N. |5 Kassign mcasp_aclkr = mcasp_aclkx;
1 G( R$ P6 C- Yassign mcasp_ahclkr = mcasp_ahclkx;3 F# f9 y4 |- P K. }) E
assign axr1 = axr0; 9 N) h. u3 G: `! H8 f) o, Y
' L5 i; v/ X0 ^+ N; C; i8 f! @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 h/ w& c: N- l7 Ystatic void McASPI2SConfigure(void)7 M" f8 o8 R0 a5 |" i0 n/ Z4 W
{
}8 a* k# Q' j( o6 o" b2 E+ O4 t" G1 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ l+ z4 _1 ~! M/ l h3 a, b& ~; EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# S: |; f. |* D$ _. d7 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- X$ i. I: B3 J- e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ g2 u7 f# r* Q$ J h0 _/ x# QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* d. {: s( L. G' u. G5 Z8 [2 M. aMCASP_RX_MODE_DMA);7 B2 ?% Y v# w& K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 {6 G5 X2 ?% i2 p9 xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 Q5 T6 [) C. l! x, s# v5 J' n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" t" @% y( s+ l1 x; oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 a, T0 t* ?, ^2 W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ z& K+ |$ ?" n. _; k9 ?3 R1 u* H' \5 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// W |. s: X& [7 R' [, m ~+ o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 r& p! |2 l! i1 u7 @# _- gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( v5 N6 x& V/ w# u9 X! L; e% j3 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) s3 l5 {. h* i& y$ X, x8 N
0x00, 0xFF); /* configure the clock for transmitter */
% A U3 E2 u& _) \+ BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; }1 n3 x8 h$ i X9 h0 ]/ z% TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; u: i9 m* w. i0 t: z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
r$ j; m. s0 I1 K- H/ z0x00, 0xFF);3 W3 P- k+ K3 D2 y
# z, Z2 t6 \ m* P5 R' t7 D$ P- k
/* Enable synchronization of RX and TX sections */
0 t3 b' b) U8 V( bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 ]( {' Q: [+ i. g$ S0 Q" s& H4 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! ]: ?- z4 z" y: L! i fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 K: G/ P" h% y) U6 c7 f/ x** Set the serializers, Currently only one serializer is set as
5 h7 `, q: e0 j$ u. L3 a0 @** transmitter and one serializer as receiver.1 [) Z( m* K8 Y3 ?7 R
*/7 k8 z/ ^7 z3 p" c- B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ e3 g8 N7 ~- a# M: \) qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 F+ p/ H+ [+ f E" L: g** Configure the McASP pins ; u) S4 p- P2 S
** Input - Frame Sync, Clock and Serializer Rx
' y! k9 o( s; k( c8 C2 |, I** Output - Serializer Tx is connected to the input of the codec 2 [+ |2 ~$ l) ^% }- t
*/3 x0 _. o0 c3 \! Q* T8 g( P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 i& R3 u$ `$ MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 O0 F }+ @2 g' ~, S4 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: U% k, {! h) u/ C' ]& ~
| MCASP_PIN_ACLKX5 G* u. ]7 W! }( B
| MCASP_PIN_AHCLKX4 [. g( ]0 b8 ?4 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; ? h2 S& \5 G, A$ N$ x! D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 R& I4 s- l9 Q. |1 K9 P8 S' |/ q# o
| MCASP_TX_CLKFAIL
! p' t- D% h, U. l| MCASP_TX_SYNCERROR
" D" a; N- P' W$ s; s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 x7 j# x" {% I& p. G* Y| MCASP_RX_CLKFAIL
& e' F8 N8 B( J) s| MCASP_RX_SYNCERROR ( j1 h% E3 m. A+ t9 Y
| MCASP_RX_OVERRUN);/ ]: h/ }& @& ]4 j! f1 [' v5 {) C
} static void I2SDataTxRxActivate(void)* T% l0 k5 D& T* i
{
7 c8 h0 D8 j [) R4 E, D4 w/* Start the clocks */7 C- Z' L1 g2 ?3 @4 `4 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" n/ B7 U' `! \( k# M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) b( Q# l" X- qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! ]. c- i& {- R. i; x* ?EDMA3_TRIG_MODE_EVENT);, F3 n& @2 S$ M8 \8 i5 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 y, ?+ D3 N" {# A6 O9 R- [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 b' u, M0 }8 G7 C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 Q( h8 @3 F l% H' T% ]) V2 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 s+ j' K! t! H% Q6 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 j# ^1 k) |2 B8 O. }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ T# A4 t4 F5 y0 R; G3 z& h7 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, `$ O; \ k* K" n }6 [( @! `4 w} C. s3 b0 ~+ g- X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 f# _% w1 [5 W) q6 p. R
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