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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 D+ m+ C: g; A+ D
input mcasp_ahclkx,' L% U! S) R$ Y9 M% @% ], k9 Q
input mcasp_aclkx,; V# h) z1 A" E0 X7 D( I7 ~ M
input axr0,6 |! B+ g5 m1 v1 L6 v9 v# N9 Z7 L6 W
6 X* R7 c- O6 O3 foutput mcasp_afsr,
' y, L& c2 k4 @5 ?: Qoutput mcasp_ahclkr,
) i- _% ?1 u. g1 j$ q2 e/ Moutput mcasp_aclkr,
& j7 F1 B7 W4 h% G) xoutput axr1,
9 _& p3 _! M2 b9 y8 {# Z; K: A" o assign mcasp_afsr = mcasp_afsx;8 d. X( _/ Y, d
assign mcasp_aclkr = mcasp_aclkx;) j! r N( x9 ^# S* W3 |) z! I r0 b
assign mcasp_ahclkr = mcasp_ahclkx;
% v, `9 a% h* N( @! Kassign axr1 = axr0;
6 b* e3 I* T+ X4 B% g3 ?. X! K+ ~2 n! K) z3 x. W- o2 }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & y3 U7 h. l1 {/ P! ]4 l
static void McASPI2SConfigure(void); n* l3 l7 K5 a" `
{" k& X3 Y' ^2 k" N; `$ h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, U' d5 h o; w. M+ Q* OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
G7 h& H+ V3 f$ q5 @" ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 l0 _. G; \. Y' T4 d: [) A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 {1 P2 ^. w7 \# ?: r$ |: V9 j; [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ i% Z+ D+ g( V
MCASP_RX_MODE_DMA);- H, J% I: n' o# `& \- d, A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; e; E, Z' n& `5 X9 A3 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 m$ I0 @3 d7 K4 ~7 K* IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 `8 ~: K4 A# \( a7 t1 j! T; C/ jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% ~' e" E* _: W2 f2 i6 d0 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . E2 B( g3 J5 h* C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ ]! o B) a* f& K& T5 I. q! \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! r4 a- R0 k' LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ ^$ h7 w! q- E! L/ @3 P/ g- f) p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) C+ I+ e2 _( q
0x00, 0xFF); /* configure the clock for transmitter */
4 e! }) r% Y jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( V4 l/ Y; R1 m( R+ U1 j# |6 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & D" G- {3 n4 R: s3 t& P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ c0 z- q/ P: S) N& r) S( o' D0x00, 0xFF);
- `( w% z- W! ?# q3 ~, @- Z6 q& z m) U$ J# v7 ~2 W: [& o
/* Enable synchronization of RX and TX sections */
' @0 v2 U1 L" nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 W; \0 A6 d5 F! |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# V5 R( P S z% r# D( u" CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
b2 t6 f2 O; M) f1 P** Set the serializers, Currently only one serializer is set as8 F& K$ F* D; `( F5 I/ n
** transmitter and one serializer as receiver.
$ O- D; ] x: E*/
; @ V1 `& H# S9 i lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 D& B/ G& L' ~ z) s' H2 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 g6 a* p. T; e; p. ?- Y5 E** Configure the McASP pins ! I+ w1 \% K) Y+ x
** Input - Frame Sync, Clock and Serializer Rx% S' g$ Y9 ^& Q
** Output - Serializer Tx is connected to the input of the codec
1 Z' T% b/ a7 R+ w3 G0 o* E) I*/+ |" @& w* Y3 \6 p( m5 y; [7 A" M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) l) r4 Y, P3 J/ N+ O: F; T& xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& y9 m% e5 [6 g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 j2 L4 z* e# [ {
| MCASP_PIN_ACLKX
; q$ }' k1 `) Z! ]/ i2 L* e| MCASP_PIN_AHCLKX; ^" d0 a& F5 V3 H2 X9 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: a' `) e E# Q! W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* k7 c6 J$ E4 C3 z' i7 I| MCASP_TX_CLKFAIL
' e6 q9 E8 F, g/ v! S+ v" U) Z/ e/ \| MCASP_TX_SYNCERROR
0 d# }! v. d4 z% N" s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 |4 {( @5 C1 e0 |8 o* m| MCASP_RX_CLKFAIL; f8 G: P# T- u8 y9 ?
| MCASP_RX_SYNCERROR + H! R2 o# E- p9 G" Q
| MCASP_RX_OVERRUN);& F% f# i: n6 [
} static void I2SDataTxRxActivate(void)
% e8 M' {! T3 ?# p* a{5 i9 I) C! B& ~7 N( i
/* Start the clocks */7 o) Z9 D- [9 n5 ` i! |8 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" i! [1 q& f& q- E) C$ y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 c7 i9 ~$ T- }2 D- R: R0 O/ F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 u7 W8 z2 L+ i/ f- W5 }& [" jEDMA3_TRIG_MODE_EVENT);, i1 A# F# x# \/ l$ j3 a) a! X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( u* B! i* H+ ^) V3 {: m' {! FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
W* k* x% ~; [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ Z3 [ x) p% V+ MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 c+ D( X+ f* n3 r% l( `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 N/ D! p! r% j! `1 N6 W$ iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! y; N3 o, ]2 X! L0 HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: A9 v' L0 b2 X3 H3 K W& ?, {}
# k: O+ f; w7 E2 m( `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % D% ^4 V9 }6 A. t. o# }
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