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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( b j o1 ?. M# {1 Sinput mcasp_ahclkx,
% W! e0 t8 X& W& H) w* ]input mcasp_aclkx,& C j1 g/ Y4 n& X
input axr0,
: ^) m ~+ o1 ] s5 Y4 B+ h. c7 r* \7 J$ d7 [0 q3 i; a7 r* Y
output mcasp_afsr,
: `7 P$ R- P9 Q% t. _* q" ooutput mcasp_ahclkr,
c8 N/ h7 X7 I' ^output mcasp_aclkr,
. y9 k8 Y/ ^1 B8 \4 a; ?: \output axr1,
1 X) t5 W& K; M; C K( P% t: p assign mcasp_afsr = mcasp_afsx;' l0 Y3 b/ u+ T, e/ a
assign mcasp_aclkr = mcasp_aclkx;
& e4 p' }' ?" R7 |% {assign mcasp_ahclkr = mcasp_ahclkx;3 J0 P+ O1 N6 n+ M: S7 a3 ?
assign axr1 = axr0; 7 x6 v& @8 w9 |4 _& u9 S3 l0 ^" F
$ A o) u6 v' _8 p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ C. M1 a0 I5 z, M4 l7 h! Z2 a7 @static void McASPI2SConfigure(void)
& S; U2 C: { y$ O# z{
& t5 H( S1 R3 h6 I% L' j4 J9 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 Z, O* [! S% u. C2 h3 k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 ?9 a$ @. Y0 f- Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 I" m: P8 l/ q& X. j# ~& sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 A E( q2 _! ~* v+ p5 G* t! O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 z% I- C3 a2 u, u$ ~6 c: ]5 eMCASP_RX_MODE_DMA);. ?# t9 T9 K" Z6 {) Q. J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 T% q. r" n1 j+ J" w% k: J# Q) D' @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 j* b# a; T9 z' y$ {4 [1 Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ h9 \) H: f& d8 H- @4 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); _ \* B4 [1 h) K4 V$ T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + b: c- Y; C3 Z" r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; j0 ^% X0 z+ J0 g! FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ w3 w1 ~2 R& BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' g# } J! t/ O8 c* x7 e3 pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' [: v" ]3 H& o0x00, 0xFF); /* configure the clock for transmitter */( l! m, H5 A* d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, s- E" A/ e. A- b4 ~, R N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % @; d4 J; P b+ T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 H% y; e6 g9 e( l- m9 S" B
0x00, 0xFF);
+ m* g% r1 `+ \) b# [1 o, A
6 {3 o+ H/ m. U/* Enable synchronization of RX and TX sections */ 7 L& o0 @; r7 ?$ m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 Z# t: N5 C+ c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ B! j9 P9 W8 l% e8 P2 R2 GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' n5 @3 d% ~' N6 A' r+ [** Set the serializers, Currently only one serializer is set as
- i4 U! `- H8 s7 u6 x** transmitter and one serializer as receiver.+ ^7 S% u4 M% L1 o8 X. D% k. n
*/4 f3 ^9 y# O; c0 K4 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. A' K) @" z x* g( k" q" @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 x6 W: G4 N* i m6 E. i- ?4 g** Configure the McASP pins
# C6 r' d Q+ G** Input - Frame Sync, Clock and Serializer Rx
" C3 I8 t: c% V/ f! O( z& r; b** Output - Serializer Tx is connected to the input of the codec 0 K; b. T* v2 Q( J( g1 }' T! A
*/7 j: e$ z2 W$ i; y% A) A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: t. H! v0 o* D; D6 ~9 v; R/ F) ^: g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 {- H( C4 t# w/ i5 Z' }2 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& M+ G, ?7 S0 L' p" X| MCASP_PIN_ACLKX# }0 B( y2 f w2 C
| MCASP_PIN_AHCLKX& d! O: D) V3 l( ?) ], c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# ?+ w$ v3 J/ k5 F. \ _4 v- pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 D9 z) f8 U0 J" \" i7 k0 i! \
| MCASP_TX_CLKFAIL 0 t+ p8 Q5 i- `' ]! b/ I
| MCASP_TX_SYNCERROR- ], c: Y$ f" }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, ~( r# l$ J& C- C! E" M| MCASP_RX_CLKFAIL
|( `6 t6 q: D# q, ?8 f| MCASP_RX_SYNCERROR & k/ n' m% w5 l- t' g& G5 G
| MCASP_RX_OVERRUN);9 n0 i% G8 s# v& K( f. S# C
} static void I2SDataTxRxActivate(void)
! h* d. C; y/ S* R; o5 _' k. K{" v* H) x8 x2 t, Y x
/* Start the clocks */
; g8 T7 R4 a' n1 }' @- MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% |. e6 N2 j- K# y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 e4 L$ Q7 |! k7 y2 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% \3 w7 K5 A o$ d. I# F8 v: c* x; h0 j' Z
EDMA3_TRIG_MODE_EVENT);
7 b+ Y( X. g- S+ U& ^5 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 _+ D: ^" }' Z# J: @0 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& D+ p1 T; |) r9 _, ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 b4 v3 l5 ^6 X( W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 |9 o6 f) K; H7 b( ?. Y; X4 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" r) U8 m1 U0 Q7 \# CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. Z/ {+ t# i; n9 v5 t) }) HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, D& n- J; R ^% H1 O% o" [
} * p# H4 e4 [$ z6 r) Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , `" A5 Y3 ~& b( c* f; O' G
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