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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 r0 k* G r2 ^6 l* D- v
input mcasp_ahclkx,2 \; P& B+ [' T+ j
input mcasp_aclkx,& L1 }/ u! u% k4 K
input axr0,' G/ j! }( y3 |+ i
( ?- _* F6 `2 q* K/ K0 L: soutput mcasp_afsr,' p( p+ s' ?: z' u. V: P' H7 ~* Q
output mcasp_ahclkr,9 J& F. g, L2 t# Q9 O* G
output mcasp_aclkr,$ K( }$ a& v% M4 g# `
output axr1,& g3 [5 o( c; W3 c' X- R
assign mcasp_afsr = mcasp_afsx;
( q+ T* ^9 G1 J( g: P! }) Yassign mcasp_aclkr = mcasp_aclkx;
$ z: g: b! K% R! K8 Z2 i7 sassign mcasp_ahclkr = mcasp_ahclkx;
* U# r* d5 `6 t4 b/ |assign axr1 = axr0; 1 L' V$ P! A$ V; q( S" X
* c. L0 c6 \. ?- p. F6 D/ {, j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " o* [, m% ?9 u
static void McASPI2SConfigure(void)0 Y8 i' ~1 B; V& O. F0 U5 R
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);# Z: G* I/ G" |9 {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 y+ ^' C) o& O! Y& \( @% Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" Q9 \, C) y% |- i/ PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 L( q5 Q5 f* H; P5 ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* c. O5 F: H7 c; o# ]MCASP_RX_MODE_DMA);
$ ^! O8 A1 _, @' Q& mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 f7 G3 ^9 T' {4 O @7 ^* I, F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; ` x+ v* T+ h8 Q; E8 j: a2 m' YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: P1 E8 M* ^- ]' ], v' hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& m1 W: {! k2 T+ n+ k0 ~, t' JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* q4 u5 e$ f2 C; c9 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 M" r" y9 J1 x ~0 A" TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 q& h- ~) Y* O+ V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # _) U% i! M% i# ^- J7 T3 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( [3 J$ T" t* b0 _, G0x00, 0xFF); /* configure the clock for transmitter */
0 e& t5 }6 X+ G# ^; t8 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- z) N" j D8 h$ eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: m. g H2 U- Q+ n5 o+ _2 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; r2 I9 r% r4 @$ w) G0x00, 0xFF);/ |( J5 T# B+ R- A0 k5 I" K' j
: p+ H5 D9 I, F) R# {- t' d' _, @/* Enable synchronization of RX and TX sections */
. N( D" g: a: p6 }- @, zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 q+ J) R( f" R, _4 }& W' I H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' q5 w8 V n; u7 c, J5 }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 ~9 b0 S# Q: ?+ k** Set the serializers, Currently only one serializer is set as, Q' O. C1 |3 f$ ]
** transmitter and one serializer as receiver.% U5 a8 s i, p9 t' q' c
*/
" W2 x) X9 |( d3 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
R. f- P% s1 v, xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** l( V: l+ a* L3 L% h8 C; ?
** Configure the McASP pins , @$ s: i: g1 u/ k$ H( {* e* ~' d* ~
** Input - Frame Sync, Clock and Serializer Rx8 b' a3 ?0 t7 N1 @; H5 r! p+ }
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, n6 t3 t) d/ O0 A6 Y8 w5 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# }& W1 [& N3 m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# Y9 I& I# U& ?3 m
| MCASP_PIN_ACLKX$ T4 G/ N- Y2 t% B* ~$ [' t
| MCASP_PIN_AHCLKX' w" r# J2 e! n+ V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 l1 T1 D! ^% w' i9 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 s, S+ x5 V" T2 ~0 Q| MCASP_TX_CLKFAIL
1 U# q6 _4 g6 A+ t2 M6 P. `6 x| MCASP_TX_SYNCERROR- h: Z R/ D5 T( |- A, ~: F2 {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, N3 s. B0 }" X. A* i| MCASP_RX_CLKFAIL, |6 [% ]" p$ p8 H7 D
| MCASP_RX_SYNCERROR
$ e1 x; c7 f5 t# }| MCASP_RX_OVERRUN);9 E8 w% y, J& n$ R9 o
} static void I2SDataTxRxActivate(void)# [6 |/ I2 ?. ~& u0 G; C
{
: ]- Q% W# h$ @* G2 v' C/* Start the clocks */
" l* s/ C4 z. s+ H# G! B& MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ t2 q% N; r4 E J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 k& a' g, B. Y8 o3 w9 ^2 y( j+ g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 ~2 j2 D- w( O9 |EDMA3_TRIG_MODE_EVENT);" Z4 k, c r+ u0 H+ t( s/ R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ x. ]: p2 Q; x& o1 C8 v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// }$ x) q" G8 F! W0 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 _6 i7 \* W% g7 a6 N0 w" z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 s7 R0 E5 E$ B% f4 E; Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 t& \# }; n, Z/ a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( c+ L3 T: @' E+ U' ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( r4 \$ b' J: n
}
+ }3 g" O6 f% c7 f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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