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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 q9 i+ |5 \ q6 d1 [' Hinput mcasp_ahclkx,2 x% x% O% | `) g8 R4 z4 R
input mcasp_aclkx,
e! Y/ l% g* n& tinput axr0,
1 O1 b3 _$ G3 x+ A, G: g7 v0 p4 O& H. T) ^# ` b4 L" \
output mcasp_afsr,
( @$ Q/ l0 H' X; F! D6 t5 Z5 a- Joutput mcasp_ahclkr, A! G. w1 D3 j. F3 X
output mcasp_aclkr,
; o+ Q' r! b# z3 B/ o! Soutput axr1,+ b% A0 {. J. f/ |8 F8 {' G( G; s) E
assign mcasp_afsr = mcasp_afsx;% X6 a- R$ [; R- |1 `: C
assign mcasp_aclkr = mcasp_aclkx;% a( m" i" C# b7 \1 V3 z9 x! Z
assign mcasp_ahclkr = mcasp_ahclkx;
/ {* ~& f2 ^( b5 Q( V* X$ fassign axr1 = axr0; $ L5 I4 o* z4 W
8 L3 N# Z+ a) S8 T7 u! k8 Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; \5 P" f% C) J
static void McASPI2SConfigure(void)" ~# p) W4 F2 U; O/ I. z" @8 L$ K
{2 ~4 E. r- P4 }' H4 O9 z! ]& p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# O: P8 l1 Y( U0 T3 [6 _6 o; C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 O6 z" B- u7 g# w& uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- E7 S/ y9 K& D9 R4 z9 V, ^2 i% F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 K# Q0 Y" C" V& RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 i7 x" M; N: ^" J5 S% o
MCASP_RX_MODE_DMA);
% M1 `- }5 n3 Z( Y: n5 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- Q; g# o/ Y8 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 F& U4 w u. a- SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& M- U) J: a& B3 u& NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 I: i A2 F' @; Y# J3 y( r1 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; T. y9 x( R3 V- ]7 }- |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// M* v1 F- A( ^; U% f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); c; l5 U7 S# B2 U/ n6 V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , t% P9 ^% M3 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; `: i) } Y3 C
0x00, 0xFF); /* configure the clock for transmitter */& f% m) F1 P8 R5 ]! I4 N r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- S7 K3 C8 P2 c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& g* e+ E; s) y7 i! vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& ^- K9 Z* R4 _8 h
0x00, 0xFF);' g( Q0 |- i" |0 A# O: t" V
: X* X- j- _6 j3 V [) d: [' L; I
/* Enable synchronization of RX and TX sections */
2 i$ Q, n. p$ Z9 j6 e' Z: eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: h% b) [* v6 W$ {6 [+ H9 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 ]* S4 @1 T, B+ s* b! a7 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: [+ m" K* S- X* Y** Set the serializers, Currently only one serializer is set as7 h+ O1 f& ^* e# C/ \& Q
** transmitter and one serializer as receiver., w6 |. b* f" B4 o: X3 O; L
*/
$ ~0 D# }& n/ \3 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 F$ Z% c2 f( v8 p9 l7 e8 h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" S5 G1 U& i9 f2 s! S8 c o* j** Configure the McASP pins 6 i7 ?7 E" H: W" _) v1 A
** Input - Frame Sync, Clock and Serializer Rx
( e1 d2 u+ J0 O5 M, B" K" ]2 L8 b** Output - Serializer Tx is connected to the input of the codec E- s# X4 @1 ^+ z
*/
1 f% L4 }. X! t2 d# V6 k5 aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ m! i1 \" X7 _7 F1 O& \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. h2 A6 G) _$ w6 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& O/ f8 h" ], P. E9 Q/ X9 u) d| MCASP_PIN_ACLKX* V/ X$ X8 ~% s- F; _, ?0 k. j1 W
| MCASP_PIN_AHCLKX
4 q8 j( }' u7 d4 a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) g' L9 A2 t7 v, h3 n8 n- DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 Y2 e* v4 P0 I8 }| MCASP_TX_CLKFAIL
( U K4 e6 M1 {& ]. h ^| MCASP_TX_SYNCERROR( }3 B7 z0 h1 H) b' ] c' `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' O0 V" q( Y5 W6 G a" Z
| MCASP_RX_CLKFAIL
* K5 m* Y3 q- q! s| MCASP_RX_SYNCERROR
* b# T3 C9 h6 n( u) G @/ b| MCASP_RX_OVERRUN);
* ^. W* w6 [$ A} static void I2SDataTxRxActivate(void)
$ O% m8 Y- c; n: w3 j% E- A$ ]2 |{, d$ ` U$ t+ f' ] ]
/* Start the clocks */1 S1 E1 q, ]9 {& ]5 u' _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- i0 z, F3 @' f+ e% W: WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 `2 U5 n, f* ] f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 z4 v! a* E, S7 a1 z9 AEDMA3_TRIG_MODE_EVENT);
0 a6 y5 c5 J& T' G3 e. kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 m5 ~, [5 G) D, ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' k% s: B& t+ O4 N: fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ c/ `. P; Y, e; xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- e, h" `/ `9 G. b7 a# f+ T2 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ P: T1 N* o0 {6 L2 S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ h! m0 H# \5 f5 s2 V- J/ A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); H! j. Z, y% q0 Z. ^, k6 A2 O
} 0 C7 c8 a# h- i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 C! l! i1 ~ L; B/ ?
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