MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
- A% f% T: @3 b, o/ kinput axr0,
9 l  J, S( @! U4 ~6 K% _: G9 _# b8 X
: p, ^% j7 Y) L: ~output mcasp_afsr,
output mcasp_ahclkr,
9 }% d) S: M; A+ m$ Q( r0 A% koutput mcasp_aclkr,
output axr1,
: a4 ]! j2 t2 j& @& d' {

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
2 W6 o& N% y& }6 e# Z( [assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

2 Y4 n. Z5 t0 W

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

( c/ G8 w- r6 N+ ?1 S( t

static void McASPI2SConfigure(void)
- U! T/ @" ?$ Z6 i; @3 F" z{
4 S1 G* L) [! w4 [7 r  AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
4 r  b+ c! y$ n; |* HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
, N7 z- b3 n0 t$ L% |7 m' fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
  C' I, j* O8 iMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ u# ?& X' {8 H- _' CMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 ?( U# U4 T  y( Y1 u6 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, j4 b1 g7 Y# cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" A" Q# k$ o/ M$ sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% q  T5 g5 R6 [0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* y; f5 j# V& C# T2 ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 s, K: M& ^/ s0 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 A, X$ U7 a6 F! s7 v0x00, 0xFF);
4 r/ c% Q6 \% g9 x" Y' B
/* Enable synchronization of RX and TX sections */
) T6 Y  }3 X' G7 K5 |  d) DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
2 _) i% }  k4 Q+ J/ P** Set the serializers, Currently only one serializer is set as
' |( |% O. s6 ]& [" M3 k4 l$ m** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
+ s; H! P: Y3 z% g*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" j" n+ d- J' e4 n5 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
4 B5 I! c' [, J! I) f! O" HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ [; ]) B& }  O) p: O) t4 r| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
  t9 e8 U  A! v5 y5 P1 C| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
% B) U8 I! y7 I2 J! A}

static void I2SDataTxRxActivate(void)
{
7 M3 C+ X* X5 \7 b/* Start the clocks */
) P- J. }: c; K; L' t% C( fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& d3 C, v/ Q0 e. d5 n  F* RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
' w5 {1 R7 I! Z$ ]" X- h  k0 Y: @" pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# [" q5 X& E) R) E2 Q6 eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
4 B" t7 \- P( k* sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( d( G/ c0 J- sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ R1 H3 q5 O: ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.