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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! C. Z4 Z8 q$ o* ^+ ~1 ginput mcasp_ahclkx,
( b* f3 c8 [) O' v) ]. _6 Tinput mcasp_aclkx,
+ _ C/ }! e; B- c- Ainput axr0,5 k# W0 |" O# s' I' O! K
; f4 a0 w$ f N5 zoutput mcasp_afsr,
+ f8 ?$ @: q1 E' U! J& t2 Uoutput mcasp_ahclkr,
7 J5 P$ K1 ~: |# Joutput mcasp_aclkr,8 @/ `! m+ t1 U9 b3 p2 k" V8 G
output axr1," C; |( g- }: o
assign mcasp_afsr = mcasp_afsx;
$ A- v/ U( V) F; Iassign mcasp_aclkr = mcasp_aclkx;, M! Y% u* N( S `$ N h. U& Y) G/ I
assign mcasp_ahclkr = mcasp_ahclkx;$ d J+ l9 Z/ e F0 [
assign axr1 = axr0;
2 B3 X# x: j" x* r6 B) s7 i: n* m2 I8 O8 o2 t. C. b6 k1 N5 x$ d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & M& z J4 ?/ [
static void McASPI2SConfigure(void)' L, V- J4 {8 |& O: r, @8 Z
{2 f+ P# z: x; |! Y7 X$ \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ H* P7 U* p1 s3 o& QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! @1 q7 {8 s( @+ v0 a; B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* P! x3 ^; B3 g- c0 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% b5 q; C1 N2 b: b1 u( sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; x, V2 z# @& `& s; Q2 KMCASP_RX_MODE_DMA);
) S: S4 W: U9 m% c, Z2 Q' W- q; f* fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 g5 O' {4 m3 `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ Y! R l3 \; A: s. f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' y! N9 }1 {4 J; k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) F3 B9 i- C3 d4 w( j* m, v$ P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . i: k# E" S6 y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( g4 h' c- B5 e. R( w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! ?/ w- o9 E% k* G3 `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 a: L4 j% N& K# o( L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. L- Y% o+ @' z& H2 Z/ z! n
0x00, 0xFF); /* configure the clock for transmitter */
5 i6 X/ y3 W# T0 [: aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& l& A1 X* k, u% i! [- Z& c8 @4 A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - _7 ]+ N c" M5 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," m* R R2 w0 m- M
0x00, 0xFF);
# I% b% X/ Y Q7 s# R# z, k. }; }+ g& H- q* S$ }
/* Enable synchronization of RX and TX sections */ + K7 z; ^4 E: M. @% V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 v$ V5 V9 \) f) R- x; w5 e1 ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 F5 C$ {4 d0 R! j& Y* u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 w7 L5 y8 y; B3 W' z3 q5 W- f3 d G** Set the serializers, Currently only one serializer is set as& I* s# f5 _, A% G
** transmitter and one serializer as receiver.- I, d9 J1 y' d3 q! ~( {/ j% m
*/
' ?% o4 Y, S7 Y3 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 Y. O" b; }, R+ j Y' p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# t+ d1 |# |6 u0 s5 X Q
** Configure the McASP pins
, \- l+ l) e) c: T: {$ p! p** Input - Frame Sync, Clock and Serializer Rx$ {2 D& O; Z4 P. Y" w. G/ y P
** Output - Serializer Tx is connected to the input of the codec
; Z" c( y: F' s' X( l4 B% ]*/5 k8 j) A- ~2 L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: u R. T' z- v/ \* `; ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( b8 f0 V2 n# P( i4 f5 M; y3 l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: B) V. R5 q2 M# j9 X
| MCASP_PIN_ACLKX1 U$ m. N* T h% A& |3 Y4 `3 u
| MCASP_PIN_AHCLKX
& r7 y) \" |4 q2 J6 w4 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 H0 U% S) d! h! |$ H- d/ `8 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - `: t( x+ |. }6 q; W/ [$ f
| MCASP_TX_CLKFAIL % A5 u1 G5 Q9 m+ x/ u
| MCASP_TX_SYNCERROR
* o9 v9 o, U; g5 l2 q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : |. Z: M* J. } F/ l7 ]5 {- x6 L: L
| MCASP_RX_CLKFAIL
+ L/ b# K1 j9 m2 b' D| MCASP_RX_SYNCERROR
% h% I |3 q9 y) K* c, b0 Y| MCASP_RX_OVERRUN);
P8 J2 k7 U& x/ d8 T& q1 F0 T} static void I2SDataTxRxActivate(void)) R( K/ Q5 D- |
{0 F7 n6 C4 l# A
/* Start the clocks */
$ E, s5 U; s: [/ `) o4 h( g* W! pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 A W8 p* V) ~& d) h- n4 EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( z0 {' v6 M0 H, e& h/ j A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' e; N3 v4 ]6 u+ M2 N5 G. V( M2 u# GEDMA3_TRIG_MODE_EVENT);
; O* z& a, Y3 p2 C4 c/ bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* Z9 ?/ P5 U; D E! ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! C# I, T/ F- T \+ G/ fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- ]/ {* {. M) O' o( Y. Y) ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 {6 E$ P9 L/ T9 G/ b# twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ B+ O0 ~4 l0 P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 _0 I7 b2 k% M# y' IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) B3 u2 C% i" s
} . k' D, m+ B7 P) w5 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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