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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 y+ l( D4 d) U* ^4 L% O
input mcasp_ahclkx,
: k K0 e- v* D1 kinput mcasp_aclkx,
8 \* \1 i# i& E% Hinput axr0,8 k7 |, \9 `9 W2 ]6 f* C7 U2 d
) V) `5 ]( \2 G" ?, s3 Z* c
output mcasp_afsr,
1 M7 M% A9 ?9 ~% ~( \( H4 E) `output mcasp_ahclkr,
' Z/ S1 S- h1 ~+ b) P: Qoutput mcasp_aclkr,* K0 e" c( [& P/ g( w7 S$ @
output axr1,0 V6 q- S8 r* R! T4 z1 a
assign mcasp_afsr = mcasp_afsx;
( H6 I, m# k& @+ K. r# ~* ^& c! d% ?2 M9 eassign mcasp_aclkr = mcasp_aclkx;3 F4 y3 T0 H2 R
assign mcasp_ahclkr = mcasp_ahclkx;
5 M3 o. L$ C# L2 O4 P5 q7 Z9 eassign axr1 = axr0; / x, ?$ ?# H* M' Z5 J7 U7 U) U# g
9 J8 y+ z# m* ^. k' |$ z/ M7 H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& v; {' R6 @# y& |1 y* ^- s5 R6 m5 Ustatic void McASPI2SConfigure(void)% ]6 \) i. K3 N9 r/ G H
{' y8 y+ d9 Z# k3 ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS); Q, H _# _8 M2 u5 m+ Z8 a/ S; k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 `9 F2 @ [6 _5 c/ M6 u8 Z+ Z" v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: T; Z7 t9 {; Q. p' g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 M1 ?. O1 Q! n" X; [' B2 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ~) l _+ C! [( U( T0 JMCASP_RX_MODE_DMA);
* c/ ~. L5 G E8 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 E9 }3 @, [, G2 ^( k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( z2 q+ w9 G# \( c+ g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" v, ~7 J* M( g1 F& _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! B4 y% S$ n7 B% X& D5 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ |; h- _( h* }( PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 z: S k) }3 R2 T7 z1 A3 Y8 V" i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 W, u* O# s/ ?$ p, x+ L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( r9 ^' v& i7 i9 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ n+ F5 u5 N6 d4 C/ o# U2 E0 G# y0x00, 0xFF); /* configure the clock for transmitter */# u, P( ]: G. g. t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- |6 _* Y) `( c: B" U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" O$ v D1 y% KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: T- q; S z Z+ `+ K6 H
0x00, 0xFF);3 u0 [* i" h7 Z& r' H: y
4 |, r) f: V+ Q, x/* Enable synchronization of RX and TX sections */ " p* A, s, b: l5 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ f0 r: N4 b$ Z5 g0 P( S, U9 L4 v, p; c3 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) r, x: i+ ~" B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
F! Y1 Q8 B5 |% K** Set the serializers, Currently only one serializer is set as
c4 c/ ], d6 u) g0 Z4 w** transmitter and one serializer as receiver.. T; g: S/ u. X7 e& o: c
*/6 A, p- |2 g* ]& t! B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 f. T! u8 A- [; UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 l5 f" K+ B& L7 X
** Configure the McASP pins
$ z" `( U: p) W, Z( f- E- Q6 T** Input - Frame Sync, Clock and Serializer Rx
' u$ l2 H$ H8 S; ]+ _9 F** Output - Serializer Tx is connected to the input of the codec
9 ^- D3 Y- P3 R( s* d% R3 ^*/4 V( h( ]9 n+ T( E) m1 g1 G! e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 o, c) |3 Z: g2 t% j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ S t5 d) n( j/ f' V QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" h0 h+ K1 v8 ]9 Q! ?: f
| MCASP_PIN_ACLKX
6 r0 ^+ X9 Q1 e| MCASP_PIN_AHCLKX. q3 K `6 ~/ ^. \1 r) K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 ]8 N2 P) f- A: w* X$ A8 {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 j) X* {9 b( ]+ P1 [9 i+ K
| MCASP_TX_CLKFAIL F; B. H) S/ _- V
| MCASP_TX_SYNCERROR& d4 ?# h5 b6 U3 F' K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * Z' V+ U$ p' t( D7 Q
| MCASP_RX_CLKFAIL) P& a" t4 y5 @
| MCASP_RX_SYNCERROR , K: v) U4 V3 Y) w
| MCASP_RX_OVERRUN);
3 D% u" I+ r2 j- K, [} static void I2SDataTxRxActivate(void)
: i; U: d. g' i( H! X2 r{
( K0 A# S. o& |- a- d" u. ~/* Start the clocks */
; b' o7 u; U) y4 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* |, K/ u* a; m( D9 }, f; J& m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: e+ r% @& a" R' W4 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, N$ _% M$ [: W: G
EDMA3_TRIG_MODE_EVENT);
9 v' H8 P1 f4 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % y _4 B% h2 d" g# n; x) g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ x, _, t+ @0 ^% N5 R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& L5 o" ~1 p7 [8 G" D { o xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 J! A4 s0 z, ]- T: [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 I+ ]( K1 v+ v: m# @" @! cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ H: p$ m2 t7 c$ s; g& `- IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
Q* R- z; }! c2 T2 P& p% k) R}
+ b( o$ }5 @" \1 F) |0 C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' H. A3 g. E) u7 X
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