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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) b. R G3 Q& S& C7 d6 q% }input mcasp_ahclkx,+ p) ~1 T5 U$ p/ A- E
input mcasp_aclkx,/ y* {! [5 s! }1 v4 J0 Z/ G9 b
input axr0,
3 L+ J! u' D+ a% M/ l/ J' l/ f6 v
8 J1 O: h5 B. L% ^: Xoutput mcasp_afsr,
! a9 \+ r, u+ ^/ z: n2 [output mcasp_ahclkr,
" u" s% ^' c( U# C5 r Routput mcasp_aclkr,
+ m8 ~% h& ^' y8 i- ]output axr1,5 N) v* M+ Z2 `; @2 z9 R
assign mcasp_afsr = mcasp_afsx;
3 f/ w3 U6 e* ]5 ?: ]- T: ]assign mcasp_aclkr = mcasp_aclkx;2 e% y: f3 u8 f- v0 ~3 G' X7 V
assign mcasp_ahclkr = mcasp_ahclkx;+ f# p+ [0 F$ J+ F
assign axr1 = axr0; ) _ o! W1 F7 c
* ]7 r8 P U5 O. @; t) Z4 b( {- b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* f( [* J$ m7 L- w& _2 Sstatic void McASPI2SConfigure(void)- L4 ?! S2 R/ n& C, r
{2 i3 i) R/ h* W- D, z4 ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" Q; ?, Y6 k+ E, k7 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ M, A$ q9 i9 @; ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, t, ]4 G% C' [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ ?: C+ t m8 s# h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 z% q" A. J! ?2 v
MCASP_RX_MODE_DMA);* n/ j" k* J/ T; K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' }( u0 y/ o# t$ q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# b% s, q) @5 t- Z A4 J1 s- z1 Z8 xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; u) `- ^; c; w2 O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 ?: e) F7 c9 L- i3 Z( x8 h) AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* f5 s7 C) j% |6 a* Q aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ S# i' ~( f/ A% g( t6 n# S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 R( V( f1 w& mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 i" ?- m1 \/ c8 T" pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ j! p3 y8 ?' p
0x00, 0xFF); /* configure the clock for transmitter */
/ ` |+ r2 G+ J5 \) d" uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. T H! S& C! _- `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 S: {* Z7 ?1 x0 |8 c# SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ U) i5 I9 M7 |* H
0x00, 0xFF);8 M: k6 ?+ ^- F6 ]5 n9 c& m. \
2 v9 P, E8 `' l: P1 l/* Enable synchronization of RX and TX sections */ ; R9 s _1 j c& d4 d" S" i# a0 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 \" d& n' e2 x0 j' ^+ hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' H; I+ a! \0 o3 L# T+ O% S! j. W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, b& v* S T& U" S u9 S4 c** Set the serializers, Currently only one serializer is set as. |- p' K: C9 R6 G
** transmitter and one serializer as receiver.
u' Q, o# T3 j9 P. v*/
4 V# Q! U o$ z3 O' ~. yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% e% v& M/ Y# }" ^0 E9 K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 ~/ o2 y3 z4 D6 [9 Q
** Configure the McASP pins
9 K0 N7 K9 J8 \" \8 a; z) w** Input - Frame Sync, Clock and Serializer Rx2 V* T9 _% L& e" h! y
** Output - Serializer Tx is connected to the input of the codec 3 ^' c; L9 M9 R
*/! e, l$ \6 _* B! G! s5 |( i- B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# ~. H- O _0 M5 Y2 u7 h$ _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 u- s( _ p. H: {# |2 `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 Q$ H, B5 `- M' m# g% Y| MCASP_PIN_ACLKX
/ e, ?6 o! z+ w$ k ~8 q) o6 l6 || MCASP_PIN_AHCLKX
* L! _, J% J0 w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* J+ o* i! Z% k; tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " T- e' }) Z8 Y3 e, A5 Q
| MCASP_TX_CLKFAIL
' ~. G" `% m) E8 A2 `* M; q+ F3 ~$ I; V| MCASP_TX_SYNCERROR
. F7 e+ G& {1 U2 F% i* n9 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; ^2 a6 l6 b3 d| MCASP_RX_CLKFAIL
^7 z r5 e6 K& J+ ~0 F) R% F| MCASP_RX_SYNCERROR 4 I! c6 a5 i4 e* {* e- Y
| MCASP_RX_OVERRUN);* }4 X$ {: b+ P0 F: m+ L8 j9 u
} static void I2SDataTxRxActivate(void)
- v, s$ A9 R" ?! o2 p4 y! D* Z{4 W: o9 _. q+ U& r3 _$ I! H
/* Start the clocks */
5 l/ [$ J' B- {4 p- ~9 lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& r+ V r; N, l; ]7 \9 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 o( Q8 z, S1 \1 G# O* Z* d( e2 G5 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: f6 l: v& ]; M/ e, A s+ v; iEDMA3_TRIG_MODE_EVENT);
& Y) \. S& T* H5 u0 s% q- dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * W& q# F+ [, r, `8 V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ s2 X: ^9 F0 D' \! O6 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 i$ h2 z" Z+ }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# u5 E3 T" k6 K$ T5 r+ b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ e: }& ^. @! v0 {" p% H$ RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# w5 y1 \3 M7 \6 i$ S. EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* w; J3 b5 S% D}
; r9 Z( A4 v7 Y2 `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 w" c0 I1 H* X8 f+ i* _ W
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