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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: ]' l% j0 H9 e" e1 \input mcasp_ahclkx,
) b: `$ P+ v& ?input mcasp_aclkx,
W; s" D: Y9 u2 z V% G" E xinput axr0,% a: P8 i9 z6 R! o
8 g$ f B* }/ x+ y3 qoutput mcasp_afsr,
6 }! X4 g5 e( Y; V3 g) D. Aoutput mcasp_ahclkr,; F2 }* n2 w4 E3 g" Q3 t* L
output mcasp_aclkr,
; s+ K* }+ k2 @$ ]output axr1,
8 Y7 G7 s$ O! G: J assign mcasp_afsr = mcasp_afsx;
. n" @& a& u% H, v# h4 x* qassign mcasp_aclkr = mcasp_aclkx;$ s3 C4 @( c; ~3 q3 M& E* F4 z1 r
assign mcasp_ahclkr = mcasp_ahclkx;
8 A3 \4 p' C! e) \/ Qassign axr1 = axr0; ' @! W8 ~6 l$ K+ i' _5 ?) G
) v) x8 B3 P9 {5 t+ Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 Z- O7 V @/ L( I" w6 E9 v9 Q7 e Istatic void McASPI2SConfigure(void)9 Q. f* e7 J# Y! B' \3 b% t Z: u
{- N9 X: E4 C0 T/ ~* C4 b9 D( S' i) X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; {; }+ i- E5 |0 N( P4 a1 C/ ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& t" C3 A% W1 ?: j7 n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" ]! e' U" O& I% d( k: @2 q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// R1 ]! J# u3 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 h5 g& D- ~; _' Z0 K1 L9 v. ]/ TMCASP_RX_MODE_DMA);
; _/ R' p5 k) E) j3 @- DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- A. X1 D( I8 M' m' X6 oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& L4 B' B0 e+ r* _- ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / C, [4 L) I6 _5 r6 ~, H/ J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ {" s q$ e O- i1 c0 ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 X% K* X: p+ i1 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 X/ R* O+ e. H* Z) XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
W: x" d, c' yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 M% g/ m, R8 G0 A3 ~7 c g6 A* U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& R% }( F2 z! e) ^4 n# x" d# q+ F- K, m0x00, 0xFF); /* configure the clock for transmitter */* I( k+ g5 r# z1 t& C+ o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 n% J8 B; k9 L' a5 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / y% D/ z# a F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) c+ q }" K+ J0x00, 0xFF);( Y! _( Z" }: P2 b# ?& J8 w
& M6 [9 ?, P* k- H+ f- X' j
/* Enable synchronization of RX and TX sections */ f- |/ r& k7 a/ h, t; [6 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- u. J% u# X( T j6 k9 ?) `7 E% b% VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 C, o3 q, X, u- o, j6 |4 a2 vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ ^; Q% k: e* F! m, _6 ]5 Y
** Set the serializers, Currently only one serializer is set as) V5 a6 r7 P/ o4 b
** transmitter and one serializer as receiver.7 b! `1 @7 t0 `6 s, q
*/
9 ^2 r9 T+ X7 `' YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ f0 O8 t2 t0 U1 U* w! z% P/ Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 d8 ^/ T3 T) N9 Y& `
** Configure the McASP pins
R. F) r& i: G u** Input - Frame Sync, Clock and Serializer Rx
2 U: X) R3 E6 M f** Output - Serializer Tx is connected to the input of the codec % `; q! p) o) ~$ {* C
*/$ @- V1 r* T3 H8 W& @( u8 A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 A+ m7 P& ^4 F$ v( P! \2 G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, n" T. q- N1 U, y6 D: \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* m5 Y1 w) y; M. M| MCASP_PIN_ACLKX' M- m6 p: z' l% H* ^
| MCASP_PIN_AHCLKX
" Q( j2 j' N( r9 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" w( s" ]9 l/ E8 m2 ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & ~. {( a) R# V2 E6 P* J: r E3 @
| MCASP_TX_CLKFAIL ( ? g- U8 n9 _% I
| MCASP_TX_SYNCERROR
7 |0 a3 ]6 a- g Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 M: {- U9 B' {' f$ V| MCASP_RX_CLKFAIL
# e8 ]$ k4 H1 {9 g3 P2 c; u% h5 V# ]| MCASP_RX_SYNCERROR
& J4 I0 f6 B& U6 j( V$ g. r9 X| MCASP_RX_OVERRUN);8 n+ s2 ]& [' b) G# ^3 m5 ~/ b- p
} static void I2SDataTxRxActivate(void)" C& B3 Z% u: D
{7 V$ J6 A: O+ w9 @
/* Start the clocks */6 S" I! O- A# m( @1 G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! R, ], [; K8 M7 y+ O( d, ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, l2 x; m+ x' C/ J, [: P9 M( W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% i% z9 ^( y8 n7 e" O1 p. S
EDMA3_TRIG_MODE_EVENT);4 z" W2 S+ k# ^6 s/ ?8 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 z& @3 B. t4 ` Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) ^1 e# O% j8 O, f- x f5 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); P( q4 ~: @8 G4 \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. u# Y; K& B t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! S+ ^. p# t! r+ U z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 }* `5 z! v+ ^; c% c: JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 Y) |' t/ K" l' C0 Z$ P}
' Y9 t6 R% W* L5 Q1 e. W% E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - C- \0 B V+ o. c _8 s9 I
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