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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
}7 O' _8 q( |' s$ N; jinput mcasp_ahclkx,
8 S1 |2 N! s# C1 F& {4 \: A4 linput mcasp_aclkx,
( `7 t1 p' Z; X4 c( J T+ O0 A6 ginput axr0,; H1 y/ ~, S4 q' n: y$ @# l
F* G7 |9 c4 L6 u; L5 `* o9 Aoutput mcasp_afsr,
6 ?, e0 v7 O3 ], }2 M# { noutput mcasp_ahclkr,0 W+ x' d$ r8 B/ t% A5 X
output mcasp_aclkr,
% R5 ^) s8 N/ d0 l toutput axr1,
" J% P* s6 @1 m% z( u: F2 A assign mcasp_afsr = mcasp_afsx;2 {# i, S1 o N" F( l6 E1 {
assign mcasp_aclkr = mcasp_aclkx;1 h8 C7 E9 D8 W0 J1 H" G* n
assign mcasp_ahclkr = mcasp_ahclkx;
* i7 t; p& B- \9 Sassign axr1 = axr0;
: M/ r% y- t/ w$ b
) Z, v D& y% g+ m3 `. A, H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, i9 A' Q4 S% F" ^" F y3 h9 @static void McASPI2SConfigure(void)
0 ?( R5 \$ ^2 y* F{
: M6 X& K) y( ~: q) ^' CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* ` O# v! w W; B, J; O- e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ U, Y% ?. I6 ~0 q4 O9 P, \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- G8 z: B- `$ ~# X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 o* V) M/ |1 w# f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- @, a" f4 g; C3 w0 GMCASP_RX_MODE_DMA);! J: w1 V" S2 D& ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) `. M, S) Z+ p" `* g1 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 V: `; g. j; m( I+ E- UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " B$ z2 p j% [& a9 T) G7 U9 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 Q, C6 D9 x) v9 N& G9 d0 m9 k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 [( b5 M7 V3 w" [9 y$ f* gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 J" P. I. R; L( p" hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 X4 m0 v4 {% E) y! _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % |1 _3 a( s4 o: b$ e# i$ E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! c8 D5 y1 c* _
0x00, 0xFF); /* configure the clock for transmitter */% o& ~5 G, A9 y: i, R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* r5 b$ k+ N8 s( [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * b) j& H: q3 Z( a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 v! T: N, ]+ D" x9 S, C! j: j
0x00, 0xFF);+ D* |$ p1 j, J. c1 p
# M ~* a* s, L: n% z
/* Enable synchronization of RX and TX sections */
# L7 f% l# ~- D8 w1 l0 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. e5 ]3 M; `2 z+ J4 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ V5 E. F& M9 [% e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( @9 a" J, `1 v! p+ L** Set the serializers, Currently only one serializer is set as" x+ A* M' [( |% S3 Z
** transmitter and one serializer as receiver.
9 {+ x: ~, ?9 ]& A7 r' y*/* U# n4 q! U/ A; D! l% X; e4 b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' [0 h( _" }: h4 F4 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 [3 H2 H: W/ h9 F** Configure the McASP pins
3 E& [) ]3 w* q2 b** Input - Frame Sync, Clock and Serializer Rx
8 k% @# S8 g Q% [0 n" v** Output - Serializer Tx is connected to the input of the codec : w' h7 a) ~8 B
*/+ O% n9 p" Q* _2 I) O# i4 w/ R5 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 ~% X$ \6 K9 A; X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 K6 O# Y3 d; L6 t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. W7 V8 G* B* \6 l| MCASP_PIN_ACLKX
. s& A3 B2 h, u1 F| MCASP_PIN_AHCLKX, k4 u& ?, b2 Y- n2 M' y4 g# B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, ~2 Z4 a% H4 B8 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( B! L, }& H* {/ N- L2 E2 O
| MCASP_TX_CLKFAIL
2 D$ B( I- e! m7 B8 a1 A; k; Q| MCASP_TX_SYNCERROR
; q1 O7 U4 G2 F; W8 G% K$ i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . v% f; m$ i8 @- E. J" U6 b% v: M
| MCASP_RX_CLKFAIL
" J* k- B: J; b: G| MCASP_RX_SYNCERROR ! U2 Z5 Q { I) b0 {" b7 H$ {- N
| MCASP_RX_OVERRUN); a+ X+ R" }5 r, ~5 f7 A4 o
} static void I2SDataTxRxActivate(void)
6 ^. l! ]0 F. W' w{6 R; n9 e) o* Y/ w+ N0 A
/* Start the clocks */& ]2 t: E+ D/ S* v# D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. s5 N" P5 n" D s9 r- Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 N' }1 y" @0 S1 s1 O T5 s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' L O4 u' O" q- V1 C+ j" ^
EDMA3_TRIG_MODE_EVENT);4 b5 f# b8 k$ d) f7 a6 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& \$ M* _! m) ?; G+ L L* vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: ~8 ~% e* F( S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, r+ X( [3 {2 ~' \& FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ M6 X( i, g) y6 R. C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 n( U3 C& {6 D: |" xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! U- ~! {( L- c+ v r0 y+ P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 E& `' G: K3 j9 o}
' U6 b |+ r" _, A+ ~! t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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