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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* ]5 H9 z" G5 finput mcasp_ahclkx,0 r/ V: U$ h' T; n: E( a3 R* o
input mcasp_aclkx,( g( t7 H, o; x; ]2 R
input axr0,( C) U2 n4 k+ J) k
3 v; Z' W% a X G- h2 G: b0 ~output mcasp_afsr,1 _, {7 b4 j1 F. Y
output mcasp_ahclkr,4 x! u( h# |2 \# C+ f
output mcasp_aclkr,
; r0 G8 P0 D2 Foutput axr1,: b7 [: Z1 K' [, T6 u/ S/ O+ [1 v' T
assign mcasp_afsr = mcasp_afsx;2 \1 G, s8 r: F' S0 I+ u
assign mcasp_aclkr = mcasp_aclkx;2 T9 Q- o/ Q; ~4 \5 G4 x8 p
assign mcasp_ahclkr = mcasp_ahclkx;
6 |, {6 W" Z8 R8 zassign axr1 = axr0;
' o* P/ G% K& ^7 o5 U4 u, M& U( A$ B4 N3 p% ^9 \ B S* d0 |7 f* P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% V1 p7 @$ Q# _$ z6 n0 G* E4 [static void McASPI2SConfigure(void)
! S/ `; b9 p5 A2 y9 X6 v{9 ~* P& I/ N" | _5 g; I1 q. a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 |' ]& X, m) e' S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, l) T8 O; z) i! }# k& V" d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% C; }0 k% f$ {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ r6 o0 `: {/ t# \) ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* Q* X7 k* H. U/ s
MCASP_RX_MODE_DMA);& N. @, ^6 X4 k/ M2 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% q' L: y' f0 L( |$ [5 y( h8 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% b! g3 G! n# N7 j, Z0 b* Z$ qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 V( x' f* R- nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# g0 }1 g, E* P3 g. j% l* @3 H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, r# X( i/ `( `5 i! j, Q* w9 ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* _: g; @5 k$ TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& H/ g+ j# y- Q/ f' g' E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 `5 l! S/ Z, _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; \. z3 w- z9 D( D
0x00, 0xFF); /* configure the clock for transmitter */! ^1 l m" ?9 }0 N, J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: x# s/ k. t$ q4 y7 m. T: Y' B }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' K# [; V& }; }) r; jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- {$ n8 h) m4 o: v2 c8 G0x00, 0xFF);
: P9 I6 ]/ t2 M+ A7 Z; D B- h
6 G' G& c* j% c/ ^; l* Y6 o9 Y/* Enable synchronization of RX and TX sections */ 2 l6 F3 w+ e) ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 O# C- e- V0 A. n6 l; E& ]% k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, m* M9 H/ l$ ~: A3 rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 }) [+ z3 P% G9 Q$ i* K9 B# y% f** Set the serializers, Currently only one serializer is set as
% q$ v% _; B3 h/ k3 x& `** transmitter and one serializer as receiver.4 K( F# h) F6 B# `. }5 a
*/
* e4 S+ }$ n: XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* E: j0 a% A6 u* b# i( K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, m) Z, w! Z+ y8 C( S& A# i
** Configure the McASP pins 4 x% T$ U0 U3 S2 {8 N+ T# U
** Input - Frame Sync, Clock and Serializer Rx
9 T8 c" [' r' y** Output - Serializer Tx is connected to the input of the codec ( v0 F4 y6 E; y6 ~
*/( `( b4 u x" g3 a) ~6 {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 R5 x3 Q: q) p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& q0 C3 X, L, n; Y5 \# X, J9 fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 x7 b9 Z* W7 Y |$ A| MCASP_PIN_ACLKX
" O1 U7 T1 t$ m, }, A* m/ N| MCASP_PIN_AHCLKX3 t; Q# A) ?; y/ ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: w: I& p( G( G' ~2 T5 U0 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 r9 Y, f/ e3 ]
| MCASP_TX_CLKFAIL 9 W, S9 N( \6 h7 |
| MCASP_TX_SYNCERROR* C& e, S% }5 M" A8 T" ~9 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 ?9 V) S2 |* Y! t' v| MCASP_RX_CLKFAIL
% j* Z# ~7 o4 _# L! q| MCASP_RX_SYNCERROR
, k9 n+ `& ]0 Y V- X- H| MCASP_RX_OVERRUN);$ c! d. ^2 G+ ]8 a" I& D
} static void I2SDataTxRxActivate(void)
# N: j0 [: A: o) v, l& V{
, K) t' _4 r" J4 l5 T2 Z0 M$ w" Z( z/* Start the clocks */
. ?4 B! z- e5 Q& c" N8 YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ R Z+ j# k0 `) d' a7 ?9 @# pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 J4 ^4 w) }1 Q3 B/ p" J5 Q) X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
]3 d+ X8 j6 l( x4 |. [( j: p. V8 fEDMA3_TRIG_MODE_EVENT);
0 Z' }1 z8 {# \- F8 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- h* O' _( e( \5 \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 b5 e) b- e8 @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 z3 Z9 g' T) x. u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- V& R6 { _. l uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- |" H+ L9 p, r* ?+ Y0 e+ Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 C9 s8 K( J* {) ?: o) i( D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 a3 S& @* p, m0 i. ~3 j }
}
! |8 p4 D! Q, P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 e; ^- T" f2 p( z7 U" n
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