MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
! u1 }+ J: e8 ]- E! c5 yinput mcasp_aclkx,
* G: X' |0 x* r; uinput axr0,
- a& F, y6 [9 H+ b( k  P
output mcasp_afsr,
9 r5 Q6 f5 y! e' ?# Doutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
/ O& U+ C+ l; B$ {5 Qassign mcasp_aclkr = mcasp_aclkx;
' w( ?* o: d1 f+ |0 ]7 H) Uassign mcasp_ahclkr = mcasp_ahclkx;
) B- ~6 ^9 H$ _  e+ n$ _$ }0 bassign axr1 = axr0;

1 @4 N. S* ?: T" _5 T+ w9 }
" l: x0 \' G2 R4 P: {" X

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

- d/ ^2 P% U% z) H9 g

static void McASPI2SConfigure(void)
- k( V( a# }: x, T  \+ ~; B{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
7 ]  r6 }' w! o4 rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 d# [4 c5 W/ N" ]' h  XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
. R" S" j4 d( i3 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 Q* x6 Q' Q  }3 j- ZMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; N9 Z2 p9 q: E) }( gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 j5 I! X% O  tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# g, U# N1 I, z& H7 V- |. FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
" V5 R: A! u2 J9 b2 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' {% k) r/ ~. C; H& d- aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% F; `; a# f+ o. [, O* l1 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ L: B' S2 o, Z# o4 k0x00, 0xFF);

, t$ R8 R7 s) N, j8 ]+ r/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: C7 W5 N% L4 m8 U$ PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
1 g, T9 A( Q( L- U** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
% u, h- n6 [+ {1 e" S: B** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
/ K; l" K' m& N5 A7 ?: _* lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; d7 l8 K6 _" [8 V# T" n$ [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ t1 w% V& N& t) UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 j. e: p7 t. w| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
9 f( y1 p/ I& n| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, i2 G# v  i/ k+ c| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
4 v% e! ?( Y3 |/ O1 ^. n) ?0 ]}

static void I2SDataTxRxActivate(void)
6 {( s# O$ p2 m( M{
' n. G& _7 {+ t$ w+ y4 ?- n9 g/* Start the clocks */
( ~: |4 ~  X. v" q4 V" ~- q9 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# l& a# K5 z, F, pEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
* I: ]8 w. [% mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 R% q# t. a/ g1 n. e4 s/ h( TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
0 V) d6 T. c4 K- v+ ~9 j7 |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
! M9 L2 C4 f/ A* u6 M- |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* e; e  {7 A5 t8 b3 R6 k4 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

% k& h6 T( k$ X$ q' R" T6 y( Z" j

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

8 z& H6 s1 L: o# ~& p