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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 A; C& b, H4 }/ F% I
input mcasp_ahclkx,
$ V+ v4 t v% Y0 i' Oinput mcasp_aclkx,( ~1 N+ ]! W; @- X: b$ W
input axr0,
% l1 S( H( K6 O" k2 \! ^* P4 Z' D* F
output mcasp_afsr,
: i5 ?& |" P U) c" P: I% V8 G! X. H/ {2 eoutput mcasp_ahclkr,/ w+ _1 L/ w7 m' d. _5 Y
output mcasp_aclkr,
, {5 k5 \* `5 U% soutput axr1," [3 s" F% `! l; j4 w
assign mcasp_afsr = mcasp_afsx;
3 L6 A7 Q, f2 T- Q P* Jassign mcasp_aclkr = mcasp_aclkx;1 Y% M7 {3 X; d+ o3 b
assign mcasp_ahclkr = mcasp_ahclkx;5 m/ Q+ e( t) f: [+ K+ s$ @% B
assign axr1 = axr0;
& M2 Y- l5 s$ W" F9 o1 C0 w9 b7 H: n0 b& h$ ]6 M( [ x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 P: |: C3 N& C, P6 cstatic void McASPI2SConfigure(void)
/ C& P( W* w, @% U% `{
$ h$ d [7 k+ I4 ?) u! DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ t" m# z# o: l5 w7 y$ W2 x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 y/ O& Q, R2 V7 z6 s1 U( AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 m1 z5 A& m5 @# q" C# N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 Q- ?2 H6 l8 w! M; \: ~3 BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) o7 _% x V' }3 c
MCASP_RX_MODE_DMA);
' u6 z6 V- [' E5 b* U9 c( L) _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( F, j; U$ M+ ^, J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: r" K. z3 x3 n' v9 x# e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# G, z" e' A6 ] [5 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! s& v1 u5 N* |5 q/ H8 {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( w: v! Z4 e2 c; e& q3 O' y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& k0 x, a( {9 d$ S/ m1 ^0 U& IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( ~3 U5 f* e0 a2 M5 U4 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* l0 |6 b6 _1 g& YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) O5 Q; o* ~# \" _* v
0x00, 0xFF); /* configure the clock for transmitter */" O3 u$ Q3 t3 n, A, x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- M8 L2 X# g) o4 ^: {3 |# x1 ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) \6 ]" h4 |, t0 U2 {) M& D c4 x7 j9 ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! b3 C1 D+ K- v' s0x00, 0xFF);
& g3 F) M8 q3 F: o. V0 U, m6 q* `& l6 W p6 D$ F
/* Enable synchronization of RX and TX sections */ 8 P9 c/ R4 F u& x4 q0 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, n- R8 X4 ]& |7 q% ~3 j1 w& \' F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ ~2 D/ X* L/ w& e" e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" ^- i) ]0 U/ S** Set the serializers, Currently only one serializer is set as
( @( y& Y1 g/ z- z5 [: A$ k$ ?** transmitter and one serializer as receiver.
( D) }( i& c/ p2 C9 a*/
+ q5 r' ?3 Z! h; H% @4 \6 dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) I" }* H+ o. O% u( L# cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' P) Z. [; }8 L# i** Configure the McASP pins
5 I+ x- e) r+ @; r% b** Input - Frame Sync, Clock and Serializer Rx
( A3 l& Z( v0 d2 h, N** Output - Serializer Tx is connected to the input of the codec ' m6 K) J) ~" {
*/* h& E3 b3 W: h9 `8 z0 f1 ?1 m+ B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% s( |( G" R2 g; g( ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 s8 x8 }8 r, jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" @, a0 H7 F; K" c5 F
| MCASP_PIN_ACLKX; J. b/ Z5 P( N6 e& b
| MCASP_PIN_AHCLKX9 w I. l- A1 Y6 c3 W& @2 G0 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" k+ I9 y# e5 e5 `9 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ ^2 W/ T5 I. V; r* f| MCASP_TX_CLKFAIL
; \' R. V* C2 |8 s' ^| MCASP_TX_SYNCERROR
& i4 D+ U" F$ i" y8 ^4 p5 T+ ^5 N! A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ d( Z8 {/ r+ k) {9 N" r| MCASP_RX_CLKFAIL
! B) I; W, d! [6 j6 Y. w* k| MCASP_RX_SYNCERROR ' A0 J. S2 K: b3 V, Q0 j
| MCASP_RX_OVERRUN);
& w. Z7 p0 G/ j1 T7 k% X} static void I2SDataTxRxActivate(void)
! j1 ?1 z, ]6 @0 V{* Z8 l' F' r2 x) K( A% [6 P9 s5 |
/* Start the clocks */
8 Y+ ~: f* W4 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; z6 h' ? u) `+ NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 `, D5 p1 _/ A5 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 K q$ x: L2 a3 B3 MEDMA3_TRIG_MODE_EVENT);: I* O1 f3 ~2 q, R/ {0 P o1 [+ @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + M& R0 E) {. B5 L$ [$ A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 v" T' i4 m$ t4 W0 P# \, DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# b3 W- V o4 Q6 X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 \0 s6 o% u, g; rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// ^: X7 J) D2 r' F, L0 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" e4 K5 l8 H. v$ h {; tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 d0 c5 z% [0 [, d' _
} # [$ H: b$ j, f) }7 A" r0 N+ E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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