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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- q; g, V+ j1 G6 K
input mcasp_ahclkx,! b) s2 y0 a G2 W6 ^% \
input mcasp_aclkx,
: g/ M0 @) q' l4 S/ Z% _input axr0,
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" d' X* D+ {1 d' s5 a& S& Coutput mcasp_afsr,
/ L5 F& R% N. T; t4 boutput mcasp_ahclkr,7 K) ~, ]$ Z n3 G& C% t. \* F( J" ^
output mcasp_aclkr,. _& J1 U- X( L* u7 B* w& [( v4 Z
output axr1,) n* \+ P% @ K& {& e( ?, M* K
assign mcasp_afsr = mcasp_afsx;/ S4 o3 b- c5 d5 ]! p, m: B. t
assign mcasp_aclkr = mcasp_aclkx;
" W3 `5 d, w/ ^( z# hassign mcasp_ahclkr = mcasp_ahclkx;6 @) y. v @# P# v! N. U" p& ~$ Y8 \
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 |4 H# g8 d6 e' e" X2 }
static void McASPI2SConfigure(void)! r7 ^& w4 R8 K/ `2 X7 H
{; V% R3 O% \+ Q# [- S8 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 @2 C+ R6 O$ Y+ _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 n, r$ }0 d' A9 K# D5 k! m& O0 sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- F# h& _ Q+ YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' W9 m/ E. ]$ u$ X- F) e! J5 ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 H: {: [6 ]2 P3 F4 o$ ^% W
MCASP_RX_MODE_DMA);
" G* }( J/ C, K* ~. c- ]+ W% g! DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: J8 ?4 g; L8 d7 a3 _9 M fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& {% F& ]/ w8 u/ aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . N% y T4 Q+ p! |. V |7 U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ L- j2 ?( E7 ~* g2 E+ j1 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 ^% H# [" t2 K3 w$ `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 M0 V9 |* C" @" e) j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); l, Z: d% r* U2 }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) y3 f9 }7 y2 r0 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 O( F9 V+ J7 u& k8 ^/ ^
0x00, 0xFF); /* configure the clock for transmitter */" ~$ W+ {& p8 s0 _# X9 [& G4 V9 Q) w1 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, O. h( S+ P* Y# d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* Q+ L. d- [5 o3 K4 |- QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 H8 L x& _/ c$ f) u1 ~; }8 Z
0x00, 0xFF);: H+ b" N! P; w
" q. `% y! ]/ |7 ~5 b3 W& h! k/* Enable synchronization of RX and TX sections */ 4 O, e" A" g; X+ ]( U/ E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; w: u( g+ q3 Q8 r! r. fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 F, `8 o0 n& Z' w* o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 E9 K' L9 \0 r, `/ Y4 G+ q0 u! d** Set the serializers, Currently only one serializer is set as# {8 V6 Z. [; n# e4 {& ~4 i% J
** transmitter and one serializer as receiver." M: b1 t) x, \2 I6 j
*/, a. h$ C9 p' A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, {* e+ J5 u" p. @- iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. i7 K1 m/ x* U2 {" U3 l** Configure the McASP pins
$ J4 z f. t' i' z: V** Input - Frame Sync, Clock and Serializer Rx+ I) U6 B7 }$ _0 j% a1 ?" l
** Output - Serializer Tx is connected to the input of the codec
# `5 U l; d7 _) _& n; n*/
: v& c' x, P' e( ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( p/ w/ c* o; P( r$ ~" i; g& v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! f/ ?) H1 b# n& @4 m) m8 B1 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# @8 w1 p2 M+ m! \4 I2 U
| MCASP_PIN_ACLKX
1 {! W3 \+ }9 r& q9 W8 Q& n6 o| MCASP_PIN_AHCLKX
4 m" E+ ~; ^( ^. U! ^& d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' a) \% R' B' d! H1 c# ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 c1 ~1 j& W& U, h- |# h; g0 }
| MCASP_TX_CLKFAIL
4 B9 u& N9 l4 }; f, d3 M| MCASP_TX_SYNCERROR0 K9 `2 D$ w* k y, L, d m, e+ P7 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 d( n# v3 y, j7 g1 G* P
| MCASP_RX_CLKFAIL- n) l6 ?4 U: T" X
| MCASP_RX_SYNCERROR
( B' B' o* P! J. w$ k+ @| MCASP_RX_OVERRUN);
) P& U0 Q9 t" h, b# R9 T4 _9 S} static void I2SDataTxRxActivate(void)7 @, ^8 |0 U# {" K3 Y
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/* Start the clocks */
$ [! Y9 l* l3 L4 ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! b/ {, s" q1 |$ ~( j5 GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ h% P( d5 u* e. a$ [3 k' TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 r8 z& k: d! Z, N
EDMA3_TRIG_MODE_EVENT);
( Z: V1 c& X l8 W% FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : `' ]) R# `- d: U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& f' z- k6 j0 x7 Q5 k k# n; rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' U; l8 I$ o- z5 W) ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; H$ o2 N9 n; v* g+ R% N# Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! r# g# n; u. T4 \' u4 }( w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 T. d0 q) m/ E; A$ nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ s8 y7 E* C* o9 a3 G; ~
} - [3 J) L n. k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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