|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( C- w8 U( J) Z
input mcasp_ahclkx,
- Z3 d8 f% [0 f. a( j6 i0 jinput mcasp_aclkx,
# P6 b3 V4 l# [3 Q& h+ | `" |" qinput axr0,9 ?# V; j2 H# O; }# V) V& k
7 d! i% o3 a6 ^8 C
output mcasp_afsr,% m+ @+ t5 K$ C/ f" O" L: T
output mcasp_ahclkr,
- p& n9 k' P; `1 |output mcasp_aclkr,
6 M& X* l& b. m+ _2 Boutput axr1,4 ^1 b7 D. Q2 |: M
assign mcasp_afsr = mcasp_afsx;
) V1 q6 K# t3 i5 _' j) G/ I- Bassign mcasp_aclkr = mcasp_aclkx;' U/ }2 d9 B1 g: ^# n
assign mcasp_ahclkr = mcasp_ahclkx;
$ Y) _- O# E- xassign axr1 = axr0; % S- v/ D( ~, w$ l" o T2 t
4 r: A, m7 @ q0 Y! r" r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! L0 Y5 s) Q Y$ T
static void McASPI2SConfigure(void)
/ _; J" o& q% C Z' p& {- H{
1 Z9 k% I9 e* X9 y' W, M* e) UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* p4 w, G) \$ B% _9 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" _$ }3 A. z7 X) O) R% p, }- I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 G1 \0 D) c. mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ y b3 M. I8 i4 q& } bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 ~& O( L, V4 ~' J7 O- V% A9 EMCASP_RX_MODE_DMA);" q0 q c5 v# \: H( b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 y4 ]( G0 Y. `/ L0 `* b3 ^9 T; |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& j+ ~# w1 {4 e8 v# m5 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* F% o% q. P; @( ` ?" n3 R/ k( ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 |4 ^% r, `/ G& D* V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 V) A& Q/ h- X# aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
N# I6 _& J4 I. eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 _ I) V6 K8 d G& B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' N( X d& X# `1 h9 K9 Y: SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 O/ n! }7 Z/ d2 e/ g
0x00, 0xFF); /* configure the clock for transmitter */) d4 r2 ]1 l" F$ u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 l5 @. U" ~& ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 L) [+ a# a9 g6 f) `5 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! F- i; k5 o- l) a0x00, 0xFF);
! j/ n, Y- F3 e! E9 o; V7 k, x1 ?
# T1 j. ?( z. q2 {/* Enable synchronization of RX and TX sections */ ' @: U) {+ @' g. ^& @; F6 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, W# ?! d0 W( s0 l0 }! `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 t4 C4 f& w9 cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 |/ O: m$ \( v# R5 u** Set the serializers, Currently only one serializer is set as8 M" D& @' D5 t
** transmitter and one serializer as receiver.
! c2 y5 }9 t" ]$ u' ~*/4 k. N6 P& T2 ?! A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) i* E9 H7 E5 s6 v- A6 C% p; M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% ]% }. c; I6 s, B3 `9 P: E; p0 h
** Configure the McASP pins
! N% |4 x' y$ Q, c) O** Input - Frame Sync, Clock and Serializer Rx4 p5 E2 o! M9 h
** Output - Serializer Tx is connected to the input of the codec
! ~( r; y& M; N; g$ J( w% f*/# q* b4 H2 N P9 y1 E2 T6 d# I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: ]" g# A- B9 v/ UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" k& g+ \2 G. R& uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' G( o$ @. F/ o4 r) ?. g
| MCASP_PIN_ACLKX: Q3 l d% p5 S
| MCASP_PIN_AHCLKX
6 I5 m( _7 o( g. G. g! |8 {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 W) U. k/ z" n( h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - c2 j4 ^; V# k% w! ?
| MCASP_TX_CLKFAIL
: X, \2 }' q+ W; k| MCASP_TX_SYNCERROR
3 k; O8 \3 |; b) y2 Q8 n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% l5 t4 J5 l# F+ }8 P( ~| MCASP_RX_CLKFAIL4 w" l( v2 @ V* {: l1 p! Z* I3 B
| MCASP_RX_SYNCERROR
]: ? E( K" t4 t" @. A| MCASP_RX_OVERRUN);
8 }/ \3 I/ k* S; N. D} static void I2SDataTxRxActivate(void)! @; _* \: ~! k% N
{0 U, O" |2 Y" W* Y/ j2 v: Y0 U
/* Start the clocks */
/ T, k& `6 \- Z+ o+ ?( p4 {5 Z1 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% l, a8 u: Z5 G3 r' B j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) Q: T) p( X1 U9 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 M5 G9 _0 e- A: r) g3 D0 s0 s
EDMA3_TRIG_MODE_EVENT);
8 c5 `6 K8 m# Q$ A7 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 y* z T# r$ D: I3 b3 C# _ SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 g) x7 x' V! s' XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# }* c7 {0 \3 E! j9 BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 s' x; x6 l* {7 {& T- m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 S3 Y1 j; I- ?3 B- T* XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% c6 D0 k0 A2 u: C# ?7 `* C# _0 k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- g) y8 G* C; i. x6 o5 U} * Z( f) K: s/ s$ n' r+ ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
: W8 g' M& o& g9 e |