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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 i7 Y2 s9 M" m; S: u! j# v4 i; S
input mcasp_ahclkx,5 K N) g& Y, \& w6 C% u
input mcasp_aclkx," s9 Z% ?) o* L9 K
input axr0,# J7 J3 h6 f* T. D/ v6 P3 R
' ~( K; h% n- p+ Q3 @8 Woutput mcasp_afsr,
8 M/ f6 @& E) k/ }5 Foutput mcasp_ahclkr,1 j" ^+ \! X2 j8 Q) ^. n" ~
output mcasp_aclkr,8 u) \1 q5 K4 ?8 }
output axr1,/ D" p" Y {! ]4 E) n/ F
assign mcasp_afsr = mcasp_afsx;
1 z2 D+ s a+ c. X# z! cassign mcasp_aclkr = mcasp_aclkx;( { `% l# l3 j( [5 j
assign mcasp_ahclkr = mcasp_ahclkx;3 ?( z3 z5 T5 Z& i3 k7 ~
assign axr1 = axr0;
7 n) H* F- `6 b, F* Q( `6 s1 R6 M0 f/ r1 N/ c6 D, q6 J8 i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- P+ T- N/ H8 W" A6 ?static void McASPI2SConfigure(void)/ @7 L% S. h/ }% u& r
{
- U5 u) ]! `& @" fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 N% [% {, O. ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 w% H) j+ t0 x" ^( }; W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( S3 B. U/ G2 V+ C+ l0 D/ vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 U v, F1 n7 G" v# M$ ~: c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 J* @3 C+ v2 p1 {( Y3 f: d% V8 U
MCASP_RX_MODE_DMA);
# J- G% b' f0 s3 mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ Z& F6 H$ z* U4 V1 D/ [! v1 P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 y$ I1 O$ ~! p+ {* oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + M2 I9 P. n4 p: S$ M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. [$ j0 g; M1 j" _5 a( V9 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) r4 ]0 ^' O7 H, P+ x& q+ X4 x3 v# |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ T- z" k/ a/ B6 u9 [9 ^$ m4 @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" r( b$ D) J* Z% F; C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 c6 P- W0 l; d6 y/ p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% E) d4 b3 {: q( Z( T/ h
0x00, 0xFF); /* configure the clock for transmitter */
$ M, @1 D) n9 Y* m2 A) rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; ] D0 o, S# r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; h. U* @8 [) G* o1 x( AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ n3 U$ v- C3 g% q2 ~: h& j
0x00, 0xFF);
' g. U' K* Q8 e2 s1 N) j; t( s i/ Q2 t' B. f3 c' K) u) I' E( J
/* Enable synchronization of RX and TX sections */
, h ~$ T% p6 Z) W; vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: f0 W6 _2 p$ e! c6 p2 Y7 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ R; S+ r# y& R- J- Q0 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" Z* N+ W0 ^" g# ?$ }3 X, s! c5 h** Set the serializers, Currently only one serializer is set as# D* N; s* k6 Q0 `6 S0 P5 S
** transmitter and one serializer as receiver.
3 P2 E) b, N5 y7 C. N' r4 W; c*/
7 t5 A0 Q4 h7 Q; k3 t! RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( ?4 J! M" g1 z9 K; W4 ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. {$ A/ h3 N8 E8 g/ o& ~! M
** Configure the McASP pins
% ]6 h0 r9 h) k" Q& I/ ^** Input - Frame Sync, Clock and Serializer Rx
/ K+ ]% E3 b" b/ y! z** Output - Serializer Tx is connected to the input of the codec
5 Z* ?3 G+ C o*/
: p$ F8 S/ i8 @ Z+ |4 y" B- ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 I* u$ {4 U( a! `- ^7 s3 QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' g9 ^* c7 Q9 j8 o% f" }. fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. {) R; k2 Q; p8 M+ Y* b
| MCASP_PIN_ACLKX w2 v+ D" T7 ^" G& k* i
| MCASP_PIN_AHCLKX
8 I0 z4 d2 P) m& ~4 E+ ^7 p: L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( c4 a/ S* s& {: w* HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 h, Y) S: ]. E" q/ ]
| MCASP_TX_CLKFAIL
2 |6 Q1 I- r; X; S0 G| MCASP_TX_SYNCERROR( A* _4 y/ T( ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ R" @0 S; x6 ]) e7 V* H| MCASP_RX_CLKFAIL1 U: R/ s, q4 n9 ^ {6 x
| MCASP_RX_SYNCERROR ( |6 ~5 N, T2 o6 A
| MCASP_RX_OVERRUN);5 m8 H( `( Z: b0 Z8 A% N2 @
} static void I2SDataTxRxActivate(void)
' Y" D! T6 l$ ^) Q h{8 V7 d1 C6 Q/ H; ]
/* Start the clocks */
7 p( _" C! d B# OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- P* ]0 N( E6 [" T4 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' e5 G9 u7 g ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ u& W( K& X7 k. T) WEDMA3_TRIG_MODE_EVENT);
3 r. I) l# N, } s# _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + s$ \+ B% M8 \( v! Z l I% |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% z' ^' L' l; o4 b/ c) V3 j5 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 P* m: t1 o- `$ ]# yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ l2 G# z/ B# d4 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, G, i. _- J3 ^9 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, W8 |! p+ s G/ KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. \7 a" E; o( S4 v}
1 u# e. C# W; l0 s; E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 t3 e- p# E2 g }* Q# j
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