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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- d5 e7 C( m' c
input mcasp_ahclkx,
! ~3 u o5 K+ |* X2 pinput mcasp_aclkx,8 C' [/ O4 _# n' B# q
input axr0,
& J( H8 ^. i' p, _ @ ^, f. Y2 C- q' r
output mcasp_afsr,
B. M3 G2 F5 n1 F; W* K% Goutput mcasp_ahclkr,
2 \! K* P6 ^1 Q) qoutput mcasp_aclkr,
* p' A6 d" P' W; H: m h) ^output axr1," R8 x* q" L7 v0 W9 ~
assign mcasp_afsr = mcasp_afsx;. \/ [5 x8 c5 G- A6 i H
assign mcasp_aclkr = mcasp_aclkx;8 U. `+ p3 T o6 {0 a$ z
assign mcasp_ahclkr = mcasp_ahclkx;
: G1 Z5 S3 w, s7 |0 u9 dassign axr1 = axr0; 2 ~. Q8 V' b# k( Q5 A7 `
. L) s- R! D4 c! Y- z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % U. H( o% P" o5 A( o4 U
static void McASPI2SConfigure(void)/ h" U+ n7 K! r) `, `- v z: V
{
( D( `2 P {9 T# e$ R# @7 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 ]( R. p- c3 G$ ^, qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 v4 Y4 @8 s9 x8 P+ R& s! WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 }. @2 h6 R% [; A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ t% Y% Y: O6 Q3 b. Q# kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ L6 e/ c! h8 H5 @, ]
MCASP_RX_MODE_DMA);. T6 P h' E2 ?9 F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ S$ E7 d3 i( \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, b% K0 d5 D% C. _1 `3 V9 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + m% x' J6 i5 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ p5 [7 f" T; q2 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * q9 |, G0 l7 v& `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 v% v9 b4 ]4 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 ^+ J4 a$ q' V D. X& `& ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . T" l: t! d% r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," E0 J! W3 G+ I, G% u
0x00, 0xFF); /* configure the clock for transmitter */$ B0 J+ j3 ]# i) O- c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ V% `' Z' {$ K% U T( f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 E2 y4 M E$ P- h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* h. a( ` o) L8 f: m: m
0x00, 0xFF);
" X: f3 X4 k$ @( S
6 l3 [( e* l* @( ?/* Enable synchronization of RX and TX sections */ 6 h, x# R. p( g- {( w$ J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& t9 m9 u) a# E% S9 G# X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 y( V- T( g( ^1 @1 V5 e0 v& s1 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ D( z, t G% y* Q
** Set the serializers, Currently only one serializer is set as
. K" E3 b4 W4 j6 F; g** transmitter and one serializer as receiver.; b5 B/ N' p2 [
*/4 j0 _% y& C) L2 o8 Q; P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 d$ B, W% U: H1 \0 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# o! W6 X: Q: Q0 z# B1 H* x' K% q
** Configure the McASP pins 3 r* V5 r9 |% r( b% H9 Y( }: [
** Input - Frame Sync, Clock and Serializer Rx
; L- a' t8 s+ O** Output - Serializer Tx is connected to the input of the codec
3 Q9 E" c# P7 u: _8 ]9 t/ C1 }; f: T*/
6 c5 S7 y1 U( A' F& H$ _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 t8 Z& f/ |+ |+ N0 s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ y+ I5 j9 C7 j9 |; `6 e T* `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 ^) k9 W) L5 s
| MCASP_PIN_ACLKX- O. M; A- \; O: ?) E
| MCASP_PIN_AHCLKX
; A- K6 s9 z C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 y) L) E9 l& X( H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ H5 Y7 h. Z- w| MCASP_TX_CLKFAIL ( L$ s/ I, z! P( |- a6 ]0 j/ N% w
| MCASP_TX_SYNCERROR
' k' X5 c) e8 v* s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- t$ z! k4 I7 {3 L, v| MCASP_RX_CLKFAIL) d! O- h- u3 A, }
| MCASP_RX_SYNCERROR
% |; x+ a" |, E5 K# W9 {| MCASP_RX_OVERRUN);- E- ]3 s- i: i4 ~
} static void I2SDataTxRxActivate(void)
, Y/ z& y+ ^, \6 @- N& A& J{8 M% {+ _+ U! s7 M( p
/* Start the clocks */1 g" k3 [ i4 L8 m3 x8 M, h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 \1 W! U" p2 _& i" [2 Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" I/ n K7 j' \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 G; Z" o5 k0 I& m- s& VEDMA3_TRIG_MODE_EVENT);/ u o3 U0 w- F0 ~- [8 x$ r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" U' r% D9 W( E3 J3 x; d& fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" r6 V! A. \ }# V: h8 XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* k" N! Q7 T- ~0 {2 N. I- CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 p d6 R! _6 @5 O- uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. N- ]# \" S' n! H8 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( d, j4 i# F5 g6 S9 J8 k6 x' N. DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ ?2 }% g* i8 g# \# e, `
} 5 E; D% K# Z9 l! E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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