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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& K, @6 A+ E- ~; z' F, v
input mcasp_ahclkx,
5 L- r7 N1 Q: x! Yinput mcasp_aclkx,
. q* Z2 ]) [7 E$ ^1 @input axr0,# D/ s3 V6 H0 G9 w
+ B, M/ |0 [3 v' l! qoutput mcasp_afsr,$ z& y5 W7 }! H$ B: ?5 S
output mcasp_ahclkr," W4 _' T4 L$ F! F
output mcasp_aclkr,
" l" y! G4 y& A) V0 ~: A% foutput axr1,2 F4 ]; ]; d2 g8 C3 v$ s& C( d
assign mcasp_afsr = mcasp_afsx;' L: ~0 o8 o& Z: a0 J$ P
assign mcasp_aclkr = mcasp_aclkx;
1 z- a g5 ~. S$ w1 b' ^+ B. c# lassign mcasp_ahclkr = mcasp_ahclkx;
$ D" @3 ]8 d' X# n2 a: ]; L. passign axr1 = axr0;
) [! v( [' r) A5 r7 `+ y4 I
/ M$ W9 M+ J, R7 I8 d9 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 x' B) D1 f% b" U7 F
static void McASPI2SConfigure(void)9 ?9 [& d7 r8 E1 [( N, A
{
6 `0 e, ~' H) C7 s4 A7 F7 uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! `; {/ i) f# U9 d+ K9 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 ?2 T7 b- c% G2 V* A# f# r3 pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 v# s& w% k/ Z) [" i7 u# `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// n6 Q9 F0 i7 S' v- h7 j1 S9 I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. k. l" w, V3 |: H* g. H; V. f+ H5 }MCASP_RX_MODE_DMA);
C3 Y* o8 p( Q% w- T+ nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. I8 O, c+ N' l+ l7 WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 g4 n* b8 T7 x3 q: e) c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 [$ [, P6 V+ j/ F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- b) @# f) z* C4 MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 O. x0 h5 d5 b' P" o3 k, e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; G5 M7 n! R h+ h6 G" m; E# Y9 `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ g' d1 g( R3 D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % L4 _' J& L* r. r, N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 V$ f3 R; s4 w- G+ N0x00, 0xFF); /* configure the clock for transmitter */$ a% }- J6 U. t$ F: A+ s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
E' O- j, V3 d+ {1 N4 i' \. wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & K0 D* A Q! D" x7 E9 v5 v8 c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* k6 @2 ^9 K$ D2 p8 s% ^
0x00, 0xFF);
$ I) }" L6 b3 p0 O) [- i4 [
7 ?( ~1 n! S; U# u! A6 M4 P/* Enable synchronization of RX and TX sections */
; E! C- Y0 d) ]' R, K- g! C, DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( i4 W( p/ f$ X" A4 ~- I5 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ k6 i) Z( o; [- H1 N% t& k+ v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ ~. l3 P" X/ t; F; J6 f/ n
** Set the serializers, Currently only one serializer is set as' U: E1 a% W3 `+ }' S3 [) ]
** transmitter and one serializer as receiver.
: q o3 a: P% B' v2 v) u*/
$ i" @( \8 G/ A7 oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# f, t+ A, A% V* N5 s" X! VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" U! F& p9 O- H K* X! a. i
** Configure the McASP pins
: |. ~4 l* _! G- Q$ Q7 j( [** Input - Frame Sync, Clock and Serializer Rx
) T( S* r" V0 M+ y7 k. E** Output - Serializer Tx is connected to the input of the codec
% g5 V$ n' h& w Z. Y6 H( S# b*/
& I& | Z" O6 T# L1 ~' JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ O4 O6 R6 e2 d5 B- R. TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: W+ F, [- A1 i0 x3 PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% x) V ?1 d& f6 S) v. _& g
| MCASP_PIN_ACLKX
2 g" E5 A+ [& X F( w. J8 Q6 J' M3 Z5 F| MCASP_PIN_AHCLKX
z! o( y* @' m1 e# ]" I3 P0 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% u; ^$ M$ A: `0 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . ?. _" b% `3 U$ B
| MCASP_TX_CLKFAIL % L7 m9 e( v4 @7 P& ^) |9 G
| MCASP_TX_SYNCERROR4 l. N0 n: L1 y& M* u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& v# c( }$ G9 h/ u O# `| MCASP_RX_CLKFAIL# I$ U6 e! I9 A
| MCASP_RX_SYNCERROR : [* a- J% x* Z0 R5 [' `$ r+ G
| MCASP_RX_OVERRUN);
5 L& `+ j k' a3 b- b l} static void I2SDataTxRxActivate(void)4 r( R# y5 x& b$ U
{
, S! T8 ^, \4 \2 C/* Start the clocks */
3 M9 c/ F, B6 G: A- |- v, l; vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); a! P( |" X y1 N, s: C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" o6 K1 v6 P' f! o0 R2 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 C8 a8 ]2 h# I W
EDMA3_TRIG_MODE_EVENT);! e2 @: g F& U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 d" g+ C" ? C' N# y V, [8 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. R/ @4 Z y& M m( MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 c4 A: X- e- Y @% P& J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! u% w: I- k9 P. ]8 z @1 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, f+ x/ M% Q8 E) G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: a. _! r7 y4 e( g3 @2 V) LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" X' o& k t" K8 b; M# @} t4 g5 W! s% U6 {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 \3 K: l t& z2 C7 o
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