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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- G3 m# {+ n& n8 H" D, J
input mcasp_ahclkx,' {6 N2 V s& U+ T3 J1 [
input mcasp_aclkx,$ b- k& R1 Q8 q0 o9 L
input axr0,
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, g/ k0 s- v0 T6 v5 a! `7 e' Zoutput mcasp_afsr,
! s! @& v: z% K. t7 V( Foutput mcasp_ahclkr,
0 V0 p( s6 U/ a# s3 aoutput mcasp_aclkr,
# G$ ] u; u/ I- A( Koutput axr1,
9 [% ]( s# Q$ f assign mcasp_afsr = mcasp_afsx;
! r7 x0 g) X0 g+ \1 uassign mcasp_aclkr = mcasp_aclkx;, H/ {3 v9 \4 T+ F, }$ p
assign mcasp_ahclkr = mcasp_ahclkx;
% ~2 _9 D/ x6 rassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 o; s+ G. f7 j- o e
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 }7 _' |, p n3 x/ d( v9 W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- e5 }5 H$ _' Z4 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 r! x0 f6 R$ I. M* J; wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 O9 c8 H' D9 R2 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 k0 E3 Q V. X* `8 v E: ~
MCASP_RX_MODE_DMA);
% {1 q* ~; ~6 x5 GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 @0 c" ]% t( N6 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 w, \' s5 U4 T/ M1 n, \! Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& X+ s! C$ v# ~% K6 PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 K+ f1 M8 p6 |- d/ ? eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, F6 L' T7 h9 k4 B$ K) xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 h8 z. P- a+ T8 [$ D4 SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 `2 ]% x5 y6 L; `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" o8 D; o4 ?0 d$ g, sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" W% c$ |* n( t7 y0x00, 0xFF); /* configure the clock for transmitter */. F9 u' Y8 z& U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 I9 @7 a" l$ s* X4 _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 [. I% h0 `& C9 E* B5 l6 q6 g1 E9 F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ Q O5 H% z9 n* T q: A6 Q5 `# b
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ g7 n) X+ B2 x& r8 F- ~+ \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% |" C2 _2 I, Z2 h3 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ ]3 C9 |; N( O% M8 R/ [ V) j. FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 h# o/ u: M0 c* X** Set the serializers, Currently only one serializer is set as4 B: S p7 Z$ F
** transmitter and one serializer as receiver.1 P$ \# V5 `+ N3 _0 P) L
*/# i: o/ N: m D: q' a' G( W" z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* ~' ^* j: Z1 p6 M8 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. }( C2 V% D: w6 a' w** Configure the McASP pins
/ y( l. T% c8 P) r8 h6 B** Input - Frame Sync, Clock and Serializer Rx
: Q7 V$ Y+ U6 E# j0 b+ V** Output - Serializer Tx is connected to the input of the codec
; o1 `: D* i' t7 E0 y6 H*/
" J( n- J: p6 `; R8 l' AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 d. B: j% m% z# K7 a/ BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) G% c9 B4 ?/ G3 j! C7 e9 {; p! I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! o/ L. h5 {3 {8 O2 ?. E: l8 L
| MCASP_PIN_ACLKX
3 A7 F! q3 @& ]& ?* k| MCASP_PIN_AHCLKX2 h3 }8 }3 l9 a; }, P% R' _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% @; m0 g$ U8 w k. R3 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
R- t9 ^* u8 h: E' b0 J| MCASP_TX_CLKFAIL
' a# o& B C1 F u, s2 [; {2 F| MCASP_TX_SYNCERROR
$ _- S$ Q: d- I+ y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & i2 x: ]0 q, z: k( K
| MCASP_RX_CLKFAIL6 j& h* E+ C4 T# b4 T3 O" u n, _
| MCASP_RX_SYNCERROR 1 R# C1 R- o2 |3 n
| MCASP_RX_OVERRUN);- h$ Y5 Q& H- x+ }3 l) \( y
} static void I2SDataTxRxActivate(void)$ b, Q: I% P7 l$ d$ N
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/* Start the clocks */
. P! a4 j; m3 O& M# a" M' i0 R! jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); Z7 w# I' b r1 H X @& x6 k9 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* r/ j2 j+ C ]6 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 _9 S) P+ N: B V$ W
EDMA3_TRIG_MODE_EVENT);
* S! [- u# Q2 Q. k0 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' B _9 |7 D0 i6 d! F2 X; I( D- REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 y* n/ n9 x1 e! I/ R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; i) B3 l. y1 T6 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: B& O \: m% K- M! l4 J0 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 i$ I+ p9 n _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 b# ~. c( {8 x, o4 z* ]! M+ i5 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; w5 r2 @5 d" J}
1 E$ U. i9 N. F. V1 w a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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