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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ \$ U0 o* l+ l: [; M; T6 i1 yinput mcasp_ahclkx,
" t$ o1 H5 H( e% @* _5 Jinput mcasp_aclkx,- o1 H$ s, z, L5 e
input axr0,
9 B" E# ^$ e% J- g# x. l9 x# g/ T7 i" f' H) J
output mcasp_afsr,
1 T, b0 b5 S$ U6 W# T9 Ooutput mcasp_ahclkr,0 }$ u @% l% |% M
output mcasp_aclkr,2 I6 Q3 } L$ [6 Q' t- [
output axr1,3 A2 ~% X7 g t! N- }! O, N
assign mcasp_afsr = mcasp_afsx;
/ C# V5 O. k/ q) Y/ Iassign mcasp_aclkr = mcasp_aclkx;
6 T: @: }; Z/ B# J( a, Z" Hassign mcasp_ahclkr = mcasp_ahclkx;
6 Z2 c" v( k5 r* u9 [/ X& [assign axr1 = axr0; / g: K+ n/ }2 V
& ?6 D" M! u1 l& z* P: `4 G( f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 A ]1 o6 g* I
static void McASPI2SConfigure(void)
. ~& A7 A5 `% E! O9 C{
* d7 J) S" r$ |0 M9 a) RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& c$ J9 [8 A# b9 u4 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: S( Z) n* W9 I/ Z% EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 I# p. w/ ]* Z7 T( f( J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ N8 Y M- F B6 m& `, |! a, y" ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, O* N7 {! R! M& [4 p$ v+ X/ ]& _
MCASP_RX_MODE_DMA);
9 `; Y$ c; c2 e/ L" {; O/ {. F) vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% i M+ d0 P w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 v: P9 O' R" b4 B! w HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 q5 w; T& h4 U# ^* P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, U( g4 ^9 G- p% K3 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' b! ?0 G/ X' O% d* |+ W: E& p& kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// }( O9 h( W4 ]; ?3 {. ~% u% Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. m6 ]9 n, [ ^. {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 \' t/ v' P" x2 c# W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 \' T0 L+ L2 X3 L# ~; n- R( @! @0x00, 0xFF); /* configure the clock for transmitter */- S# p2 L) ^$ i& @4 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& a! b/ b0 N( u: nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 c8 q- t) R2 W5 r/ |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ E0 z; d! B0 M" N
0x00, 0xFF);
9 K4 b2 R9 t, B6 G$ n$ M' ^3 a
/* Enable synchronization of RX and TX sections */ : X$ Z6 x3 x, J- c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; ~& [6 E* G5 R: g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ E/ o$ D R3 g5 K$ RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ `7 r, x6 X3 M. a: x" `
** Set the serializers, Currently only one serializer is set as
5 M# g x5 w3 t" r# e** transmitter and one serializer as receiver.
: J" S! c0 h: E*/# S$ M; w9 A) w: j% K+ q6 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 |' C+ p2 y1 @9 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) Q; y- A6 y" b! o7 r" Q; L' {# `
** Configure the McASP pins
9 Y: U7 D& m. R& M6 z/ A1 x** Input - Frame Sync, Clock and Serializer Rx
% F! E6 {- |2 J' R: i* Q3 `$ w** Output - Serializer Tx is connected to the input of the codec 5 n- R5 l3 D: l8 ]
*/
- E# [/ I7 g) b: K7 r- `1 R* F5 \6 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: u- O! W; @% QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- {* h8 X @1 f: S$ d% J6 r4 s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% }, }6 Z5 k g0 L( Q, }| MCASP_PIN_ACLKX
- [ }, ^& s" d6 X7 U. m6 z| MCASP_PIN_AHCLKX$ ^" P0 {0 O0 }' y2 u x) D/ L5 ~+ N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' n5 [( j+ r1 t2 e5 @4 @$ g7 R% W4 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 n( t7 Z+ k* P; l9 P5 \. n
| MCASP_TX_CLKFAIL
2 _' ~4 N- d4 F8 P$ N# f| MCASP_TX_SYNCERROR
& z( a c' b# t) @/ A+ |( G' e3 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 L6 c& v5 O/ Y1 U: Q* n| MCASP_RX_CLKFAIL+ ]2 S/ J( W; n; S
| MCASP_RX_SYNCERROR
2 y5 a+ `( k& K' ^| MCASP_RX_OVERRUN);* U+ T( m2 T/ p. D# @
} static void I2SDataTxRxActivate(void)
u1 E& G, `- F8 i7 s( N9 c3 l{
" p; P3 ~* [; L6 j/* Start the clocks */
, b0 I4 ~, [- j: pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! P3 G+ [! ^4 ?8 g9 c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- U2 i+ ?' i0 ]: x. a `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( e9 ? ~% y+ J" t! b: Y( w: XEDMA3_TRIG_MODE_EVENT);! h7 b$ g+ u3 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 ]$ Z2 a0 |/ h+ w' e9 I" S# w. S0 gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, ^" @7 z6 z; V0 E _4 G/ C) J- I6 V' KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 a5 K* b* b- l1 N7 C5 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 ^% _+ b3 f- |4 ~) }9 }* m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 T8 N q. e1 T! A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 w6 v; @3 o, t) ~. m4 V8 d- b2 r! XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 }0 f x( T7 }( Y- o( q) O5 {} ' e! _5 {3 U0 c9 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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