|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 H( N6 V* P& w. |, P! c; m
input mcasp_ahclkx,
, e: T; A* J2 h9 v1 tinput mcasp_aclkx,: i( ?. U/ U) u' s) \& L! \
input axr0,
. W5 [ o/ _% k* n2 D' L7 x; y6 E( S$ o: z, b+ {& h
output mcasp_afsr,
3 W1 Z( p& i1 {output mcasp_ahclkr,! N X) H* L/ a+ X
output mcasp_aclkr,
& ^( o! l( b+ C: K, k# Xoutput axr1,3 w6 W+ D. _; A
assign mcasp_afsr = mcasp_afsx;- n+ k' k$ l6 q5 S& i; c
assign mcasp_aclkr = mcasp_aclkx;
6 m/ i2 F! C( G& C; [9 e/ I% c) @assign mcasp_ahclkr = mcasp_ahclkx;5 Z* `; x9 ~5 `7 [$ ?
assign axr1 = axr0;
, C/ K+ n; ~5 c' V* C3 _7 Q! P
9 i" y+ Y) @& r6 e" y1 U. F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 m: \' i% N& p6 ^
static void McASPI2SConfigure(void)
1 x% k+ o2 d' E! L, F{
0 k6 T1 \6 h$ l- I6 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( |1 E+ O7 M0 V" J2 | x. z/ D x- s- b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. x, X2 P5 `" _& W# h1 J8 B) H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" h7 y" N- m1 ~9 c) T+ f( K& h' ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! M9 z4 x6 r* [- IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," q& d }2 W4 ~; L2 ~
MCASP_RX_MODE_DMA);
# x0 y! q& S8 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ N& j" [ j* A/ i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; v. l) ?" Q9 q9 F" G9 H& M# X' M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# C+ ~- g4 @: K2 P! C5 B6 JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
l& x0 [! C2 |! a# J& c- v8 Y6 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 Y- u/ |4 _" \9 mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; i; {+ A1 y: HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ P, P4 R1 g3 L& `! z/ pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - Y* w( w& F5 S( b/ W- c" U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% C2 ~0 Q; _6 m0x00, 0xFF); /* configure the clock for transmitter */' E1 i, r0 b' H3 H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 M& ?- ?+ e4 H5 g% ?" f" B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 a1 M% W; V8 V a, Z5 TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 X/ I) F: G$ ?% k" ^
0x00, 0xFF);! D6 y( {/ t' X d/ ^
# ?0 p8 Q, ?+ Q. e- f
/* Enable synchronization of RX and TX sections */ ( x) T ]6 F/ F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* S. y" K8 q) o M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 f2 o& b6 v; _; p! `6 x. p. Y/ |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 K% F. i# d" r, l. W9 N( y6 @
** Set the serializers, Currently only one serializer is set as
) |4 O& V- I/ b) o+ g- u1 P** transmitter and one serializer as receiver.4 c! Q% z+ W: J1 P) W
*/
( A8 m) I7 W0 H- M* R1 v1 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 |: _- a2 _ }. \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ ]( I% {" K3 [. ^9 Z** Configure the McASP pins . R. u$ l$ H: Y# R2 T9 E* w |* G
** Input - Frame Sync, Clock and Serializer Rx
! ]9 U% J, Q- ^) w4 c' z** Output - Serializer Tx is connected to the input of the codec
z0 J. A# N( S% q1 ?0 M5 n*/
' o9 [, s$ p9 S' C( _. e* qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 Z+ l! O* B& I7 j7 U$ {; b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" Z5 q/ A! [+ ~) z+ i2 M4 {, @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' L! [3 A9 w l* V
| MCASP_PIN_ACLKX, c( C' a7 U( W. o* i' T6 d
| MCASP_PIN_AHCLKX3 Q9 w7 y- C3 Z. I9 R) d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 ~4 n1 Y+ p3 ?* A# M$ q* ~0 j. @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; A( n0 _' s1 h. g
| MCASP_TX_CLKFAIL - W# B6 v9 E( z6 D ?
| MCASP_TX_SYNCERROR' ^7 Z6 M2 o5 V& X1 O& ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * j$ R6 w2 y, r# s7 ]+ Q
| MCASP_RX_CLKFAIL
9 h. j2 c, R* r0 a| MCASP_RX_SYNCERROR 5 F4 C# Y, o) F4 i
| MCASP_RX_OVERRUN);
. u6 s t7 \5 d' a} static void I2SDataTxRxActivate(void)
) x, U: j+ m1 _3 a$ G* @5 F" E/ P{" Q5 W+ T) k1 O# w- P, r. T( d% m
/* Start the clocks */. D, p( V" K0 p! u* }, T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 `3 h, k# O3 P( }& Z" K& {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ p# }* x# d" Z/ {8 l* P$ R; Y! PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. a7 M! r% v/ P4 m' U# ?
EDMA3_TRIG_MODE_EVENT);. T5 f1 n3 f8 s* E c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 Y3 N& `1 B: W7 OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% V4 e- a' @: ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 L' p& }$ H( F0 X" h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& G+ V' X: O8 I, a; O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% C$ b, l4 d; _0 X, e0 s9 \* z, d# SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% S" v1 T0 [7 i7 b. n. d" A4 q! j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% W- y0 J: Z# Q, Z( Z
} ' c8 D5 z, q. m4 r% I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' ^ y/ T+ J8 P4 g8 H
|