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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& R# ]8 H4 }0 F M0 W/ G
input mcasp_ahclkx,! c# \* h& c! d. U
input mcasp_aclkx,& X" d6 T1 F& o# a) b
input axr0,
, Y6 n) n4 M- }/ X; t* R: o2 `# X6 n7 u2 Q- u
output mcasp_afsr,
( Y' m7 l6 Q, T% W* {8 voutput mcasp_ahclkr,( m* i$ H+ t9 M1 B8 e
output mcasp_aclkr,
/ c3 G8 ^8 Z/ p& J, `, boutput axr1,3 W8 U }: {+ t' i4 \( t1 ?
assign mcasp_afsr = mcasp_afsx;
7 s4 a" q0 C `+ \/ Tassign mcasp_aclkr = mcasp_aclkx;
1 a# A2 w) K& ]6 [ B$ [assign mcasp_ahclkr = mcasp_ahclkx;* ^* z. }* z, Z3 g* b4 ^% l
assign axr1 = axr0; 6 G) i6 i1 t& \6 }. K
/ [4 W3 D1 r: i* C* {9 W b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
{% f4 F6 \+ I. kstatic void McASPI2SConfigure(void)$ A7 A- N6 Q: W) ~2 W* m& Q% S
{
0 ^0 C1 z6 y2 ~, }McASPRxReset(SOC_MCASP_0_CTRL_REGS);, L7 J1 }/ m9 F4 _) W2 D5 B9 M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 j5 B* q( O! F4 y) v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 T3 i6 G7 X! T3 I9 }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
_( C7 |) e. i+ Z3 g& iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 n2 N4 l& T f) ~- o4 |MCASP_RX_MODE_DMA);
# t" G9 d) [( a e" kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% M# I. C4 X$ ?+ D0 MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" o- `8 P7 B' vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 E! }2 j/ ~' R2 s5 k6 v( oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ R1 z4 t& e' h( X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: h9 x' a" q: C1 ~8 b3 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 M, @( A0 d0 F$ `! S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 b0 ]8 w- v7 l/ m* P; H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! n. i/ a2 {5 t6 Q, p* v# Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ ^2 l) V, [0 c; {2 ]0x00, 0xFF); /* configure the clock for transmitter */5 d- S: L- ^3 L; G* L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ N. ~. I* y" ?4 x6 Z; I. ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" B! |! a8 O4 e1 d% t2 {. QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ [0 T; \9 A$ [8 q+ k( p0x00, 0xFF);1 y1 _* Y! r8 ~: ]! z: ^
# B3 b. i& x: p; P# W; P
/* Enable synchronization of RX and TX sections */ 0 E5 z; @/ ~$ h( P7 |+ B3 m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 n; T5 p4 N" Z; w3 G8 y- M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 u. c0 B3 h0 h9 S9 n$ UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; R2 ]" G2 L* Y7 W' V** Set the serializers, Currently only one serializer is set as8 ^- }+ f! E) Z$ e F3 B
** transmitter and one serializer as receiver.: E \& t! ^2 U0 Q/ p" @
*/
* [" F' Q. l9 Z; v& wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# _) l. v' r9 @& `) O$ a i) U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
e- d3 v$ `1 i** Configure the McASP pins
' N& q3 W& f3 W( F** Input - Frame Sync, Clock and Serializer Rx0 V. E$ u& k) e' o9 Z& T
** Output - Serializer Tx is connected to the input of the codec $ o7 D7 ~7 F% J& `# f& R6 J
*/
9 ^( E6 K1 e' ~9 B. `3 jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- X& z; Z L/ q6 t: j6 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 F" ]; f9 o- @" ~2 v8 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 O1 H& o6 |8 o7 v| MCASP_PIN_ACLKX
6 I# L, L' t( w) f7 ?' h| MCASP_PIN_AHCLKX2 d5 K% m" \2 u7 N0 L# T5 B: s9 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 w# T2 W# Y' e! N1 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( U" f0 r& O0 ~0 E ]+ f0 }| MCASP_TX_CLKFAIL
8 C. [% t, M& m$ A) V8 {| MCASP_TX_SYNCERROR
4 E& X3 U' [" e( s% ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! G7 V2 f' q4 k6 _| MCASP_RX_CLKFAIL/ T- A3 Y1 H- P. l) `; N
| MCASP_RX_SYNCERROR
7 ~, M# J+ Z9 [9 {+ B| MCASP_RX_OVERRUN);2 W: C( K, s; k& V0 Y! c7 p
} static void I2SDataTxRxActivate(void)9 B" R+ \- E2 s2 ]
{& y/ \$ o" L8 z# j, W! |
/* Start the clocks */
8 U- K, B' g% z4 k5 GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. ]3 p8 L. n: y' t1 g6 E% |, TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ M N& u' J e o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ Z. P0 R: H2 [1 z7 ]: `2 i
EDMA3_TRIG_MODE_EVENT);
4 H& B1 R6 v" A+ s6 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! ~- a/ q, }% |0 U7 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ c! ?5 x- Y v7 V9 S2 x+ NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 F$ e, J# ?9 s1 w L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, Y- w% D+ q: Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 k4 Y0 P* t+ R( J! AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 z0 W! m6 T {. X9 b& _: Q8 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' {; _2 M* U G# w} 4 p( N: D% D+ a* }4 _9 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 c: r7 q$ D( w
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