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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' q$ ]+ e7 H7 ?2 a) h* z% L, I; D& _9 @* f
input mcasp_ahclkx,
! c$ g* p5 t- a$ p% {input mcasp_aclkx,* u8 J3 s1 r' `$ T- `
input axr0,
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output mcasp_afsr,/ w3 U" o6 t4 P) n6 u9 m) u% t
output mcasp_ahclkr,
+ G6 ^8 B6 w) _. voutput mcasp_aclkr,. U* k, _9 S# v& {
output axr1,
9 w- D' t' I% ^) g3 b7 j assign mcasp_afsr = mcasp_afsx;
, S/ M; g9 [ u( sassign mcasp_aclkr = mcasp_aclkx;- c& l+ m; I! y3 [$ p" X5 `
assign mcasp_ahclkr = mcasp_ahclkx;9 n b6 B( S, w1 u- i
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( V+ W* B' A% L8 ^5 H6 V! Kstatic void McASPI2SConfigure(void)
n, f, [- j, t{
+ P, F# B+ p; }# mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. Y. a* K1 l3 J% I9 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( r. X4 ?* r8 M6 M T m2 @) E3 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: N. v. Y- l h7 Y. ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% a1 t/ d1 Y2 K5 T9 \+ GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 w2 Y3 Q7 {# R& T# g' _7 u5 [
MCASP_RX_MODE_DMA);
5 P" k: a' E8 m( HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% g( J, r w8 X% J: m' I; P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
|) i7 c$ \( z" i. B# `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 Z* B5 l5 [ u4 n. H; F5 K2 e: D9 P6 TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! o* D9 H8 [& P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, M; g+ F/ t1 }: [( kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" Y3 e& o6 q. B8 L( P i& J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. W6 Q _/ o( Y8 p, ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' {8 J. r/ [) C$ C4 q* v0 y8 ^! R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; y" m0 o7 N- L- |0 Y/ m* J0x00, 0xFF); /* configure the clock for transmitter */
/ \7 E( _; }' ]: Z5 iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) l! l3 y8 _* D2 S5 |" q: p m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' |% _7 U/ d. L9 c# T/ R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 H8 l. u" H. W* |* [
0x00, 0xFF);
3 s0 X6 {) x+ b" h$ k
: F5 e H# e- \) T- P+ s/* Enable synchronization of RX and TX sections */
9 J4 T9 h; Y* {8 h4 TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, N3 Z+ X2 i. ?* [! W |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 }" R& }4 t# r9 aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% Z' |) O2 `2 }" F
** Set the serializers, Currently only one serializer is set as
2 ]0 u4 S, S3 U i& s** transmitter and one serializer as receiver.
* w! d5 f4 h" ~ J1 m*/
5 v; A* h, R' d+ z2 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& e1 [8 D7 i. v7 z9 o8 T j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 g3 y; j0 ` E* l' T- |! x** Configure the McASP pins 6 p" _3 u q& J& F( h* R: f
** Input - Frame Sync, Clock and Serializer Rx7 u% `( @7 ~" Z8 _+ ~4 U8 ^, t
** Output - Serializer Tx is connected to the input of the codec 3 m0 M9 I1 { v/ X% I6 `7 R2 Q
*/
1 _7 r# j- ^# g( I4 M xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. B' g4 C6 f$ _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 d0 W# F+ }0 u* [' o8 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 l, N* U" _6 `( F' L| MCASP_PIN_ACLKX$ i6 x* P9 I; P* f7 N' a/ ^8 J9 b# ~
| MCASP_PIN_AHCLKX
) P" V& G2 X6 j6 s, J. || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 r1 e% u3 \0 |: P; h' }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) o! `2 c* ]7 y1 F$ [1 R3 Y+ {| MCASP_TX_CLKFAIL & J+ A+ `8 A3 S8 P
| MCASP_TX_SYNCERROR
8 ` V% |" [4 q( J, t& u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" i( E# `' r6 T( }9 X5 f| MCASP_RX_CLKFAIL
* Z( s7 ~, X, N| MCASP_RX_SYNCERROR / p3 l' s5 d3 z% K; p% ]. ^: x
| MCASP_RX_OVERRUN);
) @' K9 {+ h7 K6 y7 n} static void I2SDataTxRxActivate(void)' A" q4 N! N# p6 [. Z
{
) S8 ^; r, U4 Q5 Z! t4 R6 |/* Start the clocks */
3 c" C- |4 c. Q" l" i0 R: TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# b! C, C4 P" _4 I% K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 Q6 u1 g( a' D5 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ M; `& q- N- O9 e* D4 @EDMA3_TRIG_MODE_EVENT);
; _' f. Z/ P2 G0 N* ]3 A! mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' m k+ t5 C F. @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 p6 G# ^+ [! B# Q- h5 T8 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' U' A5 W& s; U J I1 ~# @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& Y8 P6 z4 p0 h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 W x9 v% M6 s5 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- K( t) _0 i9 \) a9 F, h$ \4 \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; x* V9 z2 j; w* n
}
* u* K5 ]% O- ?% O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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