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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 t3 O' u, l, p4 v
input mcasp_ahclkx,
# r, H: G. W+ Kinput mcasp_aclkx,, F4 U2 ` L0 p. T7 G
input axr0,# z* o6 r& Y% H: i7 S* |
) N2 S( }0 j. d% w9 [7 k& X
output mcasp_afsr,1 k# E+ Q8 T& V6 J/ u; X) Q5 t" r
output mcasp_ahclkr,
9 z5 v% L8 {4 X- w4 ]) d" loutput mcasp_aclkr,: H$ v, S3 b+ I, q
output axr1,7 S5 D* _6 |3 [# B8 Q: m @
assign mcasp_afsr = mcasp_afsx;
\5 D5 h! I1 `; q' f* v8 ?: Vassign mcasp_aclkr = mcasp_aclkx;* w3 m. |# T0 P C: K
assign mcasp_ahclkr = mcasp_ahclkx;3 d1 w" w- p/ `8 R) [) d! B5 q
assign axr1 = axr0;
) J2 H% D: x) S+ g
j' u5 z( A* R9 o0 a+ E6 k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 T: W6 F+ K: @. nstatic void McASPI2SConfigure(void)5 x+ J# ?% y7 W" c" `% W+ l8 {
{
( c" }1 T* W- ^/ ~4 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 T5 x t, o" x0 {8 \# [# E0 G' V+ qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ E% H) D; V l& b( yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" P& y& V, E( r) Y! X& P" v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. Y% Q6 @; b' t8 r% B7 W' o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- ~, j8 H. B/ X7 m* g% ]5 t0 V
MCASP_RX_MODE_DMA);3 O6 f; w0 }4 F2 a' I3 j; @) d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& G+ w r" t. |' g. d1 v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) S/ w9 K: Y. G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ N$ S+ V: R6 G9 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, x& y1 F! c2 E( ]. }- hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ _8 ^8 M1 S8 A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 `, g+ ]5 X' G4 E2 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 C+ W: q$ a3 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . E! N3 x2 D4 t8 Q( J9 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% j! `) w0 x# X1 T. a0x00, 0xFF); /* configure the clock for transmitter */
6 q/ P& s2 x4 M# V- HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- y& ?0 ^ b: |( [0 x3 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" I1 c) i0 t2 @* e, j$ ^+ k$ AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 A! J/ Z1 \% y# P
0x00, 0xFF);) |: p" k4 \+ _( {+ h
% a; n) W7 j# j; n' l% K& ^
/* Enable synchronization of RX and TX sections */ 3 e' Y* A! C/ z$ ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 p. Y% u+ r( P5 IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: _2 Q4 U' a: NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 L8 S7 ?( ~) P2 [0 M/ j' T** Set the serializers, Currently only one serializer is set as
1 f' s8 E ?$ F& R& d( U+ {** transmitter and one serializer as receiver.5 n" s! @7 i" l! c: J0 q
*/: x. W. ^# F: i5 x, Z+ q& V$ }: j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' ]7 S- L) i! p' u8 z. X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ g) d: y' _) D- V, h6 ~& z
** Configure the McASP pins : ?' R3 ~) j( m* L
** Input - Frame Sync, Clock and Serializer Rx
# _& ^$ q: `7 A' U2 ~** Output - Serializer Tx is connected to the input of the codec ' n9 f4 F* l/ T; J6 R) G
*/
4 D* s: `3 ~, b8 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
k2 v* J' M& ]& G- HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* _% ~/ U! ^$ |" m+ v6 cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; G+ F. d1 F6 ~# R4 c4 ?, M3 {; i
| MCASP_PIN_ACLKX
7 b O" C: P9 J8 P| MCASP_PIN_AHCLKX
( g# Q; |+ M8 h# e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 U1 v% P3 R" `% V4 V( j' A4 G* R" QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * P% N6 G) b2 E& @! s
| MCASP_TX_CLKFAIL ! H- Z& L. f) _+ a7 s; G3 R
| MCASP_TX_SYNCERROR
6 `% X% G' o+ ~. Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ t- z# R4 P: D* C| MCASP_RX_CLKFAIL7 D: G; l0 T) \! Z w! x+ D
| MCASP_RX_SYNCERROR . [/ b1 u* w5 x0 V8 U# ]0 Q6 b& h
| MCASP_RX_OVERRUN);9 G, U0 j1 a) Y) |3 e& E- y
} static void I2SDataTxRxActivate(void)
( S! p' Y/ f+ N- P8 m{# r5 ~ P" B# B: `) j4 o y
/* Start the clocks */. d3 v7 ~9 S6 s) b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, N m1 a. `3 o9 ^0 d7 W; C; SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 Q+ `/ S& H: @! j4 K$ J3 S$ Y7 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 H- k$ |* O, P3 G, E2 \$ ^
EDMA3_TRIG_MODE_EVENT);" I2 M/ E( L/ u4 R/ A+ [* |& T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 i: J# a5 S% `' E, w3 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 J' m. Z$ I3 }$ k3 z# Q8 aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. w. C* _- s7 P* |( N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' N( `+ @& B% }7 ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 X# ^! N% x! L) Z6 o8 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( P" ~' I. @4 e3 `8 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& m1 l6 c0 U7 p6 ~5 q, k6 T, X}
5 J. m# D9 }( }8 n o/ l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! X) y x: e1 C. u4 ^5 d# t" x
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