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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ v) R# b5 G3 a
input mcasp_ahclkx,
+ K4 i% P: }/ [' k5 s# [input mcasp_aclkx,3 N1 b# D; X% R
input axr0,: @) ^5 V- \% x- @" v
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output mcasp_afsr,* m Q& U% C8 F7 t5 o' E
output mcasp_ahclkr,/ c/ @* Q& d+ P4 C4 c! @
output mcasp_aclkr, Y5 Q2 p1 r2 U% X0 d$ K: N# l+ V
output axr1,
2 Z) x& G' x5 H( T! o( x: z1 p assign mcasp_afsr = mcasp_afsx;
0 _6 a) G8 u0 h# n/ d) Qassign mcasp_aclkr = mcasp_aclkx;
! T" w+ n: f% A! X' S$ ]0 U. bassign mcasp_ahclkr = mcasp_ahclkx;
: i# i, P1 R3 |3 E9 e4 fassign axr1 = axr0;
& P2 a0 E) j& d% @; ~1 K8 s( d8 X. j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 Z4 D3 ]' k! Bstatic void McASPI2SConfigure(void)
; h) y2 F; X7 q0 Y$ l0 r' s{ k7 J0 D. U2 T1 m3 v1 C& t% u2 F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 W1 o$ ?9 e: t) \; R% OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' D$ z6 s) S1 B8 \+ E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
?% C. d1 I. q! H0 N# {, rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 y B, \4 a2 {" q7 n+ a6 s4 K& N; c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ L, a5 Z* [- o4 FMCASP_RX_MODE_DMA);
7 N) N, g/ z1 w; y3 y3 ]# a$ cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 _6 r7 F n% l [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, E& x. X+ Y1 L: A' FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 e- T7 r- p# E! U. Z5 f5 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 e: @. i( I# P( W* z, N. k, sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 [3 ^9 T& s. v8 d5 b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
z, w3 m7 s3 u, W! d6 r" QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 P d. h* ^8 Y8 S8 X( H. xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 X1 ], ^9 L& ]6 z7 i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# b/ g& y* ~; o8 V! H( q6 s
0x00, 0xFF); /* configure the clock for transmitter */4 T. i& ]6 P' ~. V9 u5 v I+ `. Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( C6 l. y m7 Z$ H5 F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % }9 E8 x3 M b, x! l+ n* B. @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. Y- O' p# q/ B- U0x00, 0xFF);( h1 I+ m' d% u! P1 D8 e2 x* H4 B
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/* Enable synchronization of RX and TX sections */
; k6 `8 }* i; f+ p) YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
@* x2 Y+ P" V/ `5 O! \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, p( s, f# r( a0 C9 [0 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" }$ X R6 `. B9 d* m** Set the serializers, Currently only one serializer is set as$ [. Y% B$ M$ x& ?
** transmitter and one serializer as receiver.
3 J0 o) W: o$ j& z4 B*/
9 c/ m0 l* |* r) i1 f) n" B. Z' |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 [; F# _) O* v% E- g9 B$ i( w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* |2 K$ a7 @9 o t: v** Configure the McASP pins 9 A0 j' d, L5 k& S" i) X: i9 Z0 ^+ y
** Input - Frame Sync, Clock and Serializer Rx
/ G: H7 A/ B3 l5 }/ D5 M: N** Output - Serializer Tx is connected to the input of the codec . u& p1 D% \( u: i2 @( I$ d
*/9 E2 n) D0 L' N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); y( l0 K8 d I' _2 T- @9 F' X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; A* J3 T+ _& `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 g |- H. F' T% A3 C+ F| MCASP_PIN_ACLKX! m* z5 d: e1 d$ e: {
| MCASP_PIN_AHCLKX
# l( U4 V, b7 w* ]' y ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. Q; P2 U+ e& U5 k& n/ N, Y b" mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR }' Q* [9 C K5 a( \4 K
| MCASP_TX_CLKFAIL ( ^, N& J! X& c/ p# E2 W" |% j6 a- l
| MCASP_TX_SYNCERROR
2 T6 }! z3 `) y- |: E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 o# d. g7 f$ L6 [% F| MCASP_RX_CLKFAIL9 [7 q" I ?# q. ~8 _
| MCASP_RX_SYNCERROR ) x) ]$ I4 \9 t
| MCASP_RX_OVERRUN);6 V9 A+ h$ D# b$ N
} static void I2SDataTxRxActivate(void)* U Y* ?' _1 n1 N7 e- F( @( n
{
: k) S! R. l" }& f. T5 L2 P/* Start the clocks */
& z3 Z7 @; R7 G2 K" z5 X+ BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 S; z' J- }: N" g6 tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" Q6 ~1 b* E6 [3 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% M* S+ B# f; i' FEDMA3_TRIG_MODE_EVENT);( y6 S+ `7 q& e2 N9 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
C1 b( V6 H5 t* NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 d% E1 j6 T6 y% JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 ^' H. x* H; g0 y8 D8 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; v' E* G' j3 P, e$ P+ n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) \6 L7 r3 i1 S% g# r6 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" n- @, u3 S2 H) s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 m( B4 O, c2 J9 q+ h
}
5 R' ^% |* I" g& a, q0 w+ u( A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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