|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% M) F8 K B" H3 k* r' Rinput mcasp_ahclkx,: C6 {, w4 J, {2 P% N" C
input mcasp_aclkx,
- h0 |1 c& h; R9 ]5 W# Finput axr0,* \& K9 a7 I4 f; R( Y3 E
3 J0 a7 k. }- P; q$ R
output mcasp_afsr,
0 U* E$ x1 T0 G$ i3 T2 coutput mcasp_ahclkr,
) x" }, a8 R3 c. p/ coutput mcasp_aclkr,; {9 i ?7 x2 L) K! m
output axr1,
: w1 b' \9 ?- F+ X0 m* | assign mcasp_afsr = mcasp_afsx;
2 `; l/ W- A. |4 \4 K/ e. y; c1 yassign mcasp_aclkr = mcasp_aclkx;
& J0 F; P9 E" E& ?$ ^$ X! tassign mcasp_ahclkr = mcasp_ahclkx;& ^: D7 C7 n# t" d" ^
assign axr1 = axr0; / c' y5 n7 @/ A2 n7 F4 n
- d! j, g5 ?( z# x+ b2 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- y' Q5 N/ K+ E p8 d; ?# _9 kstatic void McASPI2SConfigure(void)
% f3 g. @( C' t# ?% U2 r$ v{; |% h; s6 @( @ H3 o e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 m. C# b( j' |/ z) W- ~; BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 |1 E& ~5 [1 X6 w( P% gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' W3 J, I8 ~' p0 \4 a/ wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( B/ j3 R, f) m; A3 Q. t i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 s& I+ `2 E* _+ s0 u+ N6 k
MCASP_RX_MODE_DMA);* W) S! Q* }) }! V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 D$ J5 V- Z0 P8 e2 Z1 G; W2 a4 b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ d8 E; j3 X# c7 _5 _$ P! N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & t L7 t. T8 e4 C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ _4 M) {3 a8 ?/ ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; ]9 k3 O; x. E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 L8 A* ~$ f* |6 A* Q! e* O" K z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 W8 W! M/ ^1 ?& ?/ S+ V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & b* ?; ` | T9 i8 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( ]3 E" e1 z! K7 v& |* C8 x0 w2 P0x00, 0xFF); /* configure the clock for transmitter */9 x) ~2 q, A8 z# W5 {7 t% Z0 A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# n# J7 b: |- J: F: ?: p" w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! |; G' j. d- [% Y! q/ A% O" [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- H* a8 R: b& N* Q$ c
0x00, 0xFF);7 {5 ]& y5 O; m8 P
. H6 T! T1 s6 X1 n. G( }/* Enable synchronization of RX and TX sections */ . R8 T* u2 c5 [8 j7 B8 _4 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& N+ ^% @( o0 w% `+ U KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 {/ C* \. ^% I, w! v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 R/ c; Y9 Y U) F2 B S8 i v** Set the serializers, Currently only one serializer is set as" b" h7 j2 n" Q& a
** transmitter and one serializer as receiver.
) N4 [1 y. e* m O# k' E) K*/
" r) |8 _ {. O: i+ ~9 W1 ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* D4 D5 P% P' L+ K4 h' C! AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ x; r; @8 ~ \* n$ p, ~** Configure the McASP pins ( D) }7 d6 C/ V3 p! ^ N, j% J {
** Input - Frame Sync, Clock and Serializer Rx8 ]' m' I$ t* v& ^ u/ s
** Output - Serializer Tx is connected to the input of the codec 8 B& u u; [7 @9 [/ x
*/
- h5 t- o9 q8 O! VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); \7 m; X! A) W& O: }8 C. a. w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ r% J1 p. b7 I2 }2 r' @! {1 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 X& m" ~- p5 I# V, ~
| MCASP_PIN_ACLKX
8 C0 I1 b! I9 y4 j) D0 f' B, \| MCASP_PIN_AHCLKX
- j8 ~% L9 D/ M% E! C" [: m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* z6 Q6 f: y& `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 l$ R5 W H" z; x( S| MCASP_TX_CLKFAIL $ _& O0 N) M; @9 R9 T" h
| MCASP_TX_SYNCERROR
) p0 b4 ?! u# e3 s( ?4 N2 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " G; S' b- D' F2 n- \
| MCASP_RX_CLKFAIL
8 A6 N) j2 o& p! @) |1 h$ U* x| MCASP_RX_SYNCERROR
$ q6 k- F; O6 V5 ?1 w4 d| MCASP_RX_OVERRUN);, D5 b8 _; U: b0 K( k
} static void I2SDataTxRxActivate(void)
U5 o( J, p3 ?0 E{
- x% F6 X% M8 _5 w" `/* Start the clocks */# c7 I; i( w/ D0 K6 ?7 G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* |: Y/ q4 e7 A3 p6 TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! F1 ?2 f$ p/ R L+ YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& z* _1 a @" ]" S8 KEDMA3_TRIG_MODE_EVENT);
5 J. u, K& H. L! yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; u# n( T! D& X% n4 }0 ^( e& D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ W; U! D% D- `: y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 h- E( ~0 d* i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 {3 m# t6 g3 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; K W2 Z5 S8 H% }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" C& U( m# b4 K/ `% R! ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 {* i; {. F3 x- Z2 [
} 2 l% j% }7 a, ~$ Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 O5 V/ m( {6 C2 A0 ^ |