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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# q: Q+ O2 @% H) \& R6 N& Xinput mcasp_ahclkx,
& s: {0 G- p( O Q. uinput mcasp_aclkx,
: P- A8 a7 ]0 r- xinput axr0,
* M1 v, C- g2 y' g O6 k
6 Y; M2 j& r4 L" I3 w, [! b+ I; Routput mcasp_afsr,* u( z3 N" V) X7 l
output mcasp_ahclkr,9 N8 R9 J8 e! Q( V! l! d( j7 @
output mcasp_aclkr,. @: ?! O* Y. } p+ O- b6 D
output axr1,) V" @' y* L: i, P8 t$ r0 m/ ]
assign mcasp_afsr = mcasp_afsx;( I5 w5 `0 P9 S# x8 I
assign mcasp_aclkr = mcasp_aclkx;
6 @$ C, y7 c5 P6 w4 R* D6 D) cassign mcasp_ahclkr = mcasp_ahclkx;
4 h. }( ?) B: ~5 V8 E# E% b+ r4 _assign axr1 = axr0;
$ n( E" f. |( s0 P
$ H$ O5 k6 ^/ s/ ^( N* o: Q- A$ P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & T9 ]2 [1 u) v' p3 s
static void McASPI2SConfigure(void)
1 w4 v5 F) [* q, O! T3 ]{
+ ]. T: y0 m! |. R2 @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
u8 r: o% `+ iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 X9 a9 v0 g* `. x2 KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ ~5 i- L+ O9 b; u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, @2 \" e- B) F) h( P; r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, b) ^% ^( b! z8 u
MCASP_RX_MODE_DMA);
+ p% i/ A/ }3 p6 T6 ~, w, VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* u, D" k2 R( {; X( J: o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( C8 l' B9 C2 L7 [, T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. A; ]. u- M6 Y1 m/ _3 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! y, n' L, e4 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) L& L+ N8 I% H% TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ H( A0 t( `# ?; }4 G' K" V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. d1 y* Z/ g9 M2 Z; N' IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); \8 W0 S$ G$ ~. u! G! b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, R0 O& q7 I5 c* b
0x00, 0xFF); /* configure the clock for transmitter */
7 g; X* ^& W4 T+ W+ s# NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 Q E- x0 c5 `2 m2 u) c6 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 l" v' K* J, s$ A" V$ ?/ t4 PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 F, j/ ]$ ^' R4 [$ `+ t' U0x00, 0xFF);
6 I" f$ i0 G: k* O% }; s- l
2 R% R/ @/ [( O/* Enable synchronization of RX and TX sections */
2 p8 C+ @1 q: n; C9 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, V# f6 s, D8 W: H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 [7 a% F$ g @; L. F E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; j5 s3 J+ k7 R: b _' d( X2 Z
** Set the serializers, Currently only one serializer is set as
2 Y$ Q' s0 w! O+ C' l** transmitter and one serializer as receiver.- v' j9 N, d& H1 t( k/ J* u& L
*/
' `4 c5 X# x! O# _; j; PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. ]' h) r- S- @1 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! @/ [* l" n7 A! S* `
** Configure the McASP pins
$ o. F f: O6 }7 R** Input - Frame Sync, Clock and Serializer Rx7 O. m8 p, T G) H) o- ]
** Output - Serializer Tx is connected to the input of the codec 6 d. f8 a! l5 [1 b
*/, S+ J- b( D! C$ V) T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 \) O" @& W1 b0 n, Q& d+ x) AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); i' g% m- `( h7 x- m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ k! L9 Q9 q9 R9 z
| MCASP_PIN_ACLKX
0 G* |$ i4 v3 E( r: K8 a6 _| MCASP_PIN_AHCLKX
& |4 w0 A7 q8 ^, V! s+ n2 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# `- m3 R2 v7 \7 f4 X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' ~( v# O8 ~! H* v9 p5 h% U
| MCASP_TX_CLKFAIL & q2 |# u! Y$ ]8 O. R+ ?" l* Z/ Y M
| MCASP_TX_SYNCERROR
$ \& Y q' J* [" r3 v: d8 j6 K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
N" J4 C0 s/ R1 M1 a: Z ]+ y| MCASP_RX_CLKFAIL
; C) o4 `4 x9 H' d+ P7 b1 U( X" U| MCASP_RX_SYNCERROR * k `9 H) L2 {) t5 ~/ G0 [
| MCASP_RX_OVERRUN);& F7 }4 V& B! [6 B
} static void I2SDataTxRxActivate(void)! v: M. X# q- j9 y: F3 T
{4 f" \1 N5 K; Q, R* b6 O1 a5 n
/* Start the clocks */9 Q, |# c+ V0 L g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 Y3 H$ L7 L4 M( d. }+ Y9 M% }" YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! F) J* S8 q. L- XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( }8 s8 a& x j% CEDMA3_TRIG_MODE_EVENT);
/ Y$ }( Z8 J4 T) q2 ]1 G4 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . ?. G$ ]: [4 P, g' ~$ r8 D3 ^! b2 O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! [7 ~. T7 x. `" o& @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# q' @. g+ I4 o I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// Q/ Y0 \3 r3 _7 D+ F! Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 |. N. B w4 I- c" @4 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 T# j3 [- X& H1 Z8 u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 ], Y3 o, P! ^9 ^: j/ [}
) q! [4 N1 S8 ~8 q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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