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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 Y1 V4 F3 a+ ^8 m
input mcasp_ahclkx,4 r0 G/ k- m! u" F: S
input mcasp_aclkx,
) U% M2 X9 O$ m" i5 Ainput axr0,
5 R8 K( {: Y" r1 `; f3 C) d
3 H3 h, i2 A+ Q/ ooutput mcasp_afsr,
! |0 N' C4 O$ Q" v7 xoutput mcasp_ahclkr,
# o, F0 _& }- R9 i j0 poutput mcasp_aclkr,
% i- \ r0 g7 K* r4 M5 a. routput axr1,0 I: U; _* V( V
assign mcasp_afsr = mcasp_afsx;
K; A5 E" U# o9 B$ n# F, Eassign mcasp_aclkr = mcasp_aclkx;2 M6 t9 q. V, v+ p& N. r
assign mcasp_ahclkr = mcasp_ahclkx;2 |' Q% v7 N* d1 ?1 `" J: f0 I% X+ h$ o
assign axr1 = axr0;
9 `# J" ^( B/ Q5 P- i
9 h* ], ]3 j$ r; D7 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 o& Y+ e& U) N6 b
static void McASPI2SConfigure(void)) E7 [9 f+ F- x, H
{
: `1 L" a/ n7 C* @McASPRxReset(SOC_MCASP_0_CTRL_REGS);( i/ z3 { `8 k u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, g. X; K9 V) D0 X# r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ ?2 C2 u4 T; v! V- p4 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' {5 V4 u4 t6 {: k, @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 @6 p, A! u8 uMCASP_RX_MODE_DMA);1 C _4 N3 s) q9 p0 J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! l! D5 z7 ^9 B, aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 N! P' h* t4 a) h' w# e8 jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( Y2 ], N4 h3 h7 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); ^4 s8 |5 L% ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' {- w' G4 H3 y/ T9 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 @0 A; @& Z+ x" T+ I1 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: e# @$ l) G5 y% CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 q$ m5 y4 V+ _9 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* S& S3 L: h3 @0 d, R8 G
0x00, 0xFF); /* configure the clock for transmitter */
, U3 Z. W3 {( |- K% @' I$ ^2 F& sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ w7 S# N$ z; `7 i7 i8 M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 K" m) \: H. E8 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, i+ z; n6 L( {7 W- g, d9 y
0x00, 0xFF);
- j5 v( U' w6 h4 y. u
; h* P5 n9 [. v) W+ B2 z/* Enable synchronization of RX and TX sections */ 0 }& Z; z- k& x: x6 s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* z4 J8 [+ Y& r+ ]: K" O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# `# ]9 ?- A, t# ?* I! ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 s3 \' z: P# c$ _
** Set the serializers, Currently only one serializer is set as# e3 e0 g7 m3 B
** transmitter and one serializer as receiver.
5 f" W% L0 @+ ?/ i( G*/: F2 `6 Y4 ]1 a J- A+ |! E" O, X9 ?$ I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% {$ l0 }0 \( F) M" t- F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 }, J+ Q/ t: y4 [! G** Configure the McASP pins ( ^1 r( Z$ L3 R& c
** Input - Frame Sync, Clock and Serializer Rx) k" Z. F6 |$ @! ~
** Output - Serializer Tx is connected to the input of the codec ; l6 J6 F- s0 J# Y( C
*/
* \9 W/ Y+ X7 H3 v2 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# }6 A9 @# n9 C0 u+ h! ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- Q6 Q& G* S, i }. j/ }$ ^; Y# aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( n0 r! j2 w; ~ k; P6 |9 {| MCASP_PIN_ACLKX
' s) T3 w4 P9 ?. R$ || MCASP_PIN_AHCLKX
! y+ n% M8 D6 ]& S+ }' J \, R1 G! g- \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 Q6 ]: m) Y; b2 V' o+ H# BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 ^' Y0 q8 ?( D9 J4 ?6 ]% ^' [| MCASP_TX_CLKFAIL
( ~8 {% J5 t- D( q+ y; W| MCASP_TX_SYNCERROR( m4 ?/ S' U! |' ?- a3 k1 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . d& t3 [8 X! Z! \5 p
| MCASP_RX_CLKFAIL6 ~$ i: Y, X- A! ]/ |, T
| MCASP_RX_SYNCERROR R9 J" p {+ @2 R/ d' \. p6 j. P: u
| MCASP_RX_OVERRUN);
/ u" f3 n# I5 W' B0 s- L' a. }1 W} static void I2SDataTxRxActivate(void)+ p3 Y- N, b# T+ x4 j# m
{8 u1 h3 B0 {) d' ?$ ^
/* Start the clocks */; ^0 l6 o3 _( s1 H5 o/ M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 e! l' ?7 Q. w3 B2 `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. b9 D. y7 i u! a/ i8 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) @% h3 H9 C3 VEDMA3_TRIG_MODE_EVENT);
1 A# r- K" X' C1 q/ JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 ]: H6 i- E2 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; h8 F8 J4 x% L L. J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- R$ V! H# z2 R7 y- V% @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 N3 y/ S! u& R @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: x: \# z4 g; B m$ k% Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' R6 X8 q) D8 |6 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 b8 l8 p, A% [+ h5 R7 a
} 6 b$ V% s+ q5 ~# P) T- `# B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : |' H& ^% R# {# O# v8 p
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