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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# B, k; J# y+ F1 [8 Z% X
input mcasp_ahclkx,
- \9 U! i' N6 f8 J# `+ g- A" Rinput mcasp_aclkx,
7 J4 V# @0 r$ x$ s H# K% p) {input axr0,
* c) Q" q; T+ T- Q& r' d+ T. k1 K g1 z" I6 I7 D! u
output mcasp_afsr,( Z6 ?' h; i7 z" Z; f* p& S
output mcasp_ahclkr,0 ] L/ g9 C6 \7 l% Q
output mcasp_aclkr,7 d6 Z5 {. K1 E2 n3 e9 x
output axr1,
+ i- j# u# w% C" p$ L' _/ } assign mcasp_afsr = mcasp_afsx;: L, O- q! |1 @: w+ k5 }
assign mcasp_aclkr = mcasp_aclkx;
. n$ l8 E* o0 R' cassign mcasp_ahclkr = mcasp_ahclkx; @" w/ U A, u( ~7 L
assign axr1 = axr0; # d+ Y$ n& J, S5 |$ C! n
" A& M" G4 u9 d5 W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, U. \, M1 D8 F1 S$ ?5 W0 E3 [0 e4 @static void McASPI2SConfigure(void)
, i( R) q2 e' m0 I{
# ? J% L4 ]7 ~; KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ T/ B8 t' q: OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 j. y: ?+ p3 |/ C. u' AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 t$ L% k* a8 T1 IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ E4 ^8 M- U9 m- x$ [: q% B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 f2 ~! u: p+ k6 p" E$ n: k; n, P; qMCASP_RX_MODE_DMA);' O* q( I; A5 E1 N* M; f$ P+ C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! W4 x6 H. N! \$ Q+ v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 f9 ]" g6 |) _+ oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ Z) F+ c0 \ DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 q: u* f6 V" m# g, Z8 O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 E# ?) L6 b$ E _* f7 @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ p" [* R9 s& O8 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 w* ?; S E+ v* G2 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 ]3 `$ ]/ y! h8 WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 y# D, O% C' N0 w1 B" {0x00, 0xFF); /* configure the clock for transmitter */# C/ Q G4 F! W* Y* h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 {! D3 c5 g3 l* | c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 V) |6 b6 X* O7 }/ z5 u3 c: xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! l) B, Y+ T$ f4 ~" q _4 H0x00, 0xFF);
2 c) V A3 C% c0 f+ Q0 j7 o+ J9 G5 s8 H
/* Enable synchronization of RX and TX sections */
: }( I9 N2 [0 e0 K. Q0 M/ KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 ~+ n- R4 H4 N8 _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); W* }( [" X- |' ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) E, i9 u F; C8 E- _% S4 N
** Set the serializers, Currently only one serializer is set as
7 g# w5 z- T3 B% c: h$ w** transmitter and one serializer as receiver.9 S8 d# b, j- [% z
*/
# x" k7 d4 b+ w3 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) D+ k; A, J/ y# z% u- VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 x7 A8 {+ L' \* ?
** Configure the McASP pins
+ E/ @: n( M+ U, J) n8 e3 F. C' O** Input - Frame Sync, Clock and Serializer Rx3 P+ F5 q7 O7 [
** Output - Serializer Tx is connected to the input of the codec 1 R% |* C, P4 Q3 S0 ?0 @
*/
8 J- N+ x+ `6 r6 }' S9 h' c aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 @* D9 W# [ _6 M* KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 r. O6 a z n. E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ k+ {* m0 D4 @4 o6 p+ N| MCASP_PIN_ACLKX; J5 Y# d7 k j1 y3 ^
| MCASP_PIN_AHCLKX5 h" n0 S$ e/ j4 e" J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( |9 B* V. y3 c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 }* h5 @) ]( N# A5 w: Q4 M! {( L1 E& y| MCASP_TX_CLKFAIL + Z2 R X8 X( Z; `4 X% d
| MCASP_TX_SYNCERROR
, }( m P. ^) Q$ n7 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 k! r- ]8 ^6 c8 G| MCASP_RX_CLKFAIL
9 w3 Q8 H/ S, a: x9 \+ j| MCASP_RX_SYNCERROR
$ H2 W% ]- v. f$ U" l| MCASP_RX_OVERRUN);
1 R( h+ X9 M$ X} static void I2SDataTxRxActivate(void)
% w5 q5 N% ]2 m b p{
7 n+ w5 F, e8 e' l0 k4 D6 V0 v" u. B/* Start the clocks */
% s$ m0 d! E R; n' @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 O/ d/ g H h; Z, v# P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ P& S' A8 F' q; w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: E; N; [) w, V- Q$ |% G
EDMA3_TRIG_MODE_EVENT);
- N5 i5 x F$ ~. x5 I2 B9 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 l! J: Y/ U B( C* ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) o" x7 y: ?* Z$ i- F& \) `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ i5 R" X! O6 W6 \0 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 L# j+ C+ Y2 A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% V3 q% k: k: j/ Y5 B) i8 d- ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- H& h/ [1 c2 l, H5 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); a+ ~% u3 C; r; `
}
1 e! C3 g* u4 J, @% C% d# K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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