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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 m- V% _: L5 Z& ?
input mcasp_ahclkx,7 [1 q& s" X6 a5 q( m2 ]% z/ k
input mcasp_aclkx,
0 L- s/ _. C5 {8 _: o5 binput axr0,
" `5 B: p- F& `8 C& |/ W; ~" B, a6 M( `' H4 H( Z/ M
output mcasp_afsr,( q2 c! z# a, W5 t* x) a$ Y
output mcasp_ahclkr,+ f5 B) _. O0 ]$ d* `4 ^' w. Z
output mcasp_aclkr,
/ E& I: {" k+ `output axr1,
0 ~6 c* V8 o5 q# u assign mcasp_afsr = mcasp_afsx;' u$ B4 F2 M+ i( E* r) @3 ]
assign mcasp_aclkr = mcasp_aclkx;
3 Y; z$ O% W; wassign mcasp_ahclkr = mcasp_ahclkx;
7 i2 }4 I% p; L$ Wassign axr1 = axr0; 6 @; r, P/ u' r$ w! |" z
$ t+ W# |2 s6 O: O3 [3 K( x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 H$ v. c$ S) x$ a6 Jstatic void McASPI2SConfigure(void)
8 c% ?6 e! D" o{1 o7 N+ c$ l9 a( J7 s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 N' ?* x! s, j; C* }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 F# F8 W# h2 P7 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); U4 _5 I: S3 m/ {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ M5 k% F m4 K; m( X2 i) ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& M6 M* _4 z/ S9 o0 ^2 {2 X
MCASP_RX_MODE_DMA);3 f6 a3 k) f# T# B# n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ C9 A( W$ Z7 }1 [3 ~: q; t/ q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, ^# y% G- B% t! Q# K/ P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: d: ?2 t: G7 o; n# N) {- h+ uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 H# j) i% r4 i& eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: @# U: r8 f' ^; q$ j% l1 R6 S) k' ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ a7 _& j, `2 ^4 iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 B) F1 I) l: V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' A! m0 C( j' N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 W$ V' r' Y- J' i8 D7 j
0x00, 0xFF); /* configure the clock for transmitter */
0 E, b' p$ R3 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' R6 P" J+ v9 L" M* h }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 Q+ N+ g3 Y$ X; k# ^/ v: z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- h- r) Z( [- o6 v$ j9 w
0x00, 0xFF);& ^! {# g! x9 b; t* E
7 R, m0 q9 J$ k/ a
/* Enable synchronization of RX and TX sections */ l$ y& G. D0 Z7 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 z- K' n, } E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
G0 h) [; u5 o6 u. l- PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* ^3 B! S9 o- t* V1 k** Set the serializers, Currently only one serializer is set as: L2 @+ M# g, \6 @( j
** transmitter and one serializer as receiver.2 |7 m0 x; X n
*// P9 ^ l- h9 x1 s$ T& \) y/ y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# s* Z# ~4 f7 \" |( XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 r& U5 f) C( ]9 X
** Configure the McASP pins 2 ?8 ?. o3 s5 g: K( i9 l* `& c
** Input - Frame Sync, Clock and Serializer Rx
8 F; ]7 F6 \0 o6 E a** Output - Serializer Tx is connected to the input of the codec 0 G" l0 {# V5 V2 ]% q2 K
*/$ _8 O4 L2 `0 l+ ^ e! A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 u# Z5 y! a+ q7 Q. o7 s% YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% p2 A4 \2 V* T* A- y! ?' W/ Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ f H8 o+ A+ _, Y, |, p: h. u8 H* `| MCASP_PIN_ACLKX! f# i- x0 L. A
| MCASP_PIN_AHCLKX
; e3 U8 [* U9 ^7 E: A4 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 E- ?$ I5 Y1 ?: I3 s& J" i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ {4 m; W/ i0 V# o8 c- Y5 D, ~+ B| MCASP_TX_CLKFAIL 8 h) o [2 K# n# y& ]; r
| MCASP_TX_SYNCERROR) }! G% O- ^6 W# }( \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 @2 V+ B3 X* {& I4 X
| MCASP_RX_CLKFAIL
; d6 ~" \5 g5 n" c2 R| MCASP_RX_SYNCERROR
! w/ g% {/ u* ~7 V| MCASP_RX_OVERRUN);
, r9 | `/ G' f9 v: O$ T} static void I2SDataTxRxActivate(void)
" R4 D4 h) f! C( U) F7 b0 U{/ i7 O. K2 m" A7 S, h
/* Start the clocks */; [9 E! z+ `9 ?9 t) c" Z3 d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- ~: k( w0 n* W# F( J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 S9 N" z0 F3 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- `( [9 k- A2 D1 N
EDMA3_TRIG_MODE_EVENT);
4 m" d3 y4 _$ F! K) VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- `' O$ h1 {. v' d- I9 A& |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// B7 r9 e2 Y- {9 l5 M8 ]. F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ [8 V k2 d$ s* H* f5 i: N( K* p0 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; ?0 D4 @6 ~* t6 B+ `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) l5 X; `& a- d" s4 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 Y/ a' Z' j8 N$ VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# ^+ F8 n$ r$ J5 t! D' ?* [}
% } \+ v" j$ T3 R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 _& I0 Z$ h6 @1 F
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