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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ E! l3 \+ P# x9 l. j% V! w
input mcasp_ahclkx,
3 E4 v- j/ ?+ O) V% Z; Iinput mcasp_aclkx,
" E: G" X! x- f8 U1 hinput axr0,8 g& v1 R6 r0 Q" ?# a' a
( L0 ^& k& W, Eoutput mcasp_afsr,6 h5 C$ K9 ~3 q- D6 W
output mcasp_ahclkr,
. {7 F3 E+ W! I0 C2 P: G5 xoutput mcasp_aclkr,
% H3 E! e0 D* X- `output axr1,
3 ~$ h" z$ d" r% N; l4 @ B assign mcasp_afsr = mcasp_afsx;7 n) m/ B# ~4 v, ^/ P6 F
assign mcasp_aclkr = mcasp_aclkx;
( u% Q, E( Y% _9 C0 e3 Passign mcasp_ahclkr = mcasp_ahclkx;
! K0 Z$ X" ], X0 lassign axr1 = axr0;
2 q4 @8 d$ F( R( Z7 T
, s; h* w1 s( {7 z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' g- V+ T2 g1 ~- q- y% {
static void McASPI2SConfigure(void)1 a5 d( \" l6 _- Z- A& a. G
{: \- k1 V$ X* q; X2 o" t, q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ d& k# c# W7 J& X2 u9 T% J1 C- _+ kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 E5 J- P b- g3 ]# z( s+ r0 Q+ ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); {/ Y3 P: I p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% A9 V: U* s2 {0 r5 |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 M* q5 X' r" i: R& I/ Q1 b6 v8 z
MCASP_RX_MODE_DMA);, d( |1 B: ~4 ]9 L9 m) Z/ R1 y G0 O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 l7 }$ w1 {0 E8 R4 X( P5 j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ z9 T; r* u3 {8 h; w" f. a3 a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , Q5 g' p1 u( v6 K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: L2 }3 [( L. V$ a7 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 N! h ^" u: a$ a' |# y% \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' z9 m( Z+ ?: B$ B LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! S: X% z4 x3 p; ]% O' }- z0 `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 B2 A2 W- T0 b& lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ W5 \' ]( c, }. l) K7 l0x00, 0xFF); /* configure the clock for transmitter */
+ E$ o% n$ [- {3 Z+ Y& v0 q0 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 B0 R( U: W' Q7 [' [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " j% W: |- p9 b. T, [+ M) N* S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 @) J$ h) C, T- V8 H1 w$ D
0x00, 0xFF);! K# S/ A/ w6 J
. t9 m# Q. s: ]8 x# T) W
/* Enable synchronization of RX and TX sections */ 0 n2 b/ J/ w0 e, }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. K- V, X$ U4 f4 s1 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. l- ?% O$ X7 ]! f5 Q0 N/ O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! r. g* g' N: ~; z* n
** Set the serializers, Currently only one serializer is set as2 u$ K5 [* M& I) f
** transmitter and one serializer as receiver.
6 \+ a) x' B6 H! R( Y*/% z( d& ~( b. j% X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 ?7 O0 c0 {& g+ @2 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ i4 [ A# e# N/ r
** Configure the McASP pins ( J6 Q/ r3 P" x% A
** Input - Frame Sync, Clock and Serializer Rx
& L, m2 T f5 Y2 l, J& m5 M* Q** Output - Serializer Tx is connected to the input of the codec
1 Y. ]! |2 U' x$ g$ C, I*/8 L: ~4 ?) l3 E u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, `2 k$ H( ?4 l# x" |: t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- ^! U9 h7 `' ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% J* P* Y/ L3 v( @6 l& _. i| MCASP_PIN_ACLKX+ B1 E, F0 d% P6 ?: X$ `1 I
| MCASP_PIN_AHCLKX
& [. A, S8 |' m) r5 w# || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# q( f' Y7 h4 x; a( q R# o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 y9 D+ ^% i0 u9 R| MCASP_TX_CLKFAIL # ^7 W! v- B0 d% O0 n8 u) Z* e1 B! l
| MCASP_TX_SYNCERROR
& }8 ^, C7 N/ ^; q0 O- q- w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + k+ f4 z& w/ O5 t. U$ [0 U4 d
| MCASP_RX_CLKFAIL, C- s# A# \5 V
| MCASP_RX_SYNCERROR
+ c. g# J3 ?& a/ F! y% v9 S6 }| MCASP_RX_OVERRUN);
& V# A- O- t8 @- W+ W} static void I2SDataTxRxActivate(void)* c- U8 N5 F o: C
{/ a5 ]% X6 l' s" }( ~( N2 {
/* Start the clocks */7 F6 M" f( u2 I6 V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 }1 c D; a5 q8 o+ d) sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 A K; W% d4 k! b* j" u/ L, |1 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ o6 i( q& v, I f3 {; l1 aEDMA3_TRIG_MODE_EVENT);
0 j9 ^, }. U$ v" n6 K6 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! E4 w) l( E; _: REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% Q. p" e! Y+ ]- x2 \3 O5 S3 i6 `" K+ zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* S" ]! h% i/ w) j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ f8 s# t1 Y5 D0 L, o- _$ Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ ]( C, ]# ~& r' d) p3 R8 aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 D+ Q5 e: ` L* ?' P e8 O4 m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) O; ?( n( X1 g4 h+ f
}
0 L0 p* b6 O+ R, ^4 Y4 h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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