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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 _* l* C0 U ~: u+ c+ L) @" uinput mcasp_ahclkx,7 v3 o/ @/ [+ F3 S# R
input mcasp_aclkx,
# \! D! U) R6 T9 }" Vinput axr0,* b' x3 r. k" ]% M* }# c" @; u
/ T5 p' \" M0 @output mcasp_afsr,. [# D* e9 q0 s- d4 R' h8 Q( Y h
output mcasp_ahclkr,3 Q* p9 l- B) Q( i* t0 `- {
output mcasp_aclkr,
8 f' R8 \! H$ a: k4 Ioutput axr1,
, N+ [3 Q9 i$ k- N: q9 L assign mcasp_afsr = mcasp_afsx;% I5 Z4 a r% d, O( i6 V; r
assign mcasp_aclkr = mcasp_aclkx;
3 I6 M% G8 O" @4 ^2 R- dassign mcasp_ahclkr = mcasp_ahclkx;
" B z# J/ X: p9 f; A2 E+ E1 tassign axr1 = axr0; 3 u0 s+ h, H8 x. A w9 I( V( Q/ W
% D d; T9 H( z$ x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 X6 z7 Y+ V6 ~" r1 u2 Z4 @. Hstatic void McASPI2SConfigure(void)
7 y' e5 e7 D0 ~" w% h" `{1 M) Z7 \# [# @4 Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! j- P% @' R0 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 M0 i- l# D- v) s) MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 j1 ^, P' J5 ?, s5 `& }, cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# ?6 a9 B7 i" d; m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 n, M4 [ F0 s/ \6 T5 wMCASP_RX_MODE_DMA);
9 s" @" H6 o, Y+ p( H; n, B+ QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Y J/ {" U, z( @. p# rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( k2 _2 D+ Q. r0 N% N! r9 x W/ s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 B! r' A3 H2 g* r w J; `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 s% W* b8 E m( CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) X$ I4 H. a/ e: p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! c2 u, f& L. M4 E- kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, F) H A) h5 q o& g7 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % U: y; s/ u' E( b! A( I" S+ N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 w# l3 f) t2 A+ p) [
0x00, 0xFF); /* configure the clock for transmitter */+ k8 e7 j* h/ G8 T3 ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' V) G( p% q* O& BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" z8 c X: z" P+ _1 {9 ~( m( {. o( H* LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ b8 z. D, F; b2 B, P0x00, 0xFF);) ?& H1 N! O/ {" m
' g7 T5 N/ b$ j% c7 U) Z/* Enable synchronization of RX and TX sections */ 8 u( s: `+ _% s9 s/ l1 m2 B# l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 Z. T) |7 u" {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* g M( d/ e _1 v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ @) H! _& D+ H0 Y$ X) j9 P** Set the serializers, Currently only one serializer is set as# M# F& b7 S7 o' e, [4 g# T* s/ ~
** transmitter and one serializer as receiver.2 g- c; j4 C0 N1 F" K
*/# ^7 j0 w2 w# g$ N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 O: v% B$ H# p( N0 K1 E2 C* X$ qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. V# P- p* R. b, m' @' |7 ~4 A2 f** Configure the McASP pins
" ?! Z& m- k( m' D** Input - Frame Sync, Clock and Serializer Rx
& Y K% i7 @5 t, v/ `% t** Output - Serializer Tx is connected to the input of the codec . D5 u$ }- |- q& s, N5 {. Q0 y, w
*/
* ^# J: T$ i& i" j9 A8 l" j) D8 E: \ cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ x. ]" t$ m. |% \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 n- Z# J7 q8 x5 ~* U0 N( s3 I) z7 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! D7 `7 C' g2 ^| MCASP_PIN_ACLKX1 p& t! N9 d1 i7 s h( l* S
| MCASP_PIN_AHCLKX; ? }# S4 _- D7 ?5 |! |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( j3 ?& I0 @8 a; Q) [+ D! H# h8 B/ ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( L3 U& m: y6 K9 K% e+ W9 t) \6 f9 d| MCASP_TX_CLKFAIL
" W8 i/ F3 q* Z5 `1 L% s+ U0 J| MCASP_TX_SYNCERROR& ~$ |# F7 ^. j% o; U0 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . w, T/ A/ h7 ~% u; A# @
| MCASP_RX_CLKFAIL& U$ R7 f+ @7 i% n- Y- r5 R6 G
| MCASP_RX_SYNCERROR ) j! T+ n; z/ b4 ]
| MCASP_RX_OVERRUN);& e( ?8 B5 {( [( O, I: O* L8 A
} static void I2SDataTxRxActivate(void)) b. r6 S, V2 j
{
; Z, \' W; j1 u- B$ j7 D/* Start the clocks */3 v+ T8 B% \, h7 r9 ~+ b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 ?& K+ q9 X0 H& R: ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 E/ q1 B9 M6 ?8 L; h5 }- q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' u( y6 B4 N0 V7 j+ k4 N X
EDMA3_TRIG_MODE_EVENT);
& F! m( o4 C2 A- d# OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 b$ \/ h* k% Q! g. T, C }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' O$ p4 @* O. X8 N. b- ~4 fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 l: T- p& {( Y: W8 J: C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 j) e$ ^! ]2 Y% K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# _# l" H( z% KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 x* I" I# v! ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; O& s; C3 M* s: Z9 m& ]} + t4 e5 U% t( e! R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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