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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 I7 E* F; M i# h9 U
input mcasp_ahclkx,
# {2 Q8 _/ V1 p$ P3 ]2 minput mcasp_aclkx,0 \+ S3 V+ `% d4 s; [
input axr0,% \4 R9 V3 ]* ?& h
5 Z B+ G. p$ t+ _! j4 T
output mcasp_afsr,
# H8 J0 b+ z% [9 Doutput mcasp_ahclkr, k& j H1 h; r$ ~1 S. a
output mcasp_aclkr,: n0 v6 ` w B( E
output axr1,
% _ U4 Q6 s5 L' B assign mcasp_afsr = mcasp_afsx;
1 E) M3 |1 c9 z% j' Bassign mcasp_aclkr = mcasp_aclkx;
3 F8 {# }0 N, Q) ?: l" oassign mcasp_ahclkr = mcasp_ahclkx;
0 ~( C8 r0 M7 s% [assign axr1 = axr0; / ]$ N) V0 O5 B% K2 M1 C% {
9 f% {) P' U" \) v6 L N; b; K$ O2 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " I" \. n+ C0 Y
static void McASPI2SConfigure(void)4 R$ _3 D% I1 r6 K4 a, }
{
0 T' [- t2 v3 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 [! g/ H& W5 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, q' q. Y5 {5 X* }- D) Z" E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 H# w3 C+ P9 V# h7 J' u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% N# ]" Z0 _& {9 T; AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 k& k: l8 V- S: aMCASP_RX_MODE_DMA);& k0 f+ m6 K W5 {5 N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Z% D- O$ P+ V* \( r4 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 \& l' T d# }8 T5 E. h- B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . _3 ?$ v7 a$ g4 s. l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 h3 n- R6 H8 n. s JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* q- ?' M8 B' Z1 |( r8 z" @; [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 N, {; _6 b% U8 {9 rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: K8 N( t& @" l$ c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ?: y$ Q5 z2 ~9 i! @; G' eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( f5 o+ ]) g2 p, T, M0x00, 0xFF); /* configure the clock for transmitter */
2 ?6 q) ?3 x9 ]) s" JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 _! b! w# L4 J2 `8 n1 l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, G- d, g/ a. _( c3 K* {, x' dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 `0 E' r- L7 O/ x# b
0x00, 0xFF);8 G7 O. X" Z$ T2 w- e
# Q8 R6 r. I6 I. K2 D7 `" _
/* Enable synchronization of RX and TX sections */
( O. s* {2 U c# t9 i& N$ z# rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* q, V" d0 [, s* l8 X# ] ~8 w# f: ?- MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, ~& o( e# j `# Z; T4 q N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 X+ X8 K o( X; s
** Set the serializers, Currently only one serializer is set as
O& j( Y- p4 H. H" V- v** transmitter and one serializer as receiver.8 g" ?( L8 Z* q. k# W1 N# M, F0 G
*/
+ x5 ~+ w! y" R6 N3 I' o6 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ U$ H% r- W8 q0 j. z% Z6 i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) J5 z5 l7 ?8 ]6 n
** Configure the McASP pins
9 H: ]) D2 ^8 W- X! s; V5 i! L K** Input - Frame Sync, Clock and Serializer Rx
& I- y9 n# s8 o** Output - Serializer Tx is connected to the input of the codec
$ T {, X+ x8 e*/4 L( k9 }, H* n5 k7 c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); T+ A1 p& L& p( r. m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- u$ H7 H% H+ l& S: ?" s) z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 v! \$ V, |+ e/ R }+ ] N
| MCASP_PIN_ACLKX
, u! O: T- o8 q, t) }| MCASP_PIN_AHCLKX/ F( q/ \* A8 {% L0 T% D s+ i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; o, L/ T( G. X$ PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( X9 d& p' Q1 p% t, w' K
| MCASP_TX_CLKFAIL
6 k s: _8 h6 q+ }. m0 d6 ?| MCASP_TX_SYNCERROR9 S: a1 {9 v! r/ y! i/ h0 z. o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 L9 `; ^* h6 O
| MCASP_RX_CLKFAIL
3 D+ M! j. ~, D' \' n {| MCASP_RX_SYNCERROR
& U I/ ^' F# Y, y; U| MCASP_RX_OVERRUN);
1 V b2 x3 d) @* c" E} static void I2SDataTxRxActivate(void)
! c& {/ D# t' G{; L) J5 b' t# t6 Y. y1 _ R
/* Start the clocks */& C q, {6 b# a: ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 i+ j' C9 ]! [! v& [) m8 C$ `$ o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ {$ K/ E, c3 y. ]4 R, o& DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 {, p$ ~$ g' P# @* w4 f: [
EDMA3_TRIG_MODE_EVENT);
3 |; j- b% r# ?* K3 G! `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
l0 h0 s3 x# j- _. hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ b# G1 L" g# U7 {, w: f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- s: P# }0 K; s; x+ f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- r7 _( k$ X A7 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; M) w. {% G3 Y# Q7 E! DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ Z, c( O; T$ j7 U7 A% B' y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& a4 d/ w1 t4 @8 ?} 4 e, i6 X) T, ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . |* f( _+ }0 f- O5 K; j
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