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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 u: p$ f/ N+ `$ i" G! L7 P6 q; H, Oinput mcasp_ahclkx,
6 b/ p: Q4 M+ y7 N& L& o' p6 Minput mcasp_aclkx,
2 z8 ], w5 f6 n+ ?$ ninput axr0,* A: X1 }2 s2 t7 A' u' ^) Q; M
( z, g8 q ~2 ?4 |output mcasp_afsr,* [3 O$ _1 f. N* |) W) a) \
output mcasp_ahclkr,
& ]# V: Q, Q2 g" a/ S: z6 Zoutput mcasp_aclkr,0 K# y# r* Z( K, V2 b2 J) a4 m
output axr1,+ c+ A: S/ @/ \( l/ I
assign mcasp_afsr = mcasp_afsx; ]& w; u3 O1 z! X, ]- s
assign mcasp_aclkr = mcasp_aclkx;
& d+ A5 P. B9 \assign mcasp_ahclkr = mcasp_ahclkx;7 S: h6 B4 ^/ r( C7 Y
assign axr1 = axr0;
# g6 f( s4 G8 [! G
: c, |3 ]9 Q n$ J$ v2 C+ }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! j; V5 O" E8 a, r: f+ S
static void McASPI2SConfigure(void): o9 k" D0 I# V, L- i
{& T# @$ V9 U3 p, r( M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 g; `% s. a# C3 |+ o' G: f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( X1 y- e6 Y7 B W7 L$ T- dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 o4 o- |% Q1 ^! U2 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) T2 M2 }, _* U3 l* k; p+ Y4 HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 j6 k$ U' m% j% D3 c* R5 c% u
MCASP_RX_MODE_DMA);; o- D3 S4 y _! D7 T M' r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 F. b9 v3 i; n; _; fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, Y6 L$ \8 M% I# c1 M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ a5 [% j- `; SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: v+ F2 F! T( Y3 k: @3 yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % `% z3 t( T* c' H W8 U# F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* q- C' L7 Y1 n! {: w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. z' n: r, U0 U! G$ y& m' GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" n( u+ E% v+ k2 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 @5 r1 h( U9 ~0x00, 0xFF); /* configure the clock for transmitter */
/ \. z! x8 R2 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' ?: b& j- h& F; e3 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 F# e. U4 s ~+ C" y2 r) e) ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: \) `% }' g+ }6 o" l1 i# j6 S& {
0x00, 0xFF);" ]- e8 A' k& g/ O+ e' X9 z
, F3 d* l4 K3 F) Q2 }# q/* Enable synchronization of RX and TX sections */
& n3 R2 |; q; |/ H* @$ f, v9 d9 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 a2 B; R0 S) V4 \0 C" M2 z0 Q$ }: K9 e' wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- `9 a* r0 {3 K) w6 r1 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 G& Z* g$ J6 M$ Q7 P7 i3 c& z5 C1 B** Set the serializers, Currently only one serializer is set as
7 i! |2 t: x5 u- ?8 D/ Y: V** transmitter and one serializer as receiver.# Z6 P( _6 p- @7 s4 ]
*/; a; p1 r" ^! q. H$ v, s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, B" t! e: B7 s7 J; ]2 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 _/ R% L: A. n6 Y$ H2 q# C
** Configure the McASP pins 9 g: F( p s* ~4 P
** Input - Frame Sync, Clock and Serializer Rx
8 K% y7 w3 e; \8 j0 L** Output - Serializer Tx is connected to the input of the codec ( ?! u& D ~4 g& ~
*/
8 Z6 a* s5 C k8 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. p+ X7 G/ [( K8 E3 ~+ S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) @+ D9 p% @# r, r( F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 o" Q1 S% N0 ~" E8 N [* b) `
| MCASP_PIN_ACLKX2 x( H% d' w0 f( m, w3 l
| MCASP_PIN_AHCLKX
9 T, }4 f: E! _0 J0 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 f; S( f3 `. t; H e+ dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 V. C, g% o- `0 Y$ j
| MCASP_TX_CLKFAIL ' s& U* C! f2 k! M' o! ?% [
| MCASP_TX_SYNCERROR( R6 `# K( i0 [% f& t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) T3 o" G$ U% H# }& }1 ?| MCASP_RX_CLKFAIL
, F: H+ I1 L8 k1 F4 V3 R| MCASP_RX_SYNCERROR . R+ F) V" N( T* e' \7 d
| MCASP_RX_OVERRUN);
6 w6 I4 |" D5 y% M! B" R} static void I2SDataTxRxActivate(void)
7 F2 m) I) e7 l9 G$ s. A! ]{
! d( N Y4 N( p3 H7 x, ?6 d/* Start the clocks */
9 Z0 d0 o( x7 z: gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
G. H X8 `! j6 o' U. W9 W7 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 Z+ `" G8 |4 N% I7 C7 G- ?3 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% q9 Q3 f& n5 ^% fEDMA3_TRIG_MODE_EVENT);
5 K: e9 Z; T+ {2 c7 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- d6 I6 c7 U+ n r2 z9 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- s) J1 W6 e2 k) Y& E8 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 ?1 l! o+ M7 H; M. I1 l0 {, }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 I8 z8 d$ o7 k- I0 _5 p& p4 S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 ?, n5 g1 j7 n4 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 k1 r- Y/ k. @ [; q! _0 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 d& @) G$ t/ Z}
/ g/ w5 B i, ~" z h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 S% ?! k* r+ u; b f" k |