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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 C |, `6 E& F' Y% s5 v! I; ]% i
input mcasp_ahclkx,4 k( ^' Z" \0 E H t8 w
input mcasp_aclkx,- @! s* w# S5 B; C4 a2 y% x
input axr0,
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output mcasp_afsr,5 c8 g7 m' C$ B2 o5 ~8 i. @
output mcasp_ahclkr," a+ f( A" F3 h; A
output mcasp_aclkr,
% _* u$ H$ E( \/ Toutput axr1,4 e+ ?) j* v+ J+ q
assign mcasp_afsr = mcasp_afsx;
, h3 ?1 `. o/ H7 g. \2 Uassign mcasp_aclkr = mcasp_aclkx;% q y* M% f: e' {4 e0 q8 L
assign mcasp_ahclkr = mcasp_ahclkx;# w* |, K" T o8 c7 t' L8 T9 D
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % G2 m) }" w. @) ]$ J
static void McASPI2SConfigure(void)" |3 Q. I2 I( l9 d* W
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ n. t' D, |6 S4 ]& l1 h* F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 b$ A8 ~; o" t1 D" R! k7 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ Z" _$ ]# }% H! B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 L9 z2 M8 i! T' ?6 B* D( W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; b! z3 o7 I& e8 `/ g1 {MCASP_RX_MODE_DMA);
/ x- V5 q5 s' v8 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, o0 \/ v2 i# m& L9 O5 a! d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' F: s m. a8 V" x0 T' W9 f% x* u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% H' K/ G6 ?! D7 ?9 g% H% y$ LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ r: {! Y' S# m% CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , Z. N0 {6 K$ W8 o0 c0 n% R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ W0 D& P+ c$ v6 L. x6 F/ [" Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ _! w5 t% h& z1 y! i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ C+ s5 x* R u+ s- X* mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 u; P l% l- I% v. j. K0x00, 0xFF); /* configure the clock for transmitter */
2 h, e# q/ x: k& ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 A0 f) q% A3 l/ F& l) O+ e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, |6 b2 k- ?' z& q# l" \- O fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 M- v( j! v& y) R% i2 N# k! }0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ 4 u% V. W/ r* f. c4 T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, F9 U+ A' O' Q5 Z& UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* Q& y/ i$ O4 y: H6 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: n) E: a% | y7 W4 Q
** Set the serializers, Currently only one serializer is set as* b& a9 m, u) ^+ ]' K2 D
** transmitter and one serializer as receiver.# \5 |9 U8 [$ v# C3 J2 Y! t5 }
*/" o$ P6 I5 [4 X. R6 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 k3 J3 n/ [0 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
X( E' C* g0 z1 z+ P2 ~2 u** Configure the McASP pins
8 i: g) O* d0 V$ V# Z** Input - Frame Sync, Clock and Serializer Rx& b& O3 j8 h, _; A: |* e6 d" Z
** Output - Serializer Tx is connected to the input of the codec 1 i# n: ^, R5 X9 ~4 `
*/
; Z9 @- `! m( w6 Y: fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( ` h5 `* D' b' y* e2 i+ R: e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, E8 c! L$ s" @3 c; x+ WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* Z! [/ b t; m: H
| MCASP_PIN_ACLKX
8 A8 f; I0 s) b' V( ?7 {| MCASP_PIN_AHCLKX, p, K5 P! Z! v! C1 E( f u7 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' f$ u# U& D- D6 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # X2 K# ]4 {7 k* [# E( p" S! t; D
| MCASP_TX_CLKFAIL
: U7 l' d3 I! y% O| MCASP_TX_SYNCERROR
: J' z% V! U' G' F$ U0 A. N+ u6 j, e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 j. v+ Y5 z- V* `$ p9 Y: W \
| MCASP_RX_CLKFAIL
/ T: L+ [4 n0 A( D, y0 s3 J* M| MCASP_RX_SYNCERROR
/ E; [0 U& S$ u. ?4 Z5 b# W+ p( u| MCASP_RX_OVERRUN);; K4 ~" x& k' q" \+ o
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */6 d, [! i' |( _/ r! Q6 m) M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 T0 r7 }$ q# I( M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% H3 E# \& [# }' p, v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 m3 k# O* a L* ^0 b. r" gEDMA3_TRIG_MODE_EVENT);0 _2 x" c0 f4 a% {+ h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: ^0 w) h7 G, x* jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) I- w6 g2 D* z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: B' r! x0 O: W8 p2 M* x8 _6 q- _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 M5 S5 |' N' n* ]" U) E( T% dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; R8 U$ j2 k; v0 q) x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); N+ `. y2 K; V+ j6 K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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