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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' C0 D) f6 q% h U" K5 ginput mcasp_ahclkx,; n6 \: r1 c7 s
input mcasp_aclkx,; O; M3 ~% L* a8 I! M6 o2 K3 E
input axr0,
& ^! {5 k6 b& o: n7 d5 B2 [& m
3 L' _( O, M5 U$ v' Zoutput mcasp_afsr,3 {0 J6 H8 d) x5 x7 s0 h' K
output mcasp_ahclkr,
# Y8 D* D {8 J6 W" routput mcasp_aclkr,
$ `- k$ R# U. b1 soutput axr1,) m7 G* ?- z: n$ M) C
assign mcasp_afsr = mcasp_afsx;; r! y S# S0 E3 Y/ ` d
assign mcasp_aclkr = mcasp_aclkx;
; b7 D4 K4 x( vassign mcasp_ahclkr = mcasp_ahclkx;+ o+ Z4 ?+ }5 m" F6 @7 L6 e: n
assign axr1 = axr0;
7 e3 j2 p2 A) i) }7 j* B9 G4 I! c
' [6 S$ R; z# A) z W& l, l" Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
S* H; }" y9 ?& L3 nstatic void McASPI2SConfigure(void)4 l. \9 o. t4 ~! j
{
; x0 E. X! Z- g5 b! o; aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 P" P+ C2 |% y* vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! }0 R$ j; d* f- P# I3 r# e: \' `6 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% c' J! }; T) lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ U) e; V# H4 {" h; r8 I3 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- M; Y2 D) V7 \% F; M% ^MCASP_RX_MODE_DMA);
9 U$ ?" h9 Q, ^$ BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- E; K7 _. B6 c6 z. U6 U% i2 J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 ]& d3 p& x; C9 t1 p3 J0 M# K. ? }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( E8 g! S9 p& jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ R4 E$ C9 ^7 W0 U1 O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 ?7 o5 R$ Y6 H1 x( A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 D q, j2 r- F. H) Y% x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- [- D: |3 W v E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 D8 {6 ~7 y n1 g# ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 H& X7 P' z& ? d. z% z0x00, 0xFF); /* configure the clock for transmitter */. P( y% n6 c! y" ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# f" t" O: ?& {! }; |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 ^5 D/ | E' |4 v* A$ G# ^$ }) I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 P y, j L" Z; s, h9 r0x00, 0xFF);
" l* Z3 \1 M8 H+ o
0 [" U9 C. v: C) n2 R- Z/* Enable synchronization of RX and TX sections */
1 B( U8 l4 |% h+ [: ^6 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; b: V H X. W# R" _6 E3 s3 J. AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
I: t4 k- q# E' fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 q) b" H7 i# I
** Set the serializers, Currently only one serializer is set as: o5 F- V- c& j# D0 c
** transmitter and one serializer as receiver.
& c9 i: |$ w T B. z$ d. h& O* u*/6 {3 H1 g0 T- R! `: C$ U$ J1 x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ e Q: d- W7 t- f2 S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ u; ]* [4 r# ~ m0 m/ ~' c/ f** Configure the McASP pins
! f# y$ M& |# _# d. q** Input - Frame Sync, Clock and Serializer Rx5 F) T8 F& L4 _4 R: L: ?
** Output - Serializer Tx is connected to the input of the codec $ U/ @/ r8 ~8 w# ?
*/! J) z. ]3 H- L" s) Z5 Y9 k N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 {, N1 _0 f! u w6 y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% u: }2 _( j# CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 U* \7 d+ D$ a| MCASP_PIN_ACLKX
0 \* q" t2 D* }5 W* b- E# o+ p0 o| MCASP_PIN_AHCLKX5 ~1 V" G9 l* _) G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& p: l( ~) [+ ~( p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! y1 C) A5 B( k# B4 Q
| MCASP_TX_CLKFAIL
v; H) `) p5 V| MCASP_TX_SYNCERROR
, d' N! ^9 ]: o8 w" `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" m& j6 g" e1 V* H6 M# \9 {| MCASP_RX_CLKFAIL
3 G( f; X( T, c. K4 Z! [| MCASP_RX_SYNCERROR
3 S6 G: }# U( m9 ^| MCASP_RX_OVERRUN);
% N& k# ?$ f# O1 R5 f7 p P} static void I2SDataTxRxActivate(void)+ K; j2 m. e+ O3 m3 [9 o+ S9 T1 }
{
) e0 `. O6 t+ f+ ^- |/* Start the clocks */
% ^) D9 I( ^/ F4 w7 xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& p8 m4 M C: ^* u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, j3 h: s6 t1 i& a/ IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" c Z& Q7 e& m1 `; @/ FEDMA3_TRIG_MODE_EVENT);
3 x2 T/ H+ @( |) Q' x$ t. f% ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ e. j U6 Y5 }: ^! _. t+ ~) GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# o" e0 p2 p# p# \ e% ~" ?$ X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 P) z, `* B7 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# Z5 U _. P* l5 T; }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 x( `( I+ m! MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ O( s$ U+ |* l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' @1 i b- Y8 d" X9 `& C+ d
}
% z8 A" ]2 p/ T- L% j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! \" J! O& x, d' D* R' E4 k) r1 e
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