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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 ]$ o! G: \& s0 h
input mcasp_ahclkx,
9 Z* T5 d- H) E; g8 A2 rinput mcasp_aclkx,
7 m! s$ D+ B: J4 finput axr0,
8 t# _. K. ~3 {& F; Y
8 }/ s7 E& H6 v- A1 ]output mcasp_afsr,
9 E( I, l% q. l4 ?output mcasp_ahclkr,
3 N; `+ P8 U. A) z6 u8 r/ Woutput mcasp_aclkr," }) H1 @4 C1 _( S' E
output axr1,# f3 X/ D; o4 ^* ]# ^# H5 |
assign mcasp_afsr = mcasp_afsx;
, H" j8 I& Q& }3 o: q- uassign mcasp_aclkr = mcasp_aclkx;
# ~2 e X: `: s D. H/ Gassign mcasp_ahclkr = mcasp_ahclkx;
P1 C# A: g( ?0 G3 m5 g' [ @0 Tassign axr1 = axr0;
: u6 x& o0 }) D) W# H7 I6 P5 J$ \+ v
. h5 T+ S; k2 P" b2 U; w, U$ J# D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 s8 U1 Y% Y( u
static void McASPI2SConfigure(void)6 ] [# U; a7 T; P P3 {
{
* r' Z7 Q! P( KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- `1 p9 n# z, v8 f" W. t7 b g! WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- X# v i: l% r' b; C9 ?+ aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' ^% n5 ]0 F W8 E* u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ v$ o( R8 S; V& P& i% P& Q6 F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& u1 f6 k/ | Z9 J
MCASP_RX_MODE_DMA);
4 M4 i8 g, U% ~3 M dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! d- K) I! _; ^: ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 P; [) u( r- x4 ?( c" u- n, K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% M* ]1 ~: p" e MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 w. i! b, |2 ]/ b: s+ s! k4 sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 c5 \/ M. L4 [( yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 H( q2 Q, F. E) ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- L. F* H% v, J/ r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * V: }; f) U5 I8 M" f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* J1 S4 T0 V# \* a: c! Y' ]0x00, 0xFF); /* configure the clock for transmitter */
8 H7 a+ E/ j; a+ g: c* N3 }8 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ i9 s9 x1 r2 {* r5 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 ^$ O2 |6 F4 n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, x" N7 v1 f: G
0x00, 0xFF);/ u* o* V5 Z% T5 l2 f; A' @! @
9 {$ R( l1 v3 u6 v! E! \& I8 Y! s) l
/* Enable synchronization of RX and TX sections */
: L) }" C/ e) `6 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ t, F) F1 o% q: m4 ^& [! EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! P' F7 c# B# B! H, }% Q2 |# ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* L2 b, E, R; }8 p! Q* T** Set the serializers, Currently only one serializer is set as o0 F+ B' f5 U; _, H. o# w/ @/ i3 Q
** transmitter and one serializer as receiver.1 f6 J" S( e( `# Y, n0 u" B5 Z4 q
*/
. j6 \9 {# y3 @# t5 `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% ^; ^% b) H6 ]& _3 |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 h6 t/ t5 u6 C* P! H** Configure the McASP pins
0 B! K" q: k6 t7 U1 {& }5 b- _** Input - Frame Sync, Clock and Serializer Rx* J7 d; M4 P! M4 w
** Output - Serializer Tx is connected to the input of the codec
+ R6 \" v4 g0 A* k*/6 ?* P3 e; @8 p) V) n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
Y B. U8 j: i3 R5 G. K9 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- W9 R! Z- s. d, V; B3 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' Q u8 k+ M" Z3 {# I
| MCASP_PIN_ACLKX0 L5 d# ~/ y8 ^( e0 r! y5 t( ?) w* \
| MCASP_PIN_AHCLKX2 |2 U) M8 P6 T4 M1 J4 T. b+ V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 x% ]( R9 y2 g7 j0 L5 @! q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) V5 W. h- X* s, y K: p| MCASP_TX_CLKFAIL
: q" W% ^& V Y3 O' Z" J( ^/ T| MCASP_TX_SYNCERROR! q& a0 P/ G- y- K; Q/ x- n: L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * u" L2 J* E" s. H6 z* b. A1 H9 {
| MCASP_RX_CLKFAIL& O0 _/ z$ {) }3 S4 Y0 T
| MCASP_RX_SYNCERROR ' q" ~) q3 o5 P3 b1 m
| MCASP_RX_OVERRUN);
/ ^: O- j6 Z8 Z8 K} static void I2SDataTxRxActivate(void)
/ B: `5 ^2 Y" h8 F3 k{
6 k* e# \9 u9 ?! o/* Start the clocks */: g! s& g4 U' p, X2 Y: p# A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( y6 M2 I! Y4 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 {. N' I. s( k0 _2 e' v8 s: kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; @# y# f& |7 K3 Y2 w
EDMA3_TRIG_MODE_EVENT);
u: a2 h; M uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - Y4 U& Q0 @, w4 J2 [6 J8 @# C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, x. V3 u, [; L! q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 p$ z3 i' A) Q" [3 BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 f u5 O) O Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 ~# j4 f/ ^ |( k5 {1 h/ c, H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 ~% z8 c4 J5 Y, Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: _, }( A1 |6 C
} v. b3 X [ o- u6 [ E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 V, Z$ {; h3 T P5 h) l) m
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