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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ v5 w7 U& ?4 F/ z. j5 W
input mcasp_ahclkx,9 w% B# z% A; Y9 T+ @* Y
input mcasp_aclkx,
% R* R x: E ?* }input axr0,
/ i) \( g: e3 c$ \5 R1 L& I$ U$ j5 [5 }
output mcasp_afsr,3 ^# O: ~9 l2 b, q* V: S, {& J
output mcasp_ahclkr,3 f- E; N7 R- ]+ q- R
output mcasp_aclkr,
0 s0 @* W3 \ \- w+ f/ v# h& Youtput axr1,
) W# q! b' n( d1 |& c* Q! ^# M assign mcasp_afsr = mcasp_afsx;, ~2 J& h9 ~4 c. L% z A7 @/ D+ a
assign mcasp_aclkr = mcasp_aclkx;. h% @6 w4 l2 l5 I. d6 ?
assign mcasp_ahclkr = mcasp_ahclkx;3 I' i. C8 T1 l- ^8 o6 S7 W
assign axr1 = axr0;
$ |4 L* `, w5 p, _0 p0 C8 L9 W7 i5 i+ i5 k! s- Y6 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ Y- D% @6 r1 v3 Tstatic void McASPI2SConfigure(void)7 z5 N' H! X5 u( @3 p5 s
{
8 r( a+ o% Q+ d; j* @6 o4 a4 \% T( C' MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: ^. V' ^ @* T1 O' \ t% I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 |/ m; G `8 ^0 j- Y1 {1 v; ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" B4 r5 B, U+ g! \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: g) J8 u! L y C: \: y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 ]6 j7 t5 g' dMCASP_RX_MODE_DMA);7 q0 T; q' i+ r* @1 ^/ q# n2 A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 b" C7 k Y4 i+ S: }* v) X& d1 l( iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* A4 O( [& y8 G. v6 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . U. X9 N! p( M+ k; Q# l6 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) L! A9 i! e6 e4 D, S+ E& I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * |, Q8 p: u; N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( i& H& |( N& f8 |; X: H) pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# q% Q; U# ~' C5 y4 d" f: j' V+ j9 ]* M6 X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" t; j" ^. }$ ]0 U1 l3 {; ?. RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) Q1 S* [! i+ T9 Q0x00, 0xFF); /* configure the clock for transmitter */8 F6 x3 M/ i( O+ {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ h3 p! n3 Y' R0 L: L5 I1 L$ l! L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , N: i2 E/ o1 l1 J3 Z# n) X0 Z$ {7 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: C4 X; u' I7 z# |& F
0x00, 0xFF);
$ }7 |! [4 {8 W4 G/ e |: S; O/ u8 V; z9 B( F
/* Enable synchronization of RX and TX sections */ 7 a( b; B2 g) X3 B/ u: I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& W0 v) K* u, e4 ]( \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 \9 g) ^ y9 z3 w, `6 g) X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% S( o8 Z1 n$ C. E
** Set the serializers, Currently only one serializer is set as) m* c3 t: B R4 \1 w0 q
** transmitter and one serializer as receiver.7 ?4 }+ r' I& z$ G
*/6 {7 k' U# b0 I6 o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' L; y! U' B$ F* M* cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% \ p/ ?3 A, s7 \% z
** Configure the McASP pins
* f, s# o. Z+ K0 X. V0 O; E/ V** Input - Frame Sync, Clock and Serializer Rx+ d; f$ u2 i$ N$ {# Q+ E, A# D
** Output - Serializer Tx is connected to the input of the codec 2 x2 |& |' ?; x, M* z
*/
1 P" z% s9 }. j" H/ e. oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 l" z/ J' o- ~0 |" N( W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# Q7 b1 s) n: O4 |, y4 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ S5 W9 ^' _8 H; }- z3 s1 O
| MCASP_PIN_ACLKX6 d" r6 w9 D1 X, }) B6 ~) E
| MCASP_PIN_AHCLKX: t/ |9 U1 H/ `+ ?) ?( a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 L% n' }8 h6 k& J/ f0 Y8 E |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + Z/ {) k: U$ P/ F3 ^# O
| MCASP_TX_CLKFAIL
5 V0 b4 Z/ s3 M2 S# {. j| MCASP_TX_SYNCERROR
. T/ {% G' @/ Z3 `* W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & J0 }$ F! ~1 p+ \
| MCASP_RX_CLKFAIL. s' k% P8 b4 o7 ?3 Q
| MCASP_RX_SYNCERROR + H2 Q+ n* l2 @" Q/ f) t- [
| MCASP_RX_OVERRUN);
0 B* X$ S5 M' {6 w! a} static void I2SDataTxRxActivate(void)
4 L& Y% i x& U, F) l$ V/ f! O{
% e0 m P) \, z6 r/* Start the clocks */: C+ ` T( _+ _8 F" i. H6 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 f/ r. J4 k/ ?$ ]+ u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& ^* k. V3 F G* x nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 W& G. p& c( I2 D8 d! C) }
EDMA3_TRIG_MODE_EVENT);9 R& [8 c. W, S" I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: S9 `( n$ {$ Y- {, tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 A$ g2 f! ]& u" |( Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" z1 J) g1 v6 J0 M0 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ u3 x# B9 F) h2 } `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 W! [0 j% u. d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 E% h" }6 C9 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# ~7 u) U- r& r" K5 `5 J! A
}
8 a' E0 Z- A' X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % w5 k4 a8 u- g3 _
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