|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' E! R9 s/ v2 W3 U6 q
input mcasp_ahclkx,
2 f+ U" _) R1 Y, M4 F( m+ m' L3 n0 Q {input mcasp_aclkx,1 J: X- m2 e' ^) g
input axr0,
, h6 }6 q' o9 B4 ~' W9 I5 y4 A# c1 N( v( w5 V
output mcasp_afsr,% {5 X( q. f( ? T [ R$ n
output mcasp_ahclkr,
Z; ^0 m6 X1 T) S; k- {output mcasp_aclkr,
5 u. T: }5 \1 U# _0 Voutput axr1,( U9 J3 [5 ]% [- j
assign mcasp_afsr = mcasp_afsx;- Z+ N. v f: e
assign mcasp_aclkr = mcasp_aclkx;
6 `. H" O& C/ I" qassign mcasp_ahclkr = mcasp_ahclkx;5 N' Y" C' h2 ]& O) j
assign axr1 = axr0; , C! d5 I, J, N
# [0 O6 u: u8 s( `: v7 A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. e5 L* q( E+ q0 u2 y! L+ W2 Ystatic void McASPI2SConfigure(void)
- m+ _5 @0 K* k* A6 G$ H6 O{
) [8 X. j5 A- B5 E1 Z! r/ {McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 _8 Q- k9 v7 z& M4 o" s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 P; J: R( o/ t9 oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 P1 b7 ~: T4 {4 G$ K. i; C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. P) T1 B# {1 D1 r# d$ l6 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
t( [/ _! N! @( R1 P! {MCASP_RX_MODE_DMA);
8 X5 z7 [& N1 F+ ]. G- a4 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 w+ [* O; E5 r" _& _8 V/ gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 r2 V; ?. r) k% f% M* r. U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' C6 g2 G9 g+ P9 b" E" ]% KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 ?' M8 }9 d6 a$ Y8 h: p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, {' S7 m/ C3 T2 h2 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 ^; `* q% o8 \8 Q* c3 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 q+ W! p- U/ X% v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # K3 ?( G: K1 Q. {" V8 P, z& D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& L6 v+ g H* s. z& x7 g H
0x00, 0xFF); /* configure the clock for transmitter */4 M! K, z, Y% p! v# h. w8 K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 |6 J3 n" {7 x+ A2 j% p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 q5 o0 O+ z% Z" YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# l4 f* e2 f# }# G0x00, 0xFF);2 e w& I# G% a5 C" v) T* R, M
. y% D/ g( p! G0 m2 W
/* Enable synchronization of RX and TX sections */
& p- N3 `8 @# l0 t1 T& _1 o4 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; @6 O# w( H2 M4 R5 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 c+ l1 d& V9 s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 J7 P @9 l) s1 z: n" O. y! P
** Set the serializers, Currently only one serializer is set as
8 `% u% p+ L0 G. S8 c' E** transmitter and one serializer as receiver.0 M! U- S2 u1 ]$ i6 v- ?
*/
3 K* b7 n; s5 T7 p& F3 ^. MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 G+ y; {# \+ w0 w# B+ o: I! O% zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! |6 @; P9 N; g- R4 h2 N% g** Configure the McASP pins 5 y3 X. S' j7 G% s; p# `
** Input - Frame Sync, Clock and Serializer Rx
# j7 E g% D! M** Output - Serializer Tx is connected to the input of the codec 3 C8 W0 ?0 j Z$ V" o
*/1 Z, a& r* I( @3 x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 f7 N9 j/ x- `! M" O$ i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); o& l: D8 s5 V: A, v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 {+ T: \/ d3 `! }! Y% m
| MCASP_PIN_ACLKX$ Q& w6 E1 K; S ]' \3 Y
| MCASP_PIN_AHCLKX- R: G( H# ~& `4 Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 q( o( s! I4 Q9 @4 S" t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 l# y1 T( c7 w| MCASP_TX_CLKFAIL
$ {+ \% [1 E& J| MCASP_TX_SYNCERROR4 w% O# Y0 f w/ t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! a' v3 y5 b Z4 b2 a C| MCASP_RX_CLKFAIL+ H7 L; K$ U8 F- P
| MCASP_RX_SYNCERROR
" |+ J {1 {, N& n| MCASP_RX_OVERRUN);
2 A4 q6 m+ c9 J. p n} static void I2SDataTxRxActivate(void) R# e4 P3 e( a$ b! P
{
8 k; G. q+ K& L% B9 ~0 Q/ W/* Start the clocks */
& `7 _' t# o1 @! bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) B/ L5 i; ?2 P/ O( x# D# Q: y2 x5 Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' V) ?8 t) m8 t G" C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ u+ ]" O2 S0 b8 \1 p* Y s
EDMA3_TRIG_MODE_EVENT);2 r$ U) I; R& Z+ F6 `. u% u4 ?4 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( p: [; g! U8 S( r% i0 o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 ]' ~+ U! i+ [; n4 ~- Q; a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' R& B K8 ?9 ~9 ?$ I& {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. a0 T4 K. G8 [1 ]7 J* N) H% bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( j, F1 C- n, I: l# l" V" J5 `: c( e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; G" H2 d7 Z% ^6 m" z4 [' ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 ?) M; }4 B1 N1 P
}
. D2 X1 y* p+ q$ d6 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! n0 j# ?1 z0 t) W. W |