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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 I. M1 l u& _6 @0 p7 G
input mcasp_ahclkx,
" [& q. \, k7 _- e, x8 H4 ?input mcasp_aclkx,
3 G8 e/ t0 E1 a, V2 jinput axr0,
T6 b4 S9 b7 e, m1 w5 K: g1 K, T$ `/ Z: o
output mcasp_afsr,+ P# P" r! K7 {& R
output mcasp_ahclkr,
$ ~1 }* C, q1 y/ T X2 S8 ooutput mcasp_aclkr,8 S( l ~5 k2 K& O: D, N6 R
output axr1,5 Q- n. A x) e, s
assign mcasp_afsr = mcasp_afsx;
0 A0 I0 B( ]+ N+ B( Jassign mcasp_aclkr = mcasp_aclkx;
7 u7 Z! o/ @( r6 E, r+ xassign mcasp_ahclkr = mcasp_ahclkx;
) h+ H; N2 J& Uassign axr1 = axr0;
1 _: w1 i m m( T
8 P+ s$ V, G8 q% y* L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 W- J/ i; b3 Estatic void McASPI2SConfigure(void)+ W, ?- S6 j/ n! q% k1 L
{
- F: o8 R8 y; H5 dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, M% D; O% h2 u" q: e0 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; c3 l* x K1 R5 H* P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 T Z6 h7 o- k. iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) y: Y3 |/ I0 N* q. q. jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. G5 m9 X6 F% p" K2 m: b
MCASP_RX_MODE_DMA);+ H. H5 S+ N/ G: t* c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 A4 Z* P: x& q. j: X# G$ c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 H o/ Q( z& q& ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 z* u9 Y9 ^; Z6 c" M$ jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ x& P* s7 w" M1 U% S. o) D; V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 x$ B+ s' u! @# y4 _+ F8 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& h9 a7 {& r e5 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# i* T2 f+ H6 o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 A+ N& x. ^+ @ ~( X+ ?% i% o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% L& {; S) |- z# \9 k! E0 [0x00, 0xFF); /* configure the clock for transmitter */. B! E6 t0 m) f6 Z6 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 q' `7 b$ n8 }) t: O& ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 l8 Y" d! y1 qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& c; j9 s. z% V+ t ]& _! X5 T, `
0x00, 0xFF);
/ b! f# |7 v( c; A3 d# l. u+ P! j9 B
/* Enable synchronization of RX and TX sections */ ) I' F4 U5 V; p! O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# @ R6 h' o- h7 [1 r" BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 s1 w- y9 S2 x. S6 M4 q& P# eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' R! j2 Q7 I/ S) `4 P! s& W2 q# i** Set the serializers, Currently only one serializer is set as
& I7 }+ v1 q. n5 z& o8 P( H) O** transmitter and one serializer as receiver.+ q, R9 P- A4 z* B4 O% A* r9 H& I
*/8 V. w, T9 ^9 U/ f8 K9 x: t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( O* L1 h% W: g7 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. L/ ^& A1 v6 _4 [3 W7 y" N** Configure the McASP pins - s; O" H& L: P+ c
** Input - Frame Sync, Clock and Serializer Rx
; R* |( t+ A! z, l0 w** Output - Serializer Tx is connected to the input of the codec
' S: T9 G! M" B/ x7 i* E*/
% Y j8 H) }* d% U h) ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( a: T! p4 G( r/ O* qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% i* J3 o7 s. O2 w0 h, P1 E [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ z( ^5 x' p2 d4 V* g| MCASP_PIN_ACLKX
1 y& B( G. j1 [) E/ p| MCASP_PIN_AHCLKX& p+ I; {, T L& |4 L1 |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 _, Z; `; O' b) q6 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR w Q( N. h' d# X" e5 a8 @4 D
| MCASP_TX_CLKFAIL ) m( t2 }$ `4 g: g/ F; X
| MCASP_TX_SYNCERROR. @) L+ I" m' y" _- Y& Z+ T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; L9 X9 u% E$ A" Y$ u
| MCASP_RX_CLKFAIL
# ^3 @$ x2 |# T- p2 G| MCASP_RX_SYNCERROR & u, G2 l7 ^8 p' A$ J" E# z, K; C4 E
| MCASP_RX_OVERRUN);9 G) _4 J4 j4 L: E
} static void I2SDataTxRxActivate(void)9 L. v0 c+ s- F. x2 v: n' C, n
{
3 t# k7 o! y! k, d/* Start the clocks */
4 o1 }2 l7 h( D/ L4 C4 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# W7 |( u$ v& L* I9 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& U0 ?6 g9 ^' V3 `5 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! T+ [: X, j+ f* ] V hEDMA3_TRIG_MODE_EVENT);
: H+ F) R$ a$ j) y! y8 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. C H: H) D# m* HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, Y! Q1 ^/ ^. U% o& q/ vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. X# Z; l* P7 R1 x. _, }. L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- @" s3 T5 h: e, w9 j ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// u1 k& k$ {/ S1 I, B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' l3 ]0 ]) h/ I0 `4 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 H! q( I0 V2 N+ J
} ( x) v; O1 k% |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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