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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- g3 U5 N( z! z2 W
input mcasp_ahclkx,
2 Z& @) Q$ O0 |input mcasp_aclkx,* d2 w% q! [$ H/ j2 c# f* S
input axr0,1 h3 N) g! B4 R, S% c7 y( C
7 m/ _* X0 {& b; p/ i+ ~; Z
output mcasp_afsr,
& w M5 `( @3 i/ ioutput mcasp_ahclkr,
- R+ A) V: v2 C) d$ W4 y. D" coutput mcasp_aclkr,+ Q" ]" H- Y/ @, w3 m- [, q) |
output axr1,# r$ b7 l: T* ]
assign mcasp_afsr = mcasp_afsx;( @8 _+ o0 L+ [8 X1 g |6 S! E
assign mcasp_aclkr = mcasp_aclkx;
& z8 V# y9 q# t' t$ l) Vassign mcasp_ahclkr = mcasp_ahclkx;
# L1 H! ]- P3 C# p% Z5 passign axr1 = axr0; 4 J/ i4 ^- _) {# p; R5 A6 B
4 `) |# S! P: E+ ~ ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ C+ s+ G- l( Nstatic void McASPI2SConfigure(void)
! H2 g- q K7 p* M{
% ^" ]7 f7 R6 D5 F& Q* l+ O6 pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 B1 d* N* s: V+ j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 h; T* F2 u, y) c5 m2 ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 F, K* z+ i+ M# ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 C6 d" I# A. j8 U, RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) L- D5 R, M/ K+ w4 C ?MCASP_RX_MODE_DMA);
' D. q! l+ W" @) C0 u T! a% W$ _6 VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( H+ b( U3 U9 }6 W) vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ B8 v5 T+ @8 C5 G6 ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; k2 d# \8 D4 a7 f) ~1 HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 W/ S" _% i. q% t* T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 N9 ]" f; I& r4 j# i% _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- u" E9 f+ ^( D) xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); ?# W1 j# [7 m8 d; a/ R: H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. B, u! N: S% w7 x. B3 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. {! `4 Z/ C3 W% R! |0x00, 0xFF); /* configure the clock for transmitter */
! j5 V9 u. y3 V* ]- f( |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 |& u* J* o+ D8 Z4 w0 k$ }+ ]+ |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) _# ^" r7 J, M8 E1 P% sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: F% s9 z3 |: z3 |+ Y8 ^0x00, 0xFF);8 T, q/ U+ n* T' c5 @( M0 J
0 D# Z! T6 P( V5 m4 _
/* Enable synchronization of RX and TX sections */ ' M8 P' N; T7 W4 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, T4 L- C4 Q& N4 o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 E2 c( @, s8 {- m r0 x2 aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 t9 P: _8 J k" |( X5 c, L" ~5 f( y** Set the serializers, Currently only one serializer is set as) F, Q2 c% y0 |& y
** transmitter and one serializer as receiver.
$ \/ T' ^8 d3 V*/
. C; y; X' C/ o' U, ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: l% Y. d$ v6 ]+ q0 Y e( o+ E/ x; _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ a6 m6 m9 V- k N0 @
** Configure the McASP pins
2 Y4 m* M* B$ u0 N$ Q7 W, J2 O5 S** Input - Frame Sync, Clock and Serializer Rx# _& g) S k; f& J
** Output - Serializer Tx is connected to the input of the codec ; q6 k. X. f: o4 Y* A6 q. r
*/- _$ N8 X4 T; \+ [, L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 L: x3 c. b. S0 t5 D1 U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ l6 z( |& x6 C$ q" k9 E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 W# p; P) J2 V- @% L
| MCASP_PIN_ACLKX7 m) H$ k8 |: N, j! X7 a) f
| MCASP_PIN_AHCLKX* i& q; q. c! @0 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' v _& Z) S# x4 ~# j* i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ] [& @, t4 p
| MCASP_TX_CLKFAIL
# ~( F- u7 B$ G4 [# _, Q% S2 P| MCASP_TX_SYNCERROR
, ?+ D7 d. l ?/ f2 s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 Q# P( A& d4 s5 X! R& ]( F
| MCASP_RX_CLKFAIL
U8 `- k3 ?8 m1 [8 ~8 q| MCASP_RX_SYNCERROR 1 l1 ~* X z* M& v9 A- c, M
| MCASP_RX_OVERRUN);' a( j/ M. H) ~- a ]
} static void I2SDataTxRxActivate(void)0 b# D7 T( G" Q$ {
{ c7 ^- R2 O6 W: h
/* Start the clocks */. _# d( o! x. v% r9 Y/ I: V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ |" F# o5 K! D+ kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 y1 I7 ? C, `# s% @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 ]" M3 g$ ~3 `; ]1 @7 C
EDMA3_TRIG_MODE_EVENT);% s- h) Y! ~+ m9 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 b- W/ q, T, z. ?' X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 \9 Q* j, t6 t1 I/ o8 tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# b. }* X" f% Z# FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 Y6 n5 ?& J: L9 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 t- u5 P6 r2 N' B" }* x# @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( o* e& g9 b7 U: S0 H* nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 X2 D! Q3 q4 v9 V
} " ]2 F" ?5 N. ~' `+ o. M) P) j, e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 G1 d8 a$ y( d2 L3 P$ e; ~
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