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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' |6 ? d3 o4 r1 R3 w8 Y
input mcasp_ahclkx,. e1 ?4 j. x1 L, Q7 T. e
input mcasp_aclkx,$ f8 ]2 f' S7 z5 u' h# a
input axr0,: Y3 |. D) f8 U$ n
/ }. k$ j8 l( a8 ?) h, ]) q5 X
output mcasp_afsr,
8 w7 C; m) S" T2 o/ b2 Y) Doutput mcasp_ahclkr,) Y% v8 F+ w" L8 h6 K
output mcasp_aclkr, C! W7 r, }- x# M# s" X# Z2 U
output axr1,' K5 \- ]4 v5 }
assign mcasp_afsr = mcasp_afsx;
/ F, \+ x2 d0 P6 gassign mcasp_aclkr = mcasp_aclkx;) y: N- m1 r& F% H
assign mcasp_ahclkr = mcasp_ahclkx;+ ^9 g; |! X1 R/ Y8 b4 o5 X
assign axr1 = axr0;
1 R0 E( |; I/ P& ?, U+ [
3 h3 L! c' U2 b1 M: y/ u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! ?0 H+ I( l8 b. n1 d
static void McASPI2SConfigure(void)$ B; |- z- W0 o/ j: Q$ P
{. j7 i2 @ C, Z) ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! w& n3 y! G9 [0 ~; r6 ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 Z; y! S* V) a$ RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
u% N+ @5 x0 a% U$ sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 n5 W: h9 Q! K# Q$ [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! s/ \( K' F0 s2 ^* V0 u2 H- yMCASP_RX_MODE_DMA);
4 A' L* t7 X" L3 I: T+ zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, {( e6 A* M* `# K) W% _5 _8 I! Z" @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 o7 F$ B4 m+ O1 R# fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 K: N& y5 F0 U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
O/ t7 R% V4 i- OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 ]# r; k# S$ b$ u- L) EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 C* c9 Z+ y/ ^3 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: D5 v5 M' I5 U9 t* L" ^- N& i& `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" s* I/ j7 k G1 iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: J+ L# J3 t* K4 n7 b- ^. ~
0x00, 0xFF); /* configure the clock for transmitter */
: ]$ v9 r8 j E3 f4 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 x) D1 Q9 m8 ^3 y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 ^( h1 j/ e, u4 C; mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," }' K* K( z( h9 F R n1 k' d
0x00, 0xFF);, d l3 e7 S* E) M; j
* N3 d& e0 }/ C5 Z" Q/ B/* Enable synchronization of RX and TX sections */ 8 V- Q3 e! N$ _! e' b& E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' }8 w6 ^) ?) }+ ?. \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& k, @- C$ X9 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' D3 T+ L/ t* u" V" L. r
** Set the serializers, Currently only one serializer is set as
$ E" Z' i( J+ ^8 G/ R. ~/ c** transmitter and one serializer as receiver.
. |, B2 A6 |+ U) p" \6 c( s*/
6 r2 _& B) Q3 d8 j* Z: a7 _2 J" gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 Z- o7 q& o9 R: F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) V' N" [3 y; m9 ^0 s** Configure the McASP pins 2 {7 P8 q9 F5 p) [
** Input - Frame Sync, Clock and Serializer Rx
- i9 c& `) ?: N# r** Output - Serializer Tx is connected to the input of the codec
: j/ q! J: {* W0 ]+ }& T" Y*/
4 D) }0 l+ P/ b* ]$ s) \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! B0 G+ d9 K6 l. X) E+ ?2 f" g' u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; C$ w+ ]- x3 GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* _+ b8 [' \# W; ~. z0 _6 b
| MCASP_PIN_ACLKX
D4 k! s9 h3 `0 k+ I" I. u| MCASP_PIN_AHCLKX) s- c. V5 j$ m2 P, N7 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ^* o* \1 u: D7 `$ _3 `( u. {& [# W: BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! a( a' l( v- Z! p
| MCASP_TX_CLKFAIL
( p( ?; \0 m5 ?: ~| MCASP_TX_SYNCERROR
6 P H ^" l- L5 {* Z$ e' p2 w4 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( r4 R0 m. c0 P2 N ?% \. z# _9 J
| MCASP_RX_CLKFAIL
4 z, e0 E+ Z+ U' | A8 Q| MCASP_RX_SYNCERROR ; x# D3 O) \$ C# n
| MCASP_RX_OVERRUN);
S% {9 ?: H1 ?6 ?( k} static void I2SDataTxRxActivate(void)
0 d5 p0 ~$ W) I( v& T( c{0 z9 O. z E' q& L7 P9 v- I ]
/* Start the clocks */
* A3 ?3 M" f) A: ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, |; b8 P* K" ^% Y7 ^" p5 h d! O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 k9 F5 ?! U* M8 H+ R. M3 ^+ JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. h. W- [$ C8 k3 d$ L! f" ?8 g/ K8 }EDMA3_TRIG_MODE_EVENT);
$ g3 {* t& k" n* {6 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( |5 @% s, P( }% B- L2 J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; \/ W2 s7 O+ R2 S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 J# @+ g& K5 @7 U8 bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! v: S) P" z7 J0 z# T2 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% ` U! M& L2 V' J' \) nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ I. S' l' O9 U C9 h2 \# I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" y% M" D$ C: I1 L5 `} 7 ?$ B" H, H8 ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / F- Z! v9 R& l: G& r
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