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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 N- b9 J$ m3 z/ w% U! O4 y
input mcasp_ahclkx,
9 m1 _% I: r; B9 b+ Ninput mcasp_aclkx,8 {7 y5 H7 ^, M, }' N* O1 \
input axr0,
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output mcasp_afsr,- r; [" z) K# K3 P9 ?4 \- u ^9 `
output mcasp_ahclkr,+ E8 |: b% Y$ L* ]0 j, t
output mcasp_aclkr,) Q/ Q5 c$ O4 C8 s5 C
output axr1,# H3 G+ I$ P( D0 M4 V
assign mcasp_afsr = mcasp_afsx;4 Y+ t3 e- V0 }
assign mcasp_aclkr = mcasp_aclkx;
8 X% A# q, S! A. w* b( \; k$ ?3 oassign mcasp_ahclkr = mcasp_ahclkx;
6 v: z% p* Q( Z- c4 Iassign axr1 = axr0; ! w5 m8 H5 J3 z$ A$ l3 @2 r8 T
_1 w$ D2 {5 ~6 n( ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 E% G5 t- R @2 X8 B, _static void McASPI2SConfigure(void). r+ W0 Y2 E6 ]- Q7 Y ^" ?7 ?
{5 X! @/ l5 \3 v9 V: _- ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 ^ s# X; `+ `! W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 c" K- M D# }3 o& k$ @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 j" P3 _) `2 O. Q/ v7 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! U, O1 X7 V v5 d6 iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 I- w/ @ z; m& f/ CMCASP_RX_MODE_DMA);0 e$ {: V/ B& F; b8 a9 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: p6 B z; l" ^7 c; K( D0 J* [( B6 p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 i3 F$ b% t$ r. F. cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ }' B U$ t* k2 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! D. j' f" i8 s5 u" k- |5 i$ w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 p1 `3 U0 }$ s3 _7 [& A$ i# a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, q" B8 _4 d5 J6 [3 n# }* C) |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 D: S& g+ u3 w% p& T+ gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 s5 i0 k- T4 n6 A( l7 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 i# l1 i9 c- T0 e) Z( K$ [! F0x00, 0xFF); /* configure the clock for transmitter */
! J& r' E8 X7 Q# dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 `" O) Q0 k$ N0 C2 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
K+ j" X7 S# n/ D6 [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 @7 H5 }# f. x( n/ J! q
0x00, 0xFF);
$ Z$ \9 F1 F7 w/ G5 A! |, h1 }! {1 \
^$ T4 r9 t- \, E+ o. M5 H) i4 E0 {; S/* Enable synchronization of RX and TX sections */
. n3 l% \+ M; I+ j/ w' s4 HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! X% s2 U5 `3 SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( S" |* Q0 f( r8 w' y4 @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 X! G5 w6 {' r/ G7 e** Set the serializers, Currently only one serializer is set as
: f" e | ?4 U; S9 n** transmitter and one serializer as receiver.* I7 Z- ?/ a0 i$ w$ F- o
*/
1 ^9 B8 l$ o/ ^& KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* \8 j+ b2 v x8 k2 | BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& y0 r. V! S8 T% z- g/ T& ]** Configure the McASP pins
6 Q" ?) S) B) Y3 a** Input - Frame Sync, Clock and Serializer Rx
+ ^; p2 L/ F; i** Output - Serializer Tx is connected to the input of the codec
- B+ C3 g6 w# H, a6 h*/
. I- z0 o0 ~7 F: Z! ~- L7 GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- i/ v7 t9 U+ ]2 L7 L. s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. f* Y$ ?7 s- n% aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 Z7 K7 J- }' e0 M4 @
| MCASP_PIN_ACLKX
1 I# Q0 O" K1 X) V| MCASP_PIN_AHCLKX
1 G1 C. Q S) p% _: }; _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ D5 j2 X$ s1 d% g* Q/ XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* Z3 O9 Q: d4 `" f/ Y$ w| MCASP_TX_CLKFAIL
) ^; y* o x* @6 b8 b. W. f N$ _| MCASP_TX_SYNCERROR' n+ |8 @- a3 h6 t4 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 ?- M, J5 G6 w$ d0 `6 T| MCASP_RX_CLKFAIL3 M) }1 k; A% V! N, b! e. J! B
| MCASP_RX_SYNCERROR % b! F+ o6 M# F' \/ v& ]
| MCASP_RX_OVERRUN);
0 T( L: V* O# u) P: E2 @} static void I2SDataTxRxActivate(void)
" z6 }8 ~. b0 K: z{
* G% [6 f, |$ M8 l Y' f j/* Start the clocks */& N+ c* q; \3 d6 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- d! G7 F9 D: ~' Y' KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
f9 C, V& I" w- P& N5 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" z$ Z5 N" | ^ aEDMA3_TRIG_MODE_EVENT);: _9 ~* p& N6 ?8 y% @/ R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 Y& ^* f& l4 F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 G1 b5 t! _5 [7 C$ F( [" n+ E$ N! }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 p% s) g% G& g6 _2 O: f6 ]; _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 |8 e4 V0 b( q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// z* N) t2 P& R. X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) R/ s% ~/ ?& g$ OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ a. g1 ~/ E8 N* e; [} 5 m% l' Q; |9 }( b! C6 X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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