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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 N4 k/ A1 D, d; C; y; minput mcasp_ahclkx,
' `( p! O+ E- [6 yinput mcasp_aclkx,. f5 x6 f9 [4 {, b6 s, i+ M
input axr0,
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output mcasp_afsr,
& v9 v! L+ w1 Ooutput mcasp_ahclkr,
3 A6 k/ g; O" q j- u [, houtput mcasp_aclkr,6 ^! h0 b' ]/ j8 o: q8 b
output axr1,
" O4 a+ Y8 \# T7 E# ` assign mcasp_afsr = mcasp_afsx;
% b' \0 K7 j2 v/ r1 bassign mcasp_aclkr = mcasp_aclkx;
: D9 z# T7 l; Y+ V' s, \* g& ?, oassign mcasp_ahclkr = mcasp_ahclkx;
% K- w4 b& M( j2 m8 u. Iassign axr1 = axr0;
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6 O$ o/ Y' | _* z+ v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 k( M" q5 o- Q1 O+ N0 f' [$ kstatic void McASPI2SConfigure(void)
5 Z9 {% E3 R& ?9 t5 M# }( h l{7 W) |5 ^/ ^$ ?' Q+ h' N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* {+ Q" o5 p0 RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 s2 O1 G1 T5 K2 Y, pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% ^1 y) N# Q0 M0 e/ k- I' d# @, m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- o; C/ p; T2 w3 ~* s5 ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& M) P% G( G1 n ]* A( f' ?8 BMCASP_RX_MODE_DMA);
9 ?; O9 D2 n& `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 H% t- K" D2 a! p* Y$ c6 H8 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 Y8 ^ `' y, r# o9 P0 @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ N- F8 N! R6 B i. X; f5 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# T/ y0 e$ g- Y" U. L0 O" J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + |7 T, e' @$ D- O4 {3 o- }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 T$ G) i1 l5 W& h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ g5 m8 a, j2 }" N$ Q' D8 sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + u7 K" f: }; b) I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& u, z0 [5 J' b0 t$ G J+ `3 s9 q
0x00, 0xFF); /* configure the clock for transmitter */
$ H5 }0 d8 W# o, LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 S7 t# s) Y+ H/ Y: f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% {% D, f* @ V) Y0 s. rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( c" f2 {; V: @0x00, 0xFF);
) t- m$ y W' I2 x! m2 V# l
/ x5 K& ~* k- i8 Z/* Enable synchronization of RX and TX sections */
! k& T- H( C$ V; C( P# t7 t$ Q, H3 yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& t) H" E9 `. f2 M$ p6 g) X. |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) Y* ?4 [! w/ m+ u2 g! W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& v* a/ z+ c9 M% `6 ?. G
** Set the serializers, Currently only one serializer is set as0 @( y# ^ K1 ~( _0 P
** transmitter and one serializer as receiver.
0 q a+ ^4 F4 W1 e5 z7 P/ y5 c9 F% P*/" }. S4 r. ]6 W3 J: N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ @9 t8 r% J! ^; i4 C% {' B8 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' w9 N! N h8 f$ m* l2 n
** Configure the McASP pins l/ @6 x% Z0 ^4 v. Q/ b O
** Input - Frame Sync, Clock and Serializer Rx$ X# {- ?2 n0 D( N
** Output - Serializer Tx is connected to the input of the codec
. I* U) [, g6 T; e2 z. w1 `*/5 j% C( g6 ]& H& O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 \* E2 `! L% n4 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); {0 X; N% q5 N6 e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" ]) s: E# ?! L7 E* w0 N7 ?| MCASP_PIN_ACLKX
" T6 v7 g% `5 D( M| MCASP_PIN_AHCLKX
4 R$ T0 y# O9 H# F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 D: O. a% U0 o/ cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 \2 q+ ?& V% W6 e& S4 ?( ~! z| MCASP_TX_CLKFAIL 5 x, u* V: `/ O& p3 s
| MCASP_TX_SYNCERROR
1 }3 E, i! K, @; c' `& x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 X7 U6 ~% X. z+ C* [( }/ E/ h
| MCASP_RX_CLKFAIL
+ ^$ Y- b: A9 z% Z; H4 p| MCASP_RX_SYNCERROR 5 }8 @/ U: E! v
| MCASP_RX_OVERRUN);
3 z; }% \+ e# Q/ {! i) d} static void I2SDataTxRxActivate(void)+ K/ ^/ v% ?6 r3 [ x" B4 o k
{! R _( o3 A0 r; x% Q' Z
/* Start the clocks */
. }. I7 X8 G+ J) ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, }* A* L+ S$ h/ MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 C4 T1 _0 X/ k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 t. D- M7 t7 K8 g0 V0 m( P$ sEDMA3_TRIG_MODE_EVENT);
% O4 x9 z# f4 C, n' u1 o% W+ |% N# eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ g1 V& \ S- n7 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) E* @2 K; g* }3 h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 Q/ G; C, Z5 P1 y- Q9 NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 b B" L5 b9 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 T+ @% x( y6 ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 Z" {8 }, n- f; Y5 V4 {. EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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1 i' k8 K! D; y1 j) N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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