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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 `5 j8 I7 E% u5 @1 oinput mcasp_ahclkx,6 t' N& I9 o1 B# ^3 \5 l
input mcasp_aclkx,
& e% e: `0 l) Q, Y1 vinput axr0,, b1 i8 Y. Y3 h4 r
# h7 l: {' A, V* Y
output mcasp_afsr,1 W/ ^8 L# W: ]! u
output mcasp_ahclkr,
2 T8 @ d( `2 N, ? Uoutput mcasp_aclkr,
9 u# S1 O- W4 [: |output axr1,
) ^2 _: D/ V; ^( o0 m: D: ]; c Z assign mcasp_afsr = mcasp_afsx;
! t) F% J/ }: I0 I, b' o8 M' cassign mcasp_aclkr = mcasp_aclkx;" k5 m; d: F: W6 n
assign mcasp_ahclkr = mcasp_ahclkx;% f, `& R0 t! W! s/ C
assign axr1 = axr0;
( l# }" T; Y- m8 q
3 O/ M( _* T; C7 p* K+ o8 Y) a/ E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ y( z; a+ g& z; h/ f) G9 @static void McASPI2SConfigure(void) ^+ R6 e; U" v, V5 B3 t, M& x, w) ?, T
{
" Y( K( g. {5 C" E, B1 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( V% c- X: i0 t7 w' f8 n9 \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# o: M6 G& {* ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, I1 g3 V2 S5 u$ f# jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 N+ I! `) u' D7 Z6 aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ E+ b: q, g4 M' d) T8 G" W) \" x
MCASP_RX_MODE_DMA);
) R- M' L# r& E' _$ pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," |. O( A6 w( _2 b/ r J" p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 P1 C" I/ F- H0 v& kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , H+ B6 u" N% i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) o* t9 }. x) T# _/ B! Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 q: ^$ _4 q; {6 ?* K1 MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ n$ o1 Z& C; k9 b. rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* e* A$ s: Y, @, y7 v9 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# H! \5 j4 y7 X9 H0 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* O1 O9 D" b9 J9 D1 `# F0x00, 0xFF); /* configure the clock for transmitter */
& o/ e8 y+ F% m- y7 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 A& ?4 ~1 u& \& C; r. y: n! Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ x1 k; l( E; R g& n! k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 M3 L5 S {# f; l+ G" @" G
0x00, 0xFF);
) J* c1 z! O. r0 N
* P, B# y. r9 q& Z& P) [/* Enable synchronization of RX and TX sections */ % Z) o9 x- Y( O9 x: Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* o: D6 O; I: X, F7 N9 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# t, x4 o% j# K/ H% o0 \0 P- E7 c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ I/ T) x0 u# l/ w6 I, M4 X** Set the serializers, Currently only one serializer is set as
! a% B# B4 G( \# O** transmitter and one serializer as receiver.4 p" Y6 V9 g# z3 S9 b
*/; u4 O! G x+ b) ?7 r) P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( X$ R% Q, O' W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 L8 r+ s& M) G: v, c5 E
** Configure the McASP pins
& R0 Q+ H, W5 R( C$ C& S7 C** Input - Frame Sync, Clock and Serializer Rx
4 r: j; Q7 C& R: r+ B** Output - Serializer Tx is connected to the input of the codec
C" `; |4 j& d0 ^) \3 w5 ?' D6 {*/
( L9 d ]% W; l1 W; ~9 f0 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" ]! v7 P! d9 S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; f" |' m; b5 O, o4 {7 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" T! a* |$ E5 j7 s; c5 t| MCASP_PIN_ACLKX
" _( y1 Q8 M+ _0 a3 u9 I. x! T| MCASP_PIN_AHCLKX9 z6 u2 q, k w @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- ]) c1 E$ [0 X! l! ~. c8 y0 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ Y" f. C0 c" ^; f9 O| MCASP_TX_CLKFAIL ; L4 ^6 _* {2 k5 X1 p
| MCASP_TX_SYNCERROR
1 \% j3 F4 @# Y! g1 f2 h o) f1 d1 h3 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " U) l0 g4 z! A) L% C( \( b2 j9 I
| MCASP_RX_CLKFAIL; K" W2 c4 x8 e9 J
| MCASP_RX_SYNCERROR
+ \ y% L+ Y2 ? C6 m* l| MCASP_RX_OVERRUN);/ v) E, w2 O" b7 x1 O' X9 v
} static void I2SDataTxRxActivate(void)
2 `; i, K" F. Q. o( x- f{* ]; `( x2 N3 Q: K: M* j. n: i% O
/* Start the clocks */
2 s. a& z( g* c( F2 ~3 @. ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# o# g5 R \0 B+ g5 F; r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( O* G' ?% k0 Z2 \, \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 j: P' c7 ~; Z$ d& KEDMA3_TRIG_MODE_EVENT);
- T" @. j' t; A9 p$ f( E3 r% JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& ]" f/ L( H' s3 k/ A; K, _4 m& |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' d" Z$ Y4 Y7 V$ Y' V5 d$ n- K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); g$ U3 r' N- j$ x+ R5 a {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' ]! @* R. ?* y3 v1 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' Z/ n* R9 e2 k. JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" r. N% B2 C5 z0 D1 P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. V* F$ }' g, q% n7 k4 u" T/ K
}
$ `! i( ^, u( k4 {- ]. l: ^( _) l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; X# k0 G; K( A
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