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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* ^; A- U* u7 @! z5 h* g, B4 w6 }0 [- ainput mcasp_ahclkx,2 C" ~ y9 d1 G H, G
input mcasp_aclkx,: M3 z1 z! I2 k
input axr0,
" P$ |: W* ]+ ~3 z& M" a& U9 |# d5 s: p, J
output mcasp_afsr,8 S, Y( i. y5 B; t
output mcasp_ahclkr,+ N& l: R4 n/ [3 Y) Q! v t
output mcasp_aclkr,
- Y% l6 k6 _, O soutput axr1,0 H) a! O4 I) O: n
assign mcasp_afsr = mcasp_afsx;
6 C' {# Q* y6 ~' Cassign mcasp_aclkr = mcasp_aclkx;
8 i7 m+ K2 [7 T0 I6 L+ o! W0 passign mcasp_ahclkr = mcasp_ahclkx;
% S9 G8 b. W( h$ \! Jassign axr1 = axr0;
j/ L2 J. U- F2 y' j0 q& o" d+ J/ d' ?0 O4 K# A+ z7 U8 S* q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . ~( I. H; q1 ~3 `
static void McASPI2SConfigure(void)! Y" U# }+ t# P0 j) E
{: _+ L$ d+ U* Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! W1 B8 [* i& O3 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. P! u6 {8 o! x2 E# s+ W! Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: ^& ]! X' @+ ?' e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( b8 c2 i7 c* n! L$ k8 W+ @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- c3 D; L+ b' `
MCASP_RX_MODE_DMA);
6 ^$ z" t, a- ~0 h {- kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ P! X. a' @# KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 E6 V8 U- w4 [! g7 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & U2 d% Z* J3 x. s% q- `6 j# @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 }& d% X" K [9 V! [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; Y! g) Z- ~5 F! x. n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! Y6 b) z: B9 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: c8 N! {3 o9 x8 m- i5 w! A6 v: SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. ]8 t7 W t3 Y! O/ g4 w. dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. x! k$ l0 i6 A0x00, 0xFF); /* configure the clock for transmitter */
/ k2 i, n3 H' e! C; X0 SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 J, c/ h. R, n2 n" N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" z' a x0 L2 w% P. lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ p, F- p {% Z* b4 R: K( P7 S2 {$ d
0x00, 0xFF);* h) }' f' {$ @! S4 x3 m( v/ g" E
5 O. }7 d1 b& c: o" K7 u( v
/* Enable synchronization of RX and TX sections */ 1 ~) g/ o. B% x3 L- \9 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* t" d2 g* F3 J; ~3 S: B/ a, f2 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' g6 e9 p4 C$ a3 t/ WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# o P: {$ D0 ^+ U# v `
** Set the serializers, Currently only one serializer is set as# R; J- e. p) s# c( F. B
** transmitter and one serializer as receiver.+ l' U" {, _$ g4 s
*/2 s2 I& c) ^5 b6 o, x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" _, g2 k+ p* c! g9 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 I! ]& Q' X3 _) w% w
** Configure the McASP pins
9 ]1 L" m6 j+ C: t** Input - Frame Sync, Clock and Serializer Rx$ @' b1 _. i& N1 M4 t4 Q
** Output - Serializer Tx is connected to the input of the codec + o3 M6 o; V4 l k- N
*/* _, E% I6 }' l4 U, a2 {2 `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. d) Z, ^9 v4 d8 p b$ y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* x) C& y7 F# T W% w% Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 w4 k, v9 \/ m9 d, ]
| MCASP_PIN_ACLKX
( ?. P% _) a+ [7 V. X& Z1 X' N; n| MCASP_PIN_AHCLKX+ R; a; V* \* h6 ]; _8 h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 [5 {$ T2 L6 o4 d3 p9 zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 \, Z: m: } `$ c+ H
| MCASP_TX_CLKFAIL
2 \, Z/ Z+ s2 h9 ^4 N% R- `| MCASP_TX_SYNCERROR
( @8 Z, q. {5 y+ O& ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 ?4 X/ M8 O7 Y$ v| MCASP_RX_CLKFAIL9 e' s3 k! b5 ~, e* D
| MCASP_RX_SYNCERROR ' e0 C" |4 p" X$ p
| MCASP_RX_OVERRUN);% b6 N8 X9 o. ~$ N4 K5 l# P" u
} static void I2SDataTxRxActivate(void)- o9 `; V0 a( B4 N: d' P( U
{; v: z& U. V2 R- [+ I2 R2 n
/* Start the clocks */
: H8 C4 T; K6 u0 [% J% _ d/ MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& _: C1 r( n1 b2 h U/ o' c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( u: z. L" M+ D# X b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' `3 T1 P* X0 NEDMA3_TRIG_MODE_EVENT);
# x; d' @% T7 ]. v4 g8 x$ QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 x9 M3 X3 d6 `. M4 b: rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& ~1 T. x K, g+ X" xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 _& L/ _, A' x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' |4 I4 r: u: ?( A# T6 |2 u( d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% m# x; h# T# z% M) XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 _ P+ P5 P6 F& x% {$ @. u& R! u AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 S3 o: Y7 ^! M7 x
}
& G Y# C6 V; S4 K9 K, A) @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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