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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 T- i( P1 D' z3 U& K. i9 |& jinput mcasp_ahclkx,
' O% C3 [1 t* a( v. K6 Iinput mcasp_aclkx,
: x6 y/ D2 k* X2 ?7 N Rinput axr0,
% ~$ P" W8 j" h X* P5 E' }- X# H( U
output mcasp_afsr,
% o0 l' O# s+ d. A' G3 woutput mcasp_ahclkr,7 U! r/ r2 w" R2 ], ?
output mcasp_aclkr,, G, Q' Z6 N( E2 [, a
output axr1,
9 y8 R, v7 P2 N1 ]) N/ ^ assign mcasp_afsr = mcasp_afsx;8 F- j# _& K/ V) {- {6 e- r
assign mcasp_aclkr = mcasp_aclkx;$ G; k6 |+ ?5 c( M# m
assign mcasp_ahclkr = mcasp_ahclkx;
4 E$ `' Z. n" @5 |! e$ vassign axr1 = axr0;
3 [- \" d9 [/ H6 c* v( z( y S- P6 u8 i2 J/ b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % C A& K4 Q" L% g7 j
static void McASPI2SConfigure(void)
6 M, q# J3 q i( d4 J{) V! o# f1 v7 C& O, e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& |; n2 y2 v8 t2 _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 d0 r' Y9 s+ A8 t3 v( E' }8 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- z3 `4 u/ S2 s# P8 F6 X7 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( R3 V/ E e* a0 d% xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 R9 k7 R7 ^( t6 Z% o5 r' l* ^3 IMCASP_RX_MODE_DMA);% e3 T- @) a C0 r: p4 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ D2 }9 W6 x AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& C' Q7 e# k B7 {% w+ d3 z' EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 v2 b n$ H* Q. S( N8 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. M' X4 g2 R- f) O$ M: NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 O$ g9 H1 N7 G, ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" q/ T& h2 ]$ j, E) |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) t! o; ~3 e( X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; O" p1 i; `- \. eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," o9 h8 K) n6 H& M) Z, f% k
0x00, 0xFF); /* configure the clock for transmitter */
' v" [3 t* z* W+ ~8 Z* n6 d3 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! g% V" `5 D6 {' A& h' }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" v. z" a8 h! v- D9 a) J& SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# X& @0 U0 r1 D4 \; b6 {* C. E {0x00, 0xFF);
3 Z% Y! u& \: K' ?
% E: A5 ]+ d; H4 y2 M/* Enable synchronization of RX and TX sections */ ) h; H. }2 N1 z% p1 w# \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 g. H! J9 {) O1 ` Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, O0 Q. H$ B* b: R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 w7 I) p, N! ^- D4 C% J& V; g
** Set the serializers, Currently only one serializer is set as2 ]+ A4 Y+ j! S6 Z5 |0 M' Z
** transmitter and one serializer as receiver.
7 Q9 C# M: |1 Q7 p*/
" S+ }* ]; v/ k) kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( u# N/ }+ ~" v9 I8 |# d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( `* J: {8 N, V% x
** Configure the McASP pins K% B3 t; d/ o1 c0 R# f
** Input - Frame Sync, Clock and Serializer Rx) `" s1 A+ F* \; `4 k7 a1 V
** Output - Serializer Tx is connected to the input of the codec 1 y B8 E! Y9 q5 v! o( G% W7 {
*/
' H8 {$ o% r+ C2 Q' KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 Q9 F7 q' z. `/ l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 }2 d1 e+ Q, o: s" H9 J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# w$ \/ k$ D( f) F8 }| MCASP_PIN_ACLKX i! z. C0 h) U
| MCASP_PIN_AHCLKX8 T" [6 e* N$ j+ w7 u _1 N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// b; U- ~% w/ w# Y7 P) T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 c9 n* _1 \" {| MCASP_TX_CLKFAIL * |/ ]7 G- ~' [7 z# F
| MCASP_TX_SYNCERROR1 E- U% u' V5 b- }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - M) b7 _. O9 L2 E5 d
| MCASP_RX_CLKFAIL
: K4 E3 ]5 H1 y/ N: c0 U+ v| MCASP_RX_SYNCERROR
& N2 c% h4 j4 Y% U. v| MCASP_RX_OVERRUN);' U" j9 B0 j5 W$ y- f) g
} static void I2SDataTxRxActivate(void)) s# n) m. D7 j% J" S: _1 H z
{1 Z: k/ M, y0 l
/* Start the clocks */ `6 N9 Z5 B' H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, u& U0 v( b7 j1 L8 i5 Z0 UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 ]4 K; R9 w9 F- o+ K9 s) wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% p7 p1 Z7 G" c, Y( fEDMA3_TRIG_MODE_EVENT);
T& Q+ C5 l8 q4 a T- @+ jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 J& ?) q" ]. o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 c0 R9 W8 u- d% J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 j2 ?0 U. Z% \( xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 a' T" B! D% Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 e& s: [3 e) j @+ \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ y7 K. L* i5 B$ U# N) C. u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 w* a- j) I9 n% r0 R} 3 }1 ?$ \9 R/ M- H1 V( f: h3 T, D( ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # I4 L- ?2 @$ j- r# G8 x# i
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