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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, \, f' t* P* W( c/ kinput mcasp_ahclkx,
& o- I" S7 K& E5 ~input mcasp_aclkx,4 D7 H2 C9 I# f+ Y5 [1 w
input axr0,
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* G! I# |6 W6 t* |output mcasp_afsr,7 q Q, ^# @# P) ?- \# ?" j4 V. D
output mcasp_ahclkr," t# {5 Y4 G' g8 ~* x& F/ v
output mcasp_aclkr,$ f. F. m& I& \; ^. V7 B
output axr1,
h- \3 e' R( G% g2 K1 a assign mcasp_afsr = mcasp_afsx;
+ B% L- c: n, o# vassign mcasp_aclkr = mcasp_aclkx; D% @! U7 F* X) j4 J
assign mcasp_ahclkr = mcasp_ahclkx;
' G3 ]6 O+ G+ dassign axr1 = axr0;
6 y. y- f4 d+ H* b" s. X8 X9 `9 L, S( c# r2 n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 N, o1 h5 n3 I. Z2 bstatic void McASPI2SConfigure(void); a; k3 O; ]. r2 _: [" J
{9 `# K1 j- t2 ]2 ~* U
McASPRxReset(SOC_MCASP_0_CTRL_REGS); Z" |0 E6 h/ [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: |& Y/ S/ Q; f" kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- ^, ~' i# X+ \1 u# i( ^" \& eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 z9 L3 t2 z4 j( \4 E2 C* O9 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. C1 B3 J5 [( q5 \7 s& c$ T
MCASP_RX_MODE_DMA);
8 t. P' X* Q' u+ q5 F) cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," @! D* n0 e" H6 [% O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- k! t; u. R \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; k, M& F1 N- n, Z4 w7 Y; i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 a1 m% Z6 X6 a; U2 ^3 I& `8 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 m7 U* Z$ U) E" T. P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# h* \' W! J7 [. K/ e* k; R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
`: C1 ^$ n/ z, @3 }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- K, i+ c! M$ X& _0 j% w) kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. s3 L8 O H' J N# P. Z+ O
0x00, 0xFF); /* configure the clock for transmitter */
4 C; f* E7 ]! _6 b/ D" ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ h3 D6 R* F% t! P5 I+ O: O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 m3 o- j8 A/ g7 r, |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; ]: Y) H/ k% c, ]3 S4 T0x00, 0xFF);
. g+ T0 m7 |6 @. g6 o3 b% W) k( p& a9 C4 {
/* Enable synchronization of RX and TX sections */
$ h; u$ k) ?7 @# UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 M6 U- w7 W7 \* [6 |4 OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# f7 N, J5 r4 Q% WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# c! {3 u0 C) h* z: ~7 y** Set the serializers, Currently only one serializer is set as
! V; `* M7 z) t* n! c$ P: Q* B. o3 Z** transmitter and one serializer as receiver.! `& z2 K* s+ Z8 K. k! x/ h: v
*/
" S* V: V0 C" ~7 A o- _5 vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" n" R7 v& ~: @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 {* k( g+ c6 x! j" c* C** Configure the McASP pins 0 {$ ?6 l+ f4 t4 _6 d4 q0 \, k
** Input - Frame Sync, Clock and Serializer Rx) @* z5 k1 Q. u; M2 h
** Output - Serializer Tx is connected to the input of the codec
% z( W8 v( @8 x2 g5 ~*/3 n. J/ x, _! y3 g# N0 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); I! r! n9 F! n) `: ~5 \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ D5 d+ X% y; HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- c& y/ _5 R% W- q: ?" @
| MCASP_PIN_ACLKX
5 u$ y, U0 @; L4 u, N| MCASP_PIN_AHCLKX2 c0 k/ E/ Y9 o% Q+ P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" ?$ n" H2 C' _! x4 u7 \1 j% u# TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " @1 k2 B% b$ e$ H* Q' D
| MCASP_TX_CLKFAIL G3 r0 j5 P. h# S0 M5 F' |. C
| MCASP_TX_SYNCERROR
6 s; U3 S$ @; v2 A, z$ }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , L3 \# I. Q5 ^4 i( d6 ]
| MCASP_RX_CLKFAIL
' X7 v0 m, J6 V& U: c9 U| MCASP_RX_SYNCERROR
" {4 h# @% t/ z! U: J4 e| MCASP_RX_OVERRUN);
+ e! j2 `/ U# B6 R8 o" [' i8 H; z} static void I2SDataTxRxActivate(void)5 b8 k; ^: Q0 u) B! x5 Z
{: @: W) j9 q" r8 @% ^
/* Start the clocks */" P# v- k E7 @) z% e9 ]( \9 r9 a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ H, w; i3 e( q0 d: OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* a7 o. r \3 l- a( q6 x* I$ P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, F( P5 ^# `& kEDMA3_TRIG_MODE_EVENT);% y9 I( V: f1 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 H( R0 ] q6 x0 c% X2 O! vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* l& s9 |( t) N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 \1 M5 }1 c" h" lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 k4 R1 c- Q0 g% ], N' s1 c" {; U- owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 N D8 E8 Q# y0 l" J6 W) Z; }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ c$ U- ]1 p- y/ j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( e, ^) [' W# k% {& b}
) H4 ]. c& |8 D2 h3 |5 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' p2 f2 l. C: Q; i. O
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