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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- @0 b% C& ~* Oinput mcasp_ahclkx,
* y7 D5 Z; S2 T6 p' L2 K1 @input mcasp_aclkx,- }" _* t" X% Y
input axr0," z5 e) w. }1 A* s z2 E
$ b( X X/ e+ `$ z; Zoutput mcasp_afsr,
' {) d3 v1 B8 Zoutput mcasp_ahclkr,
0 ~, v4 `+ C: A" F" k- ?output mcasp_aclkr,
& o: o" x* m& G7 l, M" t0 Z: moutput axr1,: b. J; W# _, d/ W: r% V8 c
assign mcasp_afsr = mcasp_afsx;, ?+ r& U7 G$ }4 }3 H
assign mcasp_aclkr = mcasp_aclkx;
9 P4 g: B5 v0 C( C' [assign mcasp_ahclkr = mcasp_ahclkx;( @* d& A6 W1 h! G8 P
assign axr1 = axr0; d! W) R( z' \; {: E, B
; p' k) ~0 D/ o; ~) {6 `3 j/ A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 k5 ]0 b: v8 `static void McASPI2SConfigure(void)
' D& z4 N1 ]9 M6 F& u7 _{- a# g' n; ^8 c4 k9 y; W7 c/ g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( T4 r2 U7 y+ f3 g( N& z5 jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" V6 |9 t% d$ {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% N+ D- @0 O" |0 h! P9 Q# j$ _0 sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 p3 N+ A& i/ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, V: f& O7 h0 F% N$ ^2 @8 L$ X" d) |
MCASP_RX_MODE_DMA);
2 v5 p2 i! w3 Z1 L; ]4 S" xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% ~& E& p6 O7 ~) f! Q; n/ \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 V1 w8 G" U zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: P1 N0 t( p7 d0 L4 D, E$ RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& E6 P( X: P9 k6 T, k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 i9 e0 N1 B8 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 a. e* i5 [/ d j2 A$ ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 ^9 W8 @' G% \ j) Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ M, z. b7 H% s- ^2 UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 d" c; k% H$ Q _# j1 s* l
0x00, 0xFF); /* configure the clock for transmitter */
- ^" P0 f" ^4 {; |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 X, i1 o% K3 N' BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; z! h, R2 ~! a0 m$ f& f3 _7 b9 b5 f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, j2 a U% s) }. w9 c
0x00, 0xFF);: m+ t9 I. D% x- I& X$ R. o1 A
' i; [" [- }" v s/ w" p
/* Enable synchronization of RX and TX sections */ & L& i8 d) Y0 ]4 u& x- h- e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- N% w) B# e: ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 x; v1 Z, h2 F% ^% B- f+ `/ u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- I' E' q* A) z/ J$ y3 B0 a** Set the serializers, Currently only one serializer is set as
$ `+ ~& G; k5 ]( F** transmitter and one serializer as receiver.
. e. h# T1 N( i*/
7 T% [0 U7 G- V3 a. T$ c% lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* w) }1 t" g: s/ V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 ]! M& `* w0 [( V' T8 E
** Configure the McASP pins ' [6 Q; e0 @/ h3 O
** Input - Frame Sync, Clock and Serializer Rx* ?/ F# R. c! Q; }
** Output - Serializer Tx is connected to the input of the codec
* c5 R* x( f' y2 q( Q*/
2 j9 y$ H7 i. W; Q! EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# w4 V) ^' n. a. F% |2 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 ^- e% U1 o9 k/ j$ P$ c1 x4 J1 Q- B1 j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: d' N1 S3 n$ {" Z: h| MCASP_PIN_ACLKX
, O5 ^, P$ b' |! T! F$ h: _| MCASP_PIN_AHCLKX8 ] W- w1 I8 A/ Q7 k9 ?6 A( n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* f; e0 N" }8 ]( J: n& I/ UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . l e( }% |% {1 j2 e+ c
| MCASP_TX_CLKFAIL : o1 G/ E* f/ @
| MCASP_TX_SYNCERROR
# r: j O. N: \& x$ I) T$ B. R- `' }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * A( ~& k, h8 v. V: O5 C5 u# @" `
| MCASP_RX_CLKFAIL
, q; n A0 C1 n+ e- w7 e% h| MCASP_RX_SYNCERROR
' [* P, F# y( {! T6 G! Q| MCASP_RX_OVERRUN);
5 I6 q- v& A" O2 `4 z* i} static void I2SDataTxRxActivate(void). U- ?8 W/ a( {* _
{# e1 u6 s+ v3 D2 l8 d
/* Start the clocks */4 y9 T h3 Q, X6 x3 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ S( \9 l! w! v' v; B6 V mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 e4 r; ]/ r( ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& h* ^9 w# F! ]' d3 s+ _EDMA3_TRIG_MODE_EVENT);* d3 A% V. x9 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 b8 o$ J0 e& `1 M/ h1 G$ u( ^: qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 f/ a% F4 w& ?! `0 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ ]+ H! S& Y; S8 B) ^& M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 N# {2 J2 B+ m" Q" V) o7 {! W8 iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) @; v6 T' ?( i- i4 `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: V' K( z" O5 D$ Q/ XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ c, |# g& C8 e5 u
}
5 F6 l# X1 ?2 P4 d0 F' J( h, {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 E* m% q0 a: f
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