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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; Y+ q- z# `) Q: `
input mcasp_ahclkx,
% s3 m$ a+ |& s6 U9 V. |input mcasp_aclkx,0 I. u! ^, t# H/ Y7 \. I+ ~
input axr0,
, o# N* R& Z( D2 F) ~ e- c3 t. D. H1 d% c# a! r
output mcasp_afsr,
0 S B# u% z. }# B- W& Voutput mcasp_ahclkr,1 w# h' [1 z" _7 u
output mcasp_aclkr,
0 r9 M% t0 X7 j. b6 a; R: n$ Z+ Houtput axr1,
2 x8 Q* F6 X! f, ~ assign mcasp_afsr = mcasp_afsx;6 m& o: o: i4 M
assign mcasp_aclkr = mcasp_aclkx;; j; C' X, {9 Q) F1 h
assign mcasp_ahclkr = mcasp_ahclkx;
7 R6 v0 p9 i/ e9 q% ?# Iassign axr1 = axr0; , W$ c7 |$ a1 U3 y$ L7 J6 h
7 x5 y! f. y8 S2 J" N, o r$ {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 e+ d5 m: |. ]7 f. w* t5 wstatic void McASPI2SConfigure(void)
; ?0 n$ ~8 U N; g# u& \" C7 {# P9 A{
* ]1 Z' `: S1 X, p. eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 y9 A& S9 N, @4 d, l% T& ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- d5 q( o, {$ a2 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' M# `8 C0 ~3 l0 i1 f7 a2 j# s& mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// W$ d6 M1 ?6 J6 v) Q) O6 }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 o4 `2 W4 H7 a" AMCASP_RX_MODE_DMA);
5 p9 ?. ~5 j. D* fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- P& V$ s: a" _( y0 x3 y1 N) @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 }' \+ ^! f. A4 AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 ~0 E( k9 ?4 `, j# aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ U+ K- H* i- Z. n" y- WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. X- \+ U" p$ g* {3 y7 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: v& e# D; D' e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! E/ h! Z2 k5 \5 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 V0 n9 g% V6 ^4 }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 X, g; m5 b1 t0 \+ A0x00, 0xFF); /* configure the clock for transmitter */; ^# v% z& x0 n+ u. Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
h) Z* e4 w l3 gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! R y2 g. y( y/ Y1 p& J1 \* B9 t3 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
r2 r6 b+ p0 {5 X* O8 z0x00, 0xFF);
4 z* x; ?; r; n4 }* T- u& o7 E F3 g p; ~) E% p) r
/* Enable synchronization of RX and TX sections */
6 i1 j, G, D9 l/ \! O& O$ G$ {- {7 JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 O" t5 y4 h: m; o4 |2 m, A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& j, c' I1 B+ l6 j% h/ U' S7 B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; `$ [/ y* {" R4 H: E: q" V! X
** Set the serializers, Currently only one serializer is set as
& j" j: {( R7 {- z5 O5 X9 u** transmitter and one serializer as receiver.4 I, F6 d$ f% A5 q% |
*/
$ y5 j5 ]# P/ M. ^7 p, fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, C* i, Z1 t$ `0 j$ o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. L( j# K( a2 z) r- K
** Configure the McASP pins 9 C- z* k- E- X6 l2 y
** Input - Frame Sync, Clock and Serializer Rx% a4 Z9 \" o6 n; c9 s; M) \
** Output - Serializer Tx is connected to the input of the codec
' c1 A W' f. v+ L+ ^+ Q0 Z*/
0 ~- G- Z$ q: bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 R' b' W- P! G6 t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& T/ c+ h- V+ K& y3 ^9 X! ~6 r( NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 {* U7 _0 q& L| MCASP_PIN_ACLKX
* J3 }& A J+ B! _. X| MCASP_PIN_AHCLKX
4 j2 F5 M# V; y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; f* K$ F, j8 b1 S4 J% Y+ eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 |( i: ^" V" t3 I+ m| MCASP_TX_CLKFAIL 3 U* h) D" `3 [0 }8 h) O# d' F
| MCASP_TX_SYNCERROR7 l# j" O& y5 H( _( c2 {, x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- @% ^- ?8 Q" J# s( ~| MCASP_RX_CLKFAIL& R1 P1 `4 f7 J/ d* `6 F% n' W
| MCASP_RX_SYNCERROR . M! m. @( Y" k+ t: f3 i$ p2 a
| MCASP_RX_OVERRUN);+ ]4 P) ?0 T- P7 K$ Q# t: x
} static void I2SDataTxRxActivate(void)/ Z# E0 d; O* A! T8 Z
{& b* q/ v* K& `- M
/* Start the clocks */# X2 c4 Q3 M* j& g6 W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) P$ t6 p# N$ z h _ y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 {5 A! m+ e: |" I: R% L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: ]2 d* r6 S- H" y7 y( D2 b, u/ T
EDMA3_TRIG_MODE_EVENT);! B$ v3 ?6 b0 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* H( W5 a3 g E" GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
z$ V" ?& Y# N# q. u5 r, DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 N/ ?; Z3 c5 y& H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* y! E8 w+ x1 Y ]- Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% t2 E7 k1 b7 I& [2 r1 J. S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& A, I: Z* T8 F0 C8 p, M; h9 g8 U5 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ {& t; d1 N) R; Z. ^+ ]} 5 S+ N/ M. a, e6 t0 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " K* ]! R ]9 k3 a$ i
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