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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, m) A4 u/ I# D5 Q* N
input mcasp_ahclkx,9 L0 P( P& X, l# Z
input mcasp_aclkx,6 N/ C1 f! A1 z( u( J: L; R. }8 g7 S
input axr0,4 ~* _0 ], Y& s2 f- V
+ U7 s# M0 Q5 Q% s" x* routput mcasp_afsr,: Q0 N% L3 Z/ G1 O
output mcasp_ahclkr," T# Q8 c J2 H' @: j: I7 z+ L
output mcasp_aclkr,
( h$ l, p* I$ b" V7 V( P5 x* doutput axr1,
, J: D1 \* r7 L% M. ?& e n assign mcasp_afsr = mcasp_afsx;
" {# a" i9 |; ]assign mcasp_aclkr = mcasp_aclkx;/ I0 V: H# E/ D7 H2 g0 o( t
assign mcasp_ahclkr = mcasp_ahclkx;5 A1 j7 [" I& c T- m7 R/ b
assign axr1 = axr0; % U+ U4 ?* p$ F9 x
8 O' E3 {4 I3 {4 A2 D8 t* n$ K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 P; r$ ^6 d1 e- l+ ostatic void McASPI2SConfigure(void)
, W ]/ h; l S" e4 G' A- @{
, H$ s" A0 m$ B$ TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! P1 u4 c$ S/ Z# q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: O" A$ K1 E" V1 `1 ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: w; S8 a. i; H# `& D: F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: E; c* H+ F2 f6 d2 t# y! |/ L3 b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 `0 M8 {1 `( w' L# M
MCASP_RX_MODE_DMA);: d/ M5 r( @& h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 t0 G* B6 I" b/ m7 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 ~+ ~# M6 s4 L$ J7 t* A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ?! G. D1 Y* S D( C1 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 s5 a( c+ }- r. }# }; o. P5 b2 L: g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 W# k& _5 p0 a% B4 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* n* N& d7 V% J) q4 H' @: u# CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" ?# [; f7 C- z: l' n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . c) T- Y# X$ s& d7 o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( o7 z& \9 e7 O& d* A0 H
0x00, 0xFF); /* configure the clock for transmitter */2 Q. { [5 V* V, H* P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 ]0 p/ _' x4 i' U1 h' S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 I9 J) p2 ^0 F8 y0 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; J4 `6 k: A# D0 w
0x00, 0xFF);; o6 ?, j5 I' N9 G+ l9 H8 f
) B2 n- k. @- ?% j2 `( _/ e9 S4 t
/* Enable synchronization of RX and TX sections */ P0 ~. _2 m t( W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! r# i1 u: h8 Z- g& f: i7 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 i0 J/ k3 i7 w. z M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. t8 l5 Y3 u q** Set the serializers, Currently only one serializer is set as
+ }, u. f5 {- [+ M% p f' z# |! c** transmitter and one serializer as receiver.8 N5 d' g! l/ g) w% Y* z! D/ E1 \. I# I
*/
* W9 P1 E4 X; [% l8 O/ U* A3 X ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, r# Y6 Y- S( [: u3 JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# X5 d' R' W2 @5 o& L; h2 W5 R
** Configure the McASP pins n) E$ q+ G' g1 @: X7 G% A( o. Q
** Input - Frame Sync, Clock and Serializer Rx' `1 y0 i/ D- ~% C8 u
** Output - Serializer Tx is connected to the input of the codec $ k' w( u+ P% O( G( p7 r+ ~
*/
7 M# H( B, Z1 n+ {1 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) ^5 V2 Y6 y5 t* x! M* j- H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 @ ~6 |4 Z( J6 n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 O( \! \" x. @$ O9 \
| MCASP_PIN_ACLKX' ^0 A7 o h1 J
| MCASP_PIN_AHCLKX
2 F0 t) H3 P3 Q7 O' E. Y) |! ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; _! }) K: W$ u; ~( M3 T* W2 m i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 A7 P% Y B8 v$ V' D9 C. D' z3 Y$ N| MCASP_TX_CLKFAIL # a; J3 f+ I) \$ Y, E
| MCASP_TX_SYNCERROR
1 k0 L) ~" z' J; d) i! Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 Q' E( V2 D& U& i
| MCASP_RX_CLKFAIL
Z O/ G5 x* {. {6 _9 ?| MCASP_RX_SYNCERROR / J( v) y- K$ B6 ?, K
| MCASP_RX_OVERRUN);
% J9 _; x i8 c} static void I2SDataTxRxActivate(void)8 ^5 q% c/ i `5 J/ V$ `9 D
{- p3 |2 N( s5 J* ?$ H6 D8 L
/* Start the clocks */
6 ]4 M, ~, c$ O1 k1 X( N7 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, y) U3 T& G) f* t$ ]* T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 [2 g! g# P/ c9 u- H* d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& H3 K0 Z; ?* d: h3 @EDMA3_TRIG_MODE_EVENT);
% l y: b, N" x$ t6 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 ^2 \2 Q# R ?' g( E, QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ U7 \0 O* t" |; b& W j1 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: g" d* n _' S! }5 b3 N% GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
T4 m2 @0 N( ]( e$ d6 z4 ?7 L' Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 D. L# Q8 u0 @ U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% i/ _, A7 i" Z1 k5 r7 QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 Y! U" Z# m7 e- f0 ~3 f3 Q}
7 s. K6 _ N3 D) L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + i" c" f/ I, V, {& h8 W6 H
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