|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ @, @8 C2 T. i# c
input mcasp_ahclkx,# B2 Z4 O' I! G% f# P* v
input mcasp_aclkx,
0 f1 n+ c8 o$ {0 U( T6 Vinput axr0,
: Z3 S) k% U" r3 u, M! i4 ~7 q* s6 g0 A% i; \
output mcasp_afsr,3 n9 D _7 j1 @4 H1 D( Y+ X
output mcasp_ahclkr,- A: W2 a# m" d( }+ {
output mcasp_aclkr,, l) F/ M' b: U0 @! L9 v. U* f
output axr1,
" y9 T9 w) {; W1 r assign mcasp_afsr = mcasp_afsx;
, k0 f) i% e# p" Sassign mcasp_aclkr = mcasp_aclkx;7 i* e/ b$ ~ Y S: {
assign mcasp_ahclkr = mcasp_ahclkx;) J1 v9 Y3 C# H7 d! H6 \+ _6 z
assign axr1 = axr0; ( |* c, {% {- [2 f0 f$ y- I
! k( |# F8 H7 L9 X" V; F" n; u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ x, ?( r1 W5 d( S sstatic void McASPI2SConfigure(void)
; a, Y% w9 J) X' b. a! U& j{+ O! X, M) Z3 [+ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 _& y7 \0 V. q4 A. {9 K5 O- G. OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' K% v" ?7 p, t# a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; X# j9 k4 e/ k4 J6 G1 U1 N1 t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ [2 C2 t* e3 b \% |9 f @" ~$ fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 W6 \" M( G2 H' B4 x* m
MCASP_RX_MODE_DMA);
Z" G6 P+ _" J7 s5 O& XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# q8 P" i6 C; V( e' o+ n* A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 N5 { ]/ U6 p- a) K# Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 E/ l" h' K8 C& v8 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 R9 |& E0 F) [( K' r) ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! f# u3 X3 Y6 x8 g3 `: RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( ]7 Y1 {9 k5 o L7 g: m8 p& f8 R M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: i- z. L% d, H: F0 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , |4 s4 K* f1 F6 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 g0 |% m% S3 B0 f0x00, 0xFF); /* configure the clock for transmitter */
1 I& u4 C. C' cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& W# N* t! X( j! O4 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " S' Z Z2 w# Y& y7 V- C# M- U- K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. l& M5 Q, p) S% J* ?: n
0x00, 0xFF);
' v4 T5 D: S1 p, g( c( h* ]3 I, r" I& R: i+ e5 l7 a
/* Enable synchronization of RX and TX sections */
; x. T& m: }1 t% x8 R$ L1 A# ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 c$ c( E! ~1 ~ B9 g3 z1 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); H- {# c' `* i0 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: y" o0 O' x% D2 c** Set the serializers, Currently only one serializer is set as, g( U5 y/ u6 n3 c; r" l
** transmitter and one serializer as receiver.
6 D( W& S, w* y; _*// o0 \' m1 H* M+ i, u: K- c8 w# y$ ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. ?* p1 S+ h, L9 r1 E- { u' Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! _* V }$ a1 }0 Q" Z** Configure the McASP pins $ O( _, k! h! }- `% e
** Input - Frame Sync, Clock and Serializer Rx
& |" j a0 s+ @/ ^# b- d* V5 i8 @** Output - Serializer Tx is connected to the input of the codec 4 t( d) a2 R4 h6 R1 E: j
*/
; ]: t# j5 |1 {9 t4 y6 R- SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 F' A8 ?3 k1 h, l+ F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
C. @6 }/ l2 |6 e9 \% Y* j/ R: mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) I" a. F h& |# E
| MCASP_PIN_ACLKX+ h1 F% h! B$ Z% x* P' g% @$ Y
| MCASP_PIN_AHCLKX/ p. S; K: P7 F7 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- [- c( {# O/ v1 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 A) G' U2 q& S9 }! v. l| MCASP_TX_CLKFAIL . }! T) L9 U. b5 ?8 ?
| MCASP_TX_SYNCERROR
3 I6 l7 L* [! P/ X7 b. j' [) ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 W, V+ k* c" j4 d| MCASP_RX_CLKFAIL
; d5 f* L1 k% N W3 ]" [0 o| MCASP_RX_SYNCERROR / ~6 A" B) Z( R! n l* ?
| MCASP_RX_OVERRUN);! L, F( u# K9 v0 q4 b/ }
} static void I2SDataTxRxActivate(void)
5 K; P% T" e2 `3 l8 K/ E3 U$ u{3 k1 t4 R' h% ?7 B4 i- i, _4 A
/* Start the clocks */" L% C# T" v- Z4 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; j4 o/ W: u2 V1 k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 U9 P. Z. N" K" FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 A% v9 y; g- s& cEDMA3_TRIG_MODE_EVENT);
- A% ]* K7 Z6 f6 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 I( w+ S. L3 s; a6 H0 ?! qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ O8 L9 E0 Z% M- [8 Q; ~4 v0 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- R# [9 _' r n: [2 o" S" }- ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' v. c1 X. ^5 ^6 |8 |# A- Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# |9 g. n6 T3 ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ w5 H( u; T/ L# u9 {. bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 P0 w* f# I) x" J} * _+ X# D8 ~4 K; j9 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; j' @+ B# R- [" c
|