我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! E# O$ U5 Q2 o, V% winput mcasp_ahclkx,
/ T! Z% g/ \2 a9 y6 Linput mcasp_aclkx,
) q. K& |. u1 M( zinput axr0,) x+ \1 j7 A+ f0 y
: O6 o4 b& V% l8 A7 m
output mcasp_afsr,
( r; C' X8 j/ j* P4 |output mcasp_ahclkr,
+ i6 S: j! O. {3 I9 A; b: _output mcasp_aclkr,0 V3 c& |- X' T; o. u* J$ P% ]
output axr1,' @7 L, r) c7 ]3 f, |) m1 x" u
assign mcasp_afsr = mcasp_afsx;( X0 ?7 X7 l' T) {6 a/ F4 I: @5 @4 r
assign mcasp_aclkr = mcasp_aclkx;. ~- t! h8 Y, e1 X6 s4 e
assign mcasp_ahclkr = mcasp_ahclkx;& d/ Z; t. N0 W s+ N' N8 x7 ^
assign axr1 = axr0; 2 J* p7 `/ }. M
T8 k+ \ Q0 Z+ }; r" p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ B2 u/ C2 o9 E* ~/ D0 P" kstatic void McASPI2SConfigure(void)
9 B- ~9 c/ R1 ?9 Y6 t! Z/ |8 |{
6 Q" k, G9 N) z; I' eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! y0 F4 g( y. t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 `/ t# ]4 J! K* pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
g: L/ F% g# Y v* ?4 U8 zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. {7 M7 e0 Y j7 y s' X# p5 dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, \ O: U1 v5 xMCASP_RX_MODE_DMA);0 u7 @, l4 w& O4 Z* s$ r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 V& b1 E: w8 J" K' T7 e3 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; b$ X6 W$ p9 _& V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - H# p* } \7 c0 ]8 y0 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, {+ d/ A/ g/ w: [# y, qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% c! F2 q$ Y$ ~% a$ B% R- wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* g8 N& K0 `. f8 i/ E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ J4 s7 x! m* N3 b: {8 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 b. O. M) k+ W5 z* V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, o/ e4 m3 g+ _' o! @, h- Q0x00, 0xFF); /* configure the clock for transmitter */
4 a* y1 k, i: j: G- j8 w8 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% A4 Q6 r1 c' x! h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" L1 o0 i4 n( }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ n' c& w% V$ }/ U* ?
0x00, 0xFF);
- i; n [8 h, ] a! u5 ]2 J3 z; O& D6 }2 N$ [1 L3 e% B
/* Enable synchronization of RX and TX sections */ 0 W; j* Q, {& z+ t6 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- U5 l: M% x' [. v6 w' `. PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' |/ t. l) \; [5 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ S" ?8 {: C3 ^! v, {4 w( B** Set the serializers, Currently only one serializer is set as3 C8 M# n0 F% D0 d0 c# [
** transmitter and one serializer as receiver.
) F5 P6 T7 G" K4 }+ S*/! J$ v( v. d5 \. ]+ F! R5 s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 @! y' C$ a* B( l$ U% Q: B SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 u: s6 _+ I" O9 |) S0 @** Configure the McASP pins 3 a. n5 z7 z- b1 G& e( z1 O
** Input - Frame Sync, Clock and Serializer Rx( }& q7 c7 I P
** Output - Serializer Tx is connected to the input of the codec 6 c; D- m" z P; ~
*/4 v1 M# z% I6 i1 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. H8 F0 p3 Q( tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& {, J" P" ?8 C% u; x9 f6 aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 I9 E) e! o+ ^6 ]8 j% }& e| MCASP_PIN_ACLKX
# z$ t' J0 j) i# a| MCASP_PIN_AHCLKX
% Q6 x* _: }5 K$ z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ u" L% D' i7 m6 g8 b9 \5 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& K* y' L+ O% o5 U| MCASP_TX_CLKFAIL , X3 O2 G0 d9 x0 h
| MCASP_TX_SYNCERROR
7 V) s9 |( b' A+ H" Z- ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 Y3 F+ {9 m6 W, f7 ]| MCASP_RX_CLKFAIL
' s1 B( W, e; g R% |& Q| MCASP_RX_SYNCERROR
6 E8 p9 P' `' T6 D) r8 `! h3 i1 b: m2 i| MCASP_RX_OVERRUN);
9 z# c( a% U' u$ j; K} static void I2SDataTxRxActivate(void)
# Z7 }; K b; R4 Q5 t{
6 ?: N7 u% b) }" g/* Start the clocks */" `4 M* l# O" T& p* _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' L$ n+ \" r% y$ l% C, y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ Z9 r3 j. i6 E; H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 F5 ?) J9 z3 V' `7 O) o1 d
EDMA3_TRIG_MODE_EVENT);
! I8 C7 L6 x7 a& E2 ?! p# WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : K& o% C3 `2 C3 Q" G. R# ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( Y6 A9 i) J: C# S) l9 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); v9 J/ |& f1 h7 a- @% W' [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// }, {/ S0 C; _3 w. p( |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" Z6 J: x8 C/ X+ } |$ R* |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 j$ `! Z9 U- R7 W) h4 I2 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 x" G/ X' D7 q% d} 3 L8 C) n5 _; m8 o4 |; E3 o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- x6 P, F! E; W# W2 H |