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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- [9 @0 N2 h9 ?) W. |) Jinput mcasp_ahclkx,
5 U# b6 C% f' U8 p4 ^+ zinput mcasp_aclkx,3 K; c6 e, J6 n! ]) S/ u
input axr0,
8 X" ?" p8 u8 O; F3 _5 T' }
6 c$ j" T& [( U1 d8 g) J7 d1 Foutput mcasp_afsr,
4 e4 ]; O7 }# O/ Q0 qoutput mcasp_ahclkr,0 u/ s+ O7 s5 j0 c7 k, o/ J5 V
output mcasp_aclkr,
. F2 V% ]2 Q. T: goutput axr1,
: ~$ h" l" x; t# Q7 x. C. m H3 } assign mcasp_afsr = mcasp_afsx;1 `$ L! S6 l, i: o
assign mcasp_aclkr = mcasp_aclkx;( C" x" x$ ?" R# O% B% p: ?$ R
assign mcasp_ahclkr = mcasp_ahclkx;
: |- I5 I; k6 h+ f* k z1 p+ Fassign axr1 = axr0; 4 h% ]( M, V; y. B' Y
% m8 D( G+ R+ K; e" O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # G( A) e# e3 H7 m L( e
static void McASPI2SConfigure(void)3 d# o: M6 r: h
{) Y* ~& D. W2 q, H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ b# t( m7 W$ L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, r8 L7 Y) `# ]9 g" X Z! ^! j3 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' T8 ]8 c5 @' l" r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; O5 t/ O4 U# S9 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: b0 D6 K6 O9 K. f
MCASP_RX_MODE_DMA);
+ @; N1 B, x9 p( ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ d, H- @& j8 J h- G$ [0 X# [7 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 U! e% |$ V' k- N% {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 _$ _- ~2 T5 Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ B# e9 b) ?, M. D" j4 c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! a1 m9 v: M& u8 I1 d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; F1 s' f5 U' o, v6 @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, t. Z$ N; }0 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 A0 T% ^+ j- J6 h% B( Q/ S BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 z; _9 Z9 E. _, V& X* }0x00, 0xFF); /* configure the clock for transmitter */8 B0 M4 ]3 U- m6 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
W: |% N `( H& f& a! ~# `; W' H7 [& JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 x9 v0 L8 v7 q* h: F# |1 k1 b4 \* VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( P& i- t' O& E" @* [0x00, 0xFF);
' I, V' I; Y4 v* ^ |9 `5 ?9 e: s( h' Y% s
/* Enable synchronization of RX and TX sections */ & t4 _4 s/ H% S- G( y3 f! o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- j B" d. q' K) d" p f) C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 {- v$ S0 [$ h& ~9 Q3 m- uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( j; \8 i$ g9 d
** Set the serializers, Currently only one serializer is set as h0 u! g( Z* K* ?; A8 u8 x; ]! W/ F$ N
** transmitter and one serializer as receiver.& f' ?* ^7 n6 O- m8 M9 [
*/- h$ ?& Z+ F6 r1 a5 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 S7 g$ m6 L f: yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% M% k) E1 V: @
** Configure the McASP pins . G6 n) V4 G% C Y5 g
** Input - Frame Sync, Clock and Serializer Rx
" j K" L6 a. ?8 B: m$ [" a** Output - Serializer Tx is connected to the input of the codec ) g9 V9 V6 h0 R+ z& p5 q& N/ t
*/3 C7 ^" `& e3 _6 m2 W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: P6 s' b% V4 `6 u" C; |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ M( g6 m7 n8 E( I d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 ?" i) d1 ~" f; c2 F0 h| MCASP_PIN_ACLKX
8 a! b, U& N8 E$ R4 }1 b% C| MCASP_PIN_AHCLKX, x$ w6 r- i3 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ ]* } s" z! ]- nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' C( \1 m1 W6 i| MCASP_TX_CLKFAIL 5 S! [9 s+ ^6 c' R6 j o( N5 T% m
| MCASP_TX_SYNCERROR
# v2 o3 v; T; Q/ R* g" n$ ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 J/ r8 W* L; o| MCASP_RX_CLKFAIL+ m8 _& X' y5 o2 O- c( m
| MCASP_RX_SYNCERROR
9 o3 B- w* A% t| MCASP_RX_OVERRUN);
1 x* R) X8 o; Z M! u/ [} static void I2SDataTxRxActivate(void)4 u5 a# t+ ^0 X
{
+ o( Y3 ]& S0 G" A* I9 T" g/* Start the clocks */2 }* @& p- a$ t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; {% _+ `3 t; V* L" c$ SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( P" @2 t. l0 S) R( _7 H% AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 q: g, V5 x# }9 k$ ~9 a1 b/ nEDMA3_TRIG_MODE_EVENT);% _; ~3 p/ I1 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* x' M( ?5 ~& K0 bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ |0 v$ C" j. V1 X3 n0 N) C& d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, J$ V: X& L8 v) j3 i8 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# V' j, e- }' H; T( I$ G" |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 S9 U& n6 H4 i7 j h% ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 Z$ D% | f5 z4 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 B7 ?: Y6 U8 o. j9 F3 _5 r
} 6 r( m1 T8 ~$ g& q T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 S* u4 W9 e1 x8 K: h- p; V
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