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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! R$ G/ {1 I! q* Tinput mcasp_ahclkx,
- G6 Y( n8 I5 Qinput mcasp_aclkx,5 {$ s! _3 x8 p" E$ B7 I
input axr0,0 A2 s9 L9 G8 S$ g
: b. ^6 U' F2 d; joutput mcasp_afsr,
. \# V1 x: q+ l/ aoutput mcasp_ahclkr,5 m- X, }! b4 B5 G
output mcasp_aclkr,
& ]6 g, o4 K, G. c& @! Routput axr1,
1 F- H# g) A) k" f2 g assign mcasp_afsr = mcasp_afsx;
7 J! ^+ W' c0 v6 y* Oassign mcasp_aclkr = mcasp_aclkx;0 G# L7 i- k6 `$ j8 B$ l
assign mcasp_ahclkr = mcasp_ahclkx;
7 E' Z8 O) q9 T- r1 _assign axr1 = axr0;
, W. ^) j) J G3 F' G
+ W( `7 m7 O# H) X5 b! \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 |! p/ C$ ~7 o2 ^( W2 kstatic void McASPI2SConfigure(void)
3 N* c9 W! k* u, a2 _{$ g; y; u8 Y' j4 C4 x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: b+ _0 F/ E$ a1 I& E' d2 [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 @4 c2 x, O( X8 \4 ?/ F# l5 p. P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) B: B' J& l }" J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- c; G" X* ]5 U9 X1 a: y3 B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. Z& z+ E" E( r* P' J, wMCASP_RX_MODE_DMA);
% Q5 E% E; T; O8 Z9 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 t; k3 [( A, R! @! e1 x7 x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
j, d6 M) x/ S! _/ d% O& {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ Y0 \9 Q; T1 G- [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( ]6 E4 Q+ Y' r( u/ d; s9 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ I! z1 R v5 \3 X+ O5 B. {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 g2 A# b$ D" \6 T" L+ J; H/ g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. i# ]& K& G3 o6 F# ?# a7 `5 j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 T7 L6 l) [! G& d/ W$ d4 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. d T1 F6 N6 k0 K. ?0x00, 0xFF); /* configure the clock for transmitter */
+ ?5 H5 h- V$ j1 Y# bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 ?8 T/ _4 {0 E) I* T$ aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * }4 @ h3 G4 n6 Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 y) w3 z1 ?, B# C+ }8 |" i
0x00, 0xFF);: @' U& b: u1 x& b
4 Z( `! ?$ }$ y v: w% @& N
/* Enable synchronization of RX and TX sections */ ! A$ O3 }( ~6 I# L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! k- C/ ^ c2 X& y+ w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ f3 T, Z. O$ |7 W6 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, @, W6 h* B2 `, W) b
** Set the serializers, Currently only one serializer is set as* d' s4 p/ J# c9 ?0 Q) J, n, ]
** transmitter and one serializer as receiver.
. z( C3 Q) i0 |5 } e*/
( h/ [4 w7 @! E v G( a$ \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ h% k1 h# @5 M# Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& a3 g+ E; o* t# `$ S% N** Configure the McASP pins - B; r( R' q, ?% K% z J' N
** Input - Frame Sync, Clock and Serializer Rx
5 `! q9 ~ l2 i% O9 X5 u+ i Z& Y** Output - Serializer Tx is connected to the input of the codec " x( L- V9 J7 P
*/6 I6 I G* @0 ]* P: M$ A1 R! O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 {( C) d8 ~+ _" Q6 `( aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 a8 ^; q5 g$ K- W3 v3 CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 T5 D* S* N+ V- G: D! r| MCASP_PIN_ACLKX
' ]3 j3 N6 f3 N| MCASP_PIN_AHCLKX7 l$ {& O9 V3 [, Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# [1 B' R9 C6 j/ P8 `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 N, Y0 F1 M, I: j+ k, d| MCASP_TX_CLKFAIL
& U8 Z1 Y+ X* s$ f| MCASP_TX_SYNCERROR% T$ a5 K0 |4 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + t; w1 Q- d8 {/ s3 c
| MCASP_RX_CLKFAIL2 c9 C4 ~5 A0 v7 {0 e
| MCASP_RX_SYNCERROR
# R" a/ j% N* g, `% L, n| MCASP_RX_OVERRUN);; J/ X. k+ E; `9 v8 A
} static void I2SDataTxRxActivate(void). {( K6 C c" r; F- q
{
/ d1 \0 G" H; m9 R4 `. |0 V/* Start the clocks */7 I& [" J; Y, ?! H! I& l; a+ d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 p: {7 ?7 `; w; Y; _$ X( j% OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ Q, b' m0 i; W5 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
d! r0 u; g# \+ {& AEDMA3_TRIG_MODE_EVENT); Z7 U4 Z- A% \# K) @& Y. _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: M+ m2 }% A$ R9 T" rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 y# B' s! C& |: m, p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( Q! G! k% f: o% r2 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' H+ o- G* h: R. M# O9 Y/ u( q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 ?# D' G" r! p3 h2 g' AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: s# I# w8 C0 u: {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" k4 Y& C4 k5 _) F/ f& t9 r}
$ [3 j1 U* Z5 E) ]: `6 @: l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
l1 J7 j; [+ ~: J* R% p4 Z& t! T |