MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
1 _) k- _2 ^' q  Winput axr0,
5 S) Y- a( b- }2 B9 |. }* m- S
1 f4 f0 h; p- _, c" c3 Eoutput mcasp_afsr,
. ~) D& V9 d' soutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

6 ]1 \9 Q) m/ @  F4 u

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

& a5 s- N' H5 N- R% i

static void McASPI2SConfigure(void)
# }1 J" Y) \7 a1 s- K{
5 m: m& S+ s/ ?3 u9 eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; @9 A$ t, D! y2 z* j3 A. MMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
( E, k( H4 J! Y9 s' mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
1 i8 N) _( {6 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 v) t' r/ o5 u6 J. o; p3 x; C( L( xMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# @% S# f0 F/ r! WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
2 G3 Z6 e. k+ T( h& {) F8 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) g/ \/ W* L: cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 o1 \$ |& \' P: @6 pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 o$ g, v1 q/ b2 d' w0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 @0 ?/ W8 g6 G/ _8 f! cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
  ^& C# j# {( H! V# m% g7 h& H
5 \$ ]" j3 t* V% }& A' `5 i/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
- {- ^3 B# `8 V$ J- FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 l) H3 g% P9 D8 n3 VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
) Y8 ^6 }# E# R0 m' C1 F, W** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
+ t, c  q7 f: }3 S7 ~** Output - Serializer Tx is connected to the input of the codec
( z' S# w5 P$ c; E3 f6 s*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, e# G8 U) W+ P( S/ u! sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% a  h6 O+ F4 ]- M! ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 U: l5 D; d7 T: @! H| MCASP_PIN_ACLKX
& T9 b) B; l  }: R! f& D! a0 j1 c9 a| MCASP_PIN_AHCLKX
, @+ U* I8 q* u5 q| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
0 G' g- }+ {, ~7 ?% T9 T' ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 }2 y, w3 ^7 E: _, }| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
/ G' K* L( }, U4 v% x; q| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 @, r+ L1 X1 F+ _; G6 o, A9 e* || MCASP_RX_CLKFAIL
( `* K2 C3 z4 t! u  T| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
  q# N+ Y2 c/ L5 R( `3 |}

static void I2SDataTxRxActivate(void)
{
6 j- Y% u6 G4 I& T* J/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% \6 m3 `1 x8 `8 l; r/ sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
& c3 o' i7 r. q$ r/ [8 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
, \3 B$ ^# k1 x' j5 T. Y/ L, _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
: ?, {3 P! |/ [9 x) ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
' I& X1 p) Z4 }: J, y/ T4 }. Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 \/ G" l6 f+ T* ^) v+ P$ qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

! C8 j+ l, O; }$ ~: n