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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% J/ |) f! I9 J Dinput mcasp_ahclkx,: H$ ~) E8 F1 I/ |3 z0 Q
input mcasp_aclkx,) |0 ~( ^9 I% k8 s5 ~
input axr0,$ A5 f1 }$ Z9 S8 k$ @0 k; y& L% r
; m# w. X8 |$ z1 v. H% y3 coutput mcasp_afsr,1 `* K6 w" C& t/ ~: F& Q; |
output mcasp_ahclkr," ]7 d1 l) s. e3 v" W9 h
output mcasp_aclkr,; J0 s& Z0 r6 U6 @8 K$ t1 k( k
output axr1,
7 ?$ E: h$ F- \0 G assign mcasp_afsr = mcasp_afsx;
: k5 Y, a2 J4 S7 R7 R& a0 Gassign mcasp_aclkr = mcasp_aclkx;
/ V3 R( m! g, O5 o0 J5 jassign mcasp_ahclkr = mcasp_ahclkx;
5 ?& M8 F! ^: V" b5 I+ w# Jassign axr1 = axr0;
0 z' _: d+ Y, t' I) L1 T7 J& _; d* R! g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- {* b" c. D" O. ostatic void McASPI2SConfigure(void)
: M( R! f0 ]& q{
; _, M l' u# X0 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ i, D! x6 m& w4 UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: B! Z2 r K1 o! Q- y2 Z" o1 c7 ^6 X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 J9 H( i$ \# z) `5 KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' [# @& N. ]- F' O( N3 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ u/ y! ]: r8 H9 m9 S4 DMCASP_RX_MODE_DMA);. t9 R6 g7 R% \6 Z! _, c# S+ @9 A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 _0 I7 P$ z$ _5 R. J- C+ b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ t$ s2 j3 w) g+ R/ r- v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 o% o3 o1 B& L9 ^7 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# y3 ~+ {. x1 ~* E# RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 F0 I4 w5 `7 p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# i t: i! y2 Q# n5 V J YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ a6 x1 l. p+ Y; ]" h5 ]' }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' P+ R) v) N f0 Y* D4 s2 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! J7 q" p+ g5 R5 ]4 ?8 z7 r; w0x00, 0xFF); /* configure the clock for transmitter */5 n$ u0 s) m# [' E$ N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; [* v e% v4 OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 ]7 V2 P: J3 ~) B. L9 ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 Q- Z1 Q7 L C% g0x00, 0xFF);
8 T4 Z% g1 a7 n. e6 q$ E q+ |, G9 a: R& K8 [& u) J
/* Enable synchronization of RX and TX sections */
5 n' D8 B3 q7 b6 f- iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 k, l6 O- E) R% k9 e' wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ n i7 ]1 e. @- a8 |7 G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! t9 X) V1 z+ `5 y** Set the serializers, Currently only one serializer is set as
2 c" x+ z* O; L( F2 H** transmitter and one serializer as receiver.8 n, s$ d2 O1 {2 C
*/
# }. n' C5 Q \! s9 c, eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. [* j( U' C4 z! [$ a. N& H8 h% c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 o8 i7 T) y; W** Configure the McASP pins . f, g: |3 @5 J! F. |
** Input - Frame Sync, Clock and Serializer Rx0 V. @% C( a% G N2 G+ ~
** Output - Serializer Tx is connected to the input of the codec
, Z# C* o* d( p8 z* m, T*/4 w5 ~; Z1 F" M- t6 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ F9 ]3 ^ ]0 L$ U! e4 H) PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 U7 D4 a5 u% k A& z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 E2 ^8 Z d" ~1 S| MCASP_PIN_ACLKX
* E1 m5 t- w# v7 T6 \4 o. }. y| MCASP_PIN_AHCLKX
/ a6 m' ?5 v' n, M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 h& o* k- F+ T9 `! e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 e0 R1 P" N& g7 o1 q, l2 ]
| MCASP_TX_CLKFAIL ' c& W- z0 w9 E }2 n' u- o3 S# ?
| MCASP_TX_SYNCERROR+ P; C) [/ _3 E. y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! L' ^2 Q& c3 p& v3 D| MCASP_RX_CLKFAIL/ A$ m7 ?& s- i/ ?3 k" K6 w& U
| MCASP_RX_SYNCERROR
$ l" o+ g: v/ H| MCASP_RX_OVERRUN);
8 q* ?5 [% T& R0 v: a6 H5 M/ t} static void I2SDataTxRxActivate(void)
- F" \$ c4 E/ J8 N1 F! O{
2 P# M+ X) X& Y& q6 x9 o/* Start the clocks */ Q4 }9 x j0 l) t8 z ]) n1 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ j+ M$ ?8 b& t/ BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 i- H& W0 r% b0 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' v9 ?* l, L% V8 e0 QEDMA3_TRIG_MODE_EVENT);! l( m( f* p5 o! {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " }* V4 R6 H6 t5 {$ T( b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. I; X$ f0 v. \1 j7 m4 WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ X* H2 l7 F2 E! AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 v* e8 d. E# u0 A, c$ Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 E$ I, z; f+ b/ E, }2 I3 D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& i. R+ [( c0 c0 ? p6 QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) ^ k; d8 y: {8 h9 w} 6 T4 f! U; d' D' @( I) `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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