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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," G9 M4 @# d! i" W% p, g
input mcasp_ahclkx,
: W. Y7 y$ Q% Z# e7 ~input mcasp_aclkx,
& p/ w+ D( G& \ h6 ?input axr0,7 }8 A, j3 t/ k; ~& N
1 K2 r9 x2 ^; p; A5 D! h8 n" S
output mcasp_afsr,5 x; L" Q" j, W- D: b: ]
output mcasp_ahclkr,
; c5 B) j- b5 w! F( h& Z# Youtput mcasp_aclkr,
0 {* a# t/ `9 f) f0 \$ Q$ c% @output axr1,6 }3 l3 n- ~+ s
assign mcasp_afsr = mcasp_afsx;' l$ a0 Q0 L! M }3 O/ E$ i
assign mcasp_aclkr = mcasp_aclkx;
% D2 j# ?" t8 Nassign mcasp_ahclkr = mcasp_ahclkx;" b9 S2 v4 h8 _5 j6 B
assign axr1 = axr0; : V) I; X/ _# |. q6 x
* f9 c& N2 ^8 Q0 O2 F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & `7 F, T2 i, |6 D( d! z- E) p
static void McASPI2SConfigure(void)
8 V S$ {& c" a8 f* _9 k- C& d, _* ^{
- |6 l' o& {" C4 tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ c+ W8 v$ d% WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 U1 Y" K1 z/ _# b h* l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 f2 C+ K0 G" V _+ `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 ?1 i0 H: _* _. o+ ?9 D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: n& M# O; m' c8 AMCASP_RX_MODE_DMA);
: t5 L9 ~; r1 R8 u: qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% q& A' Q' ]" `2 X7 G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& P2 S$ s, O. @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- b h" J8 K/ q' v3 R/ gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; x+ u4 g3 L4 j. u: I3 h. B0 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 x( i: F; e7 a% \5 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' j/ f4 [5 W1 U3 }. z, tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* v. V4 h4 d) F c, b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- E2 }) e. |; [+ [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" a( H3 z, @# b' c$ J/ A0x00, 0xFF); /* configure the clock for transmitter */
8 C4 o# \% L5 ?& j8 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, s" K7 a O6 X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ `3 c3 I% X5 f" b' O& GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 t, J8 Q" m$ k& S4 |, j
0x00, 0xFF);4 o# w) @. ? y% o! G$ w7 D
1 N; I: q, e7 N5 p4 J" B/* Enable synchronization of RX and TX sections */ 1 v" k1 }* V5 P" G5 ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) R7 t8 i2 x( l+ s0 m% | h- ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 G6 x r. R# S* q- q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 E7 F2 K8 L4 }$ m8 k" T** Set the serializers, Currently only one serializer is set as
; |7 w+ v+ _2 T( a& u3 J3 V9 V** transmitter and one serializer as receiver.$ i( D, e- T# Q5 \ G/ k- y$ s* s/ Q& h
*/
/ R1 g# Z/ q) L& J( N' AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- R/ d3 ?/ a: f( x7 q- NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' d: h& o4 y; F# d
** Configure the McASP pins ; U& j$ c4 K+ ~
** Input - Frame Sync, Clock and Serializer Rx
; _6 l/ F Q1 y1 l0 I** Output - Serializer Tx is connected to the input of the codec
# a5 j7 u R1 P- v; @1 Y H1 i+ q*/ p% j- i5 U3 y3 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); s4 G' M8 h, J$ }( Q( ?7 @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 M: [) M/ @. d6 `4 C0 V: }& V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& ~+ U9 w+ E( ?
| MCASP_PIN_ACLKX7 {- \7 j8 q3 k/ j9 @- P! i
| MCASP_PIN_AHCLKX
# K) n( S! B7 f" c+ d" O+ H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& i- Y* v' d TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / q' S6 ]4 j$ w3 P% q
| MCASP_TX_CLKFAIL & ]/ X8 y9 G' h4 b5 D
| MCASP_TX_SYNCERROR
( M0 M2 e+ D2 ^+ w6 b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: f7 M; L8 e4 ?/ Z" F& J| MCASP_RX_CLKFAIL
7 S0 a' t; X' h* S+ d& k. f| MCASP_RX_SYNCERROR , j7 p3 k9 n4 F0 m p
| MCASP_RX_OVERRUN);
# r( N v2 y4 K( j- j; q; z} static void I2SDataTxRxActivate(void)
: ~, U- `" B" p{; O0 q0 R% ~1 }" n; G
/* Start the clocks */$ x* s& A6 e5 k5 E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: p# f* g3 b. ]1 ?" v& PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ x: c3 {* }" m4 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 j; m' N+ x9 p! iEDMA3_TRIG_MODE_EVENT);, t2 E+ [3 h$ }7 }, |1 `8 v' i- w0 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! `) B5 F- L2 D0 t5 ]+ G5 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' g9 I f8 u6 ^. `' r3 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ d* h' H5 F) k# VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ U0 C+ M l) Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ I. f! a: c& k7 T5 w3 q2 C$ X0 A6 L( _& RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 | A/ L8 z" ]* O& V3 f0 I) G+ M$ |" aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 t! o, T+ c* u6 ]; q
}
0 W6 C" R3 i( j/ g: {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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