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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 D7 i; \* X+ w* e' y W& i0 ^input mcasp_ahclkx,! _* t9 y& \% ]" H: T; ]. S4 X
input mcasp_aclkx,
/ k9 A h, k- finput axr0,* r% @. k6 T5 S6 K( ~) \* t+ l
; w& u* [& e/ coutput mcasp_afsr,
5 E/ W. M2 O$ V# g8 k/ ?' Zoutput mcasp_ahclkr,
3 m0 U( `8 j; y" m: P: Houtput mcasp_aclkr,
8 ~3 f8 t& i% y5 c3 {output axr1,+ a: s8 a$ ^$ M# M
assign mcasp_afsr = mcasp_afsx;
. ]% I+ q4 W z. `' Lassign mcasp_aclkr = mcasp_aclkx;
C C0 h, `6 L7 T7 i) massign mcasp_ahclkr = mcasp_ahclkx;
( n8 ~, |) x# C; T+ Jassign axr1 = axr0; 6 G( t8 T: b' j( I& v
/ Q- d2 c' f' O2 I* ]5 m9 t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : V* I+ A; @# t. z {
static void McASPI2SConfigure(void)" g: R! i3 F, g6 B0 M9 h
{" K5 |) J* _( s1 O0 V% v# h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 g9 o$ R ]3 ^' y# aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 O. x. o9 u3 P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* y6 k+ `9 V) R5 o, U$ ^7 ^! qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 O. i' j* ]! @) V: X, C( JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; H+ E5 [- q7 U+ i2 j3 k/ GMCASP_RX_MODE_DMA);
9 g) M0 o" H. p% j5 }" k+ [. |' v2 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- |* k `0 B$ pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% o" s; F. X* B3 D9 |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ v1 k# c5 i3 j) l) K( JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ \5 r8 _% g. Z/ o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : K/ ~7 m* P: ^* |2 B, c" q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 o0 D/ y. d M. j* o. A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 c/ A' T0 G' }: ^1 ^7 j. O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) [& T" c6 y4 k) Z4 a9 |) l- |& }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ D# ?* O! E1 N# v7 n) \' t0 v0x00, 0xFF); /* configure the clock for transmitter */
# v# q7 O& _$ }" n% u& I! wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# x: f- K2 ?" ^( W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' K2 t7 ?" P K4 \( [) X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 N& F) _: z. F& M0x00, 0xFF);7 l K% `5 f7 K# ~7 o6 i$ L* b
9 W' l1 b* T) V9 P" z& n' V/* Enable synchronization of RX and TX sections */ : P1 {1 E/ a* |. a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 z7 [& d8 X- O( w: G+ z* JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- n# h% z4 o- @% B( U* m& q" d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 e2 x4 V! e' r# G) P
** Set the serializers, Currently only one serializer is set as
" i1 ]/ d1 Q3 s& j2 g' d** transmitter and one serializer as receiver.6 ?% g% Y( E+ N' m
*/
8 e' ]5 m$ n7 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ Z6 \( ? C6 k/ x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* ?. p: p. ~0 u8 ?2 J6 u1 ]
** Configure the McASP pins * f, f. O' U* y) W q1 `; a* Z2 |
** Input - Frame Sync, Clock and Serializer Rx, M$ h! b( \1 D0 G5 J4 f( n/ h
** Output - Serializer Tx is connected to the input of the codec 8 H' Q3 d4 W2 ?: o: h2 f# C) L% [
*/. J. o0 j8 }1 s; f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 c# {! I& t7 B* ~: b% tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( n- G$ Q1 u/ w; T7 c/ K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 D& m' t2 h+ R! W0 ]6 x
| MCASP_PIN_ACLKX* I a/ a8 e h* ^; ` a
| MCASP_PIN_AHCLKX
- @7 X" w% ?- A3 d7 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& B4 B! A v, u/ I$ t* Q) v: cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' L2 n6 f! S5 U1 V [
| MCASP_TX_CLKFAIL
5 e) F. T: M5 }$ f/ U| MCASP_TX_SYNCERROR, t, u- D7 F/ _' C0 O K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " M' x7 E$ Z, u) ^
| MCASP_RX_CLKFAIL* P* b/ M4 o/ q' f5 o0 V6 G
| MCASP_RX_SYNCERROR
v, e: K& }/ A0 L: Y| MCASP_RX_OVERRUN);! [, S5 c3 V) ]0 {: \! ?
} static void I2SDataTxRxActivate(void)
2 k0 ]( s! @5 y; J6 Y" A6 R{
4 I5 @- O1 E7 D, A' M/* Start the clocks */
3 i: s$ t. ]8 Z% i8 H' ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 A9 C8 H; N. wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: T. p- n$ ?9 r* @' E! Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 e' g: G& f* l5 h% K1 P r- E
EDMA3_TRIG_MODE_EVENT);
- `" ]- \9 c6 x& O4 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 Z, W: g( u' Y3 Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 u1 i5 j; S6 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 }/ C) a6 b" @9 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; E0 G$ V( i; C3 k3 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 k% t f" O2 l* O# F" ?# s. E) pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 h1 h. u7 R7 _* i" E. @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ n4 B/ u6 s5 O( h
} ; m9 }; r. Y5 ? P# [1 G: k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / |4 v5 u/ Q! d! F6 X0 ~
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