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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( U$ L, }- u/ A% Q! D3 ^/ g. `" Sinput mcasp_ahclkx,! X3 U1 w9 L, {: w m9 s1 K
input mcasp_aclkx, Q( S3 Y" z+ ?' ?! l& @& R9 O. C
input axr0,% L' G- p& o0 w
" x& T6 Y+ N+ ]
output mcasp_afsr,. {. Y; H" ^/ |# g6 M ~3 b- t
output mcasp_ahclkr,
& X/ A$ D+ k+ X: a. F* doutput mcasp_aclkr,
; ^& z$ E( r- i3 }output axr1,: g' X* W! B0 V
assign mcasp_afsr = mcasp_afsx;* X6 O) ]( F# P8 R2 P0 S. t3 m& @
assign mcasp_aclkr = mcasp_aclkx;
* u; s$ a# W$ Q- iassign mcasp_ahclkr = mcasp_ahclkx;! }5 [6 {/ \" |7 v0 \
assign axr1 = axr0; ; X" P, {# r1 _$ E3 U/ \
, ]- i; O9 H* O2 J- ?# r6 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 M: H) H3 U2 H8 `& O6 O4 R
static void McASPI2SConfigure(void)
7 C1 `: G I h{
" c' h8 p/ e4 M, a; R! ` U, uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 f# Y \9 ?+ Q! M! j6 T3 W2 o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 s5 ]! |* Y) q, O, b! c# I2 KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 @, p9 a! L" ~& gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 \4 O+ y2 w: K' z. l# g. B% BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 J9 _! y* k1 H) r0 h# DMCASP_RX_MODE_DMA);& M. K. a# L' G; p7 O( U O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- m7 A) D0 [9 ]( a4 u2 hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 m5 P; ]! Z" k8 @( a W- A% YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ L- k: Q9 g' L$ _" y( ]" K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 `. r* H0 ?+ B/ N0 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 }& m; Z ?; u8 X \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% A( O# ~( {* [4 W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- j$ T8 c& }7 O) f* c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # b* |# b8 ?6 [3 y6 H. T4 K8 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ E% |& j% I) g6 Q9 o
0x00, 0xFF); /* configure the clock for transmitter */
3 q1 j \5 p2 Z H% b! wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( l- m, W' Y3 Y i; o. `" N8 EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: r+ s3 ^9 I; ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 {8 G/ ]. b3 T7 d" G5 Z4 Z( [$ L0x00, 0xFF);
! X, M2 w$ Q1 v! v4 x9 ?: K( z* d9 @) G$ |% x# o/ a
/* Enable synchronization of RX and TX sections */ $ a0 B, {/ a1 K4 h7 |# e( l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: t9 a( n6 L" p# g/ J0 U" mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 r1 S* c, O3 E- Y6 i( IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ j: u, Q* v: j* {8 _1 @& f* \: H( o
** Set the serializers, Currently only one serializer is set as6 y" o% t% O9 Q, ~# U7 H
** transmitter and one serializer as receiver.
+ n+ |* M, F! z$ X*/
4 |7 M: }/ {+ @$ j1 X/ R! }$ G/ v4 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, j$ V. o4 s9 Z, M9 ?' r$ s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 O4 `$ S7 ]$ j
** Configure the McASP pins
9 M, L% j8 I4 g8 U! q0 m** Input - Frame Sync, Clock and Serializer Rx% v4 Z( ^: T r) v! r& j0 C
** Output - Serializer Tx is connected to the input of the codec # H) o2 c H& e. H. y+ @: u6 `
*/
7 Z6 e0 m* E5 r, H( `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" H' s( }4 m+ B' K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: g$ b. \2 c+ t& C b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 T+ G: W5 I7 p' p/ c+ l| MCASP_PIN_ACLKX
1 Z: ]3 x% c# q2 p0 g' z| MCASP_PIN_AHCLKX
: Q' p D7 _' z) }! ]* V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) p5 P2 [, l3 q0 M8 F7 u( ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 f9 F; c8 V8 ?5 l5 @& f3 d; a| MCASP_TX_CLKFAIL 0 [* E0 m7 ~1 s# L' U
| MCASP_TX_SYNCERROR
! M& z9 x( A) X* y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 W4 q5 C% b$ I' F" O" _9 M| MCASP_RX_CLKFAIL
, g5 Q/ I5 T+ ~1 `, a! {, P| MCASP_RX_SYNCERROR
3 }& A/ _ K+ g7 Y# W| MCASP_RX_OVERRUN);
) U% \, f! }% r: Y: x+ \, M, S7 P} static void I2SDataTxRxActivate(void)" c; J8 y# x- u. \3 V) ~5 @0 K8 `
{9 F7 H8 [) t; @8 w4 ~
/* Start the clocks */
* U* v! w! Q% Y! t3 A! Z( P9 EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" z/ r/ q- f/ X) k: h7 y& dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 A- A( D: M2 ~( o, g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 P8 x9 c8 _2 w, T, DEDMA3_TRIG_MODE_EVENT); J# Y1 A; A4 {: ~- w$ d7 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 g! f3 P1 B( [4 r1 X$ h* C0 ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, |. Y# ?1 a0 u8 C' v# t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 m0 Y8 x# K A/ A1 J$ VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 S( W- S* P2 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 D5 a- H1 O4 Z. k# O+ K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& X5 N# R1 ?. Q8 b/ ]* YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 }. k: v+ s- i}
8 V. U5 j) d5 v! o' T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 _7 }( d" H1 Z) ?
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