MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
9 o0 n4 M( N$ L$ ~8 f. dinput mcasp_ahclkx,
4 L6 [4 b. ~7 ]5 u. E# h; a, einput mcasp_aclkx,
: T& ?8 @! \) g# e1 ainput axr0,
6 U( t5 O: }7 }6 ]
output mcasp_afsr,
- G% Y9 i/ P: p! v- [! p- foutput mcasp_ahclkr,
output mcasp_aclkr,
7 V  H  Y1 T) g9 r3 T4 p; K+ ]9 b  coutput axr1,

assign mcasp_afsr = mcasp_afsx;
: ]3 {. \# c. _2 @9 _assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
1 E+ A5 B7 r9 q. Q! P  Xassign axr1 = axr0;

9 a& q. o0 |" @9 V2 z, t7 r

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

( {4 |, }+ U5 c; W. {

static void McASPI2SConfigure(void)
9 \4 [* v5 S* I) }0 s{
" V- H3 v7 q0 _$ u. GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) A: b4 H8 ~) \3 v: y7 d4 g- K% I5 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
( L$ M  u: V' XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 @0 T2 _, _5 Z" m' O# p5 ?MCASP_RX_MODE_DMA);
: Y* b( m5 I% p- u5 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 M4 n6 B: K, ^4 XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( R0 h% [5 ^2 \6 r; E0 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 h" B+ `: I5 w- qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ j$ h, T* B, D( {/ z6 ~  CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 x, O: e7 J" R1 s: A9 _" CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
- u6 v; V+ r* t9 LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# h6 C- V6 [1 ^' \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
# O/ U+ Y2 d3 O% g& W** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
9 ?6 M$ }; y: s" @, Y# ~  y** Output - Serializer Tx is connected to the input of the codec
+ [0 _; _( ?: M7 V, S5 {  K, M4 j/ Z4 B; M*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
* i2 l7 L  ]) wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% h  E0 _# `1 W0 T| MCASP_TX_CLKFAIL
; E+ ^+ r% i2 @# |& u& y, L| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 t2 E+ u, N: `7 Y# \- \! h* ?+ _| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
2 u% d# M5 ^3 }5 v% q}

static void I2SDataTxRxActivate(void)
{
3 y3 F) d( O1 Z+ O: F/* Start the clocks */
1 Y' j  \2 ?, f% o9 L4 p7 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 t. Y: z5 J. H- ?. t- F2 T% n6 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
$ z, ~7 ]: h1 ]) v7 @3 ^2 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
: n1 c2 {9 Y1 x) a& v- HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- O5 I! c. v  |+ HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
# X) o. V3 A  S) c. ]3 F: aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
* N1 X7 p+ N6 ?/ |+ O  RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 ?! p0 ^, C* Z* T7 y7 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 I* M- x) x. V}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

$ A% f/ G' v! ^' p- R* K$ M