MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
) `. c6 U! c! Y, g4 _8 A# `( k8 pinput mcasp_aclkx,
input axr0,
! q+ U. ?( W0 Z7 |
# m4 t# ~. Y) n. i4 N3 goutput mcasp_afsr,
: H, B: Z4 E' @6 X% w% n1 xoutput mcasp_ahclkr,
$ y9 Z+ g1 Z6 r& F) a  ^; ?7 joutput mcasp_aclkr,
* [9 G3 L# F! n4 y$ z3 Houtput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
( Q* H/ G( l5 E5 g- h" H8 uassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

1 @' h* f6 Z/ ^

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
# p! m) s/ R5 R7 d. m{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% p/ m) v4 _) {4 GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
- G3 B' Y. N+ g) I' z5 IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% z. O; {8 h! T) i% @MCASP_RX_MODE_DMA);
9 i  \3 ~; M# _  TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* `/ q; u, H7 {MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! n7 e7 \  q1 T) b! m3 K8 _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 Y5 i4 Z' S) }  O( }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ ]) R6 O7 N# [% R1 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
& O/ q9 @+ C* X9 h0 g# u$ oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ V# v- O0 t. F, ^) R1 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 `# @5 T6 K2 m8 D) P# dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- N) u4 v8 F' }: h* t; @1 E9 W0 w0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; a4 m0 L4 R* O4 }9 D! a% FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- y# w+ m5 Y6 H! A9 p" [, Q9 Q1 j0x00, 0xFF);
' ~5 u5 `" }6 `' p8 f: u
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
: s3 v+ ~" o  ]$ Q- ~0 {$ @5 A9 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. w$ U0 t4 C$ U# u0 B9 QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
  s% P1 h9 V, w5 d** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
' G! P- Z" }  t& f' n2 S*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
( ^& q( q2 T6 C4 N; Z** Input - Frame Sync, Clock and Serializer Rx
, \6 M  x) C% M& u** Output - Serializer Tx is connected to the input of the codec
* s; R) b; G! h. ^! r% s/ S1 m7 r- g*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 _  ~4 X  N+ {1 i  }6 V6 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. V& P1 P4 C7 E  R. L; Z3 H| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
% E4 b& E. F5 }0 R& F: T3 Q| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
! `  d" J2 T% l* D: z| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, i0 o2 I* G/ z4 N* S% a- y2 Q) w" `: o: v| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
4 U- a& }5 X/ n/ U7 j# L  P+ f}

static void I2SDataTxRxActivate(void)
% l; a! D6 p+ l: i3 L$ N{
# e4 M! n, U9 k" o$ j, ?/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
3 f& u, |- U2 V8 L+ W" g5 N9 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
- Q; Q* p5 X. S0 B8 X5 l+ u+ i# cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 |0 Z) g7 I. A# _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
+ d# a8 W9 e9 D1 E+ c! OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 P- d8 v; R% P0 t8 x! FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
" t% z1 e" {+ Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: D1 n# ~7 P4 A0 Z  }4 k- }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 n' ?& U+ m9 O9 j* G# L: ^}

* u  n$ o1 S/ z0 E& c

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

& U. W! r+ }+ a8 A& k4 S