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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ m. P6 d4 F2 q$ A {2 Sinput mcasp_ahclkx,
3 _: ]9 @6 X" g7 D; V7 dinput mcasp_aclkx,
5 v& o' ^1 j7 G! Ginput axr0,
" O" {+ ~( v$ q$ s6 H) v O4 g: Q3 B+ i: R# K: Y( Y, l
output mcasp_afsr,
5 f1 H- w1 _: b% Uoutput mcasp_ahclkr,
+ H; ?/ [6 P1 q6 a& voutput mcasp_aclkr,7 ~! P4 e$ c/ s4 j4 j: P
output axr1,
) z6 S) Y& k2 h1 l2 B# \3 |2 L assign mcasp_afsr = mcasp_afsx;
, s2 d `8 O6 i8 e2 m9 u# d: `! ]assign mcasp_aclkr = mcasp_aclkx;
4 M! R( m% G' Q, xassign mcasp_ahclkr = mcasp_ahclkx;
$ |7 W/ H& ]) @7 d4 y! Qassign axr1 = axr0;
1 I1 m: t2 Q. ~8 D2 T& x1 n* l% J$ j. |& r- K+ r! U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % \$ _6 Y' `2 p" g( h
static void McASPI2SConfigure(void)
/ t1 t$ R! }( {+ c% L5 s{1 f4 \ I# `( E/ f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 d) j* s( D& k5 J. w, x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" }& X) Y! ]6 R/ |/ w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; k- j9 x; [; Q5 Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' l9 z# R9 S5 q% ?- J# eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) `8 M* t: K1 C! H( z6 [9 w6 {: lMCASP_RX_MODE_DMA);' b& x, H) d1 c: L3 l
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 |$ }' [, M* O" ] t6 N& t( b- l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 J; D( i# Y+ X" Y6 ]" Y" LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 W! U0 ~; Y6 M/ Q+ y. \0 t0 CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# r+ h2 y0 y$ a X) P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* u. N/ D( e3 j. C9 xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 r, g- K# N- U% _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# |( S; `" d* ^( g4 Q7 W- W# xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # w0 G7 \2 b7 o; g$ N. K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 q$ j0 y, m9 b4 A* d! \0x00, 0xFF); /* configure the clock for transmitter */
1 ?$ j5 g( Q8 |0 k4 p" CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" h, D- l! y" q4 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' T' |$ \0 X; z# Y( F5 V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
S- s! Y/ S, V+ [0x00, 0xFF);
! N+ q) g( U3 M( g1 b$ x9 D
9 a# m6 ]* J7 ?6 w+ `/* Enable synchronization of RX and TX sections */ ) S2 l! c- c w% b$ \- B! \8 M3 Q# Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 z" T! ~/ e* N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 B v) n/ X5 D* p( sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ U* @$ }1 q$ A. G9 k** Set the serializers, Currently only one serializer is set as- l) S/ x0 ]. h
** transmitter and one serializer as receiver.
" U" w% N( l# J) ?( V*/2 C' n+ F' e! i3 u0 e$ ?! d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 o9 r$ \& T8 {8 [! o+ G. b# ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& ?/ c( r3 j% b! Y* K
** Configure the McASP pins , `. L; D1 }8 Y" b
** Input - Frame Sync, Clock and Serializer Rx. C! v/ N9 G7 s0 w7 Y+ H5 D
** Output - Serializer Tx is connected to the input of the codec . Y9 h1 w9 f6 u0 O" F- i
*/" R+ j/ R3 J2 b3 B0 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 ]. y! |& U* n$ U, S/ jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% E/ B w3 w) ~; x0 {' ?. WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* |# L6 ?# p- `" Y1 L9 F2 {+ U9 z| MCASP_PIN_ACLKX/ b0 N2 d0 m$ T
| MCASP_PIN_AHCLKX
; y4 l$ u Y' d. D/ \% X2 U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ h! z, c' [1 \# W1 D" {2 T6 P5 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 m- A8 ? o0 z| MCASP_TX_CLKFAIL
5 a1 M/ X, n U7 K+ G| MCASP_TX_SYNCERROR3 [& {5 t4 `0 g+ R/ O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . t. I. E! P6 J
| MCASP_RX_CLKFAIL0 m J; ?7 b% b
| MCASP_RX_SYNCERROR 0 l5 `$ o4 l3 |" |4 `" \
| MCASP_RX_OVERRUN);4 l9 u4 s: J. ]* u, u8 s1 ^* X
} static void I2SDataTxRxActivate(void)/ g3 m, u7 }1 C' E
{+ d3 `0 m/ t+ p' d* G' X z. I
/* Start the clocks */' s; u5 }6 P0 V, [" `% _5 N, D3 {! U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& g$ p0 @0 V+ t/ R% p+ v# [9 A- @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( E5 \+ \( c- v m u; E" A, D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) A) P" ]4 i- ?4 e1 H) xEDMA3_TRIG_MODE_EVENT);
, T6 T1 e2 ~' g' r. K2 P+ W aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; d" H9 r. _/ G( aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' x2 f& W5 f7 r- k" a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 F" u: B5 b! g/ n+ ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 r+ C9 H. D( E* D; i' ]) ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* c6 w2 _: B+ m! }" R: ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! z7 s& u9 `. G9 t# E8 P( s [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 l# v- J/ o. X6 E}
& x* }5 Z D4 a& E; d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 o( j" ~. f6 ~' A) j
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