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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ I9 G0 t" p8 n+ Z" j- p
input mcasp_ahclkx,) T$ J$ q0 _3 [& i0 w4 U8 Y8 h& f. M2 n
input mcasp_aclkx,
) _' v( c9 J( \: Y2 {+ pinput axr0,
# z r" o; {1 t, o
% b8 a. ~ ?7 E9 j2 o: ]output mcasp_afsr,
( `7 O1 O h6 F$ ~( moutput mcasp_ahclkr,3 w' w, H# W7 R6 K% S* ?
output mcasp_aclkr,! v$ c r2 `; ?; A% w( v
output axr1,
) k2 v! D- I7 E# o# D0 A1 t' L( L: x assign mcasp_afsr = mcasp_afsx;
+ |& g2 Z. x4 H. `$ N3 Massign mcasp_aclkr = mcasp_aclkx;: u$ S( @9 |+ Y. J1 j; h
assign mcasp_ahclkr = mcasp_ahclkx;
2 M5 v2 f0 |6 v% Y/ `assign axr1 = axr0; $ s8 c" ]9 U3 D$ w9 t
, ~, N5 T- ^8 `# d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 z; k, w5 l4 P# c( t$ R
static void McASPI2SConfigure(void)2 B [. w9 K+ H4 I6 Z3 h5 r+ h
{- P- S9 r+ J9 ~! ^$ K, N- V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: }( l/ r* x9 P/ ` ?5 ^: |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ z8 [: P9 s; TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 {( i! G* i) C& Q, AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ M) \+ }# N! j+ _, z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 J' L; l2 }, ~- [# K( {" w
MCASP_RX_MODE_DMA);
; @; ^ m3 j4 R/ nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," _" k) o& j6 Y) B4 g( G% l6 p8 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# o1 B8 J9 Z; ~! G# H7 x+ U' y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! B$ c$ Q, C' K4 |3 a! A T0 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( [9 V$ ]' R1 V2 z5 b8 D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 W1 c+ h8 u6 ]/ |# ?7 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 ?& K4 h/ w- V& q5 Y# a; A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ @; t) p; _% i: W/ y! I" T) X' b, L" IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 Q5 P+ s7 z8 n, I/ jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 H' W5 b3 i& O N. Y, i, h% J
0x00, 0xFF); /* configure the clock for transmitter */
! a% {2 g0 i: R( q/ VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ K( X! k: V+ p* b, A1 V: ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , d& [( ]8 ?5 j: J+ l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 T! G. ]' G' f: f: E
0x00, 0xFF);
/ c% {2 t# k) u( g$ u( I" R7 q7 V4 I. n, N4 {
/* Enable synchronization of RX and TX sections */ % `- e: ~( k" ]4 z2 G: e) s5 w; y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 j2 Q6 H8 M) UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); I+ @8 D1 m) @9 Q& V/ O2 M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& d2 L' ^! P! u Y) V8 ?
** Set the serializers, Currently only one serializer is set as
- L, g- u8 p6 d, i$ G8 @; q** transmitter and one serializer as receiver.
7 k* y) A- q9 t. f* @; {2 k*/
0 E8 X+ H9 y) T1 C2 aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* {1 f8 i( ]. Z5 U# G7 W5 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& W0 c% C! X2 R** Configure the McASP pins
, z* [6 W3 j$ D3 [** Input - Frame Sync, Clock and Serializer Rx
$ f; K# p* T6 R9 T% E& c {** Output - Serializer Tx is connected to the input of the codec
1 E1 f: G Q% R: l2 s( V*/
3 j% [9 x( H+ g8 XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* j! c% G% v1 F' nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
e) L5 q$ Z! ^4 z+ [) RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( C M9 ^ U& {/ y% p/ q
| MCASP_PIN_ACLKX6 v9 u! {$ [ A8 \. d1 S" H
| MCASP_PIN_AHCLKX: r4 G9 T6 ^% ]$ f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 K9 k0 j, @6 B% N' mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 r- w% @& f- n! T0 C2 I# Y
| MCASP_TX_CLKFAIL ' Y% A+ ?9 t0 b1 V; b
| MCASP_TX_SYNCERROR
6 d! E- q5 \: w' f+ i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # W! d. r: M4 J- [1 Y4 S
| MCASP_RX_CLKFAIL1 o7 d8 T# _9 i2 C D8 Q1 S
| MCASP_RX_SYNCERROR
/ v6 i9 P4 M# \| MCASP_RX_OVERRUN);& S8 S4 ?9 L3 u( K2 C9 ^6 r
} static void I2SDataTxRxActivate(void)
# d9 n4 y9 n' d! q! Q; t{
: l& I9 j0 M" o2 [/* Start the clocks */# c$ L3 j c( }9 l, n$ Z, u3 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ F! B* B1 ~6 U' f. Q8 {, i8 ~' RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" N/ t! e) O" q/ F7 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 ^, i- a% U8 k$ q
EDMA3_TRIG_MODE_EVENT); f% b( ~& M7 }7 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, D6 u$ e; o$ \- pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 d, L. d+ N* j& _" p z, L- ?# bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- p4 b& Y8 Z# p. g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 }* `, V: H9 c2 b2 x6 [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ q O0 c: c B4 R& u) G! |* vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 p3 Q" h3 ^( A/ i$ R. Z2 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 m) i8 r" q- P
}
: S9 l* V7 Z# A+ ]" v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' k4 }( u/ q1 q( P
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