|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 M1 k/ q8 A- e% W: q: R+ N' Pinput mcasp_ahclkx,
7 h8 M/ M# d* p% i8 V9 K* a; Minput mcasp_aclkx,# K' a! [) l$ d% J* J
input axr0,
- l7 J2 T0 }6 |8 }7 W4 Q1 r6 g8 i5 O7 }) J0 s. ?2 _0 j
output mcasp_afsr,, ^; z- t5 ?+ R V
output mcasp_ahclkr,1 ]' `6 f0 T/ V) R9 r6 e2 s* d& A
output mcasp_aclkr,
- h1 A& v0 a& \1 b1 }output axr1,: P7 I+ H: J" \
assign mcasp_afsr = mcasp_afsx;
) |' M3 h J- ?) xassign mcasp_aclkr = mcasp_aclkx;
+ X+ a! D3 W% R1 k6 {assign mcasp_ahclkr = mcasp_ahclkx;
# ?/ m4 w" Q' T1 N( qassign axr1 = axr0; 4 _* d: q% Y* `% r0 j. d
' Y1 n1 V+ v0 V+ [% J* j( J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : p; X& s) w% C. ]7 l# M/ B- d) \
static void McASPI2SConfigure(void). Z y% l; v. J% `$ H% V9 T! S
{" \) p$ x0 \) _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! M6 w7 h1 T- j# T4 B: jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! T: r: z# X0 v) j' j6 Q1 Y1 r1 v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 m3 N+ ~, ^3 l! Z. w+ qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' ?0 z& e$ I" V& R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ G% U2 q& q. E# C3 v
MCASP_RX_MODE_DMA);9 g. w% s9 V& o! ~, C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* {9 J' P$ @. f, D* P+ X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 E4 p" l' Q( K p9 y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* {! B2 h; I) r* dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. ?- N: h: l- Z, i' QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - s8 H8 C) E a# F- n) \: R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 V; u V* A s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ y+ }6 o8 k8 }- m, [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* j3 F" j! P7 J S w8 BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- l% _" F# J2 z [, f5 Y1 A
0x00, 0xFF); /* configure the clock for transmitter */
; A* E# A& s' S, U7 b7 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' R2 d1 A: g. f0 ?' IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); l8 F( o0 Y7 p: X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 ?* E* C4 K I
0x00, 0xFF);" n/ J# l( ~" X* c7 V% ? j/ R
3 [1 p3 G+ E: N1 O' F/ X
/* Enable synchronization of RX and TX sections */
1 {* d+ x; U( r5 t' fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 i3 D, H( R: D6 j' V6 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- t" M, r3 K7 ^. F$ zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ ~8 D. T& U: U( a- A: h9 r T** Set the serializers, Currently only one serializer is set as
$ j. A+ ?/ x2 Q% L1 T4 _8 Y- B** transmitter and one serializer as receiver.& _5 j5 D, [. Q2 v( U+ x) Y2 F
*/7 c/ p/ w% a- p2 H. w s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 l2 y8 o7 b @! I$ e# WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- d; h! A$ Q( O5 K7 w/ M, b( V
** Configure the McASP pins 1 i$ W7 T. U3 k9 y& ^
** Input - Frame Sync, Clock and Serializer Rx
0 X2 @' H! z, n( o0 D; Q+ U) t** Output - Serializer Tx is connected to the input of the codec
3 I a9 h5 P. O) c*/, t/ \/ @# E& E8 ^ T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( A1 s/ t. H4 |0 G8 }/ }5 m1 y u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ V# ~6 [+ U4 H- T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* U/ K$ w5 T" a* P
| MCASP_PIN_ACLKX
N+ Z$ e2 P1 C8 v: Z| MCASP_PIN_AHCLKX* N! H) o# r0 I# G) c3 R; y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* J/ t; D0 I3 t' j4 B3 y, o' jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' P7 K7 j. B8 B4 y4 L3 X$ f8 M
| MCASP_TX_CLKFAIL
0 j# V p6 f" j( }! Z| MCASP_TX_SYNCERROR
/ T9 x6 \' q; `' K8 R+ R5 \! j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; J! c9 I# R0 U7 `
| MCASP_RX_CLKFAIL
* R- @8 `4 ^3 w: [| MCASP_RX_SYNCERROR
* C9 \: g4 K' E0 e* l: C| MCASP_RX_OVERRUN);
6 f0 d8 U5 u/ J# ?} static void I2SDataTxRxActivate(void)
; I2 i, z( r5 I& c* u+ P. b{$ N3 o! I( m( \+ ~0 f$ T
/* Start the clocks */8 X0 c( t+ j8 V, I0 u6 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* n) {0 x, H; M5 W9 Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 i8 K* V1 x, o, S# A/ J7 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& u R E! k% `# u$ s7 u2 T9 c
EDMA3_TRIG_MODE_EVENT);# d. S; B( z; i( R! n( ~+ k! A3 m: g# W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 W+ |$ t* a2 d* _/ ^+ iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 d$ o) ?! y/ P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 Z4 U7 l8 A( c% T; @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 e `5 j& L) L( C4 c$ z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! \8 U3 f- j: M8 G1 O" Y( h( i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 O+ ] I8 t6 H! w7 m- C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 L; w" r$ A: V) N! g9 V} 7 f6 r. C" D% M+ G7 M) n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 [. U) |! ~1 Y+ p3 l8 [
|