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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ \3 D9 a1 `5 y( ~# ]. Q1 a3 {
input mcasp_ahclkx,
' J- a) y/ |7 j4 Z* m2 N' Dinput mcasp_aclkx,% f1 f5 Y) s2 l- {& P0 `! G0 S
input axr0,8 R% x" h9 ~' v. f' M6 ^
/ g N6 }. l( B n6 W, a
output mcasp_afsr,
& ]# Z0 {6 J2 z( Q# ioutput mcasp_ahclkr,
9 Q; N7 c6 q: G# s, ]& soutput mcasp_aclkr,
8 c5 z- m: r1 O5 Foutput axr1,. Y! B/ X# T+ O6 W) D& v
assign mcasp_afsr = mcasp_afsx;! Q1 j0 N% k( K8 h
assign mcasp_aclkr = mcasp_aclkx;
7 ~4 f* V& Y7 k2 J& D) X, bassign mcasp_ahclkr = mcasp_ahclkx;
Y1 H9 \/ |: m* hassign axr1 = axr0; ( i! P) `9 J; j1 o1 Y9 a
& X$ ^3 M( y% G- w- D4 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% ~5 w+ O# P2 D5 j) f# ~static void McASPI2SConfigure(void)0 G2 d" P/ Y" M* v4 x& j! K
{
, z; t+ S5 p: s) V# B LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 N4 d- X& j' x# d f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 |& U1 y+ T6 wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 J0 W" R* S/ s% [3 H0 j1 o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( D( L E4 `: M) D! qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' @1 H- J+ \0 L/ g& r5 X
MCASP_RX_MODE_DMA);
" b2 A. \6 l1 e7 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ @7 j) [) l r3 _" @0 _- G) N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, U; M* v, G5 o k5 ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 A; w& T1 @6 W) t6 |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( G4 D" A8 R' ?" `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, H; Y( t& ]5 A) Q6 t8 S+ y8 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 r( c4 _( S! {3 F' d, S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; _$ D9 d6 a4 g5 P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % w: e& v$ Z2 Y3 U" R$ d1 E$ p9 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 Y) p& Y2 y! K+ V6 C* M' V" f$ n0x00, 0xFF); /* configure the clock for transmitter */
3 \, P. T- o2 t9 c1 S9 eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 I3 C' P$ F) v% WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - m ]3 p4 U2 P7 U- ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" ]' b* m' D( a7 w2 E4 x0x00, 0xFF);# ?& k W: t ?. {- ]4 S
* v1 x% d" ?: ]$ p$ e" z6 @/* Enable synchronization of RX and TX sections */ 7 A/ h- l2 v4 \$ }) `2 h2 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 F$ x' G% x: j* Q$ P# T5 [$ B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
A1 M* q2 Y/ L3 w$ g3 l- Q7 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
q7 i# h+ N. C1 M/ d** Set the serializers, Currently only one serializer is set as" H# P5 w% P! k+ h# k
** transmitter and one serializer as receiver.
$ U5 H3 j3 g7 j; A- C*/7 Y' j0 e6 e: \: ~& ]0 N- P& W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 W: M0 S" u) ^6 \0 }2 L. D' J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) K3 J7 ?1 P5 B+ \9 |- \** Configure the McASP pins
$ U U& D/ Q5 A** Input - Frame Sync, Clock and Serializer Rx
+ z) d6 ~9 n& |% N** Output - Serializer Tx is connected to the input of the codec
7 q; Z" e0 q8 O9 P; H*/
3 s: z( r& c, a$ n$ xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 C( ^, w) \: r4 j$ T$ oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# j5 k& n: _1 \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
t. j ~2 l" W2 m. g z8 V0 e* w| MCASP_PIN_ACLKX
]: h7 _& Y) X4 Y| MCASP_PIN_AHCLKX5 O& U1 x2 _# g, F# x0 \' r0 _+ K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* \% O2 [ z/ ~' t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- ~) M4 R' z/ D d3 X' ?' W| MCASP_TX_CLKFAIL , l' z2 n# |& ] D+ O
| MCASP_TX_SYNCERROR
9 z# R" U: X! ^( r: ~, {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , q- y8 O/ _5 _
| MCASP_RX_CLKFAIL$ l/ E2 z2 r% @
| MCASP_RX_SYNCERROR
8 D' g; @ |5 A3 [* S/ K| MCASP_RX_OVERRUN);
( p- O" j' \( i/ R0 r0 y @+ Q} static void I2SDataTxRxActivate(void)
$ S# G2 {! I$ O4 T6 A{
& k5 [ g/ p" i( l/ o% _4 W/* Start the clocks */
' p) R: o8 @# Y& B' b2 O" u3 P3 |, mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 T1 C: U3 v/ f Y/ G! TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// n m$ w. q; k0 [# d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# ?+ f9 H. b" n4 w. b' X# [9 R3 G
EDMA3_TRIG_MODE_EVENT);
( k+ F) h' K. n! } j8 y& MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; c a' Z$ N; \3 F& A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" g# u5 t# @6 m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 e0 z5 H2 a5 f$ t, c8 r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 O+ a* |4 V& s6 ]+ mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 _; M" w2 i% p7 d0 o. h" zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( W/ J. N- {. k; k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. ~4 |: Z# t9 o" k$ r} " E! c2 n9 W; O3 R- V) j3 s. \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . q4 V6 N! d2 ]" T: E5 D% b
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