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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 E: `% r- T7 X# u/ m a' E& @6 yinput mcasp_ahclkx,0 b5 w) a- j: x) E5 h6 d: Y+ _1 W
input mcasp_aclkx,
" x H+ ^4 b- Vinput axr0,
8 m8 p% l9 G8 C1 r L w3 O; r$ n# D" {- u1 L. ?
output mcasp_afsr,
; H# k4 \5 C) Y! a: |output mcasp_ahclkr,
* L% G- a5 b. _# }- Foutput mcasp_aclkr,4 e4 i# I$ G/ V- ?
output axr1,
+ S0 H" s. M8 x- Z) y. { assign mcasp_afsr = mcasp_afsx;% }$ M2 Q F. B0 b8 r' A
assign mcasp_aclkr = mcasp_aclkx;
3 e$ ?/ G$ k, d# v7 l, massign mcasp_ahclkr = mcasp_ahclkx;2 q! K, E* l6 {" |/ G1 F' q s
assign axr1 = axr0; 6 g! ^/ d! x) \& A2 w# z* W
( j" b( D1 }, a7 U) W& }' o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* c+ d# ?5 Z: L2 z$ g# y9 B" Sstatic void McASPI2SConfigure(void)
4 T: B5 t$ q K( d{. h9 Q; P% B1 [) r) W9 Q4 @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 k; {# d! T& f' tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 M" l5 K6 l( L) ~# Q& VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; \% `; i" O( }" D/ e/ r0 l/ `* ^& I, Q# [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 j3 Y" @1 G8 l4 I) N5 W! _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ K# L# h/ u( ?2 C% _: s0 R: S, LMCASP_RX_MODE_DMA);% O& ]( `3 `9 K" y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* o' w8 f- c% b4 F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 A* [0 z/ V4 b' o% mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 s; g0 @ z& [* q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; e9 ?3 U( H% x4 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 l% x i; n* ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
D0 c$ [% V- _( b. JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ }6 E: i! `* L& [! dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; L+ f9 y! E5 N6 I: t/ t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ Z# ~% W/ N5 B9 g# J
0x00, 0xFF); /* configure the clock for transmitter */% @( E3 \$ t" ~3 N! q/ A! N: L( h3 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* N. t- w5 Y( F0 M/ q) n9 P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( _* F0 B& J( K A- s7 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ ~) z4 i$ R1 b6 D9 _
0x00, 0xFF);
/ z0 C& f( a1 [. N
$ C6 I. [3 I6 M0 b/* Enable synchronization of RX and TX sections */
/ ]* t7 @+ w, e7 g; l7 O, a7 l4 R/ [1 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 q5 N8 H! v0 v; p' O; k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 e A2 e& ?& D: R; ]) y5 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 e7 c. Z" B$ U2 v
** Set the serializers, Currently only one serializer is set as
* b+ l9 T: h0 _: r3 v" |9 @0 W/ e** transmitter and one serializer as receiver.1 c/ }) `3 c2 ?, s2 O' x: C
*/
9 }6 {6 T1 i, f" l- b& _: c3 p3 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: u2 U% v& `$ t% U; b* TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, Q7 I! ^+ z1 B4 w4 j
** Configure the McASP pins + D. O( B0 _+ s( K! U/ x g
** Input - Frame Sync, Clock and Serializer Rx
9 F! B! _6 f( d& G" p% E0 F** Output - Serializer Tx is connected to the input of the codec , E) k4 e" q' h
*/
; \! {: M o6 @' D7 Y: u# O; vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 Q. s2 p; r% ]$ s3 u5 s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 g( V" N; Q/ L" _) XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ y7 u" v$ Q7 B5 z' H3 I: z| MCASP_PIN_ACLKX3 n# `1 g* @- g- {
| MCASP_PIN_AHCLKX! V( n4 r* G+ ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 m( f9 O' R: E. V) @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 j1 Z0 h$ V% _- P5 t/ }0 P
| MCASP_TX_CLKFAIL
# A2 r; N$ P9 {| MCASP_TX_SYNCERROR* [! }; q; @$ S3 a8 O$ Y6 c g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 f# d( o" j0 t, T" E| MCASP_RX_CLKFAIL+ e8 d: k" A# d7 x
| MCASP_RX_SYNCERROR ; Q& Z; _$ D) Y O" t) t3 ~
| MCASP_RX_OVERRUN);; C4 X" O4 C. f- Q7 L, T' s
} static void I2SDataTxRxActivate(void)
& z. ?/ @5 g, t! E{+ B# e4 H' N6 G) v, `9 g. |1 P
/* Start the clocks */9 [& O& _1 u# l+ t' }/ T9 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: h! t1 ]* o" }- W/ e/ T2 a9 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 C5 _- P E# z" t$ o' j( m$ J* i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) g5 G8 z; K/ }EDMA3_TRIG_MODE_EVENT);
" q0 X1 T! d+ `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 K: J! t2 e/ D! E0 R6 n$ |3 G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- a* J; X5 v+ `, X$ m* }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 l/ N* I$ J8 @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, s( |$ l" z' Q D9 X5 g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- r4 w& Q" J7 e+ s/ l' j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 q9 h( Y! } T& k: B% V8 c' OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ C2 B0 K* g* {; `}
b' a8 }4 O1 l$ p/ p: ^2 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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