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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. E* z+ w* x. U
input mcasp_ahclkx,
$ e9 `8 Y# R I% H% J3 c! vinput mcasp_aclkx,; d4 M* f8 G/ d) v+ Z( J; ?
input axr0,5 ?# s q5 F( o8 M8 d! z
: r i) F8 P6 P7 N! k6 X G) S
output mcasp_afsr,$ k& u! k4 ^: r+ a
output mcasp_ahclkr,
; b- I3 O! r: m* f+ y1 ]output mcasp_aclkr,8 c* ~0 L* |& H2 b f* w% Y
output axr1,
6 ]: C. ^( B+ U4 r( h assign mcasp_afsr = mcasp_afsx;
" [7 T/ i2 w# I* Q, b6 a: _assign mcasp_aclkr = mcasp_aclkx;' s* K% x8 y& [; x. j* p( T5 N
assign mcasp_ahclkr = mcasp_ahclkx;
) }3 @8 S: b% K0 |& u y& F: _assign axr1 = axr0;
& t( k% s/ q! j& t8 @; n7 |- z4 n' ~# v. M; A y) c. t% \' a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & ^1 R: V# F, G- p! @0 }
static void McASPI2SConfigure(void) n+ Z+ l6 V/ X' Q6 N Q0 }
{
3 G1 X6 z/ D5 M' x2 T4 B1 J3 R) p$ cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* j% R% u: z' a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# c1 L) D) a2 z8 r$ ?/ ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& T. M. @6 w4 ~6 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# V+ ^. K4 q D+ T$ t& ~7 A. h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* H+ D) z3 {! Q! R0 eMCASP_RX_MODE_DMA);, {# ^/ M% o1 B. S! `* ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# }" k8 [, {! u2 o# Z7 C! f2 h& nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( l; t& K1 Z* D% l7 G$ TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : ^- K& X# q, @* O# d) V% [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ M& X" }" y# @ x7 B; K& GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, _. `" b1 }( D0 y1 T0 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ L% x0 c' a2 v y8 AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) m$ x% C: @0 Q8 n! [ u1 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 i# \6 R* e' c6 g3 t" g" b" V% r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- x4 n7 M' M4 A0 x. Z9 q9 a0x00, 0xFF); /* configure the clock for transmitter */
' L3 x3 K3 l1 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# Y2 k8 G* r& w: |; b& e; d1 F: q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' P$ o$ v0 u$ a) j; p4 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" a3 w2 F( |) [4 E6 s% e3 ^0x00, 0xFF);: i5 G$ P& ~1 \* f8 y
1 v" V7 |( p* |) a) _
/* Enable synchronization of RX and TX sections */ ) t, N4 c& J" T1 I5 U* _( _- B; ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& \" P0 \- \2 M) c% U5 k' SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 H) N+ I1 h3 k$ W5 y) B, W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 U5 a3 i; v- ?- I* A
** Set the serializers, Currently only one serializer is set as
9 c1 c9 a" \+ o! w** transmitter and one serializer as receiver.
+ x! E( Q* Q( \/ D3 ~*/
6 o1 e6 [' Q2 m, h3 P/ a. y4 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" f9 h9 a; q# dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 w" w1 M) Y- l& L** Configure the McASP pins
* b, M/ ~' ~, N' O: l( S8 L** Input - Frame Sync, Clock and Serializer Rx$ C8 B% ~) i e/ H( ~/ t- \; T
** Output - Serializer Tx is connected to the input of the codec 7 m% ^5 Q d1 a
*/
8 J& d9 k# x5 F* H4 \ ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! f! | [" O, C6 G6 s2 P' fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: [+ h, Y3 m, l, e4 f2 U6 o) lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% f: t9 u, `& N4 l0 p; _| MCASP_PIN_ACLKX: N, H- L3 L0 U* `! q* t
| MCASP_PIN_AHCLKX" H, H; p/ x. O$ o: ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 V4 P$ Y, b; M5 t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; o5 ]4 @6 d! C9 ?0 H6 s' ~: [! C% w| MCASP_TX_CLKFAIL
2 c9 z/ N/ m2 {1 Z| MCASP_TX_SYNCERROR
% Q9 k# B3 ^9 k! H% A4 _' c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 R& R9 y' ~$ |2 i9 Z
| MCASP_RX_CLKFAIL
% l& e6 L* ]3 P" y6 h3 e7 P| MCASP_RX_SYNCERROR ( l: ]8 o* K. ?+ k
| MCASP_RX_OVERRUN);. Z) V' M6 }$ x }& H% o5 R
} static void I2SDataTxRxActivate(void)& d0 N9 p; m1 F
{
, e' Y. W8 L6 L" L+ d# [, Y- R/* Start the clocks */" |& s3 a4 x$ u+ ]# @/ ?( i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" e7 w1 }5 g7 R; O( @! ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; A. p2 L7 { m( W6 Z0 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: |" a: U3 C- V- P/ x# u& ?+ B* v ~EDMA3_TRIG_MODE_EVENT);$ J a0 v) ?4 d4 R, w8 M4 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 T) n2 S. [ ^$ z# u, f, `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 ?& M+ j# ^# E% g8 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ W. ?: o8 u) Z/ pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! F' K0 T4 a! y" C. j" i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 z# i& C( w: d |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" L1 ]- l5 P* H, ^, `2 q H) Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ }, \! j* r) g( k4 U
} ) L, u" M a* K! X: I, v( ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 m( k7 o6 W& |1 f- Y- _2 q
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