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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; `) r8 d: W% h9 S" @% c3 Rinput mcasp_ahclkx,
/ D3 _ I8 G7 P0 Einput mcasp_aclkx,
; w. r# U) {# \3 w- M: L; pinput axr0,3 q& [" A1 p% \: f
4 O0 x8 Y" t# ^6 r! u
output mcasp_afsr,
# I ]. _# [2 T$ U8 toutput mcasp_ahclkr,
# V: G( M* L+ A- Aoutput mcasp_aclkr,8 h4 E$ |7 F5 W3 X4 ~& u1 V2 e% W
output axr1,' x. y Q) o6 r
assign mcasp_afsr = mcasp_afsx;9 T& }( `7 @" U
assign mcasp_aclkr = mcasp_aclkx;3 ^8 i3 U2 G! [* v
assign mcasp_ahclkr = mcasp_ahclkx;% G8 s' a( R( _# I) H& p2 r i
assign axr1 = axr0;
/ y2 x2 i* [0 b* M) a3 ?. M% D" U/ C6 P: U! @7 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% [% |9 g; @( |# xstatic void McASPI2SConfigure(void)- j0 K+ \' y5 \2 t' u# T" j
{
6 t, z9 W( a; i& rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 p- l" Z7 [! R1 C. x0 IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 q( D `% X2 _0 q+ l/ H+ d7 w2 bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 Z; u. ~( h' [# v2 R* H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 n6 \6 I' I$ j5 v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 f3 W: @8 L: B. I2 f8 Z5 b9 v
MCASP_RX_MODE_DMA);, ?8 |% w4 d& i! B, r: W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 f W" v$ {% }% h% f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ ]+ e$ Y. y; @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 W) Y8 C" r* S" I' l- nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. N+ t- J" _2 F' l D# W3 H! AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 Z7 J7 |7 }3 {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 L. Z' V0 u1 g# @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; p! M" d6 J/ u1 X8 A$ e7 n6 v3 Y" n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 o) h" U1 F% n& J3 @0 c) kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 x8 C' t1 D2 z( R& m0x00, 0xFF); /* configure the clock for transmitter */
$ S1 u8 t& N) |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. h; v0 V) Q& J* T" o8 K9 b4 D; P5 MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 f0 V- Z+ y) b4 z3 N$ PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ i& ?2 I2 f. X
0x00, 0xFF);9 o7 L$ n* K+ q* [4 f! w6 g j l
/ _' ^6 o2 Y+ G7 V1 b. Q
/* Enable synchronization of RX and TX sections */
/ R0 @9 ^' @9 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; L% i( f4 P3 a$ @7 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' _% P$ s4 |' r4 W! D% I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* R# ~ x6 O1 F( E; g
** Set the serializers, Currently only one serializer is set as: u4 ]8 F2 X, ~5 U3 O( I+ z
** transmitter and one serializer as receiver.
9 `* D/ S$ Z% `* ~. ~, e8 A*/
7 P2 I# V4 ?5 f- N, v" iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, n4 d$ q; {+ |; m( @. kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' U5 X* p6 w6 q0 s9 h( D7 `5 h; |** Configure the McASP pins
/ S% \: E) s" R** Input - Frame Sync, Clock and Serializer Rx. Q3 v- W. Z# K) }8 }/ ^
** Output - Serializer Tx is connected to the input of the codec
( \# X( `+ j) P- k*/
7 m; B" t' p! YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 K- Y4 x8 S- P- y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 o2 E. P/ z% }+ m9 z% G4 Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 a4 G! Y& j5 M' }) G| MCASP_PIN_ACLKX
; ?6 q" F! o7 u+ i1 L/ j$ T" ^& o| MCASP_PIN_AHCLKX' z: \! a- D% a7 o4 N* l/ i p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 |5 I: ]0 H g# f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 u t6 B2 y C2 y
| MCASP_TX_CLKFAIL
) Y1 V/ n; L! `0 b: D7 W" q| MCASP_TX_SYNCERROR5 ~) e, L; B7 S5 @/ U& }8 O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . g+ b4 ^& O& r' R: R5 P0 y
| MCASP_RX_CLKFAIL! I2 B- M$ b3 p
| MCASP_RX_SYNCERROR
! Z! \6 Q y6 \) {; q; k4 ?; h| MCASP_RX_OVERRUN);
& N; A, ]9 g, X* a+ A# X9 a} static void I2SDataTxRxActivate(void)
1 |& I( Y& f% K* m6 I/ W{$ n; y% l) f F$ E
/* Start the clocks */" x' T: ^' T3 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); g& K, n: a- W& m- q$ d, j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" u4 S1 o- w. c, z. K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 `" s% e7 t8 p: w% e' pEDMA3_TRIG_MODE_EVENT);( Y! h, r0 a0 y) D6 U+ G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
E) w: I4 V- M2 C$ l/ Z& pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 e& L( i6 O0 r2 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- X; Q& D9 X7 O" `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 O# p9 t: L8 H9 \0 c8 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% q4 R: g( H. X" n5 C# w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 P0 l- z$ H% kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, T N8 D: k8 V
}
" M$ } t a% z) p' B5 ^2 @2 G% o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( k2 n( S% A7 D
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