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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; U& m3 r, ]- a% @input mcasp_ahclkx,
y6 n# Z! o( ~" Dinput mcasp_aclkx,
: F# d. u( U- r8 W- @/ `input axr0,+ j$ e1 [& [/ y
) E4 L- w9 I7 C/ ?$ W( F/ _
output mcasp_afsr,
6 p6 {( o+ B% w- N3 c1 ?7 eoutput mcasp_ahclkr,
' ?2 o& n7 e2 E$ ~( ]output mcasp_aclkr,
# O5 J& J* D1 N6 k/ B) @' ioutput axr1," m: z% W3 y* ]3 ~2 J
assign mcasp_afsr = mcasp_afsx;
9 [: {$ i1 x3 U: E5 S8 Nassign mcasp_aclkr = mcasp_aclkx;) c9 m- X) v, h! o) D1 k7 F' C; p
assign mcasp_ahclkr = mcasp_ahclkx;
+ [. G9 D2 p3 v: D& q iassign axr1 = axr0; - U" h0 S2 g* b
- E* _0 I" g( a+ W! `, q3 b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! F7 q9 P5 a/ `
static void McASPI2SConfigure(void)+ A5 G% G1 p5 e: M( T; Y
{
4 U+ D( H5 E6 T, H6 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% s2 U3 p2 T# D0 y; k( `) K' t* g$ P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( T' \3 ?5 ~& ~4 w" R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 ?( ?6 z. @! d' v, {- ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. p. t8 t2 r8 [/ Q1 c, xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! ?4 u) c5 Y' }$ f7 OMCASP_RX_MODE_DMA);
" b5 l# L- Z7 e( ?3 u% B+ H' DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 b; t5 x/ m k( S9 _' w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 @0 S9 j* m5 b' [; B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ o+ ^0 s F; v7 d9 `1 n+ BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 o, I; b& ], Y) s8 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % v& ^; i% W& n- C2 n. s( c, o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" v, f9 K+ `% o6 y2 l# r0 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( S( @& I3 O% P+ W) |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* Z8 T9 m2 @1 c; A4 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 I) E D* ]6 s0 Y+ S0x00, 0xFF); /* configure the clock for transmitter */
3 }- X: }8 D0 }5 n. O' f0 M7 {& ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); s, p/ h" Z. y9 K: o! L3 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& @) |: d. Z% gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: c$ s: w& T1 R4 Q/ t( ~
0x00, 0xFF);2 s4 C: f! P3 v1 h- G1 I
# L, V2 J' H4 F% M# a; b/* Enable synchronization of RX and TX sections */
D' d1 ?# P# P4 P" o( l9 mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ a6 d3 T' s9 D: z$ E c+ ~# s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! H' s1 W, O' B, tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, V9 T8 K6 G. n2 Z% y5 k% C& {7 h** Set the serializers, Currently only one serializer is set as
* G) e c' Z; h% X0 V' P** transmitter and one serializer as receiver.% {! I6 V& |9 }. B
*/' V6 m7 r# p& \5 j+ h) r3 l9 {' L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' o8 J" D3 A) ? m3 |# @4 BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; q8 j7 W- A; a$ h' F
** Configure the McASP pins ) |4 C& J; y0 o/ Y- o* `' M5 k
** Input - Frame Sync, Clock and Serializer Rx
! D4 [4 m+ g! ?** Output - Serializer Tx is connected to the input of the codec $ T3 z: v: E$ Q) Y
*/
5 k1 ?& f4 H+ A; n% \% MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# v$ C, n0 A/ U" Q5 ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% b3 t/ S. Q* N; C: q7 X4 C; x3 W3 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 e: j, ^$ w R- O+ U( m
| MCASP_PIN_ACLKX
& h D" K/ _. b| MCASP_PIN_AHCLKX
( h" z* P, W% C: o: L# G. a2 o) f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( z" f- m; t& J0 B% _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) E) l/ T. z, f M7 c
| MCASP_TX_CLKFAIL
1 n( b C5 q7 {8 }/ A| MCASP_TX_SYNCERROR
$ y: F- a/ S3 o/ g3 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 C7 T+ D. k! k) l# c t
| MCASP_RX_CLKFAIL
1 b3 x9 O, d- B| MCASP_RX_SYNCERROR
e% y' a: ?9 i" c. t| MCASP_RX_OVERRUN);
% v$ h, V8 K4 R# ]1 @} static void I2SDataTxRxActivate(void)1 W& {( l: a, ]. G' P) ]! }# O
{% z( o! r& V4 s
/* Start the clocks */( W0 B2 N" U0 d! C! ]- H9 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, D0 w s) o; V3 {" B- l% DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( [- q8 J! Y" D% W0 [, BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& ^1 [" U* s+ rEDMA3_TRIG_MODE_EVENT);( t* Y9 A0 Z3 a2 j6 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! K8 [) A7 U. } h+ d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
r' r: O# k3 u. ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. d4 n) p7 @& \) u7 B# KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: L8 A& _& o4 u% J% i! `% k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 t* R' S( L) e8 ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( F* I$ m. J( R% F: [ XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! T$ J2 H6 T, u. ~}
' u- [8 p9 g M0 W/ V6 J( `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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