|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% S, t7 k/ T0 K B& ?/ J
input mcasp_ahclkx,9 X$ @$ m: U' R4 `: B; S
input mcasp_aclkx,2 I0 q1 [% Q# a9 C+ E
input axr0,1 d; M8 E' E) J% H
* q0 B! V. i+ y m3 j* n8 Noutput mcasp_afsr,
9 \6 h5 N; b2 K$ P- F5 W" ooutput mcasp_ahclkr,( t& p5 S" {/ W
output mcasp_aclkr,6 K1 I/ w6 P. c+ X
output axr1,9 q9 B! y k! F2 m
assign mcasp_afsr = mcasp_afsx;
- r* t, d8 T j# E$ k. iassign mcasp_aclkr = mcasp_aclkx;, M9 G7 Q/ I6 X6 x6 V& {3 C" e5 ?3 t* L
assign mcasp_ahclkr = mcasp_ahclkx;
8 v1 x$ Y7 `1 j& lassign axr1 = axr0;
- X7 q6 ]+ p! d' G& l5 F+ H
6 L2 o' m8 `5 {. V/ s8 N9 |7 ?" m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, l, b1 Y& v! T1 cstatic void McASPI2SConfigure(void)1 W' ?$ O: t M R. P7 d
{
& _9 B3 D. }: ^$ p. XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: o6 ~$ x1 P$ S- h h4 @- @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ l: O- P6 Z1 ^, K% [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" i3 N6 h& b# @' xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 @5 ?* p3 B6 K. y o9 R9 \4 J- SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' U$ [2 f' I, T _2 t
MCASP_RX_MODE_DMA);
+ \/ G1 ?. m, v( ]% U' F$ `/ t: VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ]" H( t6 b9 {3 q( E- {/ \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" w; D/ C7 T8 s/ u/ L8 BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" k$ Q# R2 w4 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" ^2 {& e1 R* b- d: t }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & I4 e, `# O6 Z* U9 B4 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% Q; X9 j! P4 Z- x4 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' K7 J# m2 g& E) Z: l* }2 ]" [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) o( _6 s6 F& M+ lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 z( D6 o4 g6 l0x00, 0xFF); /* configure the clock for transmitter */8 K8 S0 `$ h1 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" n8 q4 C+ z8 n* A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 `: S- y2 `3 Z* W/ [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" w2 t& k8 A/ l9 u j0x00, 0xFF);- S2 H9 D- c6 {* k0 ]) y
1 J& B% s7 W' c. F/* Enable synchronization of RX and TX sections */
* W; W% h( I" G( _3 ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ N" q3 R& S/ t3 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 V9 _& z7 v U' V* Y/ u. S; m* y7 C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: U% L2 y& |0 {** Set the serializers, Currently only one serializer is set as% e- q, U$ L6 ^( q$ j
** transmitter and one serializer as receiver.8 K: D/ _+ _; ^) O1 K7 C
*/
' T1 ^9 ?% F; \! j- `/ NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 D! a! Z0 I7 w/ z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% Z! G9 s1 N' |* q
** Configure the McASP pins
+ r# r0 ^" `7 a8 o1 `** Input - Frame Sync, Clock and Serializer Rx3 G% N+ D" r2 d! Y# C2 h
** Output - Serializer Tx is connected to the input of the codec , x' r, M; i" M
*/# \* Y' X0 H6 k$ F( D, B3 @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
A$ N1 r/ _# X7 Z" xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 D0 e; a% m# o3 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; \- [( B5 N) O& i/ F& i! b
| MCASP_PIN_ACLKX
9 @/ ], ~$ v8 }" z| MCASP_PIN_AHCLKX
6 T8 ~0 v" c, D/ ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) e) A6 K* J$ o }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, t' L& y# R5 v0 i8 ]| MCASP_TX_CLKFAIL
- ?1 s: a6 e t M- \. U| MCASP_TX_SYNCERROR9 u! U2 h. W7 q2 n }! c/ P. W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + n2 N1 ^& n# `( D/ V1 A2 n: i
| MCASP_RX_CLKFAIL; _; _. Q" q7 R$ W) L# y9 Y |
| MCASP_RX_SYNCERROR
( Z* @, @! m( K! T5 i1 ?| MCASP_RX_OVERRUN);
/ W; Q8 r6 E% B: M: I} static void I2SDataTxRxActivate(void)
2 \1 t+ S) S1 m5 P1 ^3 q, i2 C& U{
0 k' |. q$ c7 i% O2 p# G/* Start the clocks */
4 n1 o. ~) K% J7 ?$ s! S6 ]( aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& c/ {" Y9 q$ V$ c+ O( a9 xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* X& B" p4 X7 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! T3 `8 O* k% n4 n" v3 f5 A% p, r
EDMA3_TRIG_MODE_EVENT);
( p) L7 O) L# q+ F5 {2 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) p1 W* s" r% l, t" x- ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 L: [- J3 L9 H7 Y! x4 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 r! t$ o" M3 f* M4 }8 g+ iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( r5 m6 N6 S( W' e2 L% uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" l6 S& L. @+ s( j" |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 u6 D+ K& e. L1 @9 h0 a# cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. Y. e$ P. W( E0 R1 o. T} " Y5 o( n& t/ r6 G0 j$ L* U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
( t; |! B7 Z# Y* f |