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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ b3 n7 x3 } Z5 I
input mcasp_ahclkx,
/ E0 I) f! U* E4 e# @9 R5 k" ~input mcasp_aclkx,6 ~2 m: o) p, ] L. B
input axr0,; G- X5 @5 \9 e) z9 E* O
1 Y% I1 A+ R7 O poutput mcasp_afsr,* ^+ U8 i) l3 Q& U+ s, d4 B& j
output mcasp_ahclkr,
- A4 _: |4 H5 u# h: O8 {) K0 boutput mcasp_aclkr,
' d& Y1 U: C& d7 O' u! ioutput axr1,; P# `8 X4 S' K6 \/ E$ D& `$ ]
assign mcasp_afsr = mcasp_afsx;0 X% y" K& I* I# `
assign mcasp_aclkr = mcasp_aclkx;) R7 }4 c8 P( c- X# s
assign mcasp_ahclkr = mcasp_ahclkx;
! r Y4 K" k6 S+ A' P- A2 a# b2 ]assign axr1 = axr0; ' [" R" W7 K$ Y# e5 {2 C. D
, e) J3 A4 ^8 L( u: B, J* A) L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
?$ T! A: ?; E- W9 cstatic void McASPI2SConfigure(void)+ j: {! B7 [0 W3 v* m
{
! T' B1 z- @& f0 S \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, ~+ {6 f+ ]' }" c3 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 [ b) s1 t3 y0 C2 e3 }* C1 L( ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. L" F) `& q% R8 N' d/ @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 z1 M& x: S9 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, T8 v* [) Y! J" ^/ yMCASP_RX_MODE_DMA);" C: e0 V" A% z3 i7 H% v0 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
v8 ~7 A8 B4 j6 ^# _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, V% ]+ d2 W8 B, ^; u' {/ OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; V9 B- E3 O% C n5 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: Q( n$ P5 J- E aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 A5 b0 H* s4 ]# _% }, nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ e1 c3 B7 M3 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 C) ~, l' _' L) m/ l: g9 x$ q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 [4 @; [, x- p% b" ?8 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 A8 m3 l4 K3 j' ]6 y. u$ _) \' ?0x00, 0xFF); /* configure the clock for transmitter */
. P9 P% V- T' d5 O) fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- a2 E* O: P4 l. ?) yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" V9 _4 m3 C2 F- [: IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," Q5 u" b8 x8 q, a! a
0x00, 0xFF);1 x; c% @* a' k( i
$ x- Q) o# Y3 ]! a
/* Enable synchronization of RX and TX sections */
+ G+ C' j8 J: L$ z2 Y: `6 L4 s" lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 G: L2 O7 U8 T) H* w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; `- V& I4 G* ? F. uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. j+ e. E5 N, d. v7 N* U; {
** Set the serializers, Currently only one serializer is set as+ H3 L; ]4 b0 V
** transmitter and one serializer as receiver.
5 v" ^! S3 e& O' \+ t! v6 V8 U*/6 L/ S1 S ~6 A# i/ X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# h+ @( c6 A( K5 ]+ d# O* kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; D4 v: A2 }% d, z% L** Configure the McASP pins * k# ~) o1 g" b( i- Z( K6 R9 l
** Input - Frame Sync, Clock and Serializer Rx
5 _( n2 h0 H- |" U8 k0 b** Output - Serializer Tx is connected to the input of the codec $ w, O( k) L: r& r5 f3 E
*/$ c, C% E: _4 F& n; x& n/ E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' K/ E" a, f5 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 r# p! w( g) R0 F, ]0 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 e( u0 ?- D5 I5 x c9 s
| MCASP_PIN_ACLKX, k1 e, j5 |+ Y; W8 d! [! i
| MCASP_PIN_AHCLKX/ x1 _" X- c1 _) }! |9 Q3 P7 T) ]" E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 c. x3 G1 j7 A: Z h2 A- r+ b7 k m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 c4 e. ^% U9 n) L. Y| MCASP_TX_CLKFAIL
' C8 N9 u1 _% T. T| MCASP_TX_SYNCERROR
: s/ L$ Y3 a/ I6 q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 [+ T, Z; ]3 Q5 \# w- X1 L* p7 m+ q
| MCASP_RX_CLKFAIL' H+ x0 Z* y# X& ? [5 T0 J
| MCASP_RX_SYNCERROR
+ Y1 \0 S$ L' B| MCASP_RX_OVERRUN);- v! w* Z) E; K9 g+ C& Q0 w+ \# t
} static void I2SDataTxRxActivate(void)7 H. Q& U9 b3 v, h8 C6 |2 |
{4 j5 ~' `! y& y: n: Q+ l3 M( V/ N
/* Start the clocks */
4 d( H6 M/ i) r: {' {1 p& B/ |6 L9 P1 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 t1 _2 s+ q0 `/ QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
H9 L, @- I+ ]4 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 D9 Z. Y& u A& u2 f6 M( v, ?/ d
EDMA3_TRIG_MODE_EVENT);
- o5 h" Y. Q2 X1 P- EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 K6 e/ o& o# x. Z5 q3 @$ R# m1 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 u$ T1 }2 B4 PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( |* H% ^* d# F4 c' R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 X8 |) Y! t* b" r* j& R9 p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% I8 b3 D1 b7 `2 |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# [( J: ]. g% L8 M( t8 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' [& ^; P4 B; F! Y P9 x
}
7 S. t( @" }3 u3 f$ R) V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * j' O v+ A0 c5 V
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