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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: k, D$ A+ x- @8 C7 Pinput mcasp_ahclkx,
y$ l! Q/ f( C6 g) k$ Ginput mcasp_aclkx,
y; z! v" J* @8 K* w$ n4 O" Qinput axr0,
W7 P8 K }3 y; n8 A u- x! m: t% w" I8 F5 X3 t5 M2 M6 L
output mcasp_afsr,# }& K0 l: r1 t$ z( |4 O0 `+ G
output mcasp_ahclkr,2 T" h/ @ p, [" n( u% b
output mcasp_aclkr,' s, S z; d' d
output axr1,/ Y2 l7 V0 C5 [/ _' ^2 f# x
assign mcasp_afsr = mcasp_afsx;
7 f4 O5 J8 U$ j. `/ v8 Iassign mcasp_aclkr = mcasp_aclkx;
8 x6 X/ G/ c% W& r. @9 G$ a/ B5 sassign mcasp_ahclkr = mcasp_ahclkx;4 j- A, t% s# Y7 A8 l1 K) o5 O( p- P
assign axr1 = axr0; ' o7 s+ z J# @( S
1 n# S2 a# P" I! [3 Z9 i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; F k7 j1 }% g8 Y( l( ? y# f' o Z
static void McASPI2SConfigure(void)1 j' I! I* Q- N) [
{+ f+ q, {$ r+ r3 a" ^. p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 |3 D& t) r. C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 E8 N# v* K! Y& ?: jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 B4 A2 R( u" f- NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 P# _0 _& j: M. O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 j) p9 m: i5 I' y- V9 VMCASP_RX_MODE_DMA);
% _* r u0 G6 G, UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& }' G4 Y* E! w/ W5 y DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 _, |% ?# n( V$ }% y3 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ {( E8 i' _& R7 q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* ^9 t1 T$ r' F2 U9 W6 YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 ?/ ?6 F& ^4 t" s! M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! k% h7 u. O" [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 i D, R! @/ t. k, b% [9 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' J7 i+ r- y6 {) t/ ?6 C" [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 T. h6 `; l/ k
0x00, 0xFF); /* configure the clock for transmitter */
1 g6 Q* r" E5 F0 |1 v# RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' U3 s8 u8 b& L9 J* j: Z! ^- ~7 c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : h! z9 o. I$ f" {6 f9 d; ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. X6 e0 Q: h5 I/ e: F( D1 E0x00, 0xFF);3 n: N5 c, `5 q( a
' R0 D. u$ f8 ?# B1 C) _/* Enable synchronization of RX and TX sections */
& ^" ~- P6 _% C& F2 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" C) v1 }4 F5 t' rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" w* x Z" r. n$ R# ~# l4 L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, s- u, o* O' h% r
** Set the serializers, Currently only one serializer is set as" O2 X" V! K5 o) M8 K" i
** transmitter and one serializer as receiver.
5 ^0 y' J4 G) O& Y0 z*/. q* ^: Q6 c0 \& v1 O9 }* d3 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& M7 P% m% B3 s f: V& RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) z1 w3 a: N7 X9 j% p** Configure the McASP pins $ U0 D, e; n+ C7 }; G) Q, k3 Q
** Input - Frame Sync, Clock and Serializer Rx
P% @9 {" ]% G0 K4 F1 B( M/ } ^** Output - Serializer Tx is connected to the input of the codec % F& N* T' @3 U W4 |( h
*/
' A2 F8 Z) B1 ^. X- U; OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ L7 d% S i+ W r( D! g1 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" l5 ]# n6 J5 h) K" @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 e% s/ ^1 f! S( `8 r! w9 P; ^
| MCASP_PIN_ACLKX
% Y- f! `8 H! x w! d5 C1 B# a| MCASP_PIN_AHCLKX
x( z w x) x W3 [ j F$ e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. ]$ v3 j1 U& f( o4 fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 ^% H9 h3 g+ c$ w6 c/ g% k# ^| MCASP_TX_CLKFAIL + h( l- I) s0 e
| MCASP_TX_SYNCERROR
8 n# A ~3 ]0 F! h' `1 Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# @- Z3 n/ ]+ c% W# g| MCASP_RX_CLKFAIL
, |' e( ]+ _4 f! A; M5 F6 l| MCASP_RX_SYNCERROR
R: J% s* S5 J, D| MCASP_RX_OVERRUN);0 h8 f& w, N* T# R. o2 m# W( e* p! w
} static void I2SDataTxRxActivate(void)
. }6 N1 M: B9 i+ C{9 [) f# |9 m7 r: ^. E3 {7 w; ?
/* Start the clocks */
' [$ V7 m; o# u9 q6 g. y: D# TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 ~& }$ X) e# {0 i _, V( Z* E$ mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( c) z5 W* u" u4 j1 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 B" A9 a& N6 Q2 GEDMA3_TRIG_MODE_EVENT);8 {+ w( K; a4 \- U2 ~3 Y0 ?3 O+ H! N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 P$ C* g- E+ H6 Z+ s$ _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( l" B, }2 I5 C: v/ a. l- aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
F* l$ P+ _- J. \2 |( dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ t2 S- X8 H E t. k; x2 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 [% v9 s7 a# X" ?; TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" G g3 `- a0 h# b; J3 fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# Z8 F' f1 F: O} , o |& |9 b( t* Y2 q: \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( j) f; L6 k1 l
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