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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) o. X8 `/ v# S7 L$ N/ v0 ~
input mcasp_ahclkx,
) ]' R" h9 Y: [input mcasp_aclkx,
) x8 V* f/ q4 c; q0 ~input axr0,( z1 I+ o( `2 e/ K; S; _
+ R( b. C7 t6 Moutput mcasp_afsr,
9 x5 B1 j% M |) D, ?( zoutput mcasp_ahclkr,
3 X$ ?+ v! C4 E8 L6 ^ }output mcasp_aclkr,
' n$ X1 U- _$ Voutput axr1,
" v; Z; }4 }2 o$ U$ Y6 ~ F assign mcasp_afsr = mcasp_afsx;
) d% r- U. F, _2 W4 hassign mcasp_aclkr = mcasp_aclkx;) s' p# L2 ~! M! S6 C/ [
assign mcasp_ahclkr = mcasp_ahclkx;! K X0 W) b% Z: H& F+ ^
assign axr1 = axr0;
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7 c1 C4 ?9 A0 w Q: J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 g+ ?" p, H s6 j; R1 G7 Y+ g
static void McASPI2SConfigure(void)
& [9 @4 b6 |4 g! u/ m{
( @1 x" @1 N; F. t) q) X1 }McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ M1 S* ~1 n0 c* l, R g. ]7 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' f6 q8 p& t5 ^2 }5 M% M$ n: g3 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- h$ D4 h5 i% Q! |7 N6 `- m4 ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 e0 C2 k$ ^; G( h9 N- q) W3 jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* h0 } b) {4 u2 e5 e0 D6 @! K8 r: k3 @' J$ I
MCASP_RX_MODE_DMA);
( e. Q [+ F9 D! i/ J) a8 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 P3 _+ i9 _+ g! c7 C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 y6 c8 \: M& \4 g3 t6 w" qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 n8 \0 P/ H; u& X; O/ U- ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 V \9 a3 l8 l8 `* l, a$ X9 bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ u& p) i$ z/ |5 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 F8 Q. _2 F& Y2 D# L4 @; FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 a4 w1 {& C# M+ v1 g4 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 i; ]! g Y% W7 }" I# M* d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. E- B4 I3 e1 C1 j* q0 H; B% i0x00, 0xFF); /* configure the clock for transmitter */5 Y( B2 @4 G5 k* Q: q$ g3 }2 G8 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: R5 _1 _$ r1 B8 r% t7 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 ]! T5 x+ L3 F/ k1 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' s" q+ i7 H* L+ U& S4 R, q0x00, 0xFF);# H5 H+ ~0 N8 r3 d; `
5 K5 C4 I/ n6 d. S. c1 ^1 T
/* Enable synchronization of RX and TX sections */
3 v7 e; r8 ~: c+ B- T2 }8 I2 W2 L0 |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" k1 @# I4 H) J; v* n* E" H9 s% rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" Y; [; {) _; }* l% S9 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' n+ W/ c* S2 W5 @2 k @4 ~1 g' H2 _
** Set the serializers, Currently only one serializer is set as- h9 `+ @3 y8 Y. Z( W5 x$ H. N( P
** transmitter and one serializer as receiver.
( ?2 w2 z( k4 [+ y, p$ @*/' T, r" {3 l/ N) A5 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 U4 f% B4 S5 n1 D( Y; y) O; Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 X \, P) p" ?5 a0 B
** Configure the McASP pins
! e8 a' C9 j% _* y+ M' T/ s" T** Input - Frame Sync, Clock and Serializer Rx7 i# P" x2 T2 O4 F
** Output - Serializer Tx is connected to the input of the codec
0 I {' V9 m# u- v w# @: t/ J*/
7 f) I, l+ j/ n- i4 M! hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ e( C0 b( l* _# J" VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, I; h3 J# D5 r9 |+ O. N( m( K: iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ t C% h. O3 x5 o. G; D9 X& J: W! p| MCASP_PIN_ACLKX
8 B; ]6 t6 s+ A% e9 o| MCASP_PIN_AHCLKX4 R2 E) p+ i/ B; M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( U1 B0 n9 o/ ?# n/ w# ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- z9 m% [9 O1 J- c| MCASP_TX_CLKFAIL
3 Q7 F1 L; m3 ~2 H' z| MCASP_TX_SYNCERROR
. m/ u. `7 y$ C, ^7 l9 b5 f) `& || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & v- L1 Y2 ~1 u3 S7 [$ i* [; c
| MCASP_RX_CLKFAIL* e ?1 ]& U5 O& O$ L& Y' z z
| MCASP_RX_SYNCERROR
3 Z e# D( ~/ V* P| MCASP_RX_OVERRUN);
x7 B2 v9 z# a3 z9 ~# s} static void I2SDataTxRxActivate(void)+ ^, m+ A& M8 t" C$ O$ p
{2 Q1 A6 T' H6 C3 \2 B; t. ]: C
/* Start the clocks */: o6 ]/ v3 f: m- Y* K6 G" p! D1 ?9 d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% m+ G5 ^: v7 X# ~" q+ YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 h6 v/ C6 _- a# l, ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ x' g9 Z& H; qEDMA3_TRIG_MODE_EVENT);
" P7 s+ n; r# _" u1 f. P0 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ C7 t& S4 g) z2 F6 \2 @! fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( ?7 ?8 K3 {* r( r2 K' DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# R4 E* a" N# [' b( h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 I* }0 S0 i/ V2 z! @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. S( J' x X+ O% n G8 Z4 H Q" G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. p! S5 W- L* l1 w4 W# a* ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 P; \6 j# D& D% R' [
} 9 F" Z9 M- [: w) B/ t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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