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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 L$ X; e j n2 D- W$ ~
input mcasp_ahclkx,
/ d9 i. J) M. G, L+ i+ w8 S% Z# pinput mcasp_aclkx,$ l& l3 ?& Z* u, Z
input axr0,% y, G' f; o8 U& N7 j
0 ^# ~; i( ^+ N% S
output mcasp_afsr,
- I- G1 V1 W# y# joutput mcasp_ahclkr,% o& O" p2 k6 r- H
output mcasp_aclkr,) J0 M6 o+ n1 ]/ f
output axr1,' r8 ]3 I. t: n2 Z" b9 `
assign mcasp_afsr = mcasp_afsx;0 K/ U5 Z! g' q3 p- ~$ G
assign mcasp_aclkr = mcasp_aclkx;
' z# b) b; P( @5 Z) Gassign mcasp_ahclkr = mcasp_ahclkx;
: } B* _ q; o& U0 V- R3 G* B( fassign axr1 = axr0;
4 Q- |: h/ F5 y- Z
0 L& `5 G) ]' G9 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 m- M0 w4 z' M- a) ?# X! J n7 b
static void McASPI2SConfigure(void)
e% C( K2 ?9 W4 k2 F{
& W6 _8 ^6 ~+ \: |- T& [" Z( y) aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( G0 H0 K4 D7 h6 b: q, o, \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 j+ \, X: H8 f- CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# q; y( K, n% x$ } O/ @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% y. Q% G: c+ L( G0 |9 \" \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( `( I: E( l. ~: X* P1 r
MCASP_RX_MODE_DMA);; E9 [/ {3 S$ z: T( ?: w: B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: s) ^) X x& j3 H/ {2 tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 G9 w# @, s/ C: M; q4 `8 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 A) G2 _2 L' g5 j9 L: g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
P# q' r" X1 j4 w( \; i6 |9 NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 U. B X7 O0 q* w1 Q) a" y7 SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 t5 x, o$ K" z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# W0 ~9 u0 N3 ^5 f# B; T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 U$ p9 P0 N! k1 }" vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, e, N4 v) x7 V
0x00, 0xFF); /* configure the clock for transmitter */% s6 l6 N- [* \# \8 k# }$ z- K9 p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; x. e5 J6 |, oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + M2 N' S7 k1 {5 {5 H! A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# l" N1 |8 h! i+ Z/ b& v/ s0x00, 0xFF);
2 n' c: g- C# F* @0 z2 {! |( w+ H9 p6 x' E# X
/* Enable synchronization of RX and TX sections */ 8 F+ u3 o2 F: D1 I$ p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; E; {4 I# H: ?2 F4 D, ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 ^9 `$ ~4 P& V# J* e$ O8 U- R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 f( Z5 N9 R5 d' ^
** Set the serializers, Currently only one serializer is set as
/ o( t" f3 @) k( g6 ~% F; m** transmitter and one serializer as receiver./ u4 z# H$ I; a+ r0 ]
*/
! A3 P A" }9 A* {* MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ S1 W" u' R; V @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 N, |. @' |" Y2 W; j) T- s4 F
** Configure the McASP pins * a7 k: P" L( A& s( E0 u
** Input - Frame Sync, Clock and Serializer Rx
, H# B3 c& W# @$ V I+ r** Output - Serializer Tx is connected to the input of the codec
" `. {+ }( s- @2 g$ x3 H2 ~*/4 q. B: [9 p: S. V1 ^/ h6 V, D' j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, G/ B+ u, K1 p6 A7 v7 M3 Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ ^. F+ E* a$ n( tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX a" Z& C8 Q6 B
| MCASP_PIN_ACLKX' Z/ f0 i5 i N1 }# T
| MCASP_PIN_AHCLKX, V5 W# r y; J# l, L& t' K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# [. K1 D' w8 Z& E) W o5 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 t" o. |9 ~, N5 ]8 O* || MCASP_TX_CLKFAIL & R2 a7 ~0 n( M. A6 N
| MCASP_TX_SYNCERROR
+ f* ~$ M9 y" t. z2 Q+ |: n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . [* Z4 O$ x9 A( y4 j5 m+ M
| MCASP_RX_CLKFAIL
" D" U% C- R. M9 L. T| MCASP_RX_SYNCERROR 9 a# j1 o% A6 y# G+ U& E% `
| MCASP_RX_OVERRUN);( I2 e& e* M& i7 D3 B( ^6 p4 {
} static void I2SDataTxRxActivate(void)
2 `$ j* K3 N' b{
5 e0 Z+ `" l! M6 S/* Start the clocks */$ s1 X: I4 P7 o" o/ @& F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" i# _* h9 G$ c! ^: sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( \- D" Y! Q4 ]5 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( l4 w5 @2 j4 ?' x5 s& n- ]
EDMA3_TRIG_MODE_EVENT);
1 L7 A) b; _: F2 O/ FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: h5 C; F: ?- L3 P HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 s" ?* }8 K5 h0 d5 Q) TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ r4 @2 v6 U# {6 ^$ P) s u# |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) j) T1 ?8 d; S+ P& R9 L$ [$ @- f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! T$ e! f4 W/ T6 s; g, m& s! FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 i+ C7 w- c: z; fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 y* p h1 C, `' h' c3 ]
}
6 n4 p# a+ e2 k* B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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