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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 c# V# ]. g0 J1 k* Winput mcasp_ahclkx,& a7 a2 v/ g, U3 @
input mcasp_aclkx,& B# ^" `+ ]0 A4 R7 R1 E2 p1 u( j
input axr0,
) z7 X& y0 T$ D9 ]/ k: R+ b$ a0 u4 v& C3 |3 u# B
output mcasp_afsr,
1 l6 ?2 S' I h4 S! B& k2 boutput mcasp_ahclkr,; g: R U- D- B0 A) V1 ~
output mcasp_aclkr,
9 x2 t+ ?8 @$ O% B7 U( Z/ h2 Doutput axr1,$ T& G2 y7 ~! D5 F
assign mcasp_afsr = mcasp_afsx;
( a6 T. k* {( A c6 w. T" kassign mcasp_aclkr = mcasp_aclkx;6 j* F# T7 Q4 o) n: t( x
assign mcasp_ahclkr = mcasp_ahclkx;2 ? G6 Z9 N4 D, C
assign axr1 = axr0;
: W( s. d$ E6 k& X/ M' K K0 F& R) G/ ^) k/ o& r+ R8 j* V4 c- l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 T7 n K* i( \6 N% Z; K+ K# d! p9 @
static void McASPI2SConfigure(void)& D: F+ G$ E- W% i9 @1 @
{
& I. @: S' V6 `/ G7 z4 R6 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, D, W( Q- Z6 GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 Q5 g% j: c5 e, v- [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ x4 O! D: F. o$ f" \" Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 ?3 w( G; X" Q! |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! {- p* E2 e% i dMCASP_RX_MODE_DMA);
6 \0 p2 W* g1 F+ m5 D) P1 jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: T$ s+ z3 i) k, b& Z& A. j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; K/ `! p* \! k6 wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. p& ]$ p; O D; n; r$ @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* z b7 P8 ~4 D& R4 x% a" P! ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & _9 q/ Z8 k2 x' F" e) T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% i9 Q! ]* o) H1 N2 L- \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: r( [ a5 P1 ?5 k$ h1 \. e& o( ]; Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 K# r6 R/ L1 n2 ~. U7 }3 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 W: L+ C9 d" ~6 e3 |0x00, 0xFF); /* configure the clock for transmitter */
/ X" l, I9 o9 a3 H( ]3 ^% o" IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 |3 n6 D$ q. L! X% O4 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ w$ K" S$ Q: Q! M7 LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& l( I# ]& P+ N0x00, 0xFF);( W0 ]0 U0 @! f2 i( R6 [' L
. I8 D% N' N# Q2 H/ S- J
/* Enable synchronization of RX and TX sections */ ) x( \. G0 \0 y+ h/ @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# ^# D( h+ A; W( N- D$ cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 v2 J6 C1 h' h2 n! P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; q' z: l+ z# T2 @9 y
** Set the serializers, Currently only one serializer is set as
, e- X9 V; r+ \5 X( m** transmitter and one serializer as receiver.; u- }* o w" S! m+ H, n
*/0 A: ?* ]8 p' c* @2 ?" d1 w8 P# ^8 F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) }7 X( f% t0 e* e nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: A: d# W/ z1 n9 M) h; a
** Configure the McASP pins
1 T# a5 g) f7 l- s6 m$ Z# o6 G; x** Input - Frame Sync, Clock and Serializer Rx
( U U& W% ]0 {4 G* q** Output - Serializer Tx is connected to the input of the codec
q7 N* a' ^3 O5 h# ]( \ Y# ?$ U*/8 P: x& ~. @8 c- P! X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 A0 A) Q- V* Y+ v/ m) O i% d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 r" Y7 ]+ }) ?' O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 K% y4 U8 H/ C. k# w. S
| MCASP_PIN_ACLKX
9 m6 x' e: q9 v; ?! ~1 X! ?| MCASP_PIN_AHCLKX
+ c0 J3 K0 Q5 S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% t% d2 @' Q' H' U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 h$ H7 c% |2 @- [* M1 W
| MCASP_TX_CLKFAIL
, ?4 R7 `* a/ h7 {5 D7 q+ S$ u| MCASP_TX_SYNCERROR9 t; p! l! L5 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( c1 b% _5 q+ x( T; x- s6 N4 R| MCASP_RX_CLKFAIL% |& C! y2 Z# _, O. M8 h8 q4 \* h. O
| MCASP_RX_SYNCERROR
9 M. F+ J# Y( c| MCASP_RX_OVERRUN);
# H" F' n5 Q. F} static void I2SDataTxRxActivate(void) z1 J' |/ V* ]+ D
{
8 u* O% x0 |5 ~8 x/* Start the clocks */
* U+ ]) G, a; tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ ~4 q3 U) o4 D: CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& O' E) D6 V% Z5 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- Z9 k3 N: R0 |7 u( Q: LEDMA3_TRIG_MODE_EVENT);
: N' z& ~5 B# ?, L( w2 J, hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 H, T. E# Y, I2 {) p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# C) Y# [* N& Y6 q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 J7 L3 h9 ?: I8 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- P+ x6 f$ J7 B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 g9 s4 {9 C8 l- M2 A3 I0 \+ P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" f* u7 e+ [0 E: cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" y+ |0 e& `! j) Y! H6 P} 1 L. Y4 j. [7 Z$ `& q4 z% E* O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 {- g1 j/ E# A# p/ W4 e7 Z+ O
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