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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. F, }. |) p2 g. i; x9 y& G
input mcasp_ahclkx,
% R) K& W5 z: V; C7 q: q L Hinput mcasp_aclkx,* V7 i: r4 S* n. ^# E7 k
input axr0,- G0 s0 l# i& W4 s) D- m
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output mcasp_afsr,
6 g* ~. X+ G" G4 U/ p& \8 ? \output mcasp_ahclkr,
* p( s% Y; E4 @. houtput mcasp_aclkr,; v0 M3 `* q! V% j! F
output axr1,2 Q. K; v% R& [, t+ ]6 p- p
assign mcasp_afsr = mcasp_afsx;
( f8 k. A9 t! c% J* wassign mcasp_aclkr = mcasp_aclkx;
9 ?5 v8 A# R# ^ v# F9 lassign mcasp_ahclkr = mcasp_ahclkx;
) L0 {# R7 I! @: massign axr1 = axr0;
* i5 g5 G$ q( b# [" v
7 T" u% F# K8 m+ O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , `, M% @$ Q# b! r0 A" h: U
static void McASPI2SConfigure(void)1 G: n6 M. X) }/ |% e; c
{
, x: P& ^3 c2 X0 g/ jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 [, m1 ^/ \6 _/ M7 O4 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 K, V, O' }) ?/ e2 g; IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( n5 H. P$ C. C' i" hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, {. D g! j: ]! u2 U, iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ F6 `: C$ W1 y8 S( h' A6 u6 JMCASP_RX_MODE_DMA);
/ P! j/ ]( ?" {) T! K% @; J1 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ M7 ]" V1 d/ ~7 ?9 l3 n5 D, I: |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ N/ `' C! m$ V- W& Q5 OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 I6 T' v# u: u- i0 f4 ? A. Y. EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 [3 M; f( d; `0 S6 i# J8 g5 FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ ]) |$ E/ T: V r$ g9 q) S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 y! n2 l! @+ a0 A' O7 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# U$ @4 d g3 E* P% Y/ ^/ u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ y0 W1 _* T' S( o2 B! B" }9 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! e# Y! o9 e$ \7 R0x00, 0xFF); /* configure the clock for transmitter */3 r7 T; w( A$ A; X* |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 }9 c; [4 g1 q, k& b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- E1 q! a7 W$ z! w+ _ CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ v7 {9 s6 G5 n: x8 F" J v0x00, 0xFF);. E7 A" [5 J5 |( [+ v* C; i
: z+ n; M9 D2 v9 {! v2 P) `5 Y/* Enable synchronization of RX and TX sections */ & |: X$ S3 P3 f. ]9 J5 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% v8 G% a! m5 QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# o: f5 Q' X5 S" N3 b2 V2 F- h# r/ OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. [) p, l2 v1 W! j** Set the serializers, Currently only one serializer is set as6 p) o2 B- `* t. r% k, g8 K3 @3 ~& f
** transmitter and one serializer as receiver.
6 b3 t. X; S3 _% @" E* Y*// D9 o/ o8 ^; O/ y. g3 m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, V/ L! `8 X0 j7 V( N* ?, p6 w$ ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
E7 M2 |2 O" q** Configure the McASP pins 3 w$ J7 l- g5 L+ R
** Input - Frame Sync, Clock and Serializer Rx
1 D2 i0 [ I# |! v** Output - Serializer Tx is connected to the input of the codec
) G" I. c6 i- W, V4 P# J( t( Z*/" o- r. u4 \: Z$ p% I( e; g4 L& v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; L5 ~2 Z7 K4 g0 q- @6 m/ Y M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& Z! c) V: \3 {+ eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' | C+ J8 s0 ?9 J- G' y: E( l& [0 b `| MCASP_PIN_ACLKX
0 A; w% j# B8 W9 R5 j* B| MCASP_PIN_AHCLKX
; c0 s6 h8 a7 p$ c7 z- c8 U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* ^1 C3 \+ B& e' v* w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 B: h2 m" W9 [" _| MCASP_TX_CLKFAIL ; O8 Y8 R1 C+ e5 T- c2 M" R
| MCASP_TX_SYNCERROR
4 x9 O8 g! I5 m& }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ Q/ W" [; p" z" O| MCASP_RX_CLKFAIL" h" I( B. l( W/ q, q7 {
| MCASP_RX_SYNCERROR
8 m+ V1 U6 s/ X| MCASP_RX_OVERRUN);2 @! H6 f/ K9 Q8 `8 O
} static void I2SDataTxRxActivate(void)6 r: E5 n+ m, T
{
0 O: K. g# g% B5 A# Z7 N1 b/* Start the clocks */
- r# ]2 a( X- K$ P1 A; I/ HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, v7 w F/ `) E4 G" J# o9 i# FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 S) R' |! d+ B" {4 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 P% g$ i0 k+ J [
EDMA3_TRIG_MODE_EVENT);
' F2 [3 X: B3 v7 D9 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 ~( B- `4 c% y% X5 z6 n( N X- NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' k% b p3 R+ DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, P# r3 `8 G" L- }% L1 a1 ]# _+ e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ l; l0 O/ K- J0 l: e* B) a$ P: ^ qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& E- Z# U r1 w% D) c' e3 AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# [( o. m f" ^' V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); o$ V- B; c% @0 u7 [' x( J" Z
}
- l H3 e" L" G! M8 S! |& V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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