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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 D. M/ L0 S2 N# X$ A V4 l
input mcasp_ahclkx,6 Y$ |# i" J6 ^' o" {5 q1 H
input mcasp_aclkx,
, X; n1 i, e4 }% p, I$ Ainput axr0,- Q# U% @, X" s* E
; v/ l8 x: |+ _1 m0 p
output mcasp_afsr,
" ?' f& q3 |+ C$ W! x# O( C3 v9 t! woutput mcasp_ahclkr,
4 e7 p# A/ r9 ]3 c" v# I+ houtput mcasp_aclkr,
# x7 R t0 ], G1 E- k! Moutput axr1,
# r9 ^3 Y7 x% \; E- J. B4 P2 X. D assign mcasp_afsr = mcasp_afsx;
) L& g- c4 t- _assign mcasp_aclkr = mcasp_aclkx;1 h6 n9 Y1 x2 C% Y# y
assign mcasp_ahclkr = mcasp_ahclkx;) u0 Y. ?8 P' g+ d1 T- ^
assign axr1 = axr0; f+ u% D/ }9 F4 n
4 Z& t2 k, r! @: a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' f7 _$ n( w/ b$ k: gstatic void McASPI2SConfigure(void)- f1 E8 L# M. G+ Q
{
L9 k- K9 \+ D% i% yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# o' F; @: U+ M+ b9 ^4 YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 q3 a" u3 b8 \' K( }. RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; `/ F# G" K1 v* X! q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) d5 Q) E- T( i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. l' S, p8 o1 I) i9 v' F. ~MCASP_RX_MODE_DMA);4 X7 F) U8 L( J0 a1 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 J% z( s% C% E: `4 b( l7 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 v: p9 z2 |0 Z) ]$ r" \! r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 w* G/ P' Z: o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 I% ~" @% s$ | `0 i: ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, x) U# b4 Y- A, u9 Y7 G+ `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 Z0 q* C; T: U) qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, L8 C( x+ V9 A: E! Z. B }3 }: F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 d8 j c7 \$ q8 G) t9 I7 S- @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; k: m) t8 x9 X" j
0x00, 0xFF); /* configure the clock for transmitter */2 W0 m% f! z0 x9 a* }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* }& |' c5 I5 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; _5 J5 J6 ^7 c) J" B! N- \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) R1 Q- }7 k% |! c. X4 u6 Z0 L* c0x00, 0xFF); J( U3 W# ?+ |7 D; i
e' W. u7 i4 ^) w) r q7 ]
/* Enable synchronization of RX and TX sections */ , m% P$ T1 z1 t: v; x4 W1 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 X- i! q0 U- q& ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ P" P* l' v! F; U# v; ~* jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! k: N2 P6 O4 x4 x) e! A0 L** Set the serializers, Currently only one serializer is set as9 R" \* B# R3 g8 D. M
** transmitter and one serializer as receiver.
' ~, O0 c% h- d- W8 U/ ?*/
2 S" `6 W `# b% d6 u: WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 f+ i2 H( v# L9 |8 d: b2 R9 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* A$ D4 Z& k* K) w/ _- h** Configure the McASP pins 6 W% o/ c9 E5 u) d6 ^) n
** Input - Frame Sync, Clock and Serializer Rx. Q& i' q, q; o1 H. C4 m; {
** Output - Serializer Tx is connected to the input of the codec 8 b* g9 @* B# G: w6 m) \
*/
. ]& F' | b( l$ ^9 P# \- YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 ]2 `9 H6 a2 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ q" s% n+ ~: K5 b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 X2 T; L' K( |$ C0 b
| MCASP_PIN_ACLKX) S) \: \( f G0 o1 q& K
| MCASP_PIN_AHCLKX
X: n7 M# u9 y# c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 [( v" U$ m. |* g/ G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + I5 f2 H! `4 y5 a9 n }" `, u
| MCASP_TX_CLKFAIL - ^4 Z( T( q3 H/ v( `
| MCASP_TX_SYNCERROR
7 q! B5 ~+ h, e# t8 ]5 J4 n+ c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) S- M+ W+ g7 j0 D| MCASP_RX_CLKFAIL
( {4 j7 A% [# ~| MCASP_RX_SYNCERROR
( S+ g* i7 L6 R: ]| MCASP_RX_OVERRUN);
$ R$ Q# q* @; Y! Y( i! c} static void I2SDataTxRxActivate(void)
2 ?6 S" F l* x4 s! V: t0 P- U{
! O% y% _% W, l# V5 B" ~/* Start the clocks */
# p' Z& Z: c, [% HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" C- c! T& G7 C' L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 ]% Y% Q( q7 I2 [) z! p3 n6 y! d& gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- }8 g% H+ [9 S- `' _) L
EDMA3_TRIG_MODE_EVENT);2 ?7 Q2 O% f& ]" r% B/ |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
j" |* u* N# z7 @) R2 G; IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, q. B# a, b3 l3 t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 ]7 ?2 y( \/ d" h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ \' p- j. c$ Y8 W$ W. B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, j. u! P# d) Q1 y$ k5 a; qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 t& c* F: m) N5 P; M5 N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 Z; {4 o! |* y* A3 V M% E
} & r1 i9 _# }* }+ F6 s2 K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 s8 Z+ n* q- F. }- D2 i8 w
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