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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) b( s$ j% `" }) Oinput mcasp_ahclkx,
* J3 k4 k: B. p1 D I9 X ^+ dinput mcasp_aclkx,5 Z6 {8 w$ y- \- Y4 w6 O
input axr0,, j, Q* _0 o- a2 H4 r) z+ E3 N
v4 @$ ^: a, i* Z" G2 m
output mcasp_afsr,2 O9 N, L1 m0 j
output mcasp_ahclkr,- y( K A/ ^" n/ W$ a/ t
output mcasp_aclkr,3 b5 K4 e7 Y5 M0 F% z
output axr1,; b# }# ] [6 A# f
assign mcasp_afsr = mcasp_afsx;0 E; w( @1 _% G# Z
assign mcasp_aclkr = mcasp_aclkx;) `7 `. D: m8 |: E4 v5 k/ B/ `% U
assign mcasp_ahclkr = mcasp_ahclkx;
- _/ F6 r/ V& X+ y& C* nassign axr1 = axr0; , S' a6 }* @# E
7 ]$ ?: u- u7 `1 {9 Q$ q! P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, d& F# W1 j0 N$ F6 \4 \) x" ?static void McASPI2SConfigure(void)
$ b9 _* H3 s! j" V" z{* f8 p: x9 R/ T$ Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 `/ R& l: _9 K7 s1 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& B5 T8 H+ } R2 l3 K( S6 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( P+ x! g" a( W2 D; M7 Z4 I9 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% k* [- Z9 i/ v Q7 H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 H. M& i$ }9 l* C- MMCASP_RX_MODE_DMA);9 M- o6 r, o5 Y" j* l% X( p5 V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 o7 P u4 N2 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* T+ K* k% c4 ~, n$ t0 i; aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( i$ t+ F* t+ j+ o+ B: s @* U! [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ a9 {6 u; P: p3 X( L: v1 D* D* X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) r4 p+ H% r" @" GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# ^ F0 C9 Q3 [6 D7 U% p0 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, g" T8 g% q% E. x* rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- W7 Y! @1 ]: SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 T* q) X) ^" ? n0x00, 0xFF); /* configure the clock for transmitter */
3 B, [( m2 t0 v, Q" I" ]) kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* V7 }1 S( Y+ c- Z) @; X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. z( V7 C4 C7 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 ]+ ^' F! s9 K2 f- B
0x00, 0xFF);" }6 n. G) u, A0 f: w4 h5 }, |$ W8 [
+ [$ u, R- @5 T/ R
/* Enable synchronization of RX and TX sections */
5 y* [) g K4 {" WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 A% j2 k1 {4 H( r& N' A) t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( G, f5 m/ ? Y+ z2 x' eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 \/ p- U# E7 O! o/ K% c9 f1 C** Set the serializers, Currently only one serializer is set as& V, ~, @- E! Z6 ^: X0 X
** transmitter and one serializer as receiver.
* R" ?( E9 I* \' q) ~2 u+ o0 L*/
3 C# }% m% g+ PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% [" A7 g% Q$ i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, U9 l; U( L: {# L$ K$ @5 t** Configure the McASP pins 7 _+ P" o# U" f) V
** Input - Frame Sync, Clock and Serializer Rx! X7 { Y. y; n* s# I; Z; Q
** Output - Serializer Tx is connected to the input of the codec
, C& h( o3 }4 V$ t; ]*/
! b' q2 I+ A& CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- ~! q/ z6 Z |/ H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* G+ K/ n! n+ g2 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) D4 v4 N. @$ U q| MCASP_PIN_ACLKX
5 L! \2 [: S1 t) j2 H; @# K( p| MCASP_PIN_AHCLKX2 H! j4 D Z G4 g o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 Z+ o$ k( d; a: d% C+ t. K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ }, d: H0 y8 E2 y* v" A
| MCASP_TX_CLKFAIL 1 o( U; W* c5 b9 u: [& Z, V
| MCASP_TX_SYNCERROR: h' S( S. u S" o- ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: M7 F' P* O% ~0 k9 @| MCASP_RX_CLKFAIL
8 o w1 k, N" B) }8 V8 d- C| MCASP_RX_SYNCERROR
6 i" k# T& \/ ?6 R/ i, X H2 p| MCASP_RX_OVERRUN);
; u+ Z# f/ ~, C} static void I2SDataTxRxActivate(void)
6 L9 I( F- A" f4 t{9 L, c3 n3 } q/ C3 ?5 P8 p; u
/* Start the clocks */
" C( z0 \( M$ E' \( z2 S/ a7 H; |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! Z. c5 x! K( ^0 c# rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# p+ P. I3 _/ x) D8 B8 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- Q5 G7 R. ^0 I
EDMA3_TRIG_MODE_EVENT);: g# W9 l. \( V+ x& O2 l0 a, f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - f) Q4 j5 z1 Z5 f- M* j5 N& c5 q0 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& m( {! x3 W9 [) K' `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 q0 z- a3 ]$ q6 C7 K1 W# PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' F1 q; a' y1 t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ Y* d3 C M% k9 \+ |8 }# } T% S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ L& Z3 u9 U: LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 {0 i" v; }; k. f2 h) J2 X# I}
$ e; g" }# x- R$ S2 Q8 G4 O& \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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