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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 x1 b" y- k# u5 b2 P$ e4 zinput mcasp_ahclkx,
8 U0 N+ \. X, ]/ m. {8 rinput mcasp_aclkx,0 c5 [7 L$ V) l9 I& R( @6 Q! z
input axr0,
& k, k4 U7 A+ \; N ]
2 ^: e/ q: i% y$ Zoutput mcasp_afsr,
Q3 J* ]# `' |6 b) Noutput mcasp_ahclkr,
9 ^. c& w! c2 y- f: E7 T1 Houtput mcasp_aclkr,3 P1 ]9 U! w& d/ E' K7 x
output axr1,
9 Y o% j% e) U assign mcasp_afsr = mcasp_afsx;
; h- e, x! j' T( K F2 |. P9 Gassign mcasp_aclkr = mcasp_aclkx;
7 Y$ ~- t& a t/ Kassign mcasp_ahclkr = mcasp_ahclkx;6 }/ V( a2 u! [ K# B. O7 K$ h
assign axr1 = axr0;
. j8 x) _6 |/ t5 H
% t0 {' }: K* E1 B- s& t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ p: P+ c% u( |' L. y5 ustatic void McASPI2SConfigure(void)
/ p/ E8 I8 z8 S{& n' T# f1 O2 M; O* @/ R, H, T- n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 Z c5 c e, q1 O1 WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ c9 u `- g2 |3 q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' t+ S4 C p/ Q* E) |4 _0 X- T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 ^4 A6 \' s- x+ V7 ~$ q4 y/ j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: |* [$ F) b( ^9 g
MCASP_RX_MODE_DMA);
' B6 \: D3 [5 W7 Q/ T# C* E* qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 s3 {% M9 N! w/ ]; K% a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, b5 |( u; e9 B9 N, e* n8 Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
S P0 U5 K" h% a6 Z( TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 t/ f+ g6 s6 M' j$ `9 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 m0 B8 d/ p" ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" O# T N, U- t' Q# v+ w6 R2 j0 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 J9 a3 P% B3 x; P. z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ f* A1 y( z% \1 h! |. L- d9 ^; `$ zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 p# }& o9 y3 v* I+ j
0x00, 0xFF); /* configure the clock for transmitter */, F! T8 r8 `9 ]& a* L9 C; l+ Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; ~; _& f* b g8 H7 V$ L, SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 f1 W* C4 ?5 l! `: i& G$ EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 a: y9 M, d C: g, j
0x00, 0xFF);
) Z, V1 q0 u) A7 B5 B# z. y g7 {
5 Z. s5 U9 g1 _( L' {) L0 Q/* Enable synchronization of RX and TX sections */ 8 Z3 i+ [% ]& D _2 T& i0 z) p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( |! H" \" r, a4 k$ A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ V8 k% y U/ }/ h3 Z3 i) K. kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** E' e% j( t* ]3 E: O5 z. @ b
** Set the serializers, Currently only one serializer is set as! c, q* W. N( }" [ e' L
** transmitter and one serializer as receiver.6 N3 F8 {/ ~) }# Y p& n
*/
1 J+ x0 m, u7 h( e& KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& x5 V7 P3 e) M) k, |7 a8 F: R" _5 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 p( B+ C: v' @& U& k3 U** Configure the McASP pins ) e% q3 i0 y0 x7 Y {, a9 I
** Input - Frame Sync, Clock and Serializer Rx/ d' X: r& [/ i1 X1 N0 \
** Output - Serializer Tx is connected to the input of the codec
# j W4 N/ R' p: \4 e5 T+ t. q*/
. O. Q# N9 v8 K( i+ AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; w' V; v) [; L) uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& J" S B; m$ T; I! a+ Y k& ^0 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 }0 M6 |. p) A* W4 b# R& a
| MCASP_PIN_ACLKX
, i$ q) G; |# j( E; j* A/ H' ]| MCASP_PIN_AHCLKX' V, E- O- S7 c- K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! p K3 W8 \4 R: X" h, {* j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 x; m% C3 R6 W# {- b- R| MCASP_TX_CLKFAIL - D) M- a) p3 Z$ s$ ]: E
| MCASP_TX_SYNCERROR
8 T( n! Q o1 p4 d3 g0 t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % z5 G4 b9 j8 O c7 {- w
| MCASP_RX_CLKFAIL. O1 `; y: S+ @: {8 {, q( j
| MCASP_RX_SYNCERROR 6 U. V- p X3 |* a' x
| MCASP_RX_OVERRUN);) i& b1 [$ E6 J2 O6 S
} static void I2SDataTxRxActivate(void)
& d. h# S% p3 [# U{
2 n6 }* O( d8 V% Q% L1 P/* Start the clocks */% Q* |1 y0 j3 Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 H; `9 A9 \' M( i; I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. h& k8 C& s0 y8 k% J2 f/ yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 e: y8 N* @# _
EDMA3_TRIG_MODE_EVENT);& A* K1 ^4 S! \* Y( ^7 M% c- |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 Y( |/ [. o! r! H) v% F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# Z+ c- A# G* r. J+ {! B) \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 a1 B: W5 z! L8 i7 e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 C$ v5 c$ N: Z) d9 r& h* S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" S/ u& |9 p8 J, a2 b" YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; g" H/ W7 k5 s6 l+ y) W1 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. \! k! P, B* K! ~) n- p; v} 4 ^) {" m, G; ?. e, L9 M* e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 M5 o3 {0 U/ }$ W. K+ I
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