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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 I) Y5 B1 B5 V5 H& w) [
input mcasp_ahclkx,1 B1 C+ I. D. R3 Z% _0 T
input mcasp_aclkx,! o- \% v9 @+ l" J! i! F
input axr0,8 N; V( o2 U% z9 V% A' Y; _6 j
$ o; h3 A' J# K- g/ ^0 L A1 O' b" n3 Uoutput mcasp_afsr,
" b) h- T. q: U+ Toutput mcasp_ahclkr,. ^4 V* A: _; N3 z7 y. l- F+ ?
output mcasp_aclkr,/ R, Y' f( F# b, F6 K
output axr1,
4 a5 K8 r5 w) X, R, D' E! T assign mcasp_afsr = mcasp_afsx;
4 g: Z# m0 a5 }7 ~assign mcasp_aclkr = mcasp_aclkx;
6 `/ H' K+ ~# b2 p* _' Kassign mcasp_ahclkr = mcasp_ahclkx;5 B4 g- Y6 Y- j( S& D
assign axr1 = axr0; % j1 u' b4 m7 A3 y
0 U. t' z. r3 s8 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ P3 g `) e) ]9 `9 U' T/ r
static void McASPI2SConfigure(void)4 Z" g4 j9 G" g4 u5 p4 f3 A6 x9 W: v
{
: l( u/ d' m! C aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ Y/ A) c9 e0 ?$ m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) w/ d; o- t8 d- K5 ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 `: D7 H; g K% }: uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 Y' F! o% @& cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, d* {5 M& k3 h; oMCASP_RX_MODE_DMA);
2 c F) [' @- `3 E/ D jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 t; Q$ S- \6 W& v: [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& S. [* {! O, q w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 y( b- F- l4 Y6 f" H2 N, L; f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 w2 _) E8 k# @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , }/ V- | z, ^. q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( l; n9 I2 k0 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 `, u! g1 L ]- ^- hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 ~0 ~/ R" x: m2 X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 f9 ~. o* D" z2 h. C8 A1 l0x00, 0xFF); /* configure the clock for transmitter */- K7 Z4 o O% e6 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ g& @7 s8 P3 _/ c$ O, QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ }$ C3 G. a# J6 Y9 A3 b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& `2 X# f* s# O; j# ~0x00, 0xFF);, I: Q0 ?! @+ A% ?
7 H$ {1 g3 K: E; I& K8 G* d
/* Enable synchronization of RX and TX sections */ 9 |1 G1 Y1 d+ [0 J& y) d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 J8 m6 B, g' A3 G0 @! j3 N6 G: E* y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); H- D7 F$ H8 m. k H" r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; h- }" Z- S# O# ~# p: K9 p6 Z2 r: X
** Set the serializers, Currently only one serializer is set as
1 ~2 ^. V& b. @4 E** transmitter and one serializer as receiver.5 Q% J; t" I3 T' ]5 x: m
*/
3 l/ N1 B5 e2 u2 _4 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; N4 Q; C4 Q% c. k2 RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 G/ [) ^5 }9 x0 b n8 n
** Configure the McASP pins
. z N8 j* h: u# r5 ~** Input - Frame Sync, Clock and Serializer Rx" R0 [/ S; a- P4 l' [& D' z7 b
** Output - Serializer Tx is connected to the input of the codec 9 m4 ]: r! u6 Y
*/
. z+ t/ R. K' s" `0 H0 P' BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 Y+ C D; M# _" y/ ^% O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. O+ }+ ~, o& S7 R0 T: ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 Y2 ~6 _% X; J
| MCASP_PIN_ACLKX
: c7 \* K) C: O" r9 p1 u| MCASP_PIN_AHCLKX5 l2 ?0 O0 x9 T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 T/ l5 I+ \; O5 Q$ O+ ?; n8 t7 m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' o' d7 o! n/ z3 l4 [
| MCASP_TX_CLKFAIL 9 Z4 U) {4 y: J6 R" t' W& Z" _# L& J! b
| MCASP_TX_SYNCERROR' [ y( }, l* \. J C+ N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) ^% C4 Y( B, T9 C' f& U
| MCASP_RX_CLKFAIL& c0 ?. ^# ]* K. w/ G" `1 j$ X& J8 H
| MCASP_RX_SYNCERROR ) F; |" v4 C6 G; X' S
| MCASP_RX_OVERRUN);
+ _6 c7 l# Q- o} static void I2SDataTxRxActivate(void)
. @" m t3 s j{+ l+ G# v; k( e: G) E% T% @# C% g1 u; q
/* Start the clocks */
! m. b v9 a! J' C3 P8 [* oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 F+ Z7 ?" }8 k9 y! m9 b1 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. f# b- K8 k1 [9 M1 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ c2 {& _/ Q5 F, ]( D. D( b9 gEDMA3_TRIG_MODE_EVENT);
# s+ L4 r! I1 S* _2 M) sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # n6 D! I' D( }" W; {+ {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. I' x& X# [4 ^8 U, e/ SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. f( V4 I( Q& d- s7 N( V3 { k( s, j% cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; r! |5 ~; ]. r1 x2 H$ [5 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 _$ C: r$ r' i5 |2 Y5 u0 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 B5 B4 M- u6 IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; \2 X+ B; w) u& a: {* |
}
; b# k/ o' e5 `) r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; o+ |. C# U* a& w* y3 D- P. s |