MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
) \* [/ m: D1 l" s! k3 Jinput mcasp_ahclkx,
( s) `; {% F* o, n* Jinput mcasp_aclkx,
8 [; Y4 v  D) _' Kinput axr0,

! t6 w( v0 {& s2 N) Y3 c* Soutput mcasp_afsr,
output mcasp_ahclkr,
+ H3 i& K$ X7 c+ a+ c- B" x& ~output mcasp_aclkr,
output axr1,
# |6 R8 f' Y' K% r

assign mcasp_afsr = mcasp_afsx;
, o; u& @6 N/ O6 x8 |, Q) c  ^$ T1 Sassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
6 [& T3 q  N* x8 e$ {, o" Passign axr1 = axr0;

" {( E; _/ d8 q) W" \) p

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
9 S2 v% x& k5 i+ T3 n{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! z" t% Q, I' o) p/ s9 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% M  B5 n* e& {& y! a! aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 J- O; w/ u: z8 T- p; ]MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 ~( ?; x6 X% K& U% XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ G' K  y" g. {0 g! J- {4 AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# D- s' V# _6 b: ~5 {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: o$ N. p$ x1 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; X1 R0 f) v0 r4 \9 x, ~/ RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* g( V0 s' j) l0x00, 0xFF);
" d  \. v' g" X- u8 ^8 P
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
& Y- X5 c1 P6 ~9 Z, D$ Z; K. k1 ^" jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
  p) M0 p# U! L# |, TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
. Q- {9 U$ j, ~1 Y/ r' D3 B** Set the serializers, Currently only one serializer is set as
) ]8 u/ j: g6 A; E* N** transmitter and one serializer as receiver.
6 y- C; ^; _5 u% L6 V*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ @1 j6 y, V+ ?$ d" Y; q+ SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
; ^& k' s5 A9 {* b, o$ A2 R** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
$ }  ?/ k) j2 HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 \1 w' U3 Y5 f. u5 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
  C7 t. J4 Y* x0 \; f! B| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
" P. g( z4 X8 Y) p+ A) S/ d: BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 G! Y0 q8 [; J  i. || MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
) n, Q4 ^- }! e| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- P. g' t8 ~/ ?: [& T| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
. h+ T, D6 ~2 O# X# S! X) k. c| MCASP_RX_OVERRUN);
7 ]1 J6 E3 B: n- {. N}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
2 j( f3 {9 i, c8 T* ~' ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 i8 f7 g( m' h* AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
2 z' a; ~4 v3 q. ?; r) uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ k, W  c1 U) _* x+ vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
7 y( G2 l% V5 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

* o3 k# s2 t' q( D) l, }" p

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.