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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% Z# Q4 n% @9 S( @1 J$ E
input mcasp_ahclkx,! `4 |2 L, p+ @& S r
input mcasp_aclkx,: m+ u+ W- R3 M. J% Q9 |9 f
input axr0,
7 V# o1 @% P3 o0 J2 g$ Z3 w' u4 d1 w* l R7 L
output mcasp_afsr,
, j8 Z, \6 S0 t* p+ Z; V/ }output mcasp_ahclkr,
1 P+ U7 K4 i3 J9 [2 H6 K7 i1 G$ Foutput mcasp_aclkr,
% ]( ]& a: t0 A' ~8 I8 @output axr1," l( `! Z% s4 D) G9 Z, _: }
assign mcasp_afsr = mcasp_afsx;
; @) G7 C1 P. I+ ^# \( massign mcasp_aclkr = mcasp_aclkx;2 Q$ K6 v' L$ s( g% Y9 l0 L5 E3 S
assign mcasp_ahclkr = mcasp_ahclkx;( I" o2 I- j' M2 H, b' F
assign axr1 = axr0; 4 G: b; o N# Q' ]
; n3 B: N% o- g2 n0 G$ \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- O1 q/ _3 X) I% y1 I3 Fstatic void McASPI2SConfigure(void)
9 H8 c9 _8 q$ F4 h: S9 I% I4 K{
1 `% n& W8 P C% UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. y6 @0 b5 ` M4 _+ dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 j. D* w B% a1 P' u) G+ }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 Y1 w. k" |9 h; z. D' WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 k5 m; d+ G. }& p# ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 T$ _. d3 J( M5 u1 Q2 LMCASP_RX_MODE_DMA);5 s0 |7 X* }; f) ~. n& O8 J: s2 C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 W, } G0 V+ M# R' Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; `0 A! q' A" R ~+ QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" a6 h& b( D i$ j7 [5 g sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. Q) o ]' x' n4 kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . z6 O3 B# ^) R. q) u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ i: _( x0 O; y& K: M6 a& O! wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) _" A7 k l1 Z# ]$ jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! W# r! g: r$ j$ n+ @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ M; \) z; m7 ]
0x00, 0xFF); /* configure the clock for transmitter */
9 R1 a9 r% d- A7 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" k$ w( Y' h p) _& i& G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) e0 [# {& b+ c/ ~- J( f+ L: ?9 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ L6 Z: S" G/ ?6 d5 B2 L" q0x00, 0xFF);
& n- L: Q) W, @- j( ~) w
: ~, `7 n& Y. b4 |" {/* Enable synchronization of RX and TX sections */ 3 ~# \ ]' i S: y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" ]9 X5 E! L* L0 K( Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ n" b' n0 S/ y& ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ @8 A: Z& o6 k** Set the serializers, Currently only one serializer is set as
' A- H4 w. {7 Z7 X" x* G3 ^/ N** transmitter and one serializer as receiver.
. K. Q& m2 p2 t2 b*/' B+ Q/ S& e9 x; r6 i5 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. i$ g% d$ ?+ S+ M/ J3 J- y" e+ tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( |- e8 B% D4 K5 m) U** Configure the McASP pins
' {$ i! g' J) `* H5 E" k8 I& k** Input - Frame Sync, Clock and Serializer Rx
! [3 S; ~4 ` g** Output - Serializer Tx is connected to the input of the codec
7 @$ J( X, X# w*/
6 @4 u* x: n4 g ]& x4 o8 P4 f4 F# X" \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 o* J; M0 d4 {5 x$ e1 \& |0 B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. ?' r. A) a0 |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 F X# H$ h5 [, c l* F
| MCASP_PIN_ACLKX) E; @% ^2 l; r# m! I
| MCASP_PIN_AHCLKX$ I& A1 R% ^+ v( Q i8 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! q! R! |9 c2 a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % E+ q4 {' ]5 p0 |! _/ {9 J
| MCASP_TX_CLKFAIL
+ D: `7 J6 P+ B. J% x/ o/ @| MCASP_TX_SYNCERROR* @7 n" H$ r# w3 b0 |8 P5 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' @& i+ ~7 X2 r| MCASP_RX_CLKFAIL
1 y/ N& |1 D( ~4 ~! k* Z| MCASP_RX_SYNCERROR
0 e0 B( x2 b$ \& h, f. I; t/ T2 x| MCASP_RX_OVERRUN);
2 X) a' J4 y4 `' G5 ?8 S. q} static void I2SDataTxRxActivate(void)4 \! I, a% u3 X* s! [) m
{# O. b2 X6 v* S/ r
/* Start the clocks */
/ z6 v3 Z1 v2 s0 v& w6 U- L3 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ D/ V I% N+ z6 V: v- Y" pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 q# ?& s# m' }5 ], HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) U7 z" k+ I* `& u0 n( l) dEDMA3_TRIG_MODE_EVENT);" O9 D8 s+ K+ k+ }* H4 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# g2 P0 T$ W8 qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ P: r. E a, w4 R0 x3 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 l3 V5 S# W% {: ` A* QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% \" Q. c- o. y2 \) q6 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 y; N/ I4 \4 L- H1 M: ^$ o* j" CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 a, A: v) k* o2 |: d0 \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. x( x) c6 S* V3 G6 u' c
}
) h- B4 P% M3 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) R: v) H1 W* r" m% b* L) N2 e
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