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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* ?* \% n9 a& e# b
input mcasp_ahclkx,
/ w; S$ A$ R! @input mcasp_aclkx,2 ] X, g7 e! I5 x( @3 q
input axr0,! {! M" x8 n, @: @
& ]; U8 u3 f1 J% Routput mcasp_afsr,% G2 o: Y- L& y6 P
output mcasp_ahclkr,; D" m3 ~6 B0 {' G6 d: y( Q& r
output mcasp_aclkr,( d z1 |* H0 J* ?! D
output axr1,. }7 i7 V- I; s
assign mcasp_afsr = mcasp_afsx;6 j, l6 W. ~7 w/ ?
assign mcasp_aclkr = mcasp_aclkx;6 v" W* x, z. y' T" I8 `
assign mcasp_ahclkr = mcasp_ahclkx;
+ M+ x5 w! |6 S( Z4 K6 Lassign axr1 = axr0;
) N8 J8 y/ t7 \9 A% R7 ^
8 Z- j/ Z. e5 h# T/ H( P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( O, s9 F4 y [; p) K0 h) U1 c; D0 n
static void McASPI2SConfigure(void)
7 N6 F7 A( H' X2 `: P{
, `0 ^) r. V: e7 o wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# U5 A G9 O7 X d) Q3 G. o8 M+ f {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" ^; [8 e, F9 R, yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) k: i& r6 i3 ^! ` y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, Q4 Y9 _, [8 c2 c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ E; x! u: u6 m+ XMCASP_RX_MODE_DMA);2 j1 w/ l9 }9 b, r( j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. R+ d2 H G/ Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ r" y9 A# _) W, X* dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + o; Q1 [& r5 F& I L' k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 c" q8 ]* _( p' J x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 i8 \% c+ k x2 z& d9 A% Z* fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 D5 B/ l% a9 f+ aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- E" l& L: g# j( P" WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 M4 r& u0 V0 \5 Y# B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, u9 W+ y9 q2 [4 T S/ _$ B* |
0x00, 0xFF); /* configure the clock for transmitter */: R, @+ a( e. \( w9 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 ^; h- A8 h# i P& U% c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . }" T0 g3 c7 L: U) x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( Y7 N1 L' t- j2 v
0x00, 0xFF);1 \" r4 ]3 Y' ?5 o# z1 {
( N! x' K3 C3 D
/* Enable synchronization of RX and TX sections */
% m/ o2 H% q% IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; O6 d8 F$ g2 [; z) i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 Q: G( w! l+ H9 X/ bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 Q! [+ H+ J9 e/ n4 ?( Z5 H: T, Z, B** Set the serializers, Currently only one serializer is set as
0 J: d/ ~6 A: d** transmitter and one serializer as receiver.3 _5 W& I/ M$ ~
*/. J0 _6 b1 W; V8 |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 p9 L3 e, D0 o$ L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) d4 B6 c" l2 E
** Configure the McASP pins . w! D$ F2 F1 S q
** Input - Frame Sync, Clock and Serializer Rx) j7 c6 r' A/ Z' g6 |8 ^9 `" l, m
** Output - Serializer Tx is connected to the input of the codec / \ d9 v( C; P. X5 F
*/
) C, e' }1 J! V6 U$ \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- F: _1 G0 Q }4 L, l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ Q9 v7 x( ?8 N/ M' y+ h) }* z8 zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 S9 q9 Z# S) g* T* U0 s. ?, q1 _
| MCASP_PIN_ACLKX6 m: B" R2 A, `" C
| MCASP_PIN_AHCLKX0 i/ m- c. w: P% p6 x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; Y4 f* F- @) K. S& u+ ~: m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ J6 o. H6 R7 v9 X: D! `| MCASP_TX_CLKFAIL * Y, r2 ?' D0 Y/ n2 k& C0 l
| MCASP_TX_SYNCERROR
/ X; t( X) X: H# V7 s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 b8 B+ o! N. Z+ r% A0 }| MCASP_RX_CLKFAIL' j% E# [$ c$ X/ @- j4 i. `8 [
| MCASP_RX_SYNCERROR 1 ?( ~- |9 I, j d2 z" a- {
| MCASP_RX_OVERRUN);9 M7 r2 Y2 X! r) q N3 o3 V0 n2 a4 [
} static void I2SDataTxRxActivate(void)
# |$ p. U3 ]9 p- B% `: M{
/ [+ T- B% k0 V) d& v* k$ @) `/* Start the clocks */
( x l! G" J$ O; Y4 f) n6 O4 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 h& G8 @6 {& x8 J, ~8 |1 @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( _7 U8 O m5 @+ r$ T# O/ REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. d5 G9 s7 v* C" |8 W3 }2 u, u( r
EDMA3_TRIG_MODE_EVENT);( C9 m( a; Z# M' W9 m) o0 ?, [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) z+ C; m' m. L/ Z' D8 KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: L2 Q2 m, s8 z* t- D7 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 j2 E: m) ~' H5 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ m+ F" W: B ~0 b" E' t& Y* z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 {- y* J8 L( @- u5 C, [* f1 r* d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 N3 f! n) I1 d$ g5 d1 o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& P! w2 {7 [7 }0 V% }
} 9 u/ v$ M+ I6 ?+ J+ W; U+ M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , j) Q+ p2 u+ M# l# u) X
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