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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, A. V+ E1 F; Z L8 ?9 J
input mcasp_ahclkx,- }- d5 E& R* Q6 \- m) x2 V! W$ Z
input mcasp_aclkx,
6 W; y1 R# q v) l$ m ]4 vinput axr0,
. p7 d7 p9 J% O/ @+ n5 ]. ~% Q- b' M, v
output mcasp_afsr,, A1 q# q) k0 o' @1 i
output mcasp_ahclkr, _4 S3 |! R8 |% n# b( u% ~ @' ?
output mcasp_aclkr,5 _% Z6 B+ D& t: M1 Z W) K8 w
output axr1,
b0 `2 `0 k# v* A* ` assign mcasp_afsr = mcasp_afsx;/ k i8 m4 j5 L8 y! J
assign mcasp_aclkr = mcasp_aclkx;+ u t$ V$ [; K- O
assign mcasp_ahclkr = mcasp_ahclkx;
0 n3 W, G O' j7 V2 ^assign axr1 = axr0; 1 S7 g5 u6 E$ k! k
% O) e2 V4 U: ?# W3 G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) G$ b4 f6 Y/ x4 o$ u3 T" i
static void McASPI2SConfigure(void)! Z0 y1 F k0 W7 r1 V
{
! d a5 X1 }& O7 Q( BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. l6 J/ N1 x. z3 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# \) y" O6 w" l' k8 [& w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# q% e2 C4 f9 U' i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 W/ r7 |# @9 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( K' O. b% p& C. ^( q0 i0 wMCASP_RX_MODE_DMA);
$ [# W x1 I3 e+ hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# \) O$ Z$ E: M5 M& `) b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 l# ~* J! k, G: d: L `' v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* e- U% N6 ?1 m/ Z( R3 YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 p3 V, ]% p# p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & s# t( y# |! _# l, h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* D D4 ]; Z" J! N& O8 R) lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 _. d* u, D5 O4 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' ]. P' T( L% p" q( _' UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: ^6 g5 C3 O6 x4 B+ ?5 B- a0x00, 0xFF); /* configure the clock for transmitter */
y0 f6 W. X( x. @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) O4 K4 ~$ T# ^1 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 B, a0 ]1 K7 v- JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. {5 h$ X/ y% N0 _+ `) a2 r0x00, 0xFF);
, [. \8 R2 e/ T6 m5 _) J
: U3 b5 u. K% y# E- `+ [/* Enable synchronization of RX and TX sections */ ; } O8 ~6 J* ?5 B; a8 d$ x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 z( s% d' L# @# g1 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. g) L9 t+ W5 O5 A* D y& ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. Y" a& E, [) P) b6 @2 x7 A) l) g** Set the serializers, Currently only one serializer is set as, X7 S! j/ _! u+ x4 Q
** transmitter and one serializer as receiver.- Z+ c) I. `/ K2 H0 d$ l
*/: U; B) _ H8 l& K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. W: N" `: H2 r( n' lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 _4 ]5 l5 D, z" i
** Configure the McASP pins * Z7 z* H S6 ]* @1 M
** Input - Frame Sync, Clock and Serializer Rx$ N8 G# x# _- T! K/ T/ p& R9 U. `: X
** Output - Serializer Tx is connected to the input of the codec
+ ~$ V! Q. _, }8 K, c$ q*/
1 ?& K, w" m5 D3 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 I5 _6 {! h4 f4 F1 r3 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ I; N( B5 f) ~- o. G/ {( mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# y! N A' N6 @& p1 T || MCASP_PIN_ACLKX
/ {- U* g% ?2 T, D) M; m4 ]| MCASP_PIN_AHCLKX/ F* M6 k4 v: U3 ^- }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' d0 I7 Z" ?& ^1 M& mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 h( J8 V7 R3 F5 K C p( t| MCASP_TX_CLKFAIL ; ]5 V# E& ^% m# @
| MCASP_TX_SYNCERROR
6 Z: d' W1 j# \9 J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 ]- N1 ~: J) R
| MCASP_RX_CLKFAIL) Z) ^. P) r+ C+ [) d
| MCASP_RX_SYNCERROR
# G4 Q4 z' @/ H* d0 \8 j9 [| MCASP_RX_OVERRUN);9 T6 L( O* N% y, \$ y5 t4 h
} static void I2SDataTxRxActivate(void)+ O0 y4 X: e+ H0 W
{
0 i4 i2 G, i- _1 k' @5 K+ [/* Start the clocks */6 b% X& I4 L8 R' z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 G' T4 |. p3 g* W+ n, J6 sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 v3 T( _: t8 M( \# Z$ OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' i7 b U4 i; P/ C* K3 j$ ~) bEDMA3_TRIG_MODE_EVENT);
* u) Z) Z7 J* e; GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , ]4 ]) @6 b1 l* n9 m, T0 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
d4 C' q' |9 j3 F; K. @) h% Z, xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% l; |3 g& i* F# fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( s; ]$ p3 _& X+ T; t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( t$ n& M! y2 r- n% x; N* o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, |* p, q' B G9 J* c2 m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) X% E; |, I; i
} 1 P- o9 I8 w; ?9 ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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