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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 I: o+ [; y4 j; m: Y2 a
input mcasp_ahclkx,, ^" I' B2 n5 B& I$ ^
input mcasp_aclkx,
+ E+ `/ a; b5 Q9 Vinput axr0,& g4 c) H4 ]6 ?% s$ j
! |3 x8 n3 H1 f$ ^" aoutput mcasp_afsr,/ A4 M7 ~, h# V' }2 K
output mcasp_ahclkr,+ {7 S% ]% c9 F1 u9 o% r# j
output mcasp_aclkr,+ u. C- j8 r# _7 _
output axr1,
; H, \0 \0 h0 J# V+ b0 i assign mcasp_afsr = mcasp_afsx;
9 H9 P+ p' x) N, `assign mcasp_aclkr = mcasp_aclkx;
3 l" e0 b+ Z4 j Lassign mcasp_ahclkr = mcasp_ahclkx;
/ D7 R3 V: T4 ?assign axr1 = axr0; . t( d" M/ Y- q; {* L
% n) j; `" o4 g9 z2 T" ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" O+ {- @4 L2 r# wstatic void McASPI2SConfigure(void)
5 I0 {) p6 ^% K6 l9 `{! |& i" t: }; z) l+ s0 f) |& {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 L& ?! J8 X6 n H% N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 i7 ?1 h0 }% s, i# YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 \8 M/ j3 ?9 q7 j' S h" h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% K1 s6 L2 r& Z: j8 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' W5 I. t m4 u0 r
MCASP_RX_MODE_DMA);+ X" A# ]; z% X8 |: C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; u8 _$ U4 x5 S; H) I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( E% `+ ]8 w, L( x6 d4 GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' R/ I) F2 q. A9 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 p0 w- `) C* d: n8 ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 l# T) z8 A/ x/ d5 I! EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! r, |6 C( x' e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! x1 `$ I2 p9 h8 G. ]5 Z! d9 o3 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! k* ~) H' P) A8 K3 R' A6 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 Y& L' V1 S9 S1 i# W; v0x00, 0xFF); /* configure the clock for transmitter */
" N3 Y1 {% {1 H# }9 `8 Q0 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. ?# q) ]- v4 x+ c1 o+ hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 U# l4 j9 ^4 [" ^/ o0 g; |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 d7 o2 c- T0 j( w
0x00, 0xFF);
" x" @/ P$ d& u! J2 u2 y5 V) ?1 d
1 @( p) A6 _7 t x& Y/* Enable synchronization of RX and TX sections */ ; L1 d! G8 Q+ g3 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. `& k7 j% [ }1 ^ b6 C/ IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* v8 V8 s. l) h2 Y" r1 V2 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: F# f% p) |; w+ k: p** Set the serializers, Currently only one serializer is set as
( s+ p3 f* y: i; D$ R** transmitter and one serializer as receiver.
) w5 F7 m% B* o3 d0 T7 R |/ l$ t*/. b; s0 X! E" l/ J/ q( @" i$ D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 z! D7 S2 \5 Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 X& z) _' f( F) z& k0 g5 I/ E** Configure the McASP pins
3 U' i5 {4 m/ t+ [! y0 X0 L** Input - Frame Sync, Clock and Serializer Rx
5 f1 g. g, f) |" K& ^2 o** Output - Serializer Tx is connected to the input of the codec 9 A% V2 U5 h. B: m0 C+ k
*/1 d7 m5 c; t7 O* C5 A" ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- J$ m9 l2 i8 x9 [- G) ^ R! x, UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ i# `; h% ?+ H: L( o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: T: ~! h0 D5 d1 Q' {| MCASP_PIN_ACLKX/ p4 E4 F. {4 P! T6 A1 c0 f
| MCASP_PIN_AHCLKX
/ W; r% G+ ?7 j4 a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, u4 e( I3 W! \; d' \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! a7 e; ]/ K8 F: x# @
| MCASP_TX_CLKFAIL ! ^* k; b4 ]+ O% c
| MCASP_TX_SYNCERROR
A3 y4 c; m; y9 ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 e# \- S5 d6 M3 u| MCASP_RX_CLKFAIL
" W2 ~6 E+ v% k3 l5 f( i( M* D| MCASP_RX_SYNCERROR 1 E. G$ g N+ J/ k/ v0 U
| MCASP_RX_OVERRUN);
2 \6 h1 Y, i" L$ D} static void I2SDataTxRxActivate(void)! z0 M- D% Z2 o+ j
{
l$ D! R! Y" |/* Start the clocks */
' o7 z* C( D- wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: ?# E( r, y" pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- G( v$ {2 K: A) U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% j, L; _; {2 I" ], l) Y2 ^7 WEDMA3_TRIG_MODE_EVENT);
% O$ L& `$ u: cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 L& J8 p" W {* M/ l) ]% O) P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 K1 W9 {1 H$ I; \) g! p8 G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, w* Y5 ~% c: a- jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) y0 |* |* g( {% O8 @8 P2 Q) `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 U9 @1 U5 j. b fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ _1 Y0 M8 W0 G+ F) B' @# D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ | F6 o. h) W+ Y- G3 v} 1 i9 D4 T7 ]' g% U; _* G' o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 v+ q3 j& N* f/ A
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