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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* ~2 X( q/ N5 l2 S. Ainput mcasp_ahclkx,
& P( x, f9 B% C3 F* @$ cinput mcasp_aclkx,
3 @2 O0 P; f' [, }/ P; C. s. Tinput axr0,( O- P s9 T6 }: H+ \* f
. f- O5 |5 q, l4 B! F
output mcasp_afsr,
+ K3 b. X$ ?3 p! t% i! ~output mcasp_ahclkr,
' x+ i2 [$ o/ T. ?output mcasp_aclkr,
1 _' B/ D$ \' }, { voutput axr1,
' `: T. `% V6 n! s assign mcasp_afsr = mcasp_afsx;
9 i) q3 I3 I$ N7 w! P* V7 V cassign mcasp_aclkr = mcasp_aclkx;
. o4 i4 |+ B8 X8 [assign mcasp_ahclkr = mcasp_ahclkx;* B! ]7 t/ I( D* g
assign axr1 = axr0;
) i) {; W- J8 N9 @/ x5 a* q# t; B; ~. i4 f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 E! |5 p4 g7 ostatic void McASPI2SConfigure(void)
. L2 f2 w% A$ L, T6 P# w{' [( e1 ?: B- G5 j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 b) x4 {1 ^; v: ^6 DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 b/ X& I" S+ L2 S( F D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 W& X. L' u5 A3 T% [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ ~7 V; _9 n( gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. j, {6 i* v4 h3 _
MCASP_RX_MODE_DMA);
" c3 U3 T% v9 L5 K2 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ a8 x; ~; `$ H2 l& TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' c. J# H! z6 z NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! }+ F! i' f8 \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& ~* l9 U$ N+ @' r# ^* z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + {$ |- Y }! N2 F$ i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; r* ]$ C* z7 Y. X( HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* q- B% }$ z5 H2 p6 L8 E h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 X* r( q6 n& I6 J8 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! f# F5 A( v& J. [# f
0x00, 0xFF); /* configure the clock for transmitter */; q2 T+ r" m3 f" i$ ?& A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, _4 b9 ?9 A; R1 ?' W- ~, iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 c5 z9 @: b) ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ t' b) l( f7 x8 A
0x00, 0xFF);% ?/ h- x9 \1 }: f3 W1 R
+ q6 R- O! B0 E$ a$ i8 s2 U; m/* Enable synchronization of RX and TX sections */
" ]3 B0 t( N2 i- f1 tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ y2 |" n) v% u; t$ LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 \0 g5 L5 y( o9 z& ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& W$ e1 @6 y$ C D6 B1 ]# M. l
** Set the serializers, Currently only one serializer is set as
6 s; A" U2 }/ p% w) |# m** transmitter and one serializer as receiver.
' e" r( f9 R8 r) g" h*/
5 v. s$ t0 k) M ?& k4 ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); n$ c% s3 j% g! C) c' e6 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 p, ~1 T5 r8 }# d* Y I; a** Configure the McASP pins
# O& t# [5 e8 u1 l0 M9 S! v** Input - Frame Sync, Clock and Serializer Rx
0 y. f' o$ S' K7 M* U* S** Output - Serializer Tx is connected to the input of the codec : a) N/ o( y4 f6 D3 ]4 d0 y
*/ i, E9 o# A( Z; ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 H: s! J3 B3 g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( n9 V( u S5 u' D' S3 MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 S# Q" }" G2 S: O* a9 x. P0 I5 n4 c| MCASP_PIN_ACLKX) y' o2 K* t- s, i; g& Z+ I0 S9 g
| MCASP_PIN_AHCLKX1 v8 q* f9 G; L8 J$ V" N3 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" o4 I! }) T w# iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: u! `. [5 Z) x: s: K; N| MCASP_TX_CLKFAIL 5 [( U- x# O) ~1 D. Q
| MCASP_TX_SYNCERROR
# U! N- T! R6 c4 z- }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % q" U; O; }5 c( o" Q4 b2 S% I* P, h
| MCASP_RX_CLKFAIL
p' i7 N8 o2 b+ {2 Y| MCASP_RX_SYNCERROR
1 m" n; K% e( ?& j) Q" N$ T- C| MCASP_RX_OVERRUN);+ Y- P% \( L( v- O
} static void I2SDataTxRxActivate(void)
" z# |" X$ W3 [3 r8 B{
1 I& z$ S- g: J; g/* Start the clocks */$ u% {5 x, K% t# Y8 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) m, @* ~! @8 i9 P! TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 n+ }& X% u. N! ?, Z$ s1 M, `* ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% W4 W; z, A& K- J G
EDMA3_TRIG_MODE_EVENT);5 x7 u# C) W2 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 M9 J) t! |0 k4 q7 z2 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( e% I. P" c: m4 Q- _5 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' ?6 k# \4 T5 k: T0 O6 n: C1 X% bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 _: Q5 K, T# Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 A' l; |; x$ `, @0 D; C5 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! q( H* \& w7 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; j! m) R% k7 \0 h& e" J/ E4 j}
! H- e& l1 B" E7 b7 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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