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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 [2 b' V% o. r* A# a0 w
input mcasp_ahclkx,
" k* W. ~ }0 H: ] ^, ~! Binput mcasp_aclkx,
5 B8 f- n# n; B5 @! e( u$ y/ Z2 \) y* _: jinput axr0,
1 g6 u2 @+ w1 x% q! p" M) K( W `, S& K' ^3 x
output mcasp_afsr,5 [5 ~/ s+ v- m X* h' |. F" L
output mcasp_ahclkr,
r- @- ^+ `3 r# moutput mcasp_aclkr,
3 C4 ~* e( i' m# ^8 ~7 k- f) d# voutput axr1,# J: ]: ^& h, g' S: H" k R" X$ |
assign mcasp_afsr = mcasp_afsx;
# l9 W3 k7 J5 Y) ~( d o, t: ?assign mcasp_aclkr = mcasp_aclkx;
" J* j. Y6 U" B2 F9 M! y3 Tassign mcasp_ahclkr = mcasp_ahclkx;
8 n- p( J8 v) G! i: |# ~assign axr1 = axr0;
! e# k- D( k( M5 F9 Z5 u1 G
6 |8 s) P2 L- S& p$ _5 D8 U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 {* l v. ~ o1 A1 Z& ~( J1 V
static void McASPI2SConfigure(void)
0 E$ _9 d5 D( t{8 u# V4 J, G+ {! f( `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. Y" ~6 L( d! K% BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
_& G) x4 ?3 B" NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); R! m. f' g8 F' W, {$ |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 S! e7 V h4 f3 z E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% l6 k: X' l- F! C i+ q
MCASP_RX_MODE_DMA);
; J! g. g3 i1 _8 w6 ?1 Y4 ?! LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! C: h* l; h ]; l/ ~% }6 O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% q) F$ @9 b" l; L' }" J) k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; E5 V; \6 n. RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 H* O. q" s3 Y r: b: x. WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 M9 B! c2 {+ @; i8 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* g2 L5 w$ H, @ Q; N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 _7 p. i2 w% {: C% n/ h. [2 |! `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) G+ {# x, [0 Y" |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 {- k: a. E c
0x00, 0xFF); /* configure the clock for transmitter */- G1 h* R9 y* d$ f8 R6 c7 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* i0 i1 {3 j6 d3 W, cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& O% {; r% ^& ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 k' f I1 ^& ~6 u$ Z7 F; D* l
0x00, 0xFF);
1 ~( n" e7 f0 T$ L
$ y6 l% `+ _3 Y/* Enable synchronization of RX and TX sections */ & j1 |! B) |; H) e! M" U4 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 X. K+ O) E$ R4 O$ `$ @5 t/ x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' d& d9 j0 q8 V; C. i1 d v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. ]0 h% V- W5 R, d- U+ T** Set the serializers, Currently only one serializer is set as8 ~1 A* L3 P8 G( S+ i
** transmitter and one serializer as receiver.
- d: p- a! ~ t9 p! n4 Z2 V. C1 |*/
) C: b: z, i% qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) s( r4 Y/ C5 n' M7 q/ {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- k: v, z- j) G* m! {# C) E9 t" m, G/ T" H** Configure the McASP pins
6 u! M5 {" _9 W8 E# t1 u% B$ u, x** Input - Frame Sync, Clock and Serializer Rx0 C; _ t$ s% N6 z
** Output - Serializer Tx is connected to the input of the codec $ V. b0 N3 F' z) l
*/
) u4 {) r! S! B, M! \+ \4 T% D. XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ _1 g4 }8 `% w" ~: Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, e; O5 w) p# U( }, `6 \- R a' @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. Q$ ?' o& ~5 a* Z: q4 l& || MCASP_PIN_ACLKX6 Z2 v8 u8 B7 r) T. h @+ C q
| MCASP_PIN_AHCLKX
. J/ w6 C k; }, `: m0 y: d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 E- O2 q9 @* f1 |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. l' S! o+ E" f4 s7 A; j' M| MCASP_TX_CLKFAIL
+ K7 u |! v. D| MCASP_TX_SYNCERROR" Z, }5 e& d# S. o; E0 }! T4 O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ {' K: h+ D+ h' h| MCASP_RX_CLKFAIL: C. Z* d& @" `! `9 b$ y
| MCASP_RX_SYNCERROR
! _8 y | ^- j7 I+ i| MCASP_RX_OVERRUN);6 A: u6 E" B9 z/ n+ z. T
} static void I2SDataTxRxActivate(void)% K' f$ R2 y- A1 u/ ]' T8 } g
{ h3 h2 l8 @7 Q
/* Start the clocks */( x$ ~* V1 B6 c0 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ m) L; n0 B- a, [2 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ c0 `6 V; N" }* o, T. E0 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- C4 x( o$ J' a0 d$ c" M8 q2 tEDMA3_TRIG_MODE_EVENT);
1 y$ O+ g5 ^/ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( T! ~* V' _2 e' w- J& Q! q* iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( \' D+ e1 |- H) s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 x4 a- ?! ]6 H$ {* V( q) YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& S' Y- q" ?( N& V$ E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! N9 W% C. W: s0 s1 [8 p# U+ m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* ~' p6 v' c7 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 z! {6 I& [0 n' m k7 C1 k: X* P% }
} 9 a. l% X" b" {6 O4 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - b, T# f* Q4 `5 l' V8 I4 Z5 C
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