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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' O4 s! S6 i7 m9 R' |input mcasp_ahclkx,$ d; f; Q& W# l9 q0 i
input mcasp_aclkx,4 V/ Y7 D2 y; [0 o% i9 G$ t! }
input axr0,
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output mcasp_afsr,. R7 Q2 K+ B w4 q" K2 Z
output mcasp_ahclkr,
& |5 u( Z. A" W1 I7 |% F b8 ooutput mcasp_aclkr,
' O+ o! ]0 Q" T6 u8 ?( n- D8 y" x6 [output axr1,; l& X2 v6 s% M3 Z
assign mcasp_afsr = mcasp_afsx;
* F* F9 F" y3 [$ a& dassign mcasp_aclkr = mcasp_aclkx;
; x4 O: A, k1 c1 v4 U! ~assign mcasp_ahclkr = mcasp_ahclkx;
/ X& x1 P+ {- @3 f2 b1 massign axr1 = axr0;
0 X5 K2 c+ V3 a, e2 G* v
/ a0 ^: e/ X. u' \. m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 C: q% q0 ? C4 l
static void McASPI2SConfigure(void)
w. W& Q. L: A( I0 k3 W5 j{
: O, x5 ? w% m* `" e: [4 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& o0 M; A! M, p: B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: V) i \9 G& c# E. uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 f7 z0 r4 O1 i& c r- \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; B$ o0 l% W, [% l/ G6 f2 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! ?9 e/ e/ x5 X" V5 s
MCASP_RX_MODE_DMA);
& I p3 d# d2 I) JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# p! M1 p6 \6 ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! e& P& h2 E- k1 CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) L0 v6 r3 |! x/ }7 g3 v0 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) @2 f) X- z% t$ e7 s$ d: G+ AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * K; B- n, H* @; u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' i# W1 o) t& }5 WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, N$ U) X9 o' g/ [5 A1 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ^% F3 K1 o# K7 fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ X* l3 B- T& V) R2 ?0x00, 0xFF); /* configure the clock for transmitter */' Z$ @( v; \3 F4 a/ y& {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 {; C% v9 j, l" \0 Z( CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 c b! W, e4 D) a$ RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. r: j ~) R C3 n: b6 n# S! ^
0x00, 0xFF);- O: i2 P; J9 j K" N, C/ G2 J
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/* Enable synchronization of RX and TX sections */
1 b$ G3 T, O. `' m) i+ |1 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// y7 W' u, W, I5 E! A0 V4 ^7 }/ c# i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ A9 y0 L7 j7 f9 y b2 Z5 rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 f; b7 z& f: {1 Z; V
** Set the serializers, Currently only one serializer is set as2 ^2 A R4 _" c4 }( Y) Z% H: d( [
** transmitter and one serializer as receiver.
; l& v; E2 E2 q, F, J" L*/& W+ c q+ O7 ~5 X- V$ O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
_7 Z: `) w4 F0 k( m0 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 A" t& c( c& \$ y0 R** Configure the McASP pins & W5 A$ F9 f4 [1 G( e$ o
** Input - Frame Sync, Clock and Serializer Rx5 ]' z$ ]6 M2 l1 L! A6 U
** Output - Serializer Tx is connected to the input of the codec * ?% Z6 u$ d& R, f' I
*/ F( o$ ]9 n% [# F- M& U& A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ d1 u& O3 {- z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# F7 E% S. C( ~& X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 D' B9 B% n0 }7 W0 J| MCASP_PIN_ACLKX
: _: ` S P* D; g: I4 a$ F: S3 H| MCASP_PIN_AHCLKX
9 c% O7 \: R5 q2 T7 @: w* }- P' K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 o. @. P% P! K6 d3 UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: B( }3 k4 A6 J5 L. P! ?; h| MCASP_TX_CLKFAIL
) V( @( N& X, s+ l| MCASP_TX_SYNCERROR
0 i' `1 O b$ S# T: P4 Y: r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 u- u! j6 B! x4 m, t9 [( H
| MCASP_RX_CLKFAIL
. V! }4 W0 [8 Z| MCASP_RX_SYNCERROR 4 }: h6 t. m9 l+ j7 @
| MCASP_RX_OVERRUN);; n/ D+ `4 f7 c% X
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
0 ?5 c0 X' v" h: |9 H; V' LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; b' c( @' f/ G) G$ A8 X6 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" ?6 e/ u- H) X- a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ ?3 X* i, ]% H+ d' Y3 |2 F/ j& LEDMA3_TRIG_MODE_EVENT);
' B" l! O' a, p8 q. O7 x) Y2 |& t9 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' k `: Y' F! u! O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 s+ ]; V# l3 b. g# o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ L) ]) d) }* f% A3 u: I6 j; ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 B/ U+ W# K) Q* V8 v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) s2 L \( S4 ^$ KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* V) e* t7 h0 N+ pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* V6 E2 A1 X* R3 D w/ @
} 0 }- O! H5 x. s/ l9 x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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