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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 Z$ d. ^! m3 w/ E9 s1 x3 H5 t
input mcasp_ahclkx,
+ d0 l% G) z1 linput mcasp_aclkx,
5 U) F9 U3 H$ L: r# einput axr0, z" W' \+ j! v: g0 A- ?' ?
( b2 r8 h% c6 o/ e8 Foutput mcasp_afsr,9 r1 N1 H0 p9 @# E
output mcasp_ahclkr,
, ^) n* ?' c R6 E4 Poutput mcasp_aclkr,
" g4 ^3 b' R, D5 N# Moutput axr1,
$ o& ~6 }" e% o7 s* Z assign mcasp_afsr = mcasp_afsx;0 j$ }9 Q; H9 {7 A7 H& M+ a
assign mcasp_aclkr = mcasp_aclkx;
* x! e; {4 S, o2 h+ L5 T% C. j$ tassign mcasp_ahclkr = mcasp_ahclkx;
" ]2 N% E" i; ]: W' t6 [. x, q# qassign axr1 = axr0; : M0 }7 I+ V/ _9 J
. C8 ?- P b+ [# U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 H$ J5 U( \* K; ^. Z- X$ g. O
static void McASPI2SConfigure(void)5 L8 U% _3 c) y
{
# W" d. v3 r% D. lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
r$ J. N# N8 ]5 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 v. L- |/ U2 ]: @ m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- b/ g8 j. X5 p+ E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( t1 S$ L6 Q2 U. D, N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 x* ]. d; P* W; E. l
MCASP_RX_MODE_DMA);8 P5 @- k7 ~4 A$ U! h6 t& L0 }' E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 O$ o, w, k: m9 D; p. j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ o9 [, m7 g' N, V9 K! `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 B- b4 q$ s! T2 {* r' ?2 ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 r. E8 l- s; ~* ^. _- ^3 G; |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 o3 T6 g6 |' W* J5 }$ k+ [; UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 d3 N5 W0 a" n# {( u* EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* w. w6 ^( N. N% e0 K4 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. g) ]5 [, u) D3 ~0 n$ tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- _; F6 t Y9 [ g0x00, 0xFF); /* configure the clock for transmitter */2 ]! x) r( J8 {$ [3 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! e S8 z# j' j c7 w6 X, ]4 ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 g2 x( G2 t6 I! YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' S0 h) W3 F1 \4 P5 x( @3 m' o' [
0x00, 0xFF);' O8 K# |# F# ^. A/ z$ U! t
4 F& N' H$ M) l8 B _$ o5 I/* Enable synchronization of RX and TX sections */
* S' l/ W m% `2 U' B3 cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 Y9 X% |: j' uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 F- u) l6 b! m# o3 z7 P% KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* I" j3 C6 d& B" L9 z( z** Set the serializers, Currently only one serializer is set as R: B) @4 l( Y( X6 S& r" C5 E
** transmitter and one serializer as receiver.
+ |6 d, k9 ]( O*/5 F5 {( q# O# N7 A$ {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ x1 ?- \3 |$ [! d7 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; \& {6 K. R% P3 Z7 M! y
** Configure the McASP pins ( G) J$ O8 u! i$ C: U7 Q3 Q# \; r7 U
** Input - Frame Sync, Clock and Serializer Rx/ g$ q7 @; H- z4 M( U- Q
** Output - Serializer Tx is connected to the input of the codec
* P/ K6 {0 P4 ^( \; c: ?*/+ n% C' W" Z7 c* o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 R, W6 |6 [/ Z% ~! D- XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ _ V* C3 g) N' A, Z( N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: H( a8 s# x Y- ^' e9 p3 R# d| MCASP_PIN_ACLKX( k j, ]3 ~6 B$ s4 z4 M" i
| MCASP_PIN_AHCLKX
! I/ y! v/ c9 R1 R$ L" s/ v* F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: s& d: P! {$ e7 Z1 k7 y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & S3 \$ s/ U3 Q
| MCASP_TX_CLKFAIL
2 V* o. j+ i, I6 a, v| MCASP_TX_SYNCERROR
1 Y0 Q" r! w; `' I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; }, J$ S4 u) B( v( E| MCASP_RX_CLKFAIL3 ?" B0 g2 a1 R( l" K. }2 `
| MCASP_RX_SYNCERROR
c3 a/ B6 V' w9 V, F| MCASP_RX_OVERRUN);
+ G- E) _7 v: m; U; [/ U} static void I2SDataTxRxActivate(void)+ h/ T4 a2 T5 G0 M/ W2 _- o+ r
{+ r$ u' y1 C" p h2 `
/* Start the clocks */, \0 k' m) r5 y: {9 g' W" ^6 L' e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; `2 W) C6 n: b5 B% z! iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& m p1 t5 e. v- i# C ^2 ~5 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& _, ?& X' _* p4 h% wEDMA3_TRIG_MODE_EVENT);' s4 ^* B# O& z" G, y2 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( w; V# L% Q4 E2 Y5 G2 L( N3 T# I% G2 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 D* l, d' ^! r6 O, i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ ]7 x8 N% J% \( k% v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" q; n* h6 W* ]0 S1 S Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 c* |+ Y2 E8 R+ J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 ~* Q) G( f9 x& ?5 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; O" F% q. k: M' }! e& i: q9 q6 w}
1 H$ A) a' c5 B# V! i7 E$ o+ y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - {( n3 \% m+ _5 r0 P; Q
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