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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* s! U" r) L2 J% I
input mcasp_ahclkx,$ L7 u( |3 S; K& e6 q8 K
input mcasp_aclkx,
' t2 `7 T, G1 ?& a: v6 R5 q; }/ Dinput axr0,
. G5 P1 P8 m7 J, Y
' G2 W+ n! }& _! ^* ?output mcasp_afsr,, [" H6 @/ k. G/ h
output mcasp_ahclkr,% `) }1 M. k3 a. L6 P6 w5 Y S
output mcasp_aclkr,
9 B: A% ]+ H: T2 y& |0 soutput axr1,
% ?- t* W: r P assign mcasp_afsr = mcasp_afsx;
4 e2 h8 {( G% P' `8 H8 ~assign mcasp_aclkr = mcasp_aclkx;+ ?2 H' \ e3 ^4 N
assign mcasp_ahclkr = mcasp_ahclkx;- q. K7 w+ z0 S$ ]" T
assign axr1 = axr0; % g7 G. ~. J# I2 g
+ l" N1 ]! u8 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 W. \" P8 u& E2 [static void McASPI2SConfigure(void)1 l. F: f X) \% j1 D y) `
{' o- X4 A4 D4 H5 m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 f8 O! ]8 e3 P9 ?6 I3 o6 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 v( g9 L8 d2 j& @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 Q5 V( P2 I) l- f) m" v) H" QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 \; z* B% z, z$ m* G# i9 ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 z/ c2 D8 o6 R1 y+ l
MCASP_RX_MODE_DMA);/ Y( R& j. D& u& X: n+ o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 d" e: F( a# K+ n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# o% g2 k/ }/ k9 }$ KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ |- [! ?" M3 _* J# H9 f8 s0 t" NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 K o y6 ], [$ ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, Z% G6 ^$ U P H$ l- N1 ]7 O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# p, W3 N1 ?( X2 A; a" f! N! }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' ^( N P, O) w7 U5 Y: {& u5 E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, q2 N; e9 b, P8 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 g3 B' w! Q3 a8 h6 h
0x00, 0xFF); /* configure the clock for transmitter */" c X) I- |5 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
d. ~9 J" g* P! d6 g2 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( w( w: v4 h3 Z* z! BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ D# a f _6 Q ]! l0x00, 0xFF);
6 U6 T4 F& K |6 Z7 ^/ |9 @1 `& D0 N) G+ V
/* Enable synchronization of RX and TX sections */
1 W9 r: m5 R9 U) r; TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' p1 p' @8 G3 @5 O2 @0 m& x& w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ d! V* N& ?( H& j* O4 z9 q' oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 S/ P, E% J: E** Set the serializers, Currently only one serializer is set as
' K V) i* g3 {** transmitter and one serializer as receiver.
2 j8 \4 N* Z# F1 f1 I& p+ U7 s2 n*/" ^5 G. o; l0 e, c* z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& o; O9 g! G2 ]" @! T" S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ d& R# K+ x! j" A/ b. X
** Configure the McASP pins
9 W$ n9 `/ t' D# Z8 w** Input - Frame Sync, Clock and Serializer Rx& `. C' ~% c' N! ]1 d& f
** Output - Serializer Tx is connected to the input of the codec z5 v7 c4 o) `0 b5 ~
*/- ^9 \; d0 T; S; e6 G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 N1 j- E7 a2 ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* u: y3 o- L1 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! a' L$ p" W% g* h: q
| MCASP_PIN_ACLKX" K- V3 Q3 V2 j- X" l
| MCASP_PIN_AHCLKX
- \/ |7 V, q# L( A; ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// E/ a7 f0 x" Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 w4 A% t9 {# ?3 Y' }- L| MCASP_TX_CLKFAIL
9 N ^4 E/ U O# G| MCASP_TX_SYNCERROR$ O7 v/ t& r+ \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 @; w# k# x6 f% U" j! n' ~7 O; d
| MCASP_RX_CLKFAIL8 T& a; c5 c" A, |" s, A! F6 V
| MCASP_RX_SYNCERROR $ F0 g) a) L( Q6 `/ J
| MCASP_RX_OVERRUN);
: k; o5 Y/ c" k1 j5 j n! k5 f& u- N4 R} static void I2SDataTxRxActivate(void): C; L) S% l' F
{1 w3 g% R% |# t H1 P
/* Start the clocks */
% ?7 S! h, R6 fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, @4 z! }. t: N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; |" h5 b8 a7 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, \5 a4 T/ y% b& {8 U) n) Y# }EDMA3_TRIG_MODE_EVENT);6 \7 k) m2 c) a( C6 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# y {- q5 T1 @. ~4 X# WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 R; ^# t! I) Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 M# Q5 v8 e1 Q2 f5 R6 h$ w& Q% `- aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// o) i- q6 a v3 O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" }! u$ _, F) Z" d! D: a+ I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 V4 R6 ^; g1 V+ l/ ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 Y. p' F) R5 Z/ N6 D- B} & y# ^ g, g# m/ O1 ^6 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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