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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: _* X8 ]1 T+ a9 l( r+ m5 t
input mcasp_ahclkx,% x/ D v" s. R* G. g9 K4 T6 t
input mcasp_aclkx," i' L/ A! G, ^4 {5 F2 b5 [
input axr0,
, V; s+ R- c9 ?8 t' Q8 \; j
1 p5 l/ B% V* Y& q" H! _output mcasp_afsr,
8 o5 O* L3 q" {5 M% ?output mcasp_ahclkr,
8 j/ U' X) ^& |* w7 ]* i y# |; l2 Loutput mcasp_aclkr,
; \. p" I0 U2 E7 A/ ^4 D5 v5 G7 Voutput axr1,' q2 v. n, }8 v% Y/ s! L
assign mcasp_afsr = mcasp_afsx;
0 g1 M/ c U! massign mcasp_aclkr = mcasp_aclkx;
) }, x+ l% l: B+ H! sassign mcasp_ahclkr = mcasp_ahclkx;! E# ^* e Y7 m1 a
assign axr1 = axr0; . F& k1 E: R1 @ `& O ]6 s; q% i
6 o0 l7 J' D6 \+ t( e' i1 I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! L5 }# W7 z# R Y; {4 o
static void McASPI2SConfigure(void)
9 t) h p6 I3 c5 u3 p0 e% ^{: l/ ~; ]; ^( B b# g4 {0 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 A$ |5 }. X6 E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 `6 X$ H0 O: ^* f0 B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 }& c* e$ s% DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& S# z& m1 n- @9 T$ u" t( u6 D8 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 E. ] a6 e! T& g" \2 v6 o: u
MCASP_RX_MODE_DMA);
% I8 [$ E' `0 Z; Z* yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" t$ B1 N/ N/ \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. M0 V! Q8 h- D6 v: |5 J. s) t& v3 QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' D* w7 P/ @$ M7 N" RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 |& ~/ a4 s$ E& p+ z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& O% a: u' C3 u$ ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) O, q3 |- |, Z- t5 s. mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ j# }+ z; w- ?, x, e- T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ T/ D( d+ I& WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, q0 O |* L) Z" Q# m
0x00, 0xFF); /* configure the clock for transmitter */1 C' f' J2 t. k6 S" g" p) ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& X( u! Z+ ~* f2 _8 | L# @. _) u" YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; ^) d4 y- t7 Q- v) z3 z6 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 A( S( e4 c' ?$ }( Q" R q' C
0x00, 0xFF);$ \+ h0 ]0 o3 m; V
! Y, k. R3 a% u3 x: W2 a/* Enable synchronization of RX and TX sections */ 0 C2 A) X1 r: }* {5 R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 i+ P1 f2 y5 c# B7 p$ ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; w* \6 L9 e9 e; V8 A& GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& ~* x( R2 c- a% J2 v' {4 L** Set the serializers, Currently only one serializer is set as. B5 A; T, Q, T- f. F3 Z/ J
** transmitter and one serializer as receiver.+ \& L( R/ Y3 Q" G' L' G+ u
*/! M9 O4 |$ A" ?7 d' {* I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ g# u* M) O7 y' o0 o2 c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) c* L2 q7 q9 P V
** Configure the McASP pins ( U$ ^, \$ x/ \: j) J
** Input - Frame Sync, Clock and Serializer Rx6 u3 \* \. Z8 c% z5 @7 Z" {
** Output - Serializer Tx is connected to the input of the codec ( J) e. J! ~) ], O
*/
+ ]& Q( A: O; o2 D/ W0 t: vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 s) x; g; U8 p3 y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ p4 |0 \* R7 k0 t0 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: K# Q0 n. z' e| MCASP_PIN_ACLKX2 K7 r4 `. L8 T3 Q, l' g. |# T
| MCASP_PIN_AHCLKX
! U7 f7 P6 O/ I" g# c& F% O9 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 K- D& K7 w1 i) x* t$ e iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! R4 M3 L7 w* p+ o
| MCASP_TX_CLKFAIL
* O1 U8 O& A3 g* h, v| MCASP_TX_SYNCERROR% M/ z6 y% h* S. X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & J. {) P8 ]' e" c
| MCASP_RX_CLKFAIL& _" n ~0 d& d F/ a
| MCASP_RX_SYNCERROR
4 q) I! b5 a: u| MCASP_RX_OVERRUN);
1 n0 d; E0 u3 n) w( b# q7 H} static void I2SDataTxRxActivate(void)
* ?# Y, m9 `' v7 w: p{; i8 q+ |- {6 ?. h( |7 Z: y
/* Start the clocks */3 x+ |* ?4 }. E! i4 Q+ V3 ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. E$ c. A- E f: K: R, @& j3 QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 J% B. _: R8 S0 v# p; O r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) a1 S# o8 A6 I) \
EDMA3_TRIG_MODE_EVENT);
0 u- {2 d4 m, @4 F0 P# V' }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 [) G7 L1 P) N. g- J4 p# rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ F( }& u0 U* v( ^' P+ d8 ?: B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 U F0 |6 C0 e* l7 ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 O( B% } n/ {" C% {% T0 @# |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 C8 R# e1 ~/ _' i: ?/ p$ g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% X# m' z }8 g/ A* F% D/ f6 d) y3 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# |& `# L# G, d6 D6 t- o} & r# S5 X5 K6 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 b) o' ^1 N; _5 j8 |! F, b1 w
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