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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& L1 X) F6 r' \" s% R9 K
input mcasp_ahclkx,
# T6 Z" G* R# i& Q. V) w7 Hinput mcasp_aclkx,
! O& z6 V9 Y# V7 d0 Tinput axr0,. e# R" }. E+ r
3 L. Y0 K6 N2 r. y) u4 W" Z
output mcasp_afsr,9 E. b$ ~" ]/ M, x: z
output mcasp_ahclkr,
4 o! J v: K" Goutput mcasp_aclkr,
: g3 R2 X' T) X; u7 c: I5 B# }( W: E7 }output axr1,+ k! r7 S5 N$ m0 b: E
assign mcasp_afsr = mcasp_afsx;1 k8 [" r) r& \( d7 j
assign mcasp_aclkr = mcasp_aclkx;
% [2 F K' S% I2 g$ P- gassign mcasp_ahclkr = mcasp_ahclkx;
( G% k6 [& S! Xassign axr1 = axr0;
# }% X6 K" f$ b: k. l3 q' V6 V# n) l8 p. [0 u! n2 F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " \- n' j5 k8 }! {
static void McASPI2SConfigure(void)( d# ~/ q7 m8 ]! |, L
{. t: U% M" y- c/ H( B# G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* I7 }9 D( t) k1 yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' j8 F. R; M0 |+ M, OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 J5 V: L. Q9 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- s1 V& V. M# L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 X% d% ?6 D* y$ ^( N( v& j* zMCASP_RX_MODE_DMA);4 n* C' @+ t0 X( C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 t8 a; [7 F+ H4 Z$ L. s+ b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, c% U# W$ k. h! a) ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, F5 N5 {8 ]! D" e0 ]7 Q8 U2 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( n! Z% O1 S: M# T G6 E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" d" Q3 F2 T* } D; e% @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 z7 N! Q0 ]; ]( _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 u J' Z# o) y& U1 r* E% aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " k9 L( a3 W# C9 A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 v q3 e6 f! O+ T* p0x00, 0xFF); /* configure the clock for transmitter */2 z% w3 C6 }* G* r- T* m+ @: P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 b, K2 Q2 ^; ] L7 |% M% G) aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: f# F7 F( l; L* b, I' aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; y- w' g9 h! N; m0x00, 0xFF);
' z) a( o; J& v. x8 Y3 z$ d0 }3 B) L
/* Enable synchronization of RX and TX sections */
- X2 e1 ]% E; v+ |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 e7 @ R3 Y x. w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. j' a- L% e6 M9 q7 I. q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) U1 i' G( n6 c9 h+ y8 w** Set the serializers, Currently only one serializer is set as# H8 ?& g$ u. u" d o+ D
** transmitter and one serializer as receiver.
- N) B2 Y, M3 {$ J. g' d*/
! H) P3 {4 P# S% _4 @7 Q% D5 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ J8 j4 H8 i5 g* W$ n* j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ f# r5 F* W$ f. }** Configure the McASP pins * w+ ~, t6 ? o( T8 s$ N! e& V
** Input - Frame Sync, Clock and Serializer Rx2 `/ { v4 [' M
** Output - Serializer Tx is connected to the input of the codec , a3 Z" J- Q3 A3 ]6 r4 Z# Z
*/
( _% R( {( t8 Y7 E3 B8 RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 G0 G# y& _" p$ E+ gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 y4 W8 ~( c( `# R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' v4 x8 c4 c, H- W6 J
| MCASP_PIN_ACLKX3 M" y7 v7 P! x7 d- t
| MCASP_PIN_AHCLKX
& w# i! R% G% G) N7 K# ^4 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" j2 p7 C& F: b* _1 bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. b; ?. I$ V, ? ]' k5 p* O- U# C9 ]5 M| MCASP_TX_CLKFAIL 4 `' A8 p7 z* }4 B2 ?) r9 t
| MCASP_TX_SYNCERROR. h, u: {. q. D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% g4 y. g1 D( H y5 v+ B/ p/ W| MCASP_RX_CLKFAIL
1 Q) |' T. O4 s4 h& D| MCASP_RX_SYNCERROR 6 D) b/ T6 v& O' @- n5 k8 R, n6 A
| MCASP_RX_OVERRUN);
4 B$ D% k, @ {! x) p} static void I2SDataTxRxActivate(void)
; B# K* |: p' U+ D0 T{
- t a% O# ^% ?2 Y* j) j/* Start the clocks */
" D" N3 i+ |3 I$ U3 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 j- U5 w- Q# s( _& @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 @+ P8 ?' j, M3 u$ Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ E4 p3 r# v2 q+ h
EDMA3_TRIG_MODE_EVENT);
0 w4 E. o% T1 ~* Z8 b5 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 H% O& i, e4 z6 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( E5 \2 M! m4 A: o$ c1 T; f: J0 gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* c3 j b7 }. Y" h- {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ ]4 u$ S+ V0 l' s. _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 X, Z* M2 Q% p) Q9 m# b3 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' @- F/ a4 ^% R2 a3 Q/ D6 H5 g4 mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 M# @( ?* [4 t. o1 f
}
4 C+ E, w+ ^' P" Z" a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 j- x9 V$ ]1 h1 P
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