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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 p. [3 n0 O/ S0 Rinput mcasp_ahclkx,4 b9 U2 s( Y( l2 |
input mcasp_aclkx,
8 C5 Y' M& j$ q/ @# @input axr0,0 ~0 q* a2 B! p+ c. l
: u% L! h6 e! s5 v- E7 G
output mcasp_afsr,
9 ], O) l5 ?1 |8 _( Loutput mcasp_ahclkr,: ]) @9 |' V2 ~+ w2 F8 S
output mcasp_aclkr,7 c+ ?. q/ J# V9 b0 ]
output axr1,
) |* T& g. O, Q4 ?5 z) N+ e& ] assign mcasp_afsr = mcasp_afsx;
) }- J" Z# A* n7 K; b) Z+ k' fassign mcasp_aclkr = mcasp_aclkx;
$ M- _# u. Y3 }. u6 |6 @, \assign mcasp_ahclkr = mcasp_ahclkx;
) u) S* Q& ^! u! o: E# _$ V" ]assign axr1 = axr0; / s/ j4 N) `$ a! Y4 f
5 [& o" L" p# i+ W+ u( b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : ]0 q: s' f$ r f1 ]1 `' @
static void McASPI2SConfigure(void)7 A) a! @+ b( U, A- J5 }
{
, a4 y5 L& k% X4 E% n; {McASPRxReset(SOC_MCASP_0_CTRL_REGS);" R6 I! _, V, |" n, @$ i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ r8 G& I& C3 B3 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, k0 j( w6 U6 `: t4 P8 u6 u4 G8 WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; v } b6 D# Z3 L0 |6 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 b: B% d0 ^% d# V& q5 q/ gMCASP_RX_MODE_DMA);
$ f8 a0 L8 g$ {7 R1 T: `) a5 a8 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 H3 ~+ r. w2 e9 Y, ^+ H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: }& G/ J- \6 R4 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 C j: h7 `1 ^% e5 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. x# m) X5 ]0 C. b+ S* _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 M' z" S1 @: }- _* R1 Y5 y! uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ g1 H) s( E6 M, V4 {; ^/ m4 M2 RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# k5 a$ L) U( U3 B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, S( r. K# `* Y F+ [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 S, r1 |" f% e
0x00, 0xFF); /* configure the clock for transmitter */" A7 O) \7 }6 Z+ I. l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( l! b5 }# e. ?7 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ n5 {- @3 c' I2 c4 q* cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( G; p: D8 l" H- A+ O* f Z# j0x00, 0xFF);
* s8 G( I; N* H2 [% A7 E y4 R8 A; y
/* Enable synchronization of RX and TX sections */ * \$ Z2 J2 x1 w9 q* x9 q2 a' `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! [ e" w8 r1 D4 f) U! p- L) O7 I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; x2 |% H6 W/ M) w3 `/ d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; o# X% K4 t7 n5 u, ?: n$ M+ k** Set the serializers, Currently only one serializer is set as$ }; O# @9 R U& h Q; N/ z5 \
** transmitter and one serializer as receiver.* n* d1 Q" ?. h$ y$ V
*/
( V) |; ^" t. R0 G$ a; J6 I' J3 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 C' c% a) K/ EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& s6 v3 o1 K9 |0 W7 a# O# q) c
** Configure the McASP pins x1 x6 `. f: L" v- b9 _9 N
** Input - Frame Sync, Clock and Serializer Rx+ f6 q+ D! i+ Z4 r8 i8 P+ c7 O0 A
** Output - Serializer Tx is connected to the input of the codec
* c, r% I8 W! m1 R*/# N, x4 h& x; I: N( E" g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) ~' }/ |% R# h2 b# W9 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! y! ]+ j& H0 @% q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" A4 T0 G3 Y8 Y" m| MCASP_PIN_ACLKX
- d! }. s4 D; T8 _& || MCASP_PIN_AHCLKX
! Q7 J: K: U) |! B5 }6 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 o, o# F: K: U9 T4 hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - y* f# @0 X5 j' D5 ?
| MCASP_TX_CLKFAIL : p2 Q$ M7 t2 w& [
| MCASP_TX_SYNCERROR! O1 Z' @5 ]% ^6 g* G1 D% P+ s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 [, j7 G$ \: e3 ?, F| MCASP_RX_CLKFAIL1 @3 v2 V i: a3 {- f
| MCASP_RX_SYNCERROR 9 @8 f( Y9 @& a( o8 F
| MCASP_RX_OVERRUN);
2 _6 D* Y, e. w6 d d2 O} static void I2SDataTxRxActivate(void)
# L5 V/ v( B# L; y7 Q9 J A" o{
. o+ d& k" H. C* t/ \1 @/ p! F+ X5 n/* Start the clocks */
5 r# h; {8 I+ _& z* |" w& ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ ~ z9 z* `$ k8 A! O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 w Z% _1 [4 A, V9 i' h4 N: Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 `5 f/ b4 X# |$ i1 c
EDMA3_TRIG_MODE_EVENT);4 C2 E! W9 x! u" }. f+ [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! W3 i+ U5 M x _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( u# f0 [5 L5 j- H0 ]& eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* g& h% t- v* m/ V' GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 K" o2 Y/ ?% B a8 p+ r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 Z5 }: ~" W7 T- b7 K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( O& l; g- c/ k6 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& `9 k& J b2 R0 T% F' Y
}
6 I2 I* s0 M% I2 g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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