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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- ?. x* o* ~) D: V. Z
input mcasp_ahclkx,0 \; s7 ~$ w! m3 V3 k* w: S! I# z8 B
input mcasp_aclkx,
( T- H( D$ P L& _. v' ^# J, q0 @input axr0,
1 K6 e1 D8 m4 J7 _8 d# y9 I8 ? p% S" j6 i. J4 L
output mcasp_afsr,9 B' ^3 F) X3 P1 |& g6 i, ]# e4 p
output mcasp_ahclkr,. g2 ^. G! e* \3 N2 X/ Q
output mcasp_aclkr, W1 l3 t, S2 q, Q+ B, G `/ o/ q# h& Z
output axr1,- U+ T, d4 \" }* s* @8 W
assign mcasp_afsr = mcasp_afsx;0 [8 S ^: z' E/ }. j& F$ x3 u7 _
assign mcasp_aclkr = mcasp_aclkx;" \) h Q: a9 A5 h4 d
assign mcasp_ahclkr = mcasp_ahclkx;& d$ v4 T2 a, d+ ^# H! P0 s
assign axr1 = axr0;
; @$ S/ c1 J/ E( H/ Q0 @' `
4 X) n8 \% Z2 O7 o0 c2 b. \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' v H: {% }2 cstatic void McASPI2SConfigure(void)1 ~+ ~6 F# U1 S `4 }
{$ v9 O; R6 ~ W* E# Z$ E+ h- z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' R& l# \( M! V! X7 ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 M6 D) }( @ P5 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ o# z! @8 y, TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* x- y9 R# _; g: IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 Z; z+ X3 ]: ?MCASP_RX_MODE_DMA);7 a- V7 t& a8 y) o/ `( f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 e" c' }) r% O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" b% A! W9 R8 @# R7 y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 h5 B ?, W7 l7 D8 m$ hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 ]1 A; v5 ~6 p% g* t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 F9 ]* C- z* F/ Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. G5 i$ R3 U$ z0 }% E" UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 m5 L* r0 v# D; nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( e( Q2 B2 F! r% `1 U( B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ z; L8 n# f7 F# C
0x00, 0xFF); /* configure the clock for transmitter */
. C! o# K- k& ~/ |% i- vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 @) @ D# u( Z I: J* n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; E, {* i% j9 H4 d) e$ i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, | Q- f3 N' \) Y; q0x00, 0xFF);
! t* ?( U0 K" u. Q1 w; x h, F- F; W f+ f0 V8 C/ T w. a; p9 {
/* Enable synchronization of RX and TX sections */
, ^% F$ h) Z {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 V5 Y$ Z) C* Z }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) G) X2 |5 _. R( R, W, {0 M' B1 Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ S* j$ a' S8 c4 X4 O2 m** Set the serializers, Currently only one serializer is set as; q# ?0 ?: ^: ^) p
** transmitter and one serializer as receiver.1 Y- R# S* `8 Q6 N; {7 M3 }' y% Y
*/
1 R( C9 A; s. O$ DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 y/ S/ [, _5 u, K/ kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) @) I. H. x$ y$ ^
** Configure the McASP pins & w% H- z9 f6 X
** Input - Frame Sync, Clock and Serializer Rx
! H4 |. A& F- V/ e6 d7 _; S- b1 R** Output - Serializer Tx is connected to the input of the codec 7 e) \2 w% d: t
*/1 d# q W) o. r, d3 C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 {! f) C. _# V( m& a5 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" n# ?6 A9 R% T: d" M A+ RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ }0 A" Z; N0 ]% U+ d. L2 h| MCASP_PIN_ACLKX& y6 W: G. k0 N) Y& c& k% m4 b5 m
| MCASP_PIN_AHCLKX
' b5 m3 z5 m2 n( M! `. K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 S' G& }! r* X9 y# ?$ z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ R! a0 c/ z0 L7 l- g/ q| MCASP_TX_CLKFAIL / u! G) q: O2 b
| MCASP_TX_SYNCERROR
, w& v# D7 y4 t) M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , N0 Z& P0 y% p$ g! ~2 L8 ~
| MCASP_RX_CLKFAIL3 g- z2 i1 Q. x& _
| MCASP_RX_SYNCERROR
+ d5 [2 r$ b, @$ q& p| MCASP_RX_OVERRUN);( g" z" ]- e: A( O: m3 n
} static void I2SDataTxRxActivate(void)
1 t( w0 Z& K1 U0 M# l{
7 {, m7 \( O3 @* Q0 w1 C2 v/* Start the clocks */
8 {: w6 H2 M( NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ Z6 L' R4 [: l9 [/ Y6 Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: D! A8 {# _( w. b$ U) uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 \: _& O1 h' w6 M0 [0 A
EDMA3_TRIG_MODE_EVENT);
S7 y' B6 o# i. t# m! FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) S# Z7 T/ m# @ z# T5 |( X& f9 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( K3 w, O/ j5 I* @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! x) r! a+ I4 O! t+ v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* d; V0 d: [9 h# w; ]; Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 V+ I/ X* J8 Z6 a: LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 @9 _1 s9 C8 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) i1 g4 G5 T8 G* W4 D$ z} * N% `' u/ [# V- W0 K* G. Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % m) l+ c- e) O* @7 K, q
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