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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! a% [5 I. g D+ N! ainput mcasp_ahclkx,# n) r6 W" [3 t4 H% {" q
input mcasp_aclkx,
4 x; t: A' f+ ~" m9 y: R- N+ ]input axr0,& b+ G' N9 I" p5 q* a; F
( t. i* l- y9 y+ [7 i) U K- W
output mcasp_afsr,
6 n' b* v/ I- w2 ]# }, L0 Routput mcasp_ahclkr,
. g5 c- m; r. |' ?, joutput mcasp_aclkr," z9 f) }$ L, A$ Z
output axr1,& V# S+ O2 V* i* x
assign mcasp_afsr = mcasp_afsx;, R# Q+ O1 Q* b4 `
assign mcasp_aclkr = mcasp_aclkx;
6 w# y: \- m( L) _2 d+ v2 q+ Passign mcasp_ahclkr = mcasp_ahclkx;
( i ]) `8 l, @) k9 eassign axr1 = axr0;
1 F( {* c" ^5 Q( W( |
* L: U9 z1 L6 r. v* P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" `( J; ?# b: Mstatic void McASPI2SConfigure(void)7 A) h: G. i( R2 D8 e
{% @6 v( D3 i+ ^+ y3 t# L, n( {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ E h9 K" t' X) u) J0 b6 D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 l k L! T" |7 O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" Q: t& F, a9 H, f8 P9 q+ k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 i) v! e1 P7 M# L" d/ c4 Y% Z( BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) z& G% U( L6 ]- d' MMCASP_RX_MODE_DMA);6 R* G( a3 I3 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 i( |/ l! ~4 Y! ~+ ^' n) k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 ^4 H3 r) k0 ]( OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 \: _2 C* S3 d* H9 N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. D" N/ V8 [! y/ oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - \. v7 o& P4 ~8 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, x5 L6 B+ G# C$ b Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 ^# ~! {' Y0 E8 y$ j2 s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, ?( D Q7 ]! |. W8 l: q% q' G6 eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# j0 V9 D [- n" N2 t& c0x00, 0xFF); /* configure the clock for transmitter */
! O4 k. p2 {2 q: n% ?: J( ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 Z0 @ y' K8 M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 e4 |0 D4 A; q- K1 M9 K+ cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 u- P" I6 `* T- y" H$ Q, ^. X0 R0x00, 0xFF);
5 g0 U+ l, c% B+ b1 D# l9 ^$ K) P
7 w9 X4 n9 A* o5 s! B+ s/* Enable synchronization of RX and TX sections */ - J2 w( l! Z3 R6 H% n3 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 K( ?! f0 [4 h( H- wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# r0 V+ B6 _; Y. l1 b7 i6 I1 ]+ \- qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 E4 e1 M$ G) B. |: I** Set the serializers, Currently only one serializer is set as0 b$ y* b! X% F3 y! m
** transmitter and one serializer as receiver.
: k. e) o7 m3 p' E8 r" t*// w# D5 l) p6 b+ x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 g; s. }- b" ?( T; eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 H) P! O, B3 Y$ I$ p** Configure the McASP pins
% v) h# F- ^7 O7 B** Input - Frame Sync, Clock and Serializer Rx
2 I3 I% m7 q5 D. v8 D: D: n** Output - Serializer Tx is connected to the input of the codec 3 W1 o( \+ O# d$ I' j2 I0 ~% I2 [; B
*/
* n% v$ d1 K& W0 Q ]- tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% m# h4 a, V$ y/ ~" ^: C- {$ YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" W8 f4 K7 `5 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 Y7 k4 Q$ A7 ?3 \( M0 s
| MCASP_PIN_ACLKX
' q, [( ^. l4 M. N) B| MCASP_PIN_AHCLKX
2 K; Z2 }' L* d/ K6 F5 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* ~3 l- [( _! E) V3 J9 [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 L5 n; ?" h) J: _
| MCASP_TX_CLKFAIL
0 b( E* s9 c+ }% R| MCASP_TX_SYNCERROR
1 M1 U Z7 n1 a+ m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 P3 F& l; u) N
| MCASP_RX_CLKFAIL
$ [- M& S5 _2 t G| MCASP_RX_SYNCERROR 5 L) z4 P# V) }
| MCASP_RX_OVERRUN);
$ X* s$ c9 w. v: D: J# ^% y5 [9 t+ o} static void I2SDataTxRxActivate(void)) O6 z6 v, J) e* L' |( m# u
{
1 ~3 F- l0 l5 Z& Z/ m/* Start the clocks */
$ M a' A" Y& m3 r+ h$ H! F$ u% HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 ^+ |( f5 s' I/ h3 l A/ ]8 Z- ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 R. x) s {2 b& D' I% ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- x# {" V5 D U" A; S$ R
EDMA3_TRIG_MODE_EVENT);% [. O# S8 D: l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
Y" n6 m; p( I8 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ h- z' T+ \' N) x2 B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* M' G8 ]! K% M, E! ^3 K7 ]3 `3 t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 v s9 H; [1 g- I. Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 f& w/ t4 l1 Z$ W2 P/ C+ I7 I6 T, VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ O- s/ L+ \+ O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 X& _2 f) e+ B( f1 W: {- d
} 8 A! G t! t8 S8 z4 [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % }: p5 m& _ S# j5 b. P
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