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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 M2 l# }) e! @* }9 }; minput mcasp_ahclkx, k2 {( h* w( P
input mcasp_aclkx,4 W( q! W( d+ P; P9 A
input axr0,
/ _1 x( V5 C, H" k) N
% J0 D6 ^: ^; n R! C* poutput mcasp_afsr,
7 u% l1 ^8 ~9 b1 p1 e6 boutput mcasp_ahclkr,5 E, k# E+ s0 r2 ]
output mcasp_aclkr,2 J: `0 o- \2 T2 M. Q" I
output axr1,
- K4 ]' t" E, W, U, D assign mcasp_afsr = mcasp_afsx;) ] c' Y8 T* s/ Q
assign mcasp_aclkr = mcasp_aclkx;0 e0 _! q2 ]0 ^/ s
assign mcasp_ahclkr = mcasp_ahclkx;' P- y; ^8 j: z/ K: c
assign axr1 = axr0; * E3 F" s- m/ v: N3 B& X6 ^% \
8 [( L, B7 g9 o3 g G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 `( L* Z4 I6 H8 s6 nstatic void McASPI2SConfigure(void)/ \% R# ~, A S b: F
{
[$ B4 d; T f$ i4 Z$ f. k& LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ i9 s9 Q Y: A% k, i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! E- E, u/ N7 v) r( Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 F c. k f% C* @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* W# ], u( f/ T. y( SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* t. A. M& {5 YMCASP_RX_MODE_DMA);5 k% S W( D9 b* u' L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# H2 p. j& U0 u. g( L; TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ v5 b. ]8 Y: QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, I% O8 Z* }: B! V. H$ N% s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 P; h/ F$ k! ^0 l* Q/ t# e$ `" n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, z4 ]6 y: J5 x$ d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 F$ X. \3 K7 g: f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% W4 ?% s, ~. c1 x: H9 Z3 nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ]+ e0 @6 r; b7 `; ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 L% I# l3 ~. e4 P
0x00, 0xFF); /* configure the clock for transmitter */6 E( i% k! u6 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. h2 ?, a- g' qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ j' |/ A% l5 F( y6 l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 k9 Q7 |8 D& \- g0x00, 0xFF);4 d& M5 {3 D8 S+ F! p0 [$ B
' \0 B* n+ J: n# g6 b* [/* Enable synchronization of RX and TX sections */ ! u1 v& B1 _. ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# ?6 h* D1 ] e9 Q% yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ y% N8 N' Y! F- s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 ]( s& a3 M6 Q5 p; Z7 w( V
** Set the serializers, Currently only one serializer is set as
% Y: ~0 g* {* O; j7 j: l** transmitter and one serializer as receiver.
" Q$ ]! E, m/ J8 z( @*/
6 a8 Z: o. N0 _8 v9 S0 V+ M* d- oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 R* _% L6 s" H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 U8 H6 J' J; O0 _, P% A3 H** Configure the McASP pins
$ u( g$ }3 ]! v+ }1 r** Input - Frame Sync, Clock and Serializer Rx: n+ [% C1 v5 g- S
** Output - Serializer Tx is connected to the input of the codec $ e# ^# x i7 M) f
*/
* P* ^) f5 q- n9 v- u6 y- a& i$ y1 xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. z3 u! P, b8 t* k. `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 N) t" N9 l2 t4 L* B0 MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; n! s5 R4 x- e8 t$ }" e1 X2 a
| MCASP_PIN_ACLKX6 q( @$ Z5 [) \4 N
| MCASP_PIN_AHCLKX
( ]2 `: ?7 |! A0 [! B7 j0 l: s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 f: O' Y& i0 W. J0 G8 ~9 {, S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : T3 i, v& P& V; s7 |. i
| MCASP_TX_CLKFAIL
% {2 W u+ @( r0 e7 B! P| MCASP_TX_SYNCERROR
1 R3 R0 K5 Y, J1 ~" h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 \( }7 d! [. p1 Q* t6 t- f. K
| MCASP_RX_CLKFAIL4 h7 h+ C1 o) V2 T
| MCASP_RX_SYNCERROR
, D6 A6 p# |, r| MCASP_RX_OVERRUN);
D* X8 R# `2 e$ p% i4 }1 [} static void I2SDataTxRxActivate(void)
, s. h K% Q" z/ L4 [7 o{2 D$ c- B7 v8 F7 }' |/ G$ c; L5 e
/* Start the clocks */# ^1 S2 f l0 ^7 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% L$ s8 Q& x2 @( z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! _* O# a( |" z, h! k. S: ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, {; u5 T1 N8 e X+ t
EDMA3_TRIG_MODE_EVENT);0 _; Q" |7 X; w7 U3 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 T! E: ]( E8 d" i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& {: X2 a" P; l$ m2 R& ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) O- ]% ~, X. e( J$ d j" |- XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) R1 f* H5 G e4 `) }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ V1 U* q9 { _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: X1 A8 q( B. l' @4 J3 r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 e1 M4 a) O7 I" t; {, ^1 @
}
+ N" L( E( ~5 d$ m+ O! n$ ?( \& @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 d* c3 A# U) i! W; ]! H$ c
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