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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, p8 L( f9 S! b. @& x
input mcasp_ahclkx, J0 w" N3 V; k) q# a3 `# M
input mcasp_aclkx,. s. G1 S( X; p8 ~, z" Y0 x
input axr0,/ n7 G5 G/ C) h) {
& A( c# f0 r6 A7 W5 I
output mcasp_afsr,
! i/ e! y( M8 ^# d# l) moutput mcasp_ahclkr,
) D! c9 z7 t! ?output mcasp_aclkr,
( ^& E# P2 M$ x! C voutput axr1,
7 }. e6 Z7 w7 ^% @% g% R G2 Z assign mcasp_afsr = mcasp_afsx;6 O1 }* J6 @( X
assign mcasp_aclkr = mcasp_aclkx;
- ?8 {9 l; @% b2 Qassign mcasp_ahclkr = mcasp_ahclkx;7 b$ G; W1 }2 d; ?* j& k
assign axr1 = axr0; . W. v/ P7 D; |* u: B
2 P( f3 R- F+ ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " o& P3 A$ h$ |' Z/ ^0 R' y. G
static void McASPI2SConfigure(void)* G+ ~' L4 ^2 [. t7 }
{5 Y$ p/ D+ E/ `1 J; W% T1 Z% B: o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ W a4 N2 w7 k( o5 ?9 l2 _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: ^7 \& G# h. Z! K, j D3 ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* W( T ?; W. K0 }. A- VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: d( p6 I) V- y; c! i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 T5 k0 l. f+ {, O) f
MCASP_RX_MODE_DMA);
: z& v3 S: H+ j: J- g- tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 G0 l* Y5 Q) g) u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; ]3 r T& \" p6 t$ [: ^* j3 y2 e8 YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 W5 B- K# \7 j- {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ K$ z1 s# y: i5 E* \8 p" c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 v# {5 B r6 |7 E! z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 m! A- H6 K$ J7 `* ?: ?$ M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; j6 c; ~1 P1 Y& @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! H Y$ {9 p* RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* U. ^' \7 b- W' h
0x00, 0xFF); /* configure the clock for transmitter */
' Z& h6 v. H( u8 f1 b/ n5 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 b& Y) Z$ w& I' Z9 t. XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# X; O8 R: Z/ v+ |+ {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% M- ~! Y+ a2 u( U) T' J' @: o7 U3 r0x00, 0xFF);
! ^9 \8 o& r2 x- C$ |
9 n0 o# i* o6 m6 J/ N: u+ ]5 J/* Enable synchronization of RX and TX sections */
, d+ h3 p, m7 G( U( s! AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* k9 G6 L* ?* x- I1 X1 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! k. R- H# S9 k* r+ n4 OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. _6 x. h" L3 `** Set the serializers, Currently only one serializer is set as
" D) x2 r" f% { Z. f9 V** transmitter and one serializer as receiver.
- w3 S' {. a- J*/' c0 Z' b( B3 O+ L# T$ h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( ?% a$ ^6 M) X) r$ gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% K4 N9 n# q5 Q
** Configure the McASP pins S# Q1 T: J' s7 r9 n/ Z
** Input - Frame Sync, Clock and Serializer Rx
# P& t! y# h- E* E- h( G0 g' e- H7 C( t** Output - Serializer Tx is connected to the input of the codec
% }2 u' \# }% }' _( z, I*/5 \0 \' u4 r0 s# g- `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 ?6 I8 Y7 V5 h/ j) vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% f- U9 \* E; [. XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 {1 Q* ]# G* \: J* _
| MCASP_PIN_ACLKX1 @/ ~( ^: Q q! I' f" y# r
| MCASP_PIN_AHCLKX# y$ q; w" C3 _/ _- R$ `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 `) r. O9 S3 m: e2 K$ jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 R" }: W y5 D. L
| MCASP_TX_CLKFAIL h5 T6 y# D" b" J) b" e% k
| MCASP_TX_SYNCERROR
& Z3 t) Q. C* C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 N* d% t% z4 C- s" t
| MCASP_RX_CLKFAIL
7 q Z" O4 r$ N0 r6 p$ Z" ?' B, v6 L| MCASP_RX_SYNCERROR 5 u( }* [" `0 x( }
| MCASP_RX_OVERRUN);: A0 \) X) Z- q* M5 K5 z/ r
} static void I2SDataTxRxActivate(void)
* C. x1 V9 |* f* N{
1 T y/ Q( d) @1 V/* Start the clocks */
; Q; ]% I Z9 d6 Q q) dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: z- ~9 L/ b3 f' R9 S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 d, A3 S& Z8 P+ f& H! f( l3 H7 p" {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ o/ |1 ]$ J7 q5 [8 m( V! o3 oEDMA3_TRIG_MODE_EVENT);
3 D& Z7 N6 l1 ]4 V# dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ @& U) E' L. j: r. k( ~6 G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ ?$ u1 s* p, x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- b" k, ^# j1 e; m0 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( [- Q/ w& A. y) G- h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) E- E3 j3 S8 y& i: f. s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
S2 k: f: y% ?* LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 Q" G8 q$ s3 k* G# i9 i. j}
- Q# H7 |" a$ {! }3 Z% v9 X0 P" |9 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 u: g( V; V8 A& W# B, l' Q" r
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