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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ ]2 }$ {" ]/ J& X4 Z3 v
input mcasp_ahclkx,2 w7 T6 P8 l' \. ]9 `5 p. z8 |
input mcasp_aclkx,
, T, [" J8 S! g K7 I1 binput axr0,
5 K, f( {# t; L( Y3 Y* h
+ t9 i$ h$ h; K6 qoutput mcasp_afsr,
& h( ]1 A1 q$ P* Uoutput mcasp_ahclkr,
) i# P* b6 A: r+ u0 ~, d, Y4 C* Z/ ^output mcasp_aclkr,& r, Y; v1 a, g6 M Q& H$ Z
output axr1,
) u6 }2 s# h" c4 ` assign mcasp_afsr = mcasp_afsx;
2 L' D9 M0 ~; }# Yassign mcasp_aclkr = mcasp_aclkx;/ u3 v5 |* D9 p% g5 D2 g. [
assign mcasp_ahclkr = mcasp_ahclkx;' X h# ?& O4 t( h7 z) e2 n$ u4 [
assign axr1 = axr0;
0 b. Y+ d* ]6 C: P6 e. ?
. X2 H# x. r" Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # K' a3 W% l& I- A
static void McASPI2SConfigure(void)& r: b5 B; n" B0 M& C, C/ v
{
( M. `9 o: c' N! e' p4 T$ R9 Q, IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& J4 `3 Q+ b1 \9 y7 k" K' p% W! a2 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. U, k" T" k( M" BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) F2 Q6 ~% }* y5 q* z2 s9 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. v; W- c/ i3 _% r0 u1 _7 b( a1 lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ p; g4 I1 ]4 U/ {
MCASP_RX_MODE_DMA);
+ F- A6 L$ _6 B6 p' {5 x& s5 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 }4 K, R/ m o7 Q0 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 Q9 a. _5 s! N, ]; W& p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( C, _. Q, H! e+ b* ?/ C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ x* d0 D; p0 R5 Z) z8 u% V- G4 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 z. u" z: r" A$ \3 S( }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 j) J0 ^" M' E7 x& _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 S. r* }2 V& P3 {4 {- L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * r8 \: E. ?9 a/ R* {; I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 H- a. }, D. G3 G
0x00, 0xFF); /* configure the clock for transmitter */
4 f3 @6 z! F! o* X/ B4 d3 DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 z3 ^8 W9 J' n; ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 x2 O5 w {" U* i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ T% K9 v* X" g0x00, 0xFF); _. N% O# a8 Q; t$ V" p
H7 G* P" J$ @) v
/* Enable synchronization of RX and TX sections */
& v, S7 i. V1 T( {7 d1 M& C$ v( BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 D" c- d* `; E# c3 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 x) M9 q: C, O4 c; uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 \! _2 \; r, D1 B+ t
** Set the serializers, Currently only one serializer is set as
: t! U+ y: ~* q/ a+ r& U' Y** transmitter and one serializer as receiver.
/ Y9 C; k- U$ ^* i3 M! A*/
2 j2 m- h- l+ ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 e5 J6 ~ c* A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% i* k0 D& G- o7 h* ~2 J( ]** Configure the McASP pins
; s- T, p3 s$ M) Q7 w0 {; v** Input - Frame Sync, Clock and Serializer Rx r% x+ k: u2 V o8 }" G# w
** Output - Serializer Tx is connected to the input of the codec
: X0 M; j0 j% d*/( b1 V3 u6 ^ ~8 F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ o( `! j8 a3 j- P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- l. M! d1 b k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; Z9 ]* o9 e! X7 I; Y
| MCASP_PIN_ACLKX+ o& K! L5 J* U7 n
| MCASP_PIN_AHCLKX$ g$ S& U0 ]" O+ ^& S+ b3 ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: N$ s8 f& _2 K' U! y# CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 ?1 q; ^) M3 @) j- g4 [
| MCASP_TX_CLKFAIL
U9 H9 Q2 Z3 H/ t" y| MCASP_TX_SYNCERROR" }. C8 m! R% c* x m" i7 m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % _2 C' D* Y- n* d k' F
| MCASP_RX_CLKFAIL. ~7 |" u+ Y- s4 | ]1 `
| MCASP_RX_SYNCERROR
# B8 O1 Y2 K0 C1 I4 c3 n7 Z| MCASP_RX_OVERRUN);
. x4 m6 p- b q: o" \( G* M2 M} static void I2SDataTxRxActivate(void)
5 D: ?7 W. A7 Q- F& {/ F{ R7 o' x" S6 O# R- d# L/ n
/* Start the clocks */2 U1 m3 u6 |6 {; K( O2 s+ t% Y* K* Q0 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' P+ L p- _7 i6 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 Q; c3 P" l7 i3 N# x) rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% V$ m3 b1 O/ J2 T& q5 m+ UEDMA3_TRIG_MODE_EVENT);; b$ P2 b1 p. n0 f3 W7 o: B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & Q% z( O- e# v( a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) X) Z# J: s- ^- m \/ v0 m3 c( w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# y7 v! [( e& s# v) C7 H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 Z1 u1 e4 U. ~, _; ^" Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 x/ n F" A( J! y1 n8 I' z+ h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 H: N% i; j7 J' d4 y8 ~4 w) yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ r/ l1 K: x$ C d8 \- }+ J}
# Q% J1 F" S, m. x& C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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