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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," G; ~- ^0 w7 f$ x
input mcasp_ahclkx,
0 P8 C. r( \: G. u' V: D" t: S/ \input mcasp_aclkx,1 t# ~( b8 P: `$ \7 d3 u( ?( A
input axr0,
) L" U) r4 r. {/ T8 G4 F4 O1 t$ o7 `+ C: o0 Z
output mcasp_afsr,
0 j5 m1 w; l5 Z2 ^, zoutput mcasp_ahclkr,
# O7 c9 N) X+ Y) x" ?5 {. doutput mcasp_aclkr,
# e8 i" I0 \, C( W2 f# P9 Q6 Doutput axr1,
5 U: L; \* F M4 C4 f" z assign mcasp_afsr = mcasp_afsx;
- s( a1 }/ v* H+ p/ Y" Uassign mcasp_aclkr = mcasp_aclkx;6 I' z9 A! E% |2 G4 i- r
assign mcasp_ahclkr = mcasp_ahclkx;+ E1 H# P6 Z9 e) ^$ m
assign axr1 = axr0; 3 d3 {$ @) I5 N
1 W; [- _( z8 S) w2 o3 b5 F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- ]9 u3 V2 N! e; ~static void McASPI2SConfigure(void)
g; m. L2 X% K8 W1 O{8 k/ O. \; t, ]$ Q- q2 B8 R1 S' ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 |. n* e" k# _& _$ v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; r- `" R' }. s% r) Z+ o) \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& f( a+ ?# @" F- dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( z4 P: _# ~: s+ K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) T. g" s5 K: ~/ {; mMCASP_RX_MODE_DMA);
& O' x) ^" {+ W4 w1 O5 HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, L2 y8 v' N+ o. }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* n# }/ J3 y5 B: b$ ?+ D: EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) J5 }+ n4 B6 A! T$ Y( {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ F, z9 }6 B) l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: g% A( W" U: z& t; E+ c+ zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% d: B+ L/ n% A4 JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 E: ~; ~% ^: g( T+ \) j( ~5 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); N; Y0 P: k: G9 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 N |4 \; J( b W2 G6 E6 f
0x00, 0xFF); /* configure the clock for transmitter */# o. ] P# Z: X, V9 p; C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& N/ ^8 I! o4 SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) N, J- y0 m8 [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; U0 r0 W$ c$ F. S; G. l0x00, 0xFF);$ d0 N5 q0 J+ R0 _6 Y
0 V, D9 N3 N) x0 q# F! y0 [' N
/* Enable synchronization of RX and TX sections */
! |0 ] c" s6 }' H7 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) N: f2 o( M! n1 ^+ Y& XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 S# H3 ]/ K9 ~: r& c5 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 x) r: f1 l& D& x* A/ i2 k( D" w
** Set the serializers, Currently only one serializer is set as8 o$ Z5 n3 u% Y7 O4 N8 y
** transmitter and one serializer as receiver./ E* R; J5 _- S2 a
*/( M3 @) p) p* ^6 s) R3 W- a1 o; u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: k) R$ P p! Z: t% e9 l4 }5 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* Y* j# }! {' ? f** Configure the McASP pins
3 J d$ h- Y* _6 u8 g& H" g& G& O** Input - Frame Sync, Clock and Serializer Rx
9 w4 Z* {" B; w# [ |6 m** Output - Serializer Tx is connected to the input of the codec # \) U* l. [3 |0 X% A. f+ {
*/
: x* ?% T5 F7 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- ^2 Z8 w8 W$ ]- F _% _) tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 d$ W' I% e# N V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 C5 o$ V3 ?, _4 c& _ T| MCASP_PIN_ACLKX; b( S) Z* ~7 t3 T( l
| MCASP_PIN_AHCLKX2 ~/ y. Y" d: L4 y7 D6 a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 ~( g. A) I1 G( C3 K% U' gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . Z N) E! \7 v7 O
| MCASP_TX_CLKFAIL 3 L$ `9 h8 I4 ^, Q
| MCASP_TX_SYNCERROR
( x3 [% d3 M8 Q: k9 N9 k. E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 K2 m# `* N3 j( a3 P" h& @( t
| MCASP_RX_CLKFAIL# D' v5 J1 [, G7 `* e1 u" n
| MCASP_RX_SYNCERROR * \4 E3 |9 b. y! w4 U
| MCASP_RX_OVERRUN);9 ], u5 z' x4 \0 B1 Y4 w+ Q! l3 w
} static void I2SDataTxRxActivate(void)! y6 G" L& X+ c- d1 ? y: F* y
{
! i0 a4 C1 I- b0 y) L/* Start the clocks */
1 M) n1 r, _+ A5 ? FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; m' I! r3 t+ G( y( ?$ F' L4 e |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) V! r, m9 v1 L9 [4 t2 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ t$ g. r" y5 o* hEDMA3_TRIG_MODE_EVENT);
1 }6 q5 D' l1 B% d2 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 ^( P% Q/ m, x5 \5 c5 R# `: g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 A) e- o" Z7 L& S3 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; Z# M% n% Q4 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 p5 f5 O2 b0 X+ R0 s ]- @; \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# N9 M4 |( e9 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) Z. A# [# m' M5 v7 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; e& d0 ^% _" f* ~9 t1 J7 @9 I}
* H7 e5 y: u5 y6 [- X% R9 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 p# t5 J+ W3 T3 U: R
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