|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 b4 {/ L8 e( Binput mcasp_ahclkx,
4 P% N# l5 Z& _2 m( J+ w3 ainput mcasp_aclkx,! Q( e* z, v3 E& `3 G
input axr0," P+ s% D0 q) Y6 n4 O3 S
4 _6 r2 v: G# k5 X# d: q( U+ aoutput mcasp_afsr,
1 `* J, H0 z6 E8 t0 Y0 a7 w/ ^output mcasp_ahclkr,
2 f+ m( D+ X0 ^; Q6 W3 y% routput mcasp_aclkr,: g$ y" A0 ]( n, R k$ I$ }
output axr1,- x- K/ d ?& D$ r3 G8 ]- b
assign mcasp_afsr = mcasp_afsx;1 W C5 q: e0 p% P# R
assign mcasp_aclkr = mcasp_aclkx;
2 @6 E' h$ |; k" a( a0 d1 L- wassign mcasp_ahclkr = mcasp_ahclkx;
) M9 b6 b% y+ ?1 R8 vassign axr1 = axr0; 6 ]$ S0 m8 w( a) O2 `0 `
- @3 K- U( L5 D% r9 X. C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: C( d0 R8 g `9 S/ Ostatic void McASPI2SConfigure(void)7 }7 X4 C% V1 M2 G% {( W4 n
{8 A$ q, K4 G4 U- G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 k) J9 p2 N$ O% o; a, CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 ^( v' U- |* O4 G7 X. G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 y4 o- n+ g" y5 _* I6 K! R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( _- E9 B+ j ?& `8 {0 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- E: K! v4 |: p, j- ?
MCASP_RX_MODE_DMA);
* q K$ D- r: m8 O8 PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& A+ ?9 o; s" F$ b5 CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% O+ f% p! J6 @% ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * N: E1 j+ s( M3 F' x/ F% K* l9 u' V9 _# B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! z, o$ B* Q. v/ ~1 R+ x" Q W, SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 l. |5 p% z9 h. b4 p! tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ m; p1 E1 C4 m$ f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); n5 @( |% x$ L8 P7 _. t# `: z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: A& k$ q$ m6 w" w4 l' C" xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; u% W" J9 _$ N7 F! K h0x00, 0xFF); /* configure the clock for transmitter */: \) l, i& J* O5 J" J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 `3 b7 d! L1 c$ r8 TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! t, Z( |; @, t3 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% o) o. y% {& g r7 X- X% m0x00, 0xFF);) R$ ]3 S% e$ k
. A7 a( W! u: l# \8 X0 G6 S; o9 y/* Enable synchronization of RX and TX sections */ # R% w9 j) _9 ^. }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 u* w( X; [4 t9 W" ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! Y' _# E& ~+ q& @2 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( Y8 ]. r4 J* P Z8 g; N) Z** Set the serializers, Currently only one serializer is set as. [' C+ p8 o9 |2 w! f k
** transmitter and one serializer as receiver.
& @) c E/ u0 N*/
2 {9 o" \* Z) f$ FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 z% t6 v0 r6 |6 @$ n( HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" f- `& A T# Z/ i) W! F; }** Configure the McASP pins 0 b6 z+ N( Y3 X' M
** Input - Frame Sync, Clock and Serializer Rx0 I! H3 `8 s* ?6 N" _
** Output - Serializer Tx is connected to the input of the codec , u( b5 y u% n4 m
*/8 b+ H# ~8 t/ a* l+ \! A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* d4 N% o3 e p7 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 y: g1 X5 F* c! I3 F# L' u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: a- c+ c7 G: {4 o% ^| MCASP_PIN_ACLKX z1 c& b B8 v0 T
| MCASP_PIN_AHCLKX8 g2 Z( U4 K; [1 e; O4 i% H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. q8 S! O$ j+ r/ {2 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 Z# V( O3 b5 o- m| MCASP_TX_CLKFAIL
, v3 M. }7 c- e3 ]| MCASP_TX_SYNCERROR/ P$ C# a6 R' G0 ?" n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ ^2 p" M* K$ N/ j2 F# U7 D| MCASP_RX_CLKFAIL+ j0 M7 i7 g7 v! E; k* T- G
| MCASP_RX_SYNCERROR 5 D+ t7 u6 }/ a) _
| MCASP_RX_OVERRUN);
6 }' f4 q. C. f( e" g/ C5 o6 z& l} static void I2SDataTxRxActivate(void)
7 K I" L' _5 f" ^{0 Y6 U8 W9 Y! i( j
/* Start the clocks */7 K7 j5 H1 Y; Q9 [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" J8 w. T7 q$ V- C" l! s* n7 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 b4 a9 Z' [( t' l1 K J0 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; v# b0 x- O9 h/ e+ @/ W/ }. z0 sEDMA3_TRIG_MODE_EVENT);
$ h5 t2 |0 a5 Q7 \0 v+ b) @) w, w( G2 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 m7 b/ ^4 I: A; D; M' cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 }# y X3 W. j$ ~7 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& `8 s! T) m1 `& j. JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& q3 Y q+ l: f8 [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 ^9 r0 V; b# A: j3 {5 u8 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 Z0 M% I6 o+ y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: N% M/ c4 I3 {) y! Z" L
}
4 n# y3 R$ I2 _2 X' S$ X& M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # _! i; `7 ^3 Z$ S0 Q
|