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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# {. ~! p6 Y+ E# r/ f7 P( o! iinput mcasp_ahclkx,
: o& j& l, ~& m) w3 Y+ _! l6 vinput mcasp_aclkx,
* O% I% y3 w' L; r" uinput axr0,5 O" d% f- U+ I6 V8 d% I7 Y: z: ^
" e% r6 J' o% ]( O- x Routput mcasp_afsr,1 F# t, D3 @/ V5 v; ?0 Q
output mcasp_ahclkr,9 ^; l7 ]* w( B' W$ k4 h/ a
output mcasp_aclkr,
* c+ s* {9 H; W1 w0 x/ e* `output axr1,! c' @/ X& G5 ]' `# o Q- g
assign mcasp_afsr = mcasp_afsx;
( Q7 q7 m, j/ sassign mcasp_aclkr = mcasp_aclkx;
+ d5 ~" x0 J9 {3 p4 `assign mcasp_ahclkr = mcasp_ahclkx;- b+ u; k% u5 u+ O4 L
assign axr1 = axr0; 7 T' E0 M6 @) V7 f( V& H
- [- o1 c# G$ |# K: Q5 G6 p8 B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- o$ k. H; \. ] ?) D7 Q5 J# B) V# Tstatic void McASPI2SConfigure(void)' x/ g3 s* u, A# P
{
% }% Q6 x' ~. }McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 X5 F/ K# F1 @1 }, T5 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 b- [! l( y7 d0 `2 y+ p0 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) l' L: N& p* @$ Z0 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; k0 s! T! k) `$ d9 p4 }6 u+ L0 |; C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 k6 v, O, n5 X) M X; P$ Y4 x g+ {
MCASP_RX_MODE_DMA);
5 f! t5 t& W- p9 O# `5 A% ^9 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; q/ g+ r4 P2 }, P" P/ q0 ^# D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 \6 s* m/ O: @* [- h; W/ nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; {3 W& s; d5 t+ Y6 @$ L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- Q; k% ^9 u; i5 x6 g1 k% `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 m$ p9 l% P' u& G1 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 |6 R4 C7 Q9 h& a% ?, \! G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' X e/ i7 } J& c3 `7 h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 k1 X, y$ E( ]4 d* E( lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( B% e- T, y( ~1 e- G
0x00, 0xFF); /* configure the clock for transmitter */
+ Y9 e* o, K, ~3 ]8 D: \8 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 Q1 ?, ^* J: U; R- `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 h1 S- q* t4 |, E/ d0 B8 uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 e* z- C6 y A$ ^: ?0x00, 0xFF);, p: I: x$ j7 G F/ }6 m
8 X O$ A; p! ^) S4 t
/* Enable synchronization of RX and TX sections */ & P7 i3 M- r# {" ^! V' T5 t0 W) ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) [) E1 W, W( q dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# |# P5 `* ^9 W1 @- q# g9 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* l% _, w. N0 ~ U% k
** Set the serializers, Currently only one serializer is set as
$ I0 ]0 [- _; b3 `** transmitter and one serializer as receiver.3 W7 E& r+ r/ }4 p( [& J3 ?
*/9 ?8 D' y3 V) _. j" ^' o* b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ [7 d4 L; T5 I: S* sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 X Q9 P8 X+ c/ U0 Q** Configure the McASP pins
+ Y- P" ?' V7 d/ ]** Input - Frame Sync, Clock and Serializer Rx
I! J) Z. N* J$ w3 q& b& r8 Q** Output - Serializer Tx is connected to the input of the codec ) C: G/ j# i- R: o7 M
*/
5 @$ V% I' ?, D' f( I! K& T4 uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( p/ D% i$ n4 I6 |9 W" ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& d2 |# `7 s1 ^ L1 U8 X5 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 H% W) v% l6 u2 Y; [| MCASP_PIN_ACLKX
: N3 w) j Q) M% `| MCASP_PIN_AHCLKX/ g& \5 x4 {) o2 ^. ]) t- S$ X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 N& f% a6 y' a' {9 l/ ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 s9 O9 g& g( t! a' r| MCASP_TX_CLKFAIL
9 D2 O" k: @. s, [| MCASP_TX_SYNCERROR8 G5 g6 L* N0 J- c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 f; ~& C8 U: X |& ]$ Y& O| MCASP_RX_CLKFAIL: q4 O& b4 u( o( t6 m* _5 _# G
| MCASP_RX_SYNCERROR
0 v F5 m( T7 S4 C| MCASP_RX_OVERRUN);
4 d6 N# h1 \& a$ q} static void I2SDataTxRxActivate(void)6 ` c& b% ?8 P9 H- Z
{
3 K( V& `0 m: W" S% B# J/* Start the clocks */
7 k! d; ?4 d$ Y) u& N% nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- e6 w( g' a" w' r Y# X$ UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 U) n6 n5 Z9 l! t. H/ HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ g: {7 A l, [* d/ O8 F f4 G0 vEDMA3_TRIG_MODE_EVENT);, f2 n3 u7 M" F2 G2 ^; ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 ?: Y* Z* U# W( q) J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' q. ~% s; Q) s/ P# O& K9 i+ XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- P- P0 H# i F: x- e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 G" O0 c; P; rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- ? ?! U) m7 D5 d. \7 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) e( A* U& j! j2 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 o+ n; J: ?# N) k}
3 V* h! q$ C( y2 C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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