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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 R% H! P7 {9 D x$ cinput mcasp_ahclkx,
( f) I* ]* r& p f! jinput mcasp_aclkx,
+ T! Z6 U: Y" N; ninput axr0,+ h( U: t- n! `8 U
9 f1 s: c g+ a' N2 B. A
output mcasp_afsr,% L+ p, B0 V0 c- Y9 T' l
output mcasp_ahclkr,! [# G- w0 O: I: N) G' k5 _- l
output mcasp_aclkr,
. D; _& c* s" \1 w% }, doutput axr1,
7 l1 c2 Z. x$ q% ?9 w- C assign mcasp_afsr = mcasp_afsx;5 O* O+ C/ w3 M% V
assign mcasp_aclkr = mcasp_aclkx;/ e% y, y5 @9 a2 j& @% W! }; o# H8 p
assign mcasp_ahclkr = mcasp_ahclkx;; d0 |7 \+ E8 f0 T2 @! B& f- u
assign axr1 = axr0;
' ~, {5 {$ P2 D) Z6 Y( N
4 Q6 {( e% L( s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" W/ l1 E, {* s6 n. {8 U. ^ Cstatic void McASPI2SConfigure(void)
! q) E9 \( r+ P3 s7 d. v{4 f+ n* ^. o6 M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ u0 [3 d" A6 G: G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 a- C( ~; t& M9 K6 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) U& T/ s6 f6 R2 x/ w/ xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& y+ A8 c5 y( M8 v/ j) k. g8 _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 u9 U3 d! f/ ]; F3 w2 Y3 q! Q
MCASP_RX_MODE_DMA);+ ~9 G5 U! u( z% J) K. J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
`. Q3 a s1 T TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- K; x+ f# w7 C$ J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& R" S i7 `# a% \8 g* EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% x1 L9 J5 a `) X" kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! a0 g3 E# G$ } R( ]* qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- g- Q' Y! m* K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& ?" ^7 G* ~' \/ w: b! y+ [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , _" `- Y; N+ B0 c* R7 w! h( m% s0 i# e3 X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," l. \, `* I7 [$ o k, D0 [
0x00, 0xFF); /* configure the clock for transmitter */- z5 H3 `' i* S7 }1 h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, J! {$ ? a% L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 y5 M( l) N2 J; j7 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( V( i: w% D% E; u1 Q) W" l
0x00, 0xFF);
6 F: s/ ^. w9 `* G
5 ~/ J: L: ~5 z/* Enable synchronization of RX and TX sections */ 9 j& M% P5 C$ d( o% h% |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% d* l# p% [' G# ? I- A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 Q A+ i# e3 \* i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, Y! n; U: r+ r. s** Set the serializers, Currently only one serializer is set as+ y' C4 }+ @/ D# h1 A4 T
** transmitter and one serializer as receiver.5 i7 r! H0 |' i' | ^
*/- w2 }, ~8 M f s# ^7 g1 ~+ u1 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, I1 _7 j/ M9 N- b4 Q0 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ z/ V/ F1 ^) J2 J; @6 v9 X
** Configure the McASP pins
" R' D. y7 e7 _6 X5 {** Input - Frame Sync, Clock and Serializer Rx
8 E' X5 P, J. D! g6 p+ B- N** Output - Serializer Tx is connected to the input of the codec
8 i* E6 W: C% h' t+ J( r8 F*/# F8 D6 ]1 M0 J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. {- }9 z8 L7 q A, D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 ~ ]4 x2 I6 W$ a1 X+ EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ i5 ?: N& N+ |! s8 ]& T
| MCASP_PIN_ACLKX
/ g& t8 T) p+ e( _* N4 L| MCASP_PIN_AHCLKX! a7 c: h( [' C, k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 P+ Q. a$ q6 e6 W. ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, z" \+ _; e0 I! T| MCASP_TX_CLKFAIL
* T3 I2 V; {7 j! C# b| MCASP_TX_SYNCERROR. d- Y0 ?9 Q# }" W2 r5 w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- x/ d( s9 i j' ~| MCASP_RX_CLKFAIL
% P& F5 S* Q& x; n" e9 X; W| MCASP_RX_SYNCERROR
3 x; j& x2 H* ^4 M1 F% M| MCASP_RX_OVERRUN);8 v5 Y- a( _: ]+ E5 i6 T; R
} static void I2SDataTxRxActivate(void)
8 g+ O2 t1 n* V/ T% x{
; z9 e6 s8 }1 o3 E8 o2 b& h/* Start the clocks */, ?- Y, f" K* M; P6 \$ ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! \0 J9 E& K a- m) g6 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; n3 `% z" n) o1 H: {; S) KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( X3 ]; p3 M* ZEDMA3_TRIG_MODE_EVENT);: ` O t0 T! X0 Q5 U7 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% d6 y4 V3 e5 }* v# k, E5 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: i+ k: g; P9 B% Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* w7 y& t( p& z& B! \* B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! K" Q4 i% y" B" K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! q1 m6 ^9 }+ `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: ?0 f. k Z. c0 F+ n) ~# \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; H( P6 ]5 r; U% }4 A' a% ^
}
a) Y6 Z8 R' N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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