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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* v+ r t$ L/ O& Minput mcasp_ahclkx,- t8 o( v( t4 _& H2 P: x7 a- X1 f
input mcasp_aclkx,
9 M& `0 P7 N, ]# [ |% j6 N/ ninput axr0,+ W& R: O& h3 E) n$ }4 N
+ E% |' S: f- l9 | {& a
output mcasp_afsr,8 m+ t* ^8 M+ }! S
output mcasp_ahclkr,8 O- Q- P( w- v. w2 x% _
output mcasp_aclkr,
* ^ w& w" E" k t' f Aoutput axr1,
3 h$ c' U+ m" F7 M% w0 m5 I assign mcasp_afsr = mcasp_afsx;2 M' S- i- J9 G1 ~& r- _
assign mcasp_aclkr = mcasp_aclkx;5 Z5 M) [) h" y7 \
assign mcasp_ahclkr = mcasp_ahclkx;9 {0 x" k+ I9 _' _% {1 p! e
assign axr1 = axr0;
2 V1 w7 T- y/ R7 A, ^/ _) Z# J5 ~$ n. c
1 m/ C5 m* P7 J1 O( N( M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( b, O( c* W5 W5 [static void McASPI2SConfigure(void)
+ k$ E' X: \* u3 _% B2 G" A{/ p* ^; D/ k% m% f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. \9 T# _4 X C# ]: Q2 \( uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" I7 L8 F7 [; o, n2 T9 t4 i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& l! e0 i% @1 x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' n7 R8 G2 u& y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 i$ ~2 `: r* G4 B
MCASP_RX_MODE_DMA);
% x! \4 ?# B0 \ M6 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ z. H& e& Q xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 B9 K4 E/ d, a2 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( ~/ n) G$ E+ a! ]; P" ?" h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ ~( N# D/ r0 A9 C1 C gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ X, _5 v; ?4 R/ n" ^2 z& z( U; N1 ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; T* B/ ^ R4 V- z# K% Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; |- ^9 j9 @9 F' u% uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 N( B1 b5 @# aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, n" @) L8 u- a I9 S7 n
0x00, 0xFF); /* configure the clock for transmitter */' W/ s+ ~+ @- B1 e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& u+ V) C$ T$ U# j* i8 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ M5 u( r% Z B! c9 D8 ]3 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: @/ a; _& M0 ~/ p) |9 ^9 @0x00, 0xFF);
+ ?+ Z5 \" S* ]! M7 _( W9 H+ B5 H: w. N0 S
/* Enable synchronization of RX and TX sections */
! _+ ~2 Q" u; }. aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ q8 e0 S q5 o1 K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# _, r5 n$ a; k3 A& @' S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& K8 L; }' k' r* W A( q+ P4 q** Set the serializers, Currently only one serializer is set as9 X6 `! [5 Z+ k# E$ d1 u
** transmitter and one serializer as receiver.5 f' d; r- ^9 y3 y$ p
*/
4 a5 v9 e3 L) d0 @+ eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: [! B5 K; O/ ?: {8 X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 K/ a( e9 @1 f
** Configure the McASP pins
2 Z. ?, m& I2 Q/ V2 m m2 N** Input - Frame Sync, Clock and Serializer Rx1 h" N, ], D: o" a+ e. x
** Output - Serializer Tx is connected to the input of the codec + y3 @ W# [( K; @" o
*/
8 z- @' Y. w) t3 w( VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ R6 K+ \2 ]3 x" h" Y" N5 b6 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 a& p W" ]3 D8 e9 k( R8 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 W/ R5 j3 X/ R
| MCASP_PIN_ACLKX
$ F+ p! { v; E& ]. ^| MCASP_PIN_AHCLKX
& o4 D3 j3 b6 F* ]8 O% {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ u( Z+ y' q7 e K3 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 N/ c. Q$ L! f/ i+ R5 ]/ J3 S| MCASP_TX_CLKFAIL ! N5 R5 \0 C9 V Q( H- ^0 m
| MCASP_TX_SYNCERROR( ?& o) \9 g) K/ \) r5 F4 Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 ^# z8 Z% \$ f- K9 M7 M' c| MCASP_RX_CLKFAIL1 S2 k) |/ v8 C
| MCASP_RX_SYNCERROR , l8 f) D2 a4 T: y( j. t: @& j5 D: g! d
| MCASP_RX_OVERRUN);
2 z u6 j/ @3 M T} static void I2SDataTxRxActivate(void)$ w6 t) E/ n+ z* L0 @
{. t4 V2 i) h+ y+ x( S+ E
/* Start the clocks */. [# S V$ g3 W! z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 N* S' \9 x# X6 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 T3 W& `- W6 o; ^. k5 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 u, n7 [ E+ k3 X/ [. o' a
EDMA3_TRIG_MODE_EVENT);
, u; c' z" E- f8 @. z0 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ `. R( H5 \1 F% p1 H3 b! DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' l2 [& S' w% a. U' g: o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. X# u% E1 p/ t0 M7 o) l; r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; t p9 R9 p# `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 B/ o4 J/ M- J0 L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 [2 K, P0 x; |' kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( p% g' y, H8 ^. a& e
}
' D- a% S* s# r+ ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. Z* r/ V) ~' h {
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