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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 X# ^& b% ]" g
input mcasp_ahclkx,; k T0 i% A; @! P( Z; i3 z
input mcasp_aclkx,
3 C& e6 B; R+ J, b( @1 Sinput axr0,& C* u" j) ?9 T3 X" k
+ E3 Y1 R& P0 [. w" U& k& G9 z- Xoutput mcasp_afsr,
0 I/ K# z8 z s' { x- @, Q" }output mcasp_ahclkr,( H+ f' ~2 W" l I5 _. \5 L3 I
output mcasp_aclkr,
2 S) ?( K+ B9 w7 ?) doutput axr1,7 B! g! e: H% n" }0 v
assign mcasp_afsr = mcasp_afsx;
: {2 R- x, W3 K8 J. s8 ?+ Uassign mcasp_aclkr = mcasp_aclkx;
& \/ z& Y/ n: I8 ~* Q$ lassign mcasp_ahclkr = mcasp_ahclkx;# N* C0 S# u x3 w2 X7 C8 ~# C
assign axr1 = axr0;
/ E* ]" S$ ]$ T0 ?5 G$ @7 ~6 Z* w3 G3 w2 E! p9 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 l1 W/ A- ]. B5 V, T% Y* f3 K
static void McASPI2SConfigure(void)
: R/ t* M+ a: ^7 W4 N{
' T2 E6 U9 ~7 Q8 k9 pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! c, R2 J9 k9 L$ z0 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 B. J! W8 b* \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; {( @) m0 `/ m8 c+ wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* q0 ^6 B! g3 t. gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! i, K$ m% Q5 j0 P7 K! d1 pMCASP_RX_MODE_DMA);! m5 L4 y2 c8 b$ W7 n1 b) t" w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& i2 u; n3 [! }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: s+ D( c) I9 i4 E! e O( \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 M% b3 U0 f5 E$ i$ B/ J$ |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 w8 E* T9 u6 H( r+ h. m6 ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 C' G3 U: c' B% q/ C6 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) u, T9 U# u$ f9 b: F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- t7 u$ x% y- Y- e S4 m9 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! {9 Y% V; ^, v, d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 A5 h0 Q. R1 X) L O+ f; |2 f" {0x00, 0xFF); /* configure the clock for transmitter */, }3 [0 B! Y; o( i! r* q1 e7 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 E; [; X: s- G+ A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; K4 Q0 M7 ^9 N @/ V( P/ }6 E; xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 o4 v4 {" Z4 A1 o0x00, 0xFF);
, F. b1 B, S* E/ l \. o$ b( \9 c$ j _( ^6 X# d
/* Enable synchronization of RX and TX sections */
& s2 Y5 v/ I3 y3 I/ vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; n' y: v8 {: |7 a9 B* t9 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; n) y" Y& [, O' T% o# q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 s7 z' Z% [2 `( J' N7 Y
** Set the serializers, Currently only one serializer is set as
: n6 d" V4 F; L! B' g" o4 g7 w** transmitter and one serializer as receiver.
3 V% R a6 H. V: {$ d) E" @*/* f' ~) w& n! l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& p+ L1 {" t8 {# R F! gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 o6 T8 i C9 i* m7 o) H** Configure the McASP pins : x% |, L) k/ w; a6 o+ g
** Input - Frame Sync, Clock and Serializer Rx, S, |. ~% h8 p9 @; L: n: X
** Output - Serializer Tx is connected to the input of the codec
8 E4 T2 w% U' v( P5 l# B0 E: ?*// E5 s5 B2 {2 T1 `, e( J9 i9 @5 Y9 q4 O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( y9 n; `1 y. A c$ sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 B/ u& i6 d4 K% W# n" G: ?# z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! S9 _# o* o( B. j| MCASP_PIN_ACLKX
% z$ |4 o' G, w5 i- K) u! z| MCASP_PIN_AHCLKX
4 D. `( U. f2 K7 F( _7 ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 P, @- b% v: _6 B6 N6 T0 V' }( @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# M, U5 s7 N/ w' m| MCASP_TX_CLKFAIL * x, Z" M9 K7 e# g9 h' F
| MCASP_TX_SYNCERROR
$ R0 M* f$ g3 J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( h& J4 H: ?) t. U3 _: a/ d| MCASP_RX_CLKFAIL4 O. x" w1 a0 y- }2 C3 `9 J
| MCASP_RX_SYNCERROR * F: N3 G) b! [8 r! z3 L4 U
| MCASP_RX_OVERRUN);$ ` w" u) M( l: G
} static void I2SDataTxRxActivate(void)
2 x$ A- J) |/ P# R! v{: P7 |7 c5 r3 c
/* Start the clocks */
# Y7 `$ _3 ]. i n% A7 i2 p/ R% fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& i" t! z" F( nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) i8 p* P# X* S2 R6 T8 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, C" k; P2 ?: ]1 p+ F1 q7 |
EDMA3_TRIG_MODE_EVENT);1 V+ h5 b' Z1 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / z; h4 c6 `* B) d+ t8 w' @; P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ c" U- k) @* I0 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' r# B( k4 P# _* H) P. A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 l# w& D& O" G1 B' y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: b& @6 t- \! H% V3 F) O" ^7 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! E9 j7 y& @4 x. Y1 q3 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 |# R m+ g' _
}
1 z3 \# L; b! V7 G% c/ l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , q. W& {# J- q Y& S j
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