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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 o* N- A; i" H9 m# _8 c iinput mcasp_ahclkx,
! U1 m9 k8 U' k% D4 t) p' ]; _0 jinput mcasp_aclkx,) }" `' t6 t* `
input axr0,4 r5 p$ k/ J0 v' \& p7 K! g+ u7 }& K
* _# s& s, D/ ^ Xoutput mcasp_afsr,
1 ^1 ?& X+ j0 \7 n6 ~+ f" e3 x! E, @output mcasp_ahclkr,
3 |5 x& X9 M {output mcasp_aclkr,/ W B) c' m3 d8 D
output axr1,
4 g: R$ }9 _7 s3 U assign mcasp_afsr = mcasp_afsx;
# A. p. u) w8 Jassign mcasp_aclkr = mcasp_aclkx;5 u2 j: X% ]6 l9 g1 ^2 D0 r2 `
assign mcasp_ahclkr = mcasp_ahclkx;
/ _- A$ z4 }. q6 q# l7 Dassign axr1 = axr0; 3 X, R2 ~% e% B6 D5 Y3 Q1 c
6 Q& c, B" `) M2 ?( |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 O; u: g5 m, M* U$ X" rstatic void McASPI2SConfigure(void)0 n- L1 O! A8 U, W5 x$ H
{
, n5 M5 }/ A4 P( }- ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 Q$ o8 t- m$ \$ j) C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) V0 w0 I0 Q2 v& Z7 \$ N+ a- U# pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" z0 o. N( Q4 e! n1 x2 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ E' w( J6 q) s/ O2 e( l) wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) m/ a. b! ]* E+ |: ^% Y7 r# U, |MCASP_RX_MODE_DMA);# ^ j. s% D1 a/ A; W+ { @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, s: g5 O2 S, e. L# y6 _. wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- |/ O* L0 v8 ]# k" w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, m; O7 H- Y0 Z) j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 D4 v. @( h/ c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - j$ ^7 A3 V# U0 o, U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// {4 u$ {4 U0 i8 R& w, p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ B' U2 _+ K9 J* u7 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: _$ P8 n, i1 o8 F: RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: `) j+ w+ o6 c( Z3 j, v0x00, 0xFF); /* configure the clock for transmitter */6 a+ V. g5 I( E: [$ O: u) P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% V1 u8 g( k4 [6 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , k2 @8 [' D& v+ E7 F i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; j8 A* m$ {* G# A, |2 q$ G5 E: c, X0x00, 0xFF);+ ]& }3 a/ S7 ~3 K
$ M/ e. c2 N' \+ Q+ z) c
/* Enable synchronization of RX and TX sections */ 2 C2 }. k B u: ^ Q8 n# u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 L: ^! M$ l" Y2 J5 e2 x) z* h% V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) {) l. y5 L; D# M ?: oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' ]4 |' T( E# z
** Set the serializers, Currently only one serializer is set as
' W( A4 e$ R" R0 m- k7 V** transmitter and one serializer as receiver.
4 [2 i' \/ Y) x2 Z*/
_: x! b: P; s) H' [! J3 C* cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! U' n& w( F5 x2 \; cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' X/ o( e+ [$ A! A7 ?. G, \1 i
** Configure the McASP pins ! O0 y: i: Z8 [, k& |0 |! Y, c
** Input - Frame Sync, Clock and Serializer Rx
7 y( W7 T3 N1 J$ f9 s** Output - Serializer Tx is connected to the input of the codec % U) h' p* b) h/ e
*/+ F) V( Y- e2 @7 ?% B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ C/ x! m& Q- o S: C3 x& DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. r* w/ Q, a4 k7 O3 V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: M) u: F0 L$ ]+ S, P1 r( r
| MCASP_PIN_ACLKX" Q) i( A. \$ U
| MCASP_PIN_AHCLKX- S( p& T7 S$ Y3 D u$ w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 P7 F8 \$ M1 L% e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* k) I" F/ I: D4 Y/ M/ D| MCASP_TX_CLKFAIL
7 a* S0 a" S S: C" q7 }5 Y* A| MCASP_TX_SYNCERROR
( B; N4 A1 r% J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * F' O, y* d2 Q" O. B: V
| MCASP_RX_CLKFAIL
& Q9 j3 j9 d1 ? H) F+ R- P| MCASP_RX_SYNCERROR & j# V! U5 C& c u
| MCASP_RX_OVERRUN);
; G9 b* f- M, J: {3 f: |} static void I2SDataTxRxActivate(void), A3 s0 F6 v! ]7 U# }+ k6 O9 [; T2 V
{, D* o; t% O% V6 I ~
/* Start the clocks */
3 c ]! Z/ D% |# E3 `! tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 M2 ~- Z7 t1 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 D. s- U9 l0 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 {' X2 a6 } {$ yEDMA3_TRIG_MODE_EVENT);6 Y" L* C2 ?; k. O8 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , @1 U8 q0 j# Q, N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% B! L% ?$ s7 SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# l1 T6 Z# c$ c& u9 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ e" U, E; S/ U/ V5 T3 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( h; M% e1 u7 G w* v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 P- x l/ W7 u/ CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ `6 Q0 ?: y! d+ n} 9 q# B$ v5 b! X# l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
u* w( i% t6 }' K |