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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 D* g+ ~* j1 A9 q
input mcasp_ahclkx,1 w" s: z+ F9 ?& }$ Y% i! j* C" r
input mcasp_aclkx,
! d& A! I! [1 q N4 o$ winput axr0,
) z) l& Z. \0 L6 W, j* E8 \4 N& p$ y: p
8 N- J4 {& P( x' z4 W* ioutput mcasp_afsr,
/ N* {% o$ L7 @; _/ _output mcasp_ahclkr,
3 s8 d$ _" s! I; K6 j5 Boutput mcasp_aclkr,( G( E7 ^8 h) O- u
output axr1,
0 z/ V7 G4 x# A% a1 k assign mcasp_afsr = mcasp_afsx;
* Q1 L. \+ b0 o" _assign mcasp_aclkr = mcasp_aclkx;
+ Y8 N5 {6 I0 V0 eassign mcasp_ahclkr = mcasp_ahclkx;4 N; ?8 @4 `% x8 Y$ @
assign axr1 = axr0;
' N& {! C2 }1 N* K2 Q6 c: I, ~- R9 A; i' R* u' Q4 Z6 |) L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ Z" C+ q# o: h( D. d+ Ystatic void McASPI2SConfigure(void) C: c0 n7 t4 z
{7 b4 }$ n7 C) g7 Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 l2 X/ o; W L9 m0 I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" {+ }6 P' j) q( Y$ `1 G; @4 b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( Z# Y6 K( k n6 \5 `9 I4 A$ P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 \, {! p# i. K g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 y2 T7 X% Y6 `, n4 r# M! o
MCASP_RX_MODE_DMA);* H( b3 a+ w/ ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 g' N( G3 K# r$ b4 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 T3 X) U" L+ l+ g( B7 HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 U1 A$ c# R' C/ O2 D& MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) q; `8 p3 h2 P/ _ h7 L& j& ?# p) D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " Q! o# }9 X: i Y j" n, B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 p' {6 w, R; d. I" U7 PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 m5 Y0 B! ~, nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " B$ ~$ I7 H( _% U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 b% ^$ J7 e% Z. r& v* \$ U( U
0x00, 0xFF); /* configure the clock for transmitter */
( S* s. t8 _& [/ @) ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ u) {% k( c& K! B' M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( G$ r/ g" m+ Z# J, g! IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' Q% O/ j+ B# ?) P6 K
0x00, 0xFF);
" ]- @8 _: @9 c! t; F
' X' ?0 {% @& d# O" j; Z/* Enable synchronization of RX and TX sections */ : [: A8 r* R8 [+ B! s' {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; C# P9 |/ k: J/ zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( i( C- P! S# z: |* ~5 |- EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* _2 h: _. w1 S
** Set the serializers, Currently only one serializer is set as
) _9 E( I" n2 Z' A9 ~8 e/ z+ y( A** transmitter and one serializer as receiver.% `4 f( k8 S; U* j" k8 @0 m3 q
*/6 P: j( n- J$ J7 B/ G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
W8 P5 g. _8 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 Y+ z8 x# i0 ~* V: W
** Configure the McASP pins
0 v' Y% W1 a" h& I' S9 o2 v: z** Input - Frame Sync, Clock and Serializer Rx0 {( p/ ~$ ^4 w+ d- H+ a* _
** Output - Serializer Tx is connected to the input of the codec 0 i# g& e* q( C& M0 C' H5 ~9 K
*/, A* z' R3 k2 d# c- T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; y4 i" x+ W* V( ~6 r$ E' ]* D6 x f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 o; P) b) u5 Y! ?; w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX r4 p, V" }& c( y0 S: t. j g
| MCASP_PIN_ACLKX+ k+ D+ F- i4 C; L y' @
| MCASP_PIN_AHCLKX9 J0 S8 {+ V4 k, @: L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 f! t8 @" c! p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 M; C. v% N7 b) D/ n3 C5 a. y| MCASP_TX_CLKFAIL # H3 t+ R2 C& @ Y' D7 V
| MCASP_TX_SYNCERROR
- ]/ B8 y. g2 ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * W' q) v u; [' u
| MCASP_RX_CLKFAIL& p: e7 Q. H7 r3 o; X d' a- r% R: z
| MCASP_RX_SYNCERROR
3 l" U; b% R: h, [- t- T| MCASP_RX_OVERRUN);
0 ^4 p- Q9 e1 i} static void I2SDataTxRxActivate(void)
3 q& v9 c. k- r" Z% Q{
9 l A% X$ O0 A. {/* Start the clocks */0 ?, }. w8 j& U8 i) a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ b2 ]+ a+ Q& I& `2 Q9 ]( tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- ~+ j' c: u; D+ k6 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 B( o2 J: F" N& D. k6 MEDMA3_TRIG_MODE_EVENT);9 _/ f/ C# U H! Q% k! x$ U5 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' F v! _) G+ t& bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% m0 N; ~) o: x: [; A0 e c* k2 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! E" ~* z3 J+ N6 V' PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: N8 z5 @( R+ {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 o; I) B( R1 VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ a4 c8 V; S- Q5 _4 v6 [, e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' {2 V) c n0 w, b}
# h$ @* m& u [5 U( B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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