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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 D; a. z* f C7 ?- A1 ]" l+ h5 }
input mcasp_ahclkx,, f) L+ J$ x0 f. t. C
input mcasp_aclkx,
% {& P2 ]0 a3 H5 @ _( S6 ~ R9 ]input axr0,
& s+ \- U# X4 G) o( Q6 B8 J
2 G0 s. f, P( F+ x" b4 K" youtput mcasp_afsr,
: I( z2 @+ e7 Voutput mcasp_ahclkr,. V5 R& o) X2 M! e
output mcasp_aclkr,
) o' Y8 o0 w' q% {& Aoutput axr1,5 S" Y8 ~0 u$ p0 h% a
assign mcasp_afsr = mcasp_afsx;$ n0 {1 S: Y) [, {5 p
assign mcasp_aclkr = mcasp_aclkx;2 z/ b, s0 r' v; u- r
assign mcasp_ahclkr = mcasp_ahclkx;: s- e0 ^( j' v; m7 t" D. Y
assign axr1 = axr0; " K; K; Q6 A: I# |# ^
2 @: _; [# S+ I% W/ _" u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% r. v+ F8 U" z6 @static void McASPI2SConfigure(void) |! j7 {+ q) i& E. L, O A8 y, B
{
& P# v2 C/ k7 D& c7 SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) k. E+ ^4 k+ G/ z7 L1 f! m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* S$ ~1 d( c% c. k) Q! ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ `: F' G/ z$ N2 t! S3 W T$ B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 ?9 h- D9 z( Y7 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 d: w; T; W2 q" w2 \2 m5 q
MCASP_RX_MODE_DMA);
, l. G8 i$ q- k# E: W7 e! ^- iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
k$ y7 `5 \! {, s$ [' Z0 {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. m- i* ^* p: K' e' T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / e0 ~! P% b5 L, g0 `, H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( D0 \+ [, v5 Z8 RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 Q/ K( M. J, J ^9 SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 {( v/ a7 _% J' SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 P: {! |7 o- \5 H7 d& F7 j9 IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 J' E0 L; X3 _! }. L( s: hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* g; h* e( L- n, a$ `2 S0x00, 0xFF); /* configure the clock for transmitter */
# F/ @5 _. B I; p7 e3 OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. x3 L ^! S, @6 X$ k- HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , ~( \' L5 F+ j% `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ z, X" q% f" X% ?6 H4 \
0x00, 0xFF);4 Q; ]0 @8 s, B0 @! v; K: G
; f, B4 J) M9 w0 R, R
/* Enable synchronization of RX and TX sections */
9 ?: |: N m" g3 K* dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 }8 z6 z1 ]# C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 H/ `; X3 S% pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 U: Z; [- I$ G** Set the serializers, Currently only one serializer is set as3 s! o) d+ ?, z# e* {; ?
** transmitter and one serializer as receiver.
* C) ?+ q; g5 \; H( h: w9 N*/
9 k p, M* S$ h) BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 @5 F8 m3 D& E6 QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 O, @) t D& A** Configure the McASP pins
" \! [+ v3 c, V: g- @** Input - Frame Sync, Clock and Serializer Rx- W: y: L% C3 o& W3 q8 F* f
** Output - Serializer Tx is connected to the input of the codec - {1 S1 o Q; v% ^- Z
*/) s& Y; d$ t1 h5 f9 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# o$ f4 ?8 Y$ v( _' q4 OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. j; f) L9 `8 S/ OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 E: ?, _* [( Z1 j1 N* {0 e| MCASP_PIN_ACLKX
: s- @1 M; @3 k4 A| MCASP_PIN_AHCLKX1 D, S% H/ }: d' \! ?5 _8 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: H8 n6 Y1 E6 q3 G% O2 J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 j- B: R( b- E$ {6 H| MCASP_TX_CLKFAIL
1 `; s# L/ h% n1 J# ~| MCASP_TX_SYNCERROR
% s9 j& b5 j& S& k/ O# @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 e9 J) q: [" E9 F2 G5 S
| MCASP_RX_CLKFAIL( F! q' e' L+ D0 u
| MCASP_RX_SYNCERROR
9 G& |+ K6 ]9 G% O% i5 x| MCASP_RX_OVERRUN);8 j% u5 z4 @: r: B, m
} static void I2SDataTxRxActivate(void)
R" G# u, F9 H7 E% |& E, ~6 r{* k+ X8 N7 [! h6 {* ^& G
/* Start the clocks */5 [0 g( v: G! g. T. z! y$ S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 I# u3 n5 W6 e3 M! O% t; ]- i* i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 x7 Z1 M" f$ a4 a dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 t8 e9 A7 @+ N: @5 P1 v
EDMA3_TRIG_MODE_EVENT);& Q0 |; _) v6 ?+ D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( J" d* ~2 m8 g2 a) {7 a: T; u J8 V. MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ D7 K' N' ~* ` n K4 |$ YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# ~( K ]( o' T) @& G4 J$ NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% @( [ q# G! p- b4 |# Y& n6 @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
q) T6 c9 Y7 } r4 d& ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- {8 U$ `! d0 D: A" _9 c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 ]9 `8 A# q/ v3 \7 _3 C6 o/ O# R
}
. c# q T2 m) n1 x+ n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # I6 F' }' K" v& n
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