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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 V& B7 m& { x( g& K3 kinput mcasp_ahclkx,
( z% d" n1 e* Ginput mcasp_aclkx,
5 v; s8 T+ m" |5 I% A( y9 i' c! I8 Tinput axr0,9 G0 J$ u; _' W
: q" D0 ]$ J* {% ]
output mcasp_afsr,& i5 j; o+ @$ T1 O) E
output mcasp_ahclkr,
' b; x5 C3 L, `2 p* [8 Loutput mcasp_aclkr,* Q3 t, y' t! J* Y& C) r
output axr1,
# d- T N: \! k: l& F assign mcasp_afsr = mcasp_afsx;
% M" z/ L- [! `# A8 q3 P) R- passign mcasp_aclkr = mcasp_aclkx;( j1 [2 G) S2 f, o7 }/ Z( K
assign mcasp_ahclkr = mcasp_ahclkx;, i# n2 U9 F) q1 y6 ~. ~
assign axr1 = axr0; 7 d1 R0 b+ _5 Z3 |0 ^# x* X
0 s: Y( a$ }: B" T" D# C5 E! w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! u6 D- v' M3 f
static void McASPI2SConfigure(void), e" W6 [. L1 Y W+ S% w2 J
{# I) r7 V6 g/ }. y1 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- p9 x- |. s7 DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ G- q, g8 j" e& v( u( R8 Z3 r# CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 m% [% m/ s$ ~/ `5 w8 k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! w) Z) e! O, z& oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 r9 ?8 n% g8 Q+ H6 w0 F2 Q" K" JMCASP_RX_MODE_DMA);
+ d. ]! j/ V% ^+ lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' D- k& P( @( e3 }) d. I% P- DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) M. z) Z. \- z) u3 x6 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + |; {" w) Z5 n, ~2 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- o" m7 D8 |* A( e0 I, S( wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) b- j. k5 o8 }1 e! R Q7 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// m0 J0 j2 ]! _$ J5 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( [0 j9 H+ h+ _6 |0 c3 hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 ]: \0 Q c9 k" ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- C& P, F8 \# f" I, M4 g
0x00, 0xFF); /* configure the clock for transmitter */& X8 K' w- Q3 a7 Y) _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( Z6 L0 R- A' ^7 X! P. [; p4 v; BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. g! i u( Z4 w6 L5 zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" W& u: f4 a$ _6 X: z, q" ~0x00, 0xFF);
9 T, Y5 E; H% @7 _) B4 p3 a
1 K5 v0 [1 f7 _% O/* Enable synchronization of RX and TX sections */ ' Y+ H3 f$ }8 w( U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// E; n, ?' V5 j# ~% L# n) ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 f) K7 E: g. g( jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. P4 [/ y, e6 L* `$ C4 D( K# X9 n** Set the serializers, Currently only one serializer is set as
. g% g- A! F9 [1 f$ ?/ a** transmitter and one serializer as receiver.0 A( a# F! F- y( i1 Y
*/
( g" I% A" N) O# A. b9 U! k( oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! M, _! n# z1 s! N g+ G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; S6 r5 P h+ `& ^+ b# _0 T** Configure the McASP pins
. O# ]% h! x8 N/ ]** Input - Frame Sync, Clock and Serializer Rx
3 s+ P8 _& r5 Z( n p2 l** Output - Serializer Tx is connected to the input of the codec
+ ?" J9 }$ x0 T$ E. b5 D7 r*/
0 c0 m; ?9 _4 K* k8 z/ F, f6 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# ]' A. ^: N( L c7 o8 v! I! TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) I7 r( z5 k; D* Y' G% f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- b8 v W7 K- x p# @ D
| MCASP_PIN_ACLKX
+ i- r9 } m7 H$ q- L5 e/ d| MCASP_PIN_AHCLKX
5 Y, ~% a0 y# C3 E* ]- f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 X1 [# ?# P* ~. g7 m4 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ ~0 q' F' t- [7 {+ X2 G, J% w* r| MCASP_TX_CLKFAIL
& C, ^ R- m; m9 L1 ?$ t% U| MCASP_TX_SYNCERROR
. r2 k I7 S6 ?; l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ x: n1 y3 R' Q' E, V| MCASP_RX_CLKFAIL6 \# `" N" s0 ~6 k: v" \
| MCASP_RX_SYNCERROR
\! c' G, T# q x) W| MCASP_RX_OVERRUN);2 M! R1 t/ C- S, c( g
} static void I2SDataTxRxActivate(void)
6 ~" \9 t/ Y& p0 P{
% l8 o! A5 W! _7 u/* Start the clocks */
! m; X+ s' I* e2 S$ U BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 w+ W: F, E! {+ a+ kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 z# H- y5 T3 ~7 M' I S8 Z! c* LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; u$ E0 v, g3 i. L
EDMA3_TRIG_MODE_EVENT);7 h/ O9 [: ]8 H+ Y1 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " y! _" ~# i( r5 l( W9 l) C* Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 \/ t8 t7 L3 q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& X& \6 @ i7 t6 ]) w+ eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! V+ h$ B8 v, f/ w& _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' |! ]& o9 p; a' O* E, b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# z$ M O/ k4 \4 j% i, r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% {3 W, M, t* w) c( R} 1 M) k3 r& w7 a0 k& P- d. r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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