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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 l2 p; x; ]( Zinput mcasp_ahclkx,3 o5 ^! s) ?1 c, U* t
input mcasp_aclkx,
6 B0 b. X6 h; u) }input axr0,
) M4 Q* `" _; e- s- U) k
) F& c/ G8 E7 m7 doutput mcasp_afsr,# f! R; g' R0 y& f" G) S. P# ]
output mcasp_ahclkr,
6 H+ A7 T. O4 @$ Loutput mcasp_aclkr,
q/ m* s" l2 J7 L& a1 e0 loutput axr1,
9 e: L& s7 D& v: I& l/ I assign mcasp_afsr = mcasp_afsx;
, a0 D2 W- I; S3 tassign mcasp_aclkr = mcasp_aclkx;
) n6 v( b0 Q6 G4 y; k2 t- yassign mcasp_ahclkr = mcasp_ahclkx;
, N8 @! q) i7 C P2 Rassign axr1 = axr0;
3 n( w' }" t/ \: G) m
% G& I& \' R6 [3 Y! G# E7 G! u* S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ y& i* u& f; R+ D- |: O
static void McASPI2SConfigure(void)* k' o6 x# `$ ~# k0 f
{
# R: M6 Z8 Z7 _7 S8 _, ^: ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* D9 o( f. B# GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 c. t; @) N. ?, bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. Z* y( U8 d7 W6 U/ k/ p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 p% h4 `; a8 v9 h7 tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: h7 n2 T* a) U3 l! n, |2 JMCASP_RX_MODE_DMA);
" G& r+ l3 z5 `5 O! l6 A9 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; b8 K K+ p* ?' Q% SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 _: v% C* Z& v' j; j; C: MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! s6 X0 N! w7 P& |9 g& t s$ h; Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 T6 A; } K# a4 ~7 d7 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; M" D, n5 ?5 q4 @& r" oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 i6 m3 A; Q. P0 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 j7 |7 p Y7 M# }+ i6 N# q5 ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); J2 X+ z7 e' ^ O! y l' A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# F- P& P* O3 H5 G7 ~; g/ p0x00, 0xFF); /* configure the clock for transmitter */
. o( I6 G% {: z* y- ?0 f7 q5 i. G5 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 o' E* M* Q( @5 j$ U; f( l' i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* i) T2 |, X; O) \* q% u$ @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, `5 Y4 \: I0 G6 u2 j# z, N
0x00, 0xFF);
' ~6 j: v# R# S5 ? @- X! P5 o" I* l
/* Enable synchronization of RX and TX sections */ * X8 b7 P" F$ K: D9 j& m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; O% k# ` _( Q$ B9 \/ l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# F" I8 q! H5 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 g$ a$ s. D9 A0 u; ^+ o/ ]** Set the serializers, Currently only one serializer is set as, ]; a6 q) g: h( S5 C0 P
** transmitter and one serializer as receiver.
2 L& a0 K+ G6 q% {*/( J" y3 b( R" H0 g2 F4 q- {7 b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); n2 U' o4 o1 w6 v3 y5 |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 \/ B2 }. c7 [. D" d& E
** Configure the McASP pins + r% c7 ?! k% `* C% h: f
** Input - Frame Sync, Clock and Serializer Rx7 m2 g9 f5 n8 B; O# Z/ Z
** Output - Serializer Tx is connected to the input of the codec 3 d4 _% J5 I4 A8 C* x; ?
*/
9 i* F s4 [! d1 ^$ n1 ?! tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 m+ b+ m6 |9 i6 J1 L0 X3 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 n+ C u3 ?& t S: V8 K2 v' A: aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 a; W& ^" g: z| MCASP_PIN_ACLKX8 p4 v( v: e4 n
| MCASP_PIN_AHCLKX, W; z2 s6 ^8 P) F4 g3 c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% [: c$ U$ g$ G" UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- t, O& n9 d1 v3 J2 e| MCASP_TX_CLKFAIL
6 ~$ W$ B2 `* K. @! G| MCASP_TX_SYNCERROR, C u$ g3 I! ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + u7 F* j' l1 f$ Z& L
| MCASP_RX_CLKFAIL
3 ~, a- Y$ a2 Y4 p; r2 M; W| MCASP_RX_SYNCERROR , [: ]. O6 K' q
| MCASP_RX_OVERRUN);2 ?4 K( ~/ D& @3 |
} static void I2SDataTxRxActivate(void)
. ]6 T% o! o1 z# c{& B' k0 z" [! K- @! ?4 ~ B9 C
/* Start the clocks */
' j. `) G) `; D8 w" t" x0 K2 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 Y9 j. i+ ~5 I1 o% v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 C, U$ ^$ C# N7 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 j0 J& c* o- q* REDMA3_TRIG_MODE_EVENT);/ ~8 }' }2 q( V: z7 }5 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # f* {* b5 C: ~3 Z; |& m/ `7 |3 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# y2 M: z5 |5 o; s9 |' |9 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; n4 f, N8 u6 o3 b& Y4 h! d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, u* A2 u! _$ t# i" E1 [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! H- t2 N8 c; r2 b0 @4 ^' wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ I. f/ E8 p" m6 }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# K6 K/ V7 c/ @" _$ C& ~- \( j! q} 6 b" N. b) P( C8 X- L) o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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