|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 P% u4 P0 N& r3 o0 V+ Ginput mcasp_ahclkx,7 Q7 g! {; x4 f' k
input mcasp_aclkx,
& Y8 f, d! j0 m/ S& Q) t" ?input axr0,& z. O) t" U' c6 \! B+ @
" R2 c. x& d* b. P V4 U
output mcasp_afsr,
" y2 r0 T) s4 N% @ T% Q: L) soutput mcasp_ahclkr,
9 {3 j4 J$ A3 j1 W6 ?1 aoutput mcasp_aclkr,! A% W9 R" w3 W
output axr1,% w! j. X) @! b( |$ {9 p% g
assign mcasp_afsr = mcasp_afsx;
: O$ L' o1 z# `. M3 yassign mcasp_aclkr = mcasp_aclkx;
9 H2 n H% u9 e9 ]5 ?assign mcasp_ahclkr = mcasp_ahclkx;
8 k6 B9 A8 } Y% e2 eassign axr1 = axr0;
2 ?; H% f3 n2 I& t; x" A; x$ `
3 W; i$ i# e, N& G1 i. C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + Y8 S n- B0 {) g3 p
static void McASPI2SConfigure(void)
! b i6 j$ x# d: K{
/ I9 x+ W7 ~. i' `) }/ C& B) LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% t) h) y- K& F0 M$ ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 I( k1 c, G; P' V) }) x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* _ x3 t+ W' K8 B( m% S( q+ U6 {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- y6 [5 P) R+ g6 S* b" DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: [+ g8 i. I% C5 H1 cMCASP_RX_MODE_DMA);$ M% X0 p- r3 L+ g% T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& [3 e f% p% ^1 U9 kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ x5 |2 t* U2 m. v) _6 }- U( L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 C3 U, W, M- L" W- A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( `) Y( _& S' n% B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ m4 J) C% h) ]0 Z) i' eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 u; V4 o/ z: zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 G4 T8 l4 V1 C& z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# }% v& a+ w3 e& |* h) e% z: C. qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ Q5 t) b- h% R! V. D. n0x00, 0xFF); /* configure the clock for transmitter */- T# e2 t- n( h, D- R; p8 U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 S3 D9 P3 u2 w, M/ X1 H. b9 H. pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( `4 l! q' e5 e }% O: C( p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 ^" ^0 \# `% f; H2 Y; f0x00, 0xFF);( ~+ ], v, u& V3 x! o# K
$ ]5 L; C* O; |/* Enable synchronization of RX and TX sections */
8 W0 |( y9 @$ M, Y! }- ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: h0 Z* c: m9 \+ q$ D7 m+ |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 ?9 r7 F( r1 P) g: X% w4 `8 V4 X1 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) e$ r* d1 b. Z) b* ?
** Set the serializers, Currently only one serializer is set as
" ^' n4 v; ~+ W x9 X** transmitter and one serializer as receiver.
7 f2 R! R4 z. @# M( l, U*/
3 J3 r) J& F7 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ p u F. B) w8 ?/ i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 |) x$ x0 x' f** Configure the McASP pins
; F# y6 \. v) J$ J) F+ x9 P' m** Input - Frame Sync, Clock and Serializer Rx5 }! ?+ q, I3 T& k0 q4 C% f. V
** Output - Serializer Tx is connected to the input of the codec
3 a4 M4 Q3 q% r* k4 m*/
0 h: c8 e: \0 l3 V9 l7 U7 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! A3 W1 Y) o$ @) B) T% w/ l: S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" ~2 D7 Z. G2 H2 g) M; r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 Y: P! d: d$ m& G x6 Y6 M2 @
| MCASP_PIN_ACLKX" g+ z( y5 D% `! x
| MCASP_PIN_AHCLKX7 Q; X, j, G& I8 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 R( C: d j# Z$ u' N" J4 D! ?, \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
P: ?' R5 R4 g" l& t0 x3 O2 r| MCASP_TX_CLKFAIL
. e1 [0 A. N8 ?+ Q% L| MCASP_TX_SYNCERROR
' A! @# J2 |' G9 K1 q, g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 z$ u. c4 t1 r( z. u| MCASP_RX_CLKFAIL
0 `8 n" n+ T B5 m6 {| MCASP_RX_SYNCERROR $ t' b6 _) f1 y0 V
| MCASP_RX_OVERRUN);- Y- w6 W2 K D
} static void I2SDataTxRxActivate(void)* E3 _6 \' @ E: D
{
* e' a, y" _8 e+ C. ^8 K0 z% x/* Start the clocks */
* t: [2 r0 }+ b0 h$ L- p+ i {7 q) sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 r# M$ n, d4 K5 R2 q9 n8 z RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ S1 M# M% S4 g& I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 Q$ ]& H5 w9 g# ~
EDMA3_TRIG_MODE_EVENT);
, u& E) u$ F2 B3 {1 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) { D; v* l4 \! D; S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ w1 c7 R/ V! r4 _: f8 SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& I# [/ n7 p. g) o$ T8 D- {$ ~) I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ ^3 L5 M/ o) N, G- }8 ~/ {( S% G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" Y7 B1 b" p$ p7 q$ D* v/ ]/ `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. D/ r: g- X, v9 a0 C6 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- z) w6 `8 [2 l5 w; ~3 V, d) t
}
+ f; i4 N$ x: a! E+ p g+ Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 Y% z# S+ H, K0 P$ n- T$ h& h
|