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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 i! H0 ]7 U& z2 zinput mcasp_ahclkx,
3 R A8 _0 h7 S8 ]input mcasp_aclkx,
; f8 @$ ?7 h9 u* R/ _" Finput axr0,
: i8 {; Q# I& q8 ?0 z) y1 l& P
& }0 c8 M1 r. s. v7 J$ Goutput mcasp_afsr,
" C$ @$ i" M9 m- x' Z8 J) t- \5 O+ voutput mcasp_ahclkr,+ E, Q8 s" F% |9 d/ l1 R Y
output mcasp_aclkr,3 w+ y6 T; `. I; B+ c* W! P1 j
output axr1,
, Y4 e5 p8 k/ b {: J) T5 R4 g assign mcasp_afsr = mcasp_afsx;
5 V1 g6 W/ g4 kassign mcasp_aclkr = mcasp_aclkx;3 x) I( o0 b4 H
assign mcasp_ahclkr = mcasp_ahclkx;
4 c& g" m. H; H. a$ k, Zassign axr1 = axr0;
4 \) x% F: F' P2 ^) Z+ K6 C$ }; |) R! a3 \0 |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( }2 }$ d; I/ Q
static void McASPI2SConfigure(void). W4 ]) b; L% i! O. n1 S/ {
{
8 z9 H0 ]3 l" BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* Y/ D6 r* u& F1 s7 VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 @$ u) [8 y6 t* ?% O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: p, @2 Z5 Z. R/ d/ h7 U! Q" K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% ]/ N3 A8 `5 V3 y3 F8 o. ?" M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( W. S( ~6 v4 e/ A6 g _/ A* x# LMCASP_RX_MODE_DMA);2 \& ]) [! Y( D2 p8 K: L( Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ c$ P% j7 f @9 ] }9 U% hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ n. K% |, s3 w! B7 I% k0 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 e! E% D- o: L1 f" L" I' o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" h& `& a- I3 ?1 h: Q( f: zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : T2 {# D1 K' G8 D8 m- k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 a2 I0 x9 m$ j! T7 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( R) a' h! a. M3 w& H' YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : F/ J8 m" X& z/ z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! {3 V2 k$ l( \$ W# H* j
0x00, 0xFF); /* configure the clock for transmitter */! M" h, [ c, D9 Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% N0 S1 a' ]. z1 C( C- cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 l- }, m9 n% [& n) MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 C( a. j. K- _
0x00, 0xFF);$ h0 V) \' V- k+ T! q3 i+ C2 v
/ }; v5 |, k0 b* g7 {1 N9 H3 z2 D/* Enable synchronization of RX and TX sections */
9 |: ]0 d O, W1 \- }% u) @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' u6 O" M; F& A7 e( t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 \2 ?' z9 C6 t0 U7 v$ \# d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; P9 I# I8 H Q; o5 f
** Set the serializers, Currently only one serializer is set as8 l! Z# D4 S) U
** transmitter and one serializer as receiver.9 R, E/ G4 R( N% \5 F0 m
*/
1 w, u& ~2 n1 L- H( y6 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% N( R0 g' j) M0 |9 G" J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( n+ }9 ^! P! o# r** Configure the McASP pins - R: O' C [* k/ W- F1 e% ~$ K7 J% t
** Input - Frame Sync, Clock and Serializer Rx" z- c6 `; w3 E2 Q! A
** Output - Serializer Tx is connected to the input of the codec
& G% B4 W5 [# T) [2 }* U/ E*// K+ }, j1 L; o2 c1 O5 h4 F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 i( n( z% y7 \% T; p7 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& D$ m/ I: b, p- o+ o7 X6 ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ X6 [, E, K( J# ^5 p
| MCASP_PIN_ACLKX
. e2 N6 C5 i5 F3 C8 O, x0 n! s| MCASP_PIN_AHCLKX
/ m" D7 a( D2 |1 v9 Z0 C: M; T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" Y+ r0 e/ O& l1 Z6 O2 DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% g0 l R( D& }| MCASP_TX_CLKFAIL
1 K) [4 ]% G2 g| MCASP_TX_SYNCERROR- p; ~) g6 W( x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 s, Z: O# [- P+ R
| MCASP_RX_CLKFAIL' E( R& b9 b; G
| MCASP_RX_SYNCERROR
1 x1 P- F0 ~, _7 s/ M| MCASP_RX_OVERRUN);4 q$ h7 M$ b: ~! K7 I( J- [
} static void I2SDataTxRxActivate(void)% Z: u1 P( {# V L
{
: G M9 o7 P; j0 }+ n; @/* Start the clocks */
) z; d. W9 U( |, |" H6 g7 w/ ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 D" |/ g4 F/ `" Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# U8 G, N. [. X$ s5 K) ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, ~- D5 K/ b8 k& o6 mEDMA3_TRIG_MODE_EVENT);
/ u# i" c, q. |* a/ Q+ k$ y: M; uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " q& w; h3 }0 N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: N; |/ [! M0 ~ C" {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 A% O1 {4 W' L& x& B% J+ `) k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) N4 t6 s# p+ S; h6 j9 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 D2 ^/ l) c) L( o0 k! C, vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 E8 B) ]( U7 j e/ n% \& c6 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% D; k# c3 T' j9 B9 Q
} 4 o$ J: Y4 a @& L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( z% m: b0 c2 S h0 ^! _0 {+ b {
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