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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% f6 `" t0 q. H# }; n6 N2 b. linput mcasp_ahclkx,
/ I6 C, }+ e; e$ f3 F* z2 `5 ^input mcasp_aclkx,4 @3 O5 U% l1 \6 \8 [
input axr0,
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, B8 A; c4 y, woutput mcasp_afsr,
9 q% U% y6 a0 G0 D1 `output mcasp_ahclkr,
4 \- u6 \; Q" youtput mcasp_aclkr,
3 ^% C( t1 g4 p4 youtput axr1,
2 f1 |! k- ?: l5 B O9 l assign mcasp_afsr = mcasp_afsx;
+ _9 v8 z, P2 _; ~' k1 ~assign mcasp_aclkr = mcasp_aclkx;3 }$ W+ l' f8 u
assign mcasp_ahclkr = mcasp_ahclkx;
' V6 O4 z( g0 C1 o% Tassign axr1 = axr0;
/ G/ l9 @' h- x9 ]* D- U/ p" ~9 [/ {7 q) j& n# e* q/ c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& J7 Y# k: v* Tstatic void McASPI2SConfigure(void)
- l- f, O$ Y6 m+ m# Q: e, D{
6 Y3 c) f0 \4 C. |) O" F% I9 r& YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ Z: ]. k2 V7 _" P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ C; q( _5 j% g+ S' z6 Y9 J+ W( IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 Q' |/ {- i& x8 n0 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) ?: n4 W# `+ L, UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 b& M h6 i3 i* r& |+ g7 B& y( b0 L2 d
MCASP_RX_MODE_DMA);
# \, B: F5 a& u& d5 Q8 PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 H2 d& r6 Z% d9 N3 {$ C) [: KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 z* J# E+ t7 K3 \, @4 VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' _, b/ I4 D; z7 Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 u6 ^5 {6 k* \+ Q( A6 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 q, b2 E, p a: bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 q4 ^% |2 B7 X$ L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 N [8 i- J4 c2 t# [2 F2 x" u" m/ d' iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; M, p" U& r! ^4 X. UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# U# d% m' N5 k$ Q; @' z+ ]4 n
0x00, 0xFF); /* configure the clock for transmitter */
) |. l" ?9 E3 \9 J4 _ kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 U5 g I: a! x" Q' BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" H* T5 t* c8 F; j/ tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 e' q4 v4 N. q3 E8 u0 t! S2 p0x00, 0xFF);
7 K* S7 i& T3 M/ j3 r- S1 l, i: v5 c8 [3 ?
/* Enable synchronization of RX and TX sections */
8 e, n1 l7 ?. G. MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' z5 p( l- n; @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( V9 Q7 k# B& a: w+ v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' W* \& H, }) f/ r- n6 c
** Set the serializers, Currently only one serializer is set as
3 b" T* ]# t) Y- _4 v! I** transmitter and one serializer as receiver.6 K4 W: `7 M' w9 @1 \
*/! l2 p# c& v0 P) H( r1 n- y9 L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 o" i% Q7 [5 Q' Z8 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% V: v/ Y! K7 R# Q7 |: {# {
** Configure the McASP pins - A, r# d" O( o+ j
** Input - Frame Sync, Clock and Serializer Rx4 C. K# B) `( Y9 v! [( T1 \% y% q
** Output - Serializer Tx is connected to the input of the codec
) J% f* Q& s- u*/% F/ Z9 O: ]2 V+ ]+ }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ Z; [( G0 k0 |1 T6 E% B1 [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 h' u( o! k( ^3 b; a# B4 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! G: j* v" Z( J; Z" o; N+ |. Z| MCASP_PIN_ACLKX
j' T$ m4 @0 {0 G' h v: w" E# i| MCASP_PIN_AHCLKX. {( m) m Q* O* \* @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# \0 w1 p+ F O5 Y! v4 L: M; N1 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 O2 Q' a8 v! A$ G p; ?
| MCASP_TX_CLKFAIL
' u0 K( }* A9 {) s| MCASP_TX_SYNCERROR
5 C0 H% E9 q% P% W ^1 N. H! \$ l) y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- o2 \' O! Q( W! b* }/ l| MCASP_RX_CLKFAIL* `: |6 R2 A+ e0 C/ ~
| MCASP_RX_SYNCERROR
8 g# G; r) A8 m5 \2 q- z) M| MCASP_RX_OVERRUN);; H; v! U2 W! j- A; z1 i& w9 b$ }
} static void I2SDataTxRxActivate(void)) Q5 E+ Y) I X6 {$ {1 a0 ]
{
1 X8 x; e+ G2 p9 E8 M( }5 ~. ~/* Start the clocks */
" l1 r) a `' k) fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* o3 [" ]7 }) _0 m o0 VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
_7 Z. a/ [8 \# V/ J6 e8 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& G0 w' A9 \8 n" V
EDMA3_TRIG_MODE_EVENT);9 _# x& I& y/ w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( `7 j, m8 Z1 w8 l; I4 S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ `4 F' K8 P0 r, x: Y8 ~+ a1 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 q8 P( v7 E8 n% c/ G, gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. Y1 T$ v# K$ h. Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 _ w7 O% W7 R+ @% `) e, D7 nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 ?2 [- C) `( @/ gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; _- n; i g6 I/ p4 D
}
b* w; L o M1 \ [# k/ V. Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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