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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 i' O; w, t' m& L. L- {- S
input mcasp_ahclkx,
. o% }4 E( b. G7 c: `input mcasp_aclkx,
' F% Z' N5 g7 o: }' e9 o1 `input axr0,: @) e0 `' e5 C5 s
/ j( \! L; Q& t1 Q" C ^/ G+ `
output mcasp_afsr,
. H6 c7 A6 W5 Y" houtput mcasp_ahclkr,
) Y5 N8 y q. h0 F- v/ Goutput mcasp_aclkr,1 @; Z/ M, O% q* v2 E1 x
output axr1,
& I5 K1 p, g2 x: Y( K4 x9 {- _ assign mcasp_afsr = mcasp_afsx;
! `: ?/ M! G* ^0 E dassign mcasp_aclkr = mcasp_aclkx;2 Q5 g4 F. \; Y- x) d$ y
assign mcasp_ahclkr = mcasp_ahclkx;
. m# w: w ]1 R. A8 a6 z* aassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 @4 w% V3 f( Q3 d: u8 p
static void McASPI2SConfigure(void)
4 l6 z U& f! i{
% P2 [# E9 K) p6 M3 }" z* gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' K+ j! d! G' ~3 [" B' F7 w/ wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 [0 y/ Q% {2 x$ S3 B! M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. R/ W6 b$ X2 R% [. o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ a3 Y: S+ U3 z6 i+ mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* b0 p7 i9 V' G7 EMCASP_RX_MODE_DMA); |. k0 r. r( ?8 v6 e8 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ M* U" D; G+ M) }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( F g+ t; h5 T: Q% F# M2 c( ~% DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # ~0 g% L2 h8 n" Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" S* l7 _0 w1 f8 j& S0 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* c+ @, j/ x6 l" [. }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ a7 c. I. ?: A1 B5 L" `$ }+ l- p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 O$ m9 Y, a' T/ V. B2 YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' E4 _3 c8 \6 Q* z! v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! z4 E. l2 z; f9 [( g8 F
0x00, 0xFF); /* configure the clock for transmitter */
9 s O( E$ }& E0 ~2 f0 _# tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" b9 p s2 z) A* V2 k; L* ?, q% ~4 }# u2 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - ^$ P, J3 z7 V1 b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ E# w; T# I% o3 }3 r! ?0x00, 0xFF);
+ s; ?9 C9 x5 g! y
" Y3 F5 P4 a" p* f/* Enable synchronization of RX and TX sections */
+ z3 f; S: w' D+ I8 N& fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- J1 E! B0 P% u$ K2 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( q7 a' Z- Q3 I/ i3 e! j' Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- R% }" D9 `& s, K! D0 q** Set the serializers, Currently only one serializer is set as
2 m9 h9 Q9 I& L' T** transmitter and one serializer as receiver.
( ^. L1 s/ }$ U# c, ]& P*/0 `! ?. ~$ K6 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ ]9 ? o) L7 s2 N! TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( Y* i3 q# J2 w** Configure the McASP pins
% |' z3 \' ^6 l/ I* \$ A9 |+ r** Input - Frame Sync, Clock and Serializer Rx& e# O' i8 |/ {4 B3 ?
** Output - Serializer Tx is connected to the input of the codec ; ~1 |; h- |8 D- A: s2 t1 ?/ F
*/$ W7 v* q9 d, Q/ T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; }, V( E: ~) X' v& r. p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ U. [4 r5 o) l0 n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. x [/ I- M5 P: n, R3 A. t" B
| MCASP_PIN_ACLKX
- ^/ A$ j# F5 c" @% b4 T2 A, R" m6 L| MCASP_PIN_AHCLKX% ?1 s; f- {5 I: h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 Q. A, b2 h0 {1 S+ L4 x" j$ X1 p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 Q" o4 q% k. H/ o5 b7 e- C| MCASP_TX_CLKFAIL . X# S' H+ K( z- o0 P/ T2 n
| MCASP_TX_SYNCERROR
' I7 r! M5 B# z9 A! m( P' w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) c2 ?! m2 y; h+ }& s
| MCASP_RX_CLKFAIL& g' `/ Q9 v y2 c6 C
| MCASP_RX_SYNCERROR 1 k/ |# x+ {1 d0 b/ S
| MCASP_RX_OVERRUN);
& v) a8 a! K0 [4 ~/ @4 M9 e- k7 Q# U) W} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
, B, z# o/ Q; E' B6 T0 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 ^8 ?/ G" q$ f$ W8 @, H' S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 e% H( ?# d& C0 ~1 H0 |% a# U; uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. K6 e+ F# s7 j6 ?% c- X6 _, c
EDMA3_TRIG_MODE_EVENT);( Z" \8 k7 |- v/ H' Q$ q) K1 X- W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , A% R( t) s9 w% t) v# `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; a+ \9 {8 y7 l1 |& CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
p. q' j: C/ v4 G6 t/ Z- ]4 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 z3 a7 r; r5 B- P) b! r! V$ P# uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 M A3 m9 q' YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( }+ n$ s$ ]- v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) v- i5 Y9 E( g' F* n V3 F
}
' D4 q0 g9 i( \ `' G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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