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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& B3 Y3 a$ |8 d G/ O
input mcasp_ahclkx,2 v) W7 h: {; Q0 O8 V' I3 H
input mcasp_aclkx,5 Z B( y9 z% |0 m" M/ s
input axr0,0 A! `* b6 N9 f0 i4 L( a
# O0 Y/ |8 n/ ?7 u4 ^output mcasp_afsr,6 a5 H8 y3 u" l: I
output mcasp_ahclkr,
6 v4 R- D3 D% Y+ i9 M9 boutput mcasp_aclkr,9 x" J4 q8 Q, h, M" K
output axr1,
4 M+ q" Z. [3 M( V4 F# L' ` assign mcasp_afsr = mcasp_afsx;
7 r" ]+ }' @/ Passign mcasp_aclkr = mcasp_aclkx;
2 _9 C9 k$ |7 U @assign mcasp_ahclkr = mcasp_ahclkx;/ n0 a, o+ n) ]8 ~0 B0 _; {. N
assign axr1 = axr0; ( N- J* j" x" r
, x2 k3 q5 s/ Y/ M/ S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: k4 J' F6 p1 Z3 `* Q* d% hstatic void McASPI2SConfigure(void)
( o, L* ~* I, @{- E: T, ]6 p, s' ]6 b3 J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. G$ k/ G8 v* \6 M% f# y/ ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 C5 [' j& y) L+ E, ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ n$ E& e7 c' M" WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, i6 l: i+ K6 G! r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# [/ ~6 a, ]8 p1 j( @+ F6 W) J6 T
MCASP_RX_MODE_DMA);& u5 m8 h5 r9 B5 V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 g. S% C. D$ N: y/ `6 d# x5 |* X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) x) Z3 L- b( \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 c7 p, k$ N' W5 X) p) U {& {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 P8 k. W2 i% Q3 DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% S( M& k/ T( C- T- x z& G! uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, N6 \, v& G6 Y% B, Z$ oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 j" ~' d. e% ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- y& b2 A9 q4 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: s/ p7 N% Y1 H
0x00, 0xFF); /* configure the clock for transmitter */
; p0 O# z( D8 q) S& @* _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# a0 i o; o: j" GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. y- ~3 W& Y# d' Z$ _! gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* v: N6 i& h0 [- @
0x00, 0xFF);3 y" X' Y% K0 ^+ ~' A
4 L% Q" c; ], z
/* Enable synchronization of RX and TX sections */ ( G+ l! H& f6 Z/ @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ J1 \) c% n8 [$ B" yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% n' e1 l& f S% ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) g% T/ f0 ?. p7 ^0 \; A
** Set the serializers, Currently only one serializer is set as. ]. P* @. E- O8 Q
** transmitter and one serializer as receiver.
* k0 v4 f& Q1 g- O5 @*/1 E. N5 R$ h* \ `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 E6 V/ w' J& Q: ^8 T, _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) N' _+ Z& N. e7 U
** Configure the McASP pins
) V- N# ?7 d/ k" F+ L- g+ a** Input - Frame Sync, Clock and Serializer Rx5 M: r- B# |. ~; [3 H1 w( v
** Output - Serializer Tx is connected to the input of the codec
1 ]8 v4 C8 B* h*/' Q% O- ]/ R6 v( [4 c# g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' @. ]0 `& i% L! V. L9 W) oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 }! R3 z1 Y4 B: M+ o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( Y$ M; A2 }6 P' q% ]7 d| MCASP_PIN_ACLKX
# t/ N6 }, ?8 I2 J9 j3 ]7 A| MCASP_PIN_AHCLKX
+ ~" y2 f, M) O7 a; D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 `" o1 m+ ]3 h+ z. t* O% Z& U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! U0 G4 K# p% Z) h. U# y
| MCASP_TX_CLKFAIL
1 [1 d/ S0 j* @4 U| MCASP_TX_SYNCERROR
p8 ~6 A, p/ O2 j f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ W; v G0 f G9 M, o& R% `| MCASP_RX_CLKFAIL
+ a! x1 ]! _7 R5 T/ O% @) P| MCASP_RX_SYNCERROR
& S+ d" |4 i, |1 z1 `| MCASP_RX_OVERRUN);6 Q" W6 t# z. K+ Q6 F- n7 O
} static void I2SDataTxRxActivate(void)
X+ F7 q" v) x9 {7 ~{
: ]2 W5 N% P: h$ t8 c/* Start the clocks */
( P: J2 ?; f/ |$ I8 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* t8 V+ B2 W0 Q3 \! n" c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; ?' j. N6 g5 t% o- I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ ~4 \3 @# H# O
EDMA3_TRIG_MODE_EVENT);0 j$ Y( f, ^) @) e, H' [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 F( X7 n5 i/ Z! w3 \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( c" J) V5 o5 j5 t. o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. P9 d" b" j/ t+ _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! i0 d) E3 W/ h/ J: Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: y' Z8 m8 `1 s# P! e: O& D$ A* c, K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' L1 @ @7 q% |+ u2 Q6 pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ k5 [2 Y/ c; j; j
}
. w6 E4 T) n% {! r" @( Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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