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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 ~ L) i, V1 h) \input mcasp_ahclkx,
& `- U' m8 U/ Z6 C8 i4 v% |# kinput mcasp_aclkx,3 V: g8 z8 n9 @9 D+ q) p& J
input axr0,# _( P7 h! K( Q2 D& T: _' }
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output mcasp_afsr,: W6 |, B1 e4 H0 M( u8 j- z
output mcasp_ahclkr,
) d' z2 ?1 b0 q7 foutput mcasp_aclkr,
2 G6 N6 ^# Q j# [+ `output axr1,' e# U8 J; L* a
assign mcasp_afsr = mcasp_afsx;
9 r# r- L+ E. C3 A/ Rassign mcasp_aclkr = mcasp_aclkx;
2 p$ s7 o! b$ @assign mcasp_ahclkr = mcasp_ahclkx;
, G- ?4 |+ \9 }assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 L; d; ^& S6 }% R8 q; J9 t, I
static void McASPI2SConfigure(void)
9 B# F6 P6 ~; D& Y) }) T3 E5 t# y. A{0 b) L0 |5 }1 }( T# y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. f4 R' Q; ]5 i' x4 V [3 d& J: a6 oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ U' g' j/ R' a7 ?' x7 A7 A" kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ i* z/ [- u4 V1 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: R! B: {' ~9 I5 MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% E; E9 p' ~1 G! e3 u9 [MCASP_RX_MODE_DMA);7 ]/ [0 k- k6 ~- `$ u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 C3 H# K$ w) x- f* ^/ OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 L% _( k" k- ]; m `' q0 u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 G! d! J/ I/ [. G, _# b: m' YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 b3 s) v( R: Q. } J/ V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" z: H, q3 r* Q; Q# q% g( J. I- a7 C! aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 P; f. m0 ?+ P" D X- RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 H& c2 _" g' G- J3 O* z' X) M9 a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ O5 Y' [# O+ G9 i4 kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: A( j5 v, _% s6 M1 ^) V& [
0x00, 0xFF); /* configure the clock for transmitter */8 s9 o; }5 E# `- S' u) r" W- |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% y% P# B' Q% G B5 J/ ~& y( sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . ^7 y7 X, Q! ^( \) w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
E& r- o; d. \0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ " y- j6 K: q' p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, ?4 Z6 i1 |; o4 K$ @- |/ j& S' c/ XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 w7 n) ]* R' K. _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ x: C, u' n+ B* ?( S
** Set the serializers, Currently only one serializer is set as9 k, x9 C" g' M2 r
** transmitter and one serializer as receiver.
" x: E8 C) P) L, i*/ c" A& j* S$ X% s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, y- h( }8 f4 o$ B" N% AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! `+ G3 ^' Y& t% D; N** Configure the McASP pins
6 R; G& ]4 K) p" K** Input - Frame Sync, Clock and Serializer Rx
- Z+ S, {0 B: N: ^** Output - Serializer Tx is connected to the input of the codec Q9 A4 u: V4 t
*/
5 x- j! F; q, h1 J. rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); Q6 y h4 Z" u; b( `1 J. a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' ~* i6 Y( g9 m( c6 U1 U$ f/ W) i& p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 C2 |: g2 E, m7 x$ l! f, \) e h
| MCASP_PIN_ACLKX5 ^% ]) E: n' ]
| MCASP_PIN_AHCLKX6 h5 _/ F" b8 M4 b( ~$ g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 J- R, C) [/ U7 i5 F0 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ {, x0 H! Q3 j| MCASP_TX_CLKFAIL 3 N2 o# W) l/ Y$ s7 @ _1 I+ ?
| MCASP_TX_SYNCERROR
% n8 e3 q; O5 w/ n! c, G$ g/ I6 G+ P9 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - Y8 b( s k" v
| MCASP_RX_CLKFAIL: k! h4 Z1 J3 s) H; q, U5 u' m6 v1 j8 l
| MCASP_RX_SYNCERROR & F( C' }' }! ?3 C7 l8 U# C+ V
| MCASP_RX_OVERRUN);
! h% ?3 I' `; L6 m: a} static void I2SDataTxRxActivate(void)
, S. `) @ j. F0 f/ p/ t{
3 }3 W6 Z: U! r. g4 G8 C/* Start the clocks */
6 d- }$ y1 z0 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. @' l) g W4 F. @: b3 LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, m1 S! G3 J$ `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: F1 s0 W$ J6 S" J0 W
EDMA3_TRIG_MODE_EVENT);! K$ ?8 l+ T( D2 [, G5 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' H* Y9 Q2 L" {2 e" }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- M5 g) B f3 R. i' n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 \/ k% a6 o7 }- X! d& X* wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 u# e% D4 N0 U# Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 O$ r; w! e, _" l$ S, k0 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 q0 ]2 @+ n! ]4 l1 {, bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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5 K f [3 |) g, ]% d8 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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