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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
Q' L l0 E4 ]" J& t6 Ginput mcasp_ahclkx,7 J3 O6 {7 B2 Z
input mcasp_aclkx,. |, V6 n& a5 @$ [( ~- Y, I
input axr0,
/ I$ l4 x( z! {" A3 Z: d" n* [' ]" ?0 t2 x/ k9 d
output mcasp_afsr,
) U% u" {9 }! S, M) s woutput mcasp_ahclkr,
* ]2 {3 R, a# \/ p1 l% aoutput mcasp_aclkr,
+ u% u' U9 M! _- N2 Z8 B, l) koutput axr1,4 S0 {9 B$ z$ D5 G4 u/ U8 i$ y
assign mcasp_afsr = mcasp_afsx;7 c' x9 X* {6 `) M1 t4 t; |
assign mcasp_aclkr = mcasp_aclkx;! L/ }8 H/ H' Z) B; F5 V
assign mcasp_ahclkr = mcasp_ahclkx;+ J. D& f& p1 F. V9 g2 G
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 e* ?: g# V9 K: ^9 N7 X; wstatic void McASPI2SConfigure(void)
1 N* i2 i; O9 S8 A{3 G0 X" o; T" U: m0 ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ Y" n8 ?3 H" _) BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 |' o+ m7 ]2 R/ `$ d) r3 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, H4 @ t7 ? C, }; \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; z$ y( K! R! J8 w9 }% jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 r; W' o% ?8 U/ L
MCASP_RX_MODE_DMA);0 r) z$ G; \& S) v( P; H0 x6 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; h& E5 {$ H, O' q! I% LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. F1 \' x+ C5 b6 w$ J. NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& j K. n4 K) r) d8 x2 f0 iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 d1 u8 F7 [0 W8 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; X; h% L" X: z' PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( O q/ [/ C8 L8 [ `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& o% k1 W. _. m6 X/ d: fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 l. ^" l( q5 O" CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," g0 P& X0 x3 H% p m2 @! e" @
0x00, 0xFF); /* configure the clock for transmitter */
' o0 k3 o! K$ j9 i8 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" s: V8 t' y- C# K& w7 r& V FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) B' N' c+ G1 f q- h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 R2 Q" D& ]" [8 u- A( [, Z
0x00, 0xFF);8 z# ^) m( F, U
. Q4 k8 G0 Y" r6 l* y/* Enable synchronization of RX and TX sections */
6 X+ p7 B$ ]) Q) G% yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( H6 Z# u! C' }2 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: p+ @+ E& u* k3 s* k$ AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# i1 b3 ?/ d* P& \3 ^
** Set the serializers, Currently only one serializer is set as
; g0 w; s+ f' e6 q: j** transmitter and one serializer as receiver.$ }# L$ T) i M& y: ~
*/
) ^/ G6 S4 ^- |2 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ u8 U* o/ f, Y! a2 b% U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 a: h1 t8 `" @6 \- N7 F+ m** Configure the McASP pins - N% _+ ]/ Q' X- L X, r
** Input - Frame Sync, Clock and Serializer Rx
( E5 E& t9 [! Z" Z- F5 p** Output - Serializer Tx is connected to the input of the codec
2 {+ ]5 G0 j+ k*/5 Q) ]. R# K- l" d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" K7 s" f' v9 |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ O; R. ^% T+ H" r) N- UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, z. I1 Y( k, u( M9 Q; f6 H
| MCASP_PIN_ACLKX
( v8 a- Y# ~9 C5 l% a( G( l| MCASP_PIN_AHCLKX, D/ w6 Y1 N- L m+ E! F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, o! W! s) O/ b- E( a) D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 M3 C: ^& k% k" C* m& l7 ~
| MCASP_TX_CLKFAIL 0 T! e) t; X7 C) y6 m `
| MCASP_TX_SYNCERROR
- A* |, G1 {& W' V" x" j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ C1 T+ `1 d! m
| MCASP_RX_CLKFAIL
' h" i: [4 T: ~# f8 K" X0 w# b5 P& K| MCASP_RX_SYNCERROR
6 ? I% Y' z/ c% P; _; g| MCASP_RX_OVERRUN);" @# g$ [9 G& c$ E% v
} static void I2SDataTxRxActivate(void)
. `2 N9 J9 k+ |2 @{- B9 f$ k" Y6 ~" x( W) }7 B
/* Start the clocks */5 F1 Y9 Y9 @0 ]( F, O1 @8 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& G1 t$ t9 n* f% ^4 @4 qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' I6 \) i# a' ^7 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 b0 z: t9 Z2 N5 ]& Y1 }/ u
EDMA3_TRIG_MODE_EVENT);
& ]4 J" ? j4 L" Z, REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 H( h9 d8 Y3 x, P5 m* y" qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; G( W& G L( q! S$ o# }& F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 L2 q, J( b+ w; Q P+ y) WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) t# V" I5 D: f6 V# T8 iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 B; {& s6 o2 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% b. K4 q1 [. u! Y. y% S' A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ Y {4 P: A" L y/ ^}
0 h- X. H% v: p1 X. Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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