MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
5 b/ K' _$ w& T' ninput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

output mcasp_afsr,
' q7 P( B6 ~5 C: n0 Zoutput mcasp_ahclkr,
6 f/ J' r+ b3 Y: ~6 O# `4 s! N& S% Houtput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
2 V. C. v" z0 [6 a) U4 dassign mcasp_aclkr = mcasp_aclkx;
5 P! b. w0 t$ ~6 y; a  }assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

' b. |5 d6 D" W

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

; f+ s3 E7 ^1 G

static void McASPI2SConfigure(void)
{
: S3 C5 P/ |8 B& l7 CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ F. u7 n3 L, W* P; `: i" y3 d  t) gMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
5 z! L: c8 G( f4 I* [! VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
! l( R2 b# e4 ?  jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 I2 i# E# J7 x+ b# A6 WMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* N2 o$ C- k" W0 A+ TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
5 I8 j+ A! b7 O+ V# tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ w% X  Y8 `. s& ]+ _" H' wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
6 c2 @9 u) f7 O
/* Enable synchronization of RX and TX sections */
6 r4 K% T% J" aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 l8 ]" j9 R$ K, e7 e6 B4 t5 S# BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
+ j' _0 Q% A0 u* r** transmitter and one serializer as receiver.
! A) Z& T# S/ d; i! J* F9 _*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
3 J" ~9 F- M9 l; G9 n3 w; j; ^0 t** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
2 I4 A/ D4 }8 c* b. X*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ h' l, G7 Y& VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 y, d% Z6 B4 Z1 m& q5 m9 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 z- H6 t8 w( U. ?| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
# F2 h3 u, m1 b) \1 _| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
, w# }2 p) l4 ^/ F! M; \; q| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
1 c7 w! k$ m/ t2 [3 U: A% a7 Z. Q{
/* Start the clocks */
! }; P- h: D0 ^5 G& Q0 w( {# dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: B. o' s0 f8 B8 O% xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# D: S" ~' g4 g% I5 qEDMA3_TRIG_MODE_EVENT);
5 P+ V; b* _2 a) jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
  i0 l+ {  Z/ eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
8 W8 o) J: w1 z' [' Q  H- RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
( c  h  y' X( k- p- D" Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
; H+ D  U) C4 ]% s; iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& I2 y) t: T" k7 ~5 w" G}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.