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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) Q& s+ k8 z0 \5 \6 F
input mcasp_ahclkx,
; a T4 B8 b" |7 n C1 e; F" rinput mcasp_aclkx,
- q9 V. i V( G/ B- ^& [3 Hinput axr0,7 X8 T# j5 l0 x
/ z( u, u( {( u M" R
output mcasp_afsr,& j) h) e5 W# R& v2 }/ m
output mcasp_ahclkr,2 P# r3 w: ^- t: w9 C; g+ n
output mcasp_aclkr,6 W! e) N8 `3 N, _! B8 |8 B. N: t n/ P
output axr1,
1 V2 Y8 I& }% O! V6 Y assign mcasp_afsr = mcasp_afsx;
F, t. x. I4 @* L" B+ Gassign mcasp_aclkr = mcasp_aclkx;
, s( }( V' Q; B' X, }( ~& c; sassign mcasp_ahclkr = mcasp_ahclkx;! |6 n. [* O3 x/ h1 G$ z
assign axr1 = axr0;
' m8 b$ W- s4 i3 m9 O
# t; X. [) J" P x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ q# p8 e$ p7 F7 ~static void McASPI2SConfigure(void)
+ ^; z, @0 R3 h; @; m( O( R{
4 y6 j$ p! b- O2 V. r# x DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 _1 L+ ?- f* L1 U2 {/ xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! z/ N/ N' O( s% D* yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# S9 C o$ u; @" S! z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; f, j7 ]6 u. M" ]0 Q% D8 n& [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# }& G" e4 g! W- C/ L- `MCASP_RX_MODE_DMA);
& g U- ], L `1 H+ @3 G: tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ }9 O8 t& {: s* ]. ?7 Q( T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: ]6 d/ q2 w) Z# U7 b( e) Y1 s8 g. ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 ~+ ?# B8 ]9 \* K+ B' XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% N" X4 i7 D! _! {; Q& h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 I6 p7 o% d( @0 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; s) I5 W+ \7 w( p5 J TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 z/ z3 V1 V3 v4 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . u. p! }' ]% A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ Y6 V ?/ L7 p& i. e; b/ |+ P0x00, 0xFF); /* configure the clock for transmitter */$ D5 D# R4 [/ M: E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 R2 Q8 v1 y, C* R& |# b1 @6 z5 sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * G. K9 Y h; h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& ]; c0 D$ J7 W3 \$ ^' N1 J9 o, P, t5 E0x00, 0xFF);! I% O5 Z# p3 ^5 {7 r: _: J9 m
. f. u' z$ _9 b" _% z" S/* Enable synchronization of RX and TX sections */ ' S; E2 q% g4 Q6 q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) l$ W0 R# U3 e- Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) \0 @8 p5 I- ^5 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; M9 U6 f4 l( p0 Z
** Set the serializers, Currently only one serializer is set as0 ~2 O$ |! Z% F& g
** transmitter and one serializer as receiver.5 E0 @: s7 `4 o. c( x" W% I9 I
*/' w* x4 U; \; N0 v% R0 A$ T2 q' Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 d* i' I' D- Z7 }: {& d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) ^; T* @! B: O2 k" x3 ?** Configure the McASP pins
- [1 M) R8 Z, ^+ y, K3 r% [** Input - Frame Sync, Clock and Serializer Rx
\8 e+ y9 i: l1 y** Output - Serializer Tx is connected to the input of the codec
; }+ m# V' A1 g* J+ A4 T*/
+ I3 l8 s, Y- X. {/ DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% K+ ?. l* D! T+ m( Z8 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ s, @: ?+ I) f5 S; n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 z' L5 C }& [| MCASP_PIN_ACLKX
: l0 M1 O$ W+ u6 `| MCASP_PIN_AHCLKX
; j+ U: a/ V: w4 y' s( v; w% E2 e x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 e" P# K) v1 f$ E5 {# D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% m2 c, J Z }9 T| MCASP_TX_CLKFAIL
: z6 d9 E" |+ M2 ~5 O- S| MCASP_TX_SYNCERROR
* d% q H& l- E" U% n3 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 a- O- H: Y+ J0 p3 n' l. [/ e
| MCASP_RX_CLKFAIL5 b5 X R: d3 b L3 q
| MCASP_RX_SYNCERROR 6 t3 f9 O9 w/ A% N" W0 x% q7 g
| MCASP_RX_OVERRUN);/ n. l, T/ H4 M% e) U
} static void I2SDataTxRxActivate(void)" q. n+ U$ v( o6 j3 g+ q
{& i; Y$ |0 N" ] W' ~* Q- V$ s
/* Start the clocks */: x. U! b$ n, p; [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- i1 s( Q5 h$ x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* ~9 K+ c- |% C( |( v3 l% J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" `2 I; r! N% L' J# q5 y% s/ y9 [EDMA3_TRIG_MODE_EVENT);1 |! f2 h* F$ C7 x9 E8 _+ o7 h' Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . l: ^ q" L( j+ ~$ l, C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 | I1 o6 j+ a# ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, F4 [9 G; P- z% L+ ^/ ~, d. h4 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ z# p! u7 b) `( wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 R$ x( c& D& b( S) g$ cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ w4 O5 P/ b% S9 d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 i A/ d+ a& P8 K
}
. F. Q4 T1 q* W7 q. n5 ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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