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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 D: z3 o' c; ^9 b" }
input mcasp_ahclkx,
& O. o* I& R$ B% l" Sinput mcasp_aclkx,0 |3 Z4 S6 ], I# T1 S
input axr0,
! K5 y" O) j, J" i8 v" {( Y/ R& r/ l
output mcasp_afsr,
" Y% Q( _/ d b1 u+ T/ @1 S" e0 Boutput mcasp_ahclkr," U, i2 m! r$ z- y: [/ P
output mcasp_aclkr,
" r6 L0 a; v2 Goutput axr1,4 u) z, `$ M! E; V
assign mcasp_afsr = mcasp_afsx;' L: m# U- u& ^4 D
assign mcasp_aclkr = mcasp_aclkx;
4 V4 F9 t6 n) }8 M2 F5 s- L# r1 @$ O lassign mcasp_ahclkr = mcasp_ahclkx;
) `7 }( t! H- S) d* Bassign axr1 = axr0;
; s6 z! @& w ]8 \2 ]) c0 z6 b3 G$ c/ d( L" e4 P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . H& J- }; D) a+ ~/ a$ y# Q8 N* H
static void McASPI2SConfigure(void)
8 A j8 [0 n' k1 p2 ~ x1 Y5 i{1 b5 O* B9 n9 h; U0 m* c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 @- w% M5 a, F- h- g' O8 j& D( eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 {7 S$ Q& b2 N5 ?! {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; I; p$ J, d |) C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% ] Q: |% L8 u) x3 |. uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' {1 [: y& V; j- B
MCASP_RX_MODE_DMA);- V7 [! @6 N0 O# f& M) C( q, W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 Y; \/ V9 I! W% y" D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) p6 ^, ~% e9 s) L2 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 u. \4 Q$ L# l! @/ Y/ ]8 q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) j" L2 w) ]# R. uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; |' k t2 o& S- n' r; I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 E0 k8 P/ T7 k) _; ], t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% K" e6 P% m6 v6 A$ q. DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ l2 V: ~3 v; o' b/ e2 o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- F5 k6 X; R2 O1 q& o0 [0 W
0x00, 0xFF); /* configure the clock for transmitter */- z+ L+ H- u* {- H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 f+ h0 k+ C. x K' A- |% f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / S) m, {* S8 I/ q$ J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- {0 V: Q& _. N$ d% M* _( }7 F
0x00, 0xFF);/ z k: B% J! B, l1 p! B
8 `; \+ o5 V' f7 A& }
/* Enable synchronization of RX and TX sections */
% J9 V+ m0 k9 }; a: y% uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 V- y) t8 `, B) h( `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ ^% S% F" ^7 ^# h: k" ~/ A6 A1 KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. Q, u* B8 t" W4 M
** Set the serializers, Currently only one serializer is set as
$ _% R0 E" O1 R# m** transmitter and one serializer as receiver.7 ?! t/ p. p# L2 _2 W8 E* _" v
*/
0 i" l8 y8 K* s2 D1 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" L1 N1 o) X4 x m% H. h9 xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' t2 ~2 ]/ t3 q) i% e
** Configure the McASP pins
6 U+ z2 {0 [0 G" e0 Q4 I** Input - Frame Sync, Clock and Serializer Rx
! ^) b2 D) A+ i+ V3 C** Output - Serializer Tx is connected to the input of the codec : z. ~, w0 t( @) C. ?8 _
*/7 Y2 ]4 D/ A) N& s& Z7 z3 Y5 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 F% V, V# n& S: ~0 H3 m# x, @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ S# ]' @) p6 T' F% aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' h: j4 s+ Q: t1 v% |$ O3 j% F
| MCASP_PIN_ACLKX0 |/ @" `. Q2 N: U3 z8 K) ^2 X9 I
| MCASP_PIN_AHCLKX* K+ n: C6 h% x0 e) S$ u: F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" F) `/ z; n k0 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # A2 M9 |/ H$ _
| MCASP_TX_CLKFAIL ; ` x! G5 R; R$ R# o3 c
| MCASP_TX_SYNCERROR, m" \7 Z. e4 X0 E+ s q8 p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. |" u5 A2 e# n. g* L; d& `| MCASP_RX_CLKFAIL
, S: B: y% \2 z7 z$ J8 U8 m| MCASP_RX_SYNCERROR
\! J9 w' r- ?4 B| MCASP_RX_OVERRUN);1 j7 E; V" Y$ ]: _) m) J3 z d
} static void I2SDataTxRxActivate(void)
0 g2 _( u! W# D: ]$ \7 G{% g0 j c# o# M) i, X! E6 P
/* Start the clocks */
, Y' e$ W4 h0 E" F/ A% A$ w8 }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# I8 v$ V* Y. P2 i MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 p! H0 e$ v5 b/ S* ]2 G. B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 l# P% _2 |" c6 B% g" ~( BEDMA3_TRIG_MODE_EVENT);
7 p- D& z+ V1 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( J2 l3 y4 J1 c! x" u Z2 M$ SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- m# o7 J Y6 Y- S' }7 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' @9 x) U/ w- Y) Q: d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- m x) q# D& e/ K* [1 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& ]! d0 _0 q$ J4 Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 B. x# l* M7 HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. {. \* w" Y! G0 @& Y# \" t}
9 k6 y# ]! E6 F* o+ ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . I- u/ o' s- W; y) L
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