|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 Q7 j, O# @/ ?, [% Z+ R$ {/ x
input mcasp_ahclkx,& w2 C E3 C+ x& i7 K
input mcasp_aclkx,
7 C" K* _* C$ h0 F$ d1 Y( Iinput axr0,
5 I1 f+ X3 a2 s+ Y: V- m; N s4 K0 L! f& J, |+ D
output mcasp_afsr,- w+ z7 D6 {7 D1 O7 o
output mcasp_ahclkr,0 b: A, X7 g' g1 N. t8 B% ]
output mcasp_aclkr,, Q- z! R+ D0 y3 w- e
output axr1,
( D* ?( f; Z u' v5 `8 C assign mcasp_afsr = mcasp_afsx;
' {: b0 v% R' O6 Zassign mcasp_aclkr = mcasp_aclkx;9 L+ f/ `% R& I% k" d3 w
assign mcasp_ahclkr = mcasp_ahclkx;
6 w8 h2 }. j; hassign axr1 = axr0; ; s6 i) y' X+ K+ ?; u' @- z7 M, K
" m5 ]. _# u, ]; N/ s4 S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ f8 G0 |, {% u1 @# V- pstatic void McASPI2SConfigure(void)0 W0 D0 p1 [ Q9 A5 z( W( V
{0 n- l2 {! Q" y5 J7 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' y* P$ h4 ?2 c9 c ~+ gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! S G: _* x T) }/ qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: j D7 Q [. F) {6 \, ]. e8 F5 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: q* r0 X) a% d3 I8 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ?8 t: t# Y8 u2 w% [
MCASP_RX_MODE_DMA);2 d, W; B! Z. {2 K) U! m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 \6 A# E+ `$ [: ~7 W3 g3 ^: \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 n8 G& J0 Z# L0 JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( A, Q4 A1 k8 b, e! x. L5 ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
P- c! \' p, A& NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 T N/ w ]+ |8 q+ @. k. s% Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 X4 s9 R# m; \- l8 M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ j+ G- e$ \" A" mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 B7 n ?3 T2 x, w) g9 X/ ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 N3 d' `# a5 g, k) N% D. x6 D8 V# W0x00, 0xFF); /* configure the clock for transmitter */
) u) \, h i: ]- l5 _. HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 G' |: g& U) V. R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( V4 x7 x6 v* [, C0 n- d. DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 Y9 e8 v* ~+ D8 d, K6 U
0x00, 0xFF);
5 A1 r4 a+ a: @
( G) X' ~7 [7 N7 M+ H& F/ ~/* Enable synchronization of RX and TX sections */ 3 [( y9 M0 y$ v2 D m$ R: L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 g: L' f d3 e/ e- n' `' n* j! {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 g+ C7 ]" S6 w+ kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 [# m( \+ a/ f' _( ^2 {1 {6 V7 V% ?** Set the serializers, Currently only one serializer is set as* s4 c- I- R) j- ~- Q& D$ A$ H8 n
** transmitter and one serializer as receiver.$ t' x; b0 _$ h
*/
$ t( K. J8 g* J- Q4 g5 g) A5 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 x( i+ _$ ?5 [1 G j; l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( P2 D' s, L1 l) y
** Configure the McASP pins
" g& d9 g, @! Z% n/ m. [% Z& j** Input - Frame Sync, Clock and Serializer Rx
3 G% r4 x: K& o M: q% z** Output - Serializer Tx is connected to the input of the codec ' Z: J! p7 z5 G" R+ I3 G
*/- t& c' I; H1 S' [; {) H* @3 F5 `* r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
n o [) A' R. R% d) uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# |& |* @+ j( U0 x1 `) t9 I: j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! m* G2 N# b) }. c9 K
| MCASP_PIN_ACLKX
, V: W3 O6 \( |9 h8 i| MCASP_PIN_AHCLKX! O- V/ D9 Y! p' U, o: [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" C. |7 X7 ~, |! I0 m, L: z* j4 g/ S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % }' @' A, L6 _2 ~
| MCASP_TX_CLKFAIL
3 m- Y# p5 b7 p* r0 i| MCASP_TX_SYNCERROR& r) K5 s" t9 C4 E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 j) B% p6 E: W% F
| MCASP_RX_CLKFAIL
M8 Z0 s% K- ^2 } @7 }4 U| MCASP_RX_SYNCERROR $ d/ z8 L: ^0 {7 x
| MCASP_RX_OVERRUN);( h9 \6 L4 L: j
} static void I2SDataTxRxActivate(void)
. m2 F; N. X ]{
6 M* e4 K) x/ W' I/* Start the clocks */
; R1 S2 J7 ?+ y3 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" d) S, @4 `: j6 R7 C K* y3 q0 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 P! J+ t9 Q$ M! h1 s% L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 B, N3 n/ B5 G" q! F! c+ B6 iEDMA3_TRIG_MODE_EVENT);$ R6 k# M5 z/ m$ `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ^$ o( [8 _0 K2 {: h5 ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, [' }1 Q8 {0 e& LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ \: u: W% _& s" w. T& A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 x5 |3 }! C$ j1 g! t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 q. k! r2 x) u% T, z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& @/ K- Q2 p1 n: v' X# ?' i }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 Q7 n4 ]6 G6 w$ e}
. M. L" g% f8 E( Q' Q- V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 J; S: v/ j, w/ K |