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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; j: h0 T0 {$ s$ D2 f! N
input mcasp_ahclkx,
- V) p9 |0 H E) b. Linput mcasp_aclkx,5 B8 y* t" n9 P [* W f
input axr0,. F, V* q* O4 a+ A* _# D8 y) A
3 B/ k2 ?0 Z9 s9 u9 `! poutput mcasp_afsr,; w; C: l! E3 O2 {/ n8 O
output mcasp_ahclkr,( I2 k( E) S4 n5 j( H! y
output mcasp_aclkr,
$ R" D# b& c' o; Noutput axr1,
' O4 y1 m6 ~0 d: T& } assign mcasp_afsr = mcasp_afsx;
# f4 \" k$ t0 l1 k, {0 j! [" sassign mcasp_aclkr = mcasp_aclkx;- v9 J/ M' n3 h
assign mcasp_ahclkr = mcasp_ahclkx;
! m" [0 C9 E+ u2 G% [5 Wassign axr1 = axr0; $ X! x9 f- e3 Q/ y' D6 H P
- j2 G y& U. O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & D* A1 O* N i; U" v
static void McASPI2SConfigure(void)
8 U9 P \7 y8 ]4 H! s/ l4 @* E9 `{
5 o! P2 r* Y6 C B' BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( r: J% M7 g ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ v0 R% w8 h5 E7 \5 C; x9 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 }6 K0 q/ A3 A, ~' G# i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# ~+ X# r r1 r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
B* ]% Y/ m, L R, DMCASP_RX_MODE_DMA);* ?" r/ v; O& e4 n( B; G2 u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 U. }' K# S0 F' [; S. FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 ^9 t1 z5 D2 s$ o1 i! @" B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : K) M0 v' ^- U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- J5 C5 L, @7 \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & H% p8 S' w( Y' x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 F6 K- l/ H1 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- C$ _& `+ Q' B9 j$ R5 h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* e* T9 E7 T4 J" A8 |* b: EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 x, K, C% `" Y0x00, 0xFF); /* configure the clock for transmitter */) S/ ]" a' k6 I/ Y5 Q1 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* D3 q) A( }! e3 N. @3 |% \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 C6 c; B9 _ R. \9 s( |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& x) v! k+ U1 z; p) q/ Q0x00, 0xFF);9 w* U h8 g# |2 b& s
8 X8 D+ c' l: `* \/* Enable synchronization of RX and TX sections */
" G8 y( I& I$ n- L$ P( ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: m( D' R9 W/ M7 [: C: ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* N) s& Q5 K6 ~6 A- C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% R; e2 ]' v3 ^8 h/ {** Set the serializers, Currently only one serializer is set as
) x, R$ G2 y: _, f' ]** transmitter and one serializer as receiver.: o r1 H0 ~* r: y
*/( I i. _# p5 H( t8 Z/ d% s! y3 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ z( L t1 k& m; K! s6 ?4 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& L( n9 I2 v: s, x7 B4 _7 C" [
** Configure the McASP pins 4 G: b; S( E5 z8 F
** Input - Frame Sync, Clock and Serializer Rx+ S$ T7 R$ Y b" v2 y2 F: V
** Output - Serializer Tx is connected to the input of the codec
9 k( X* ^& s8 p+ ` c5 {" w*/
' a1 y) V0 f- WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ O. t" a! T- e6 X# K, y% a$ ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& f& N, s0 Q2 C: J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( j3 V5 M2 G! D" Y
| MCASP_PIN_ACLKX
) s; T# ?2 M3 p' |* _8 ]/ W| MCASP_PIN_AHCLKX
& C4 P R5 ^: y/ E; S$ x( G5 || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 c, u! l& f/ KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! _! v- `7 c+ m& w6 ^4 \! A
| MCASP_TX_CLKFAIL
& J: o: ^7 |) N& t* [' H| MCASP_TX_SYNCERROR
1 M1 O7 Z2 T' L V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . |( m8 k, {8 U _
| MCASP_RX_CLKFAIL
$ g4 f+ Y' ]/ b3 h) ?+ Q2 u& S| MCASP_RX_SYNCERROR 9 Y `1 \+ R; d4 q- q& f5 n
| MCASP_RX_OVERRUN);& r/ p# T4 d7 d0 a3 ]
} static void I2SDataTxRxActivate(void)# y% B5 a) {; [! K5 D1 [9 N! _2 i
{
7 T% q8 R+ Y4 ~; _) z/* Start the clocks */0 l! U8 T/ V6 M8 b# E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ j( u' x& ^& Z5 \8 Y$ G+ O3 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ e6 u! m8 I3 s! qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," w; b3 ] j: ?& \5 `( T
EDMA3_TRIG_MODE_EVENT);; [8 I$ o" V. {' q: i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* W+ V7 E1 h) F5 |! TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 X; V& n7 {) z } r% R8 |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 F" A$ p( e" n. t4 H( [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; M5 X7 M/ c# r6 h+ r# m8 T" O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, @) B9 ]+ L. F+ U o' A0 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( m& a% ]2 y& n3 a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% R* H9 b3 J8 p7 {6 i}
9 b% E% p v- v# J" ~9 \7 r) d" ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* M ?" g, }0 |/ Y- F+ |' @9 [ |