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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ E- O2 u' i* H6 A$ S* v: ]) F* @input mcasp_ahclkx,8 Y, j* ~0 j" |- n& ^0 o' ~# e) x
input mcasp_aclkx,
1 v$ t3 u+ z2 A! ?9 b+ _input axr0,3 y6 \0 |+ {6 b) w
5 G: l# T/ B$ O9 ?5 r& t2 X* N6 y
output mcasp_afsr,
; e# o% E* A9 Y3 u' H% |) boutput mcasp_ahclkr,2 U2 K; V( l" j. h' L( h. Y& {4 ^. o
output mcasp_aclkr,1 s2 e- c- F1 ~5 |0 P1 y0 h
output axr1,
" \, O1 V( P3 U# \6 J assign mcasp_afsr = mcasp_afsx;7 `: U F" X% ~: J0 s8 |
assign mcasp_aclkr = mcasp_aclkx;
* E8 N. J: N1 X" B- f. p- xassign mcasp_ahclkr = mcasp_ahclkx;
9 {) y* f4 v: V2 I, B( Aassign axr1 = axr0;
q! x- H2 D4 l/ w
. v$ S3 ~* f; O4 F' p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* t% |4 C+ i" }$ ^4 q) ostatic void McASPI2SConfigure(void)
) `' K6 W" Z- S( N4 ]{% {, u; _: @$ A4 k' E) m4 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 g" Y7 H3 P! }6 S+ B' W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, G( m0 V/ d7 ?; a! k/ R4 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# G7 ^- R0 W; n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* P& h* W3 X e1 ~4 L- ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& T, w" }) q; \" {MCASP_RX_MODE_DMA);% _- {2 h7 e! |+ H; f0 I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! J6 g0 Z, I8 Q7 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 v2 i: O4 |7 O' G$ V( s+ ?: Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" X e/ J: ^; k5 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 r$ W# C8 o9 d; |5 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ o4 A9 r2 ]( ?! N9 k. D$ q, @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% F3 ]+ F: e3 k& \& j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 H5 [( |8 R* `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 J# [9 w ]; w+ u/ I! X; UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# I8 ], v- i+ |% ^
0x00, 0xFF); /* configure the clock for transmitter */
- K7 k9 V- s% t: A, N# c" r* wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! t' D1 a: @! m; y, X5 U* qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 z' F. N' W( V2 M9 Q9 _' IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, Q; u) l1 F# j, ]% n% d0x00, 0xFF);
' b8 F! X+ Q6 \" w5 m7 F
8 f" }. |9 ?! p/* Enable synchronization of RX and TX sections */
% ?0 @, l$ E' c4 _ O+ Z# \8 A8 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: ~ A2 l$ s& V: N$ N! H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ s5 ]! }$ I' `. j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! d5 l/ G' N: ]( B5 F** Set the serializers, Currently only one serializer is set as d D7 M2 X' E6 }" T
** transmitter and one serializer as receiver.
' G& b& A, j, ~9 s$ Q+ F*/
# @+ a L( `' y! Z) k ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 m$ K. K. D% {) Q4 \! @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 ?- }7 j) G R2 ~- ]: {7 W# }* I
** Configure the McASP pins 8 m$ l$ d* ~' e4 g$ u! D+ S9 I
** Input - Frame Sync, Clock and Serializer Rx
$ x) |0 q9 g; _** Output - Serializer Tx is connected to the input of the codec $ w0 q7 W$ t1 r$ g. n' i/ ^% U+ F
*/
6 t0 K' I3 ?4 i( }) S9 g, _1 kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ a( _ ~# v( y( BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ X- [) k. _( E8 A; J) }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 e- C' }+ C" u| MCASP_PIN_ACLKX
u9 s+ J2 R2 o) x" k. M| MCASP_PIN_AHCLKX3 j# R" X! h' U* F' i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 c6 Z: F6 O" Z* f# ~. [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- d, H" z7 @3 M- a+ d/ X4 w| MCASP_TX_CLKFAIL ( G* t1 @8 p J& p8 b0 B+ G" Z1 r
| MCASP_TX_SYNCERROR1 u* e* E; g L8 N- P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- K# z5 x% w: e$ l| MCASP_RX_CLKFAIL; n$ a* o) z e2 H5 }& Z
| MCASP_RX_SYNCERROR
$ f( G2 \- B& z9 ?| MCASP_RX_OVERRUN);: Z# r& N" a% O: Z; l+ f+ _
} static void I2SDataTxRxActivate(void)
, m7 n# W, @1 M- Q# f* y$ y# |* _{1 g8 d5 Q, ?* n" N8 `: u
/* Start the clocks */+ E' W+ J$ p) |* h( q% j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) V, V" F+ J, s9 z- IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( N1 h8 g; t0 ^/ w7 r% ~% m7 {! D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, x8 m- t, O4 q+ ]" N
EDMA3_TRIG_MODE_EVENT);
9 \" z [5 W" j3 u6 O- f; P0 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! l3 q* O1 p1 [+ Z- V4 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( b" R2 h; W( e dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ U& i% ?0 d) nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! W7 a* T3 d0 o. M \9 v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
]$ z" ~# m* R4 FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% d% b9 ?1 S$ V M1 O: p$ G/ d/ x' s9 ]9 TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ Y5 s; q" q' p1 S7 Y' n6 h5 p}
3 `* c& T' B0 u% }: a) D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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