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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: q! Z0 F' q1 z6 ]! r. y5 y: Pinput mcasp_ahclkx,
- s5 ]" ^& V4 o. v t4 iinput mcasp_aclkx," l" @, f% `% I/ y+ h( T
input axr0," E& p+ t& q# n$ O' [$ x
1 T3 x3 A* |: loutput mcasp_afsr,
\1 ^) r' P. Koutput mcasp_ahclkr,% Z! |/ {1 W7 T( A, i: }" N) h
output mcasp_aclkr,# |( b3 u. j1 o* Y3 j8 I
output axr1,/ _. I1 P" }- R
assign mcasp_afsr = mcasp_afsx;. K: P( _% D7 m% L$ a F H
assign mcasp_aclkr = mcasp_aclkx;
9 G/ z0 }. x. Q1 p6 V. [+ h/ Oassign mcasp_ahclkr = mcasp_ahclkx;
! ]& ]% ]8 B% u+ @* l; O+ bassign axr1 = axr0; 3 Y( L% D5 h9 x7 S
) D) u! u/ o9 x0 L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 Y2 M- _: b, N( d/ S5 Pstatic void McASPI2SConfigure(void)
, _. a2 S$ q9 t9 S, h2 B. u+ u" X{+ ?1 U" Q3 B6 v: c5 i9 `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 k$ {$ Y9 k% I$ ^/ D' sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 H: } ^' X; E& J5 j2 |8 G. Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ v8 \0 }3 K7 G# N7 K: w8 h+ R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 u, J4 K" {' t% {+ GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 J& {! Z! h$ ], \( l5 dMCASP_RX_MODE_DMA);, x9 g* x, ?$ l% [" Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* Q& e# ?6 k6 o3 }' U1 mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 t5 ]! |$ [' y1 T$ M: D/ _/ X" J! j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 _/ N& t1 B- S, AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- p* Q; u4 `, BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 U* i. d: k% A h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 F, [ P7 O$ y% C& J% x8 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; ?8 \/ F+ O' f) H- V1 m" a c( q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + a) N8 o$ W3 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 t6 t- h. K7 {0x00, 0xFF); /* configure the clock for transmitter */+ ]7 W% A( ~5 s; @2 A- X' I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' w0 ~1 }% `+ G6 dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 Q0 ~2 Z9 G) I# X. b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 R3 X4 `. i/ v6 c, z% m- i" D0x00, 0xFF);
% {) S7 x' {+ a3 V# p
- b' \, B; p6 K7 [/* Enable synchronization of RX and TX sections */
1 L6 T# @* t6 a; B& l- ?2 c# ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; D* K0 i c0 w' n3 n: e) qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 M5 b! w# ^ L. r+ d$ y% y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- P! A2 k' ~' n. p7 e
** Set the serializers, Currently only one serializer is set as
9 l; {$ B; y4 m** transmitter and one serializer as receiver.5 v4 S1 l/ O* b% m9 o( D+ y( E
*/
' f7 j) I0 G( @' ]( X- r6 XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 u( O- Q4 b+ y7 J% _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* i3 B. i1 K8 o T X3 l }) q% [
** Configure the McASP pins
# |# T& B' n0 b2 C- V o** Input - Frame Sync, Clock and Serializer Rx
) o# a7 [% [( i7 g4 E** Output - Serializer Tx is connected to the input of the codec : W, I+ x f" A0 Q5 R4 c1 a" s U
*/# |3 ^: R) f! U, r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 ^1 @4 L) E7 O4 z) AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# ^. i: k a! |2 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 a9 k$ ]0 ]4 L* u. o8 v0 g8 B; R
| MCASP_PIN_ACLKX
5 `& b+ z: \! X8 K& f% `4 z. A- G p| MCASP_PIN_AHCLKX% W' d! [# e7 s7 Y1 t" t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& t8 `( y( J) dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & B* H2 |! b/ r4 Q3 o
| MCASP_TX_CLKFAIL
' N; a; i8 R, \6 Z% @* n| MCASP_TX_SYNCERROR
/ V8 ~% M& _2 n, L. J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ s b7 I0 _8 I| MCASP_RX_CLKFAIL$ ^0 ?* `0 j1 S/ T: t! m
| MCASP_RX_SYNCERROR ( E+ X. `" g X2 Y5 z# g
| MCASP_RX_OVERRUN);
. ~7 @# Y R; W# F} static void I2SDataTxRxActivate(void)# T) e1 x; b9 [; j1 B" d
{
2 B. ~0 a3 R) o4 W! k( ^3 T% p/* Start the clocks *// k" k4 z* ~* c+ p. A' y2 ?/ M4 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) l- C3 y5 L0 O- P$ W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 a1 F) ]* E/ ~' u0 a7 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; K d( m3 E! E4 pEDMA3_TRIG_MODE_EVENT);
0 L7 |3 H* T, a% l& Y/ J( ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - K: L% c: a# o5 i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 }' J& b: U7 Y% _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( y) w1 ]6 q! n u" M- q# V- vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* a' a t+ v, m/ B/ ~, c8 [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" T( c& R7 l2 |6 E! z1 l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ f T/ j5 F& R7 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* x Q/ T! b- Y5 ~
} ( T6 Y" C# I+ y0 P! g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 d& k# z; z0 ]
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