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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 @- ?. J3 F2 s/ ~$ \8 x4 ~input mcasp_ahclkx,# B9 T2 R" N7 r1 ?# [: Q
input mcasp_aclkx,2 ]3 h8 b* w4 ] i4 D
input axr0,
9 d. g4 W6 @: r& F. y- u/ _7 z( P. H7 ~, t" T2 D
output mcasp_afsr,- S' r' _/ ?0 l' S* t- g, `8 h
output mcasp_ahclkr,
$ H% ]' {/ i2 m0 houtput mcasp_aclkr,
9 o. R9 q% s8 p- g) houtput axr1,* o5 ^' Z: |5 Z5 D
assign mcasp_afsr = mcasp_afsx; V4 e* k5 o0 V6 ^+ i
assign mcasp_aclkr = mcasp_aclkx;' L9 j( b0 z% B8 ^7 J4 j" O( C
assign mcasp_ahclkr = mcasp_ahclkx;# H& }* i8 q3 y6 w$ ]4 X" s
assign axr1 = axr0; 9 U0 i- W8 |! o2 q3 t
0 R9 A$ G8 ^% u+ m/ f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 c7 N1 g: I6 c1 V6 P. t4 |1 R+ {
static void McASPI2SConfigure(void)* b' M" k3 J6 y3 @- U
{$ y( \) E% e. ^- @0 W2 J0 o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: F& P& i. v( e( W+ ~4 a& {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 u L6 C7 N" B5 R$ a- GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) Y# `4 e9 k9 F) P4 H8 nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 o8 _( {8 p( k' r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, f5 n+ D C0 w% ^MCASP_RX_MODE_DMA);; J4 Z2 i8 `9 x* ]5 c3 M7 d1 ~* F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ z" s8 ^; t# m2 S3 X& v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: ^. E" f2 ^7 _( [- {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 \6 @" L9 X- \2 v- b- ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; u6 x0 h% V. w- F' a FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 Q3 w# ?9 `, M$ p6 \ kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 F2 U! |4 y7 G4 B& kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 M4 Z$ ~7 U, xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 @5 S) U: k: B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 ?6 @: D3 V/ x
0x00, 0xFF); /* configure the clock for transmitter */. Q( k q+ c$ O9 n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ }) N/ C# |; W' S- v' |" jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # v! u% V. W) m& J! O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, l& H ~& {5 r3 U# e. K, A; B b% g
0x00, 0xFF);
9 z. h; b. |' m4 O* |1 j* t- A( i( ~ r; R+ G0 b) T
/* Enable synchronization of RX and TX sections */
: T1 J1 {& [: z4 l" W5 x7 D# aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" N _; v! |6 w6 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% B4 O" ^( p* z, S; n% h& JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ ~, Y6 |5 H3 @) Y' P% j# T) i
** Set the serializers, Currently only one serializer is set as
9 c/ u- v2 w+ o: z% ~" }, L0 F** transmitter and one serializer as receiver.1 J. B) u$ x7 `" J B2 x
*/
$ f) k3 [1 W/ M4 HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* j. G: G- a, |, F$ y SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 S' Q, |; I" D** Configure the McASP pins
% ~, m0 _+ ^; h$ b** Input - Frame Sync, Clock and Serializer Rx6 r3 v* G2 ?4 T9 D/ R* ]; z4 @
** Output - Serializer Tx is connected to the input of the codec
1 y+ v0 ~: k; M7 K*/) E( c" a9 S" g' f/ S6 F8 G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); C' ] P2 ?% _, h8 Z Y( G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; o4 y, @$ n: `# b3 p2 }; v9 a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; `% l/ |2 g1 c- F% k; T' Q| MCASP_PIN_ACLKX+ a1 t' d' ~$ C% j+ C) c" a
| MCASP_PIN_AHCLKX3 n! ~& p. K# ?% U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 Z) J$ x- [7 @$ Q7 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: ~) j5 ], Y" k4 ?9 m4 K| MCASP_TX_CLKFAIL
: j' ?+ |3 z8 O( G2 z3 S3 c| MCASP_TX_SYNCERROR
& x' ?* }/ {1 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 t8 k3 G$ a5 N. b3 K8 i5 e8 \
| MCASP_RX_CLKFAIL
% \4 s& r# C4 F! @| MCASP_RX_SYNCERROR
: q- @, D% T3 D| MCASP_RX_OVERRUN);0 q1 t |! t: Y3 F% j% |6 s
} static void I2SDataTxRxActivate(void)6 p7 P3 d) g1 B
{
# H) K/ E" ~ m- ^! Y( p5 U. q/* Start the clocks */% K% [3 E U m8 K+ t+ V! [. t: d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' ?1 S3 @/ w' L) R7 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( t, j% e/ k& ?3 B* H. u I( yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 N1 ]' y {/ j- w0 p# a; NEDMA3_TRIG_MODE_EVENT);: L( I: x0 f$ s2 r( \* P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 m9 B4 r4 Z4 ?8 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 q: s7 {- Q) FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 K2 {) _9 \: w [/ g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% @3 |7 x+ r% \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. h% w9 D+ ^6 l- M2 ]- V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" _, {. e5 E3 [$ P& o9 K$ D% V! }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" H: q' z8 ^; ~ f- ~. k4 z4 C# K* F: G} 5 T5 \" \7 `: x9 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 ?) A, V( M( u9 q8 @- y9 X ^& W
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