|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 c) T$ E/ t# s/ g% _2 `8 D6 Uinput mcasp_ahclkx,4 W) B$ z) g V' d3 Z" `
input mcasp_aclkx,
0 j8 p6 k- z/ `# S; zinput axr0,+ U2 J t/ Z9 O" ]
9 f9 a, M, o6 Joutput mcasp_afsr,/ S* k# n; X! ^+ |8 f% Q' w5 X
output mcasp_ahclkr,; J# H& ^: v! P( O
output mcasp_aclkr,
' U' o5 h5 \2 houtput axr1,
1 p" X" ]6 Y* e assign mcasp_afsr = mcasp_afsx;
( y4 I( f- s9 m9 Jassign mcasp_aclkr = mcasp_aclkx;! `; E% z0 ^8 l
assign mcasp_ahclkr = mcasp_ahclkx;4 a# Y2 d6 i6 Q% E5 }6 D; {$ v) a
assign axr1 = axr0; 9 E6 i' j" [3 I* e, P6 f
1 t4 i; P/ D- i9 B; l6 o( ? ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 w/ c+ e) Z- T3 `
static void McASPI2SConfigure(void)
" u; `; Z( T5 F' A% w{7 u$ ]0 T5 p+ p% ?7 j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, Y2 m" p2 O" U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 z& L: _4 e) J; W6 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); [. N, Y$ ^* s4 n) L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 A2 x9 m) [! F7 D2 nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 G+ _" M3 }" [' x FMCASP_RX_MODE_DMA);
1 x. `2 e: g: k, ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" r7 T* _+ d' y$ {; I8 @( tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' M' S9 ^( J& j) w- Q1 q5 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 a7 O- k& | bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" O; t5 P% p5 Z0 a! L- VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ h) V) e- e6 y: \, r3 Y. PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* P7 R* b" s/ f2 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ t! L- h4 _' p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 V5 n' x) r- X8 e& X, j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 [4 T+ i' F; P6 m* [0x00, 0xFF); /* configure the clock for transmitter */6 I' J8 ^- a) ~ q, ?7 v; W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 }* m7 P* V2 Q3 Z# N% sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( v" F/ A( S' n8 X+ d* }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& N' M* o+ ?- T0x00, 0xFF);
: G& o3 g. h) N q$ _- z0 X$ `6 z' N
/* Enable synchronization of RX and TX sections */ 1 H/ L2 K2 f Z% B& s0 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( x1 a4 X" r6 s% {* }& n; `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ ? \- P! X% q; ]" E; A# n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; x- l0 G! j8 M9 g, d** Set the serializers, Currently only one serializer is set as
0 l5 o. B3 N o! `* p** transmitter and one serializer as receiver.# u( F* I0 {) d; G
*/
! g$ l1 [7 d* J6 {- T$ oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 ?* ~: z- ~9 O& Q1 u) O, U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 d5 m! Q) M I7 w
** Configure the McASP pins 3 B0 n/ N0 A1 A* E$ H3 n4 L
** Input - Frame Sync, Clock and Serializer Rx2 u8 k( ?0 d0 w; @
** Output - Serializer Tx is connected to the input of the codec , c5 P+ m/ H m; N8 |" x
*/
* Y; o) K* Q w( _* nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: F' N3 L0 R* n X* _* EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% y* Y' t; Y1 G" B7 b+ t* O+ Q$ }% q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' u1 R5 A- e" `| MCASP_PIN_ACLKX' f3 z$ ~/ I+ N: O. F3 n9 D5 T
| MCASP_PIN_AHCLKX/ t& Q$ [2 u, w/ o+ x3 v1 [3 F. D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 @8 d+ w2 G, OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. z6 S7 c3 E& E# d* T: O| MCASP_TX_CLKFAIL $ F; z& r' E& V
| MCASP_TX_SYNCERROR
" b0 s0 R- o) T( l f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 h9 ?8 N2 X" p: p& c" L| MCASP_RX_CLKFAIL
( b2 ^. Q7 s$ C( Z |5 Z| MCASP_RX_SYNCERROR , p- W0 T6 l1 g# [3 A/ Y! l: z
| MCASP_RX_OVERRUN);
! b: [- T8 A4 m3 `" Y4 O7 _* T} static void I2SDataTxRxActivate(void)
$ R( x* M' M, ]# R1 q{
& X" K. e4 O. @# c9 C/* Start the clocks */8 k+ P/ ^2 Q. S- p, O4 H F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# ^4 y. p$ a6 r- p7 A# t, S s" W3 P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) H0 ^ y" c9 P- z5 Y' A6 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: ^' c7 y9 G1 _9 K$ D7 C
EDMA3_TRIG_MODE_EVENT);
1 P* R+ v) {% Y& `# tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% z) Q3 ?' ?& wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 e0 A( v- ^+ L) PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ i* @$ t6 F3 C; S" J2 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. {. P; n7 K* I# ]" ~/ G. Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: G5 y' v8 W) ~: \+ m- kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 c+ X/ T' h1 G( K9 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 @! j8 h$ x2 | S4 r) Z} ' J3 ^" O* Y. ]- @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 O4 Q0 S( P$ V0 S" S5 g
|