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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) a# J5 g: B# f# B; tinput mcasp_ahclkx,
$ F! `# k+ R/ _5 O. o, ^, o U. Finput mcasp_aclkx,
4 D8 R7 N2 c, J3 d% Q: _# Zinput axr0,4 X- E* {; y9 U! d
5 i6 Z( x. g j* F( R. t) W9 Q* foutput mcasp_afsr,
. a$ W% Y" z" T% q- ^/ @output mcasp_ahclkr,- ]) \4 @ ^, s" Y$ Y9 F
output mcasp_aclkr,9 j1 z6 L) b: R6 T' e1 ^
output axr1,
4 |8 P, T1 G& P) f. ?& F9 u0 Z assign mcasp_afsr = mcasp_afsx;& d6 U) R5 ]3 q
assign mcasp_aclkr = mcasp_aclkx;
* R6 z& u+ L8 x6 n# p4 ]assign mcasp_ahclkr = mcasp_ahclkx;' H) u8 Y: O5 T% L) u
assign axr1 = axr0;
0 A3 r! @# [; T& n E2 B# U7 q* @4 l3 A1 E, Y, l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: l1 r! u1 U# Xstatic void McASPI2SConfigure(void)
& f, J- Q$ ~' H- M) M{
7 @# J4 Y+ [" W: U! G" l$ t6 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. L' w& n5 Q, [4 e) u5 }4 h/ u, tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 c7 z4 n8 I8 n/ H, Y$ mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* k* y0 C0 L# A" }1 ^ w- tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! L6 P8 B% e: `5 I' `, C/ HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 h1 B: t5 u! a- c- F K
MCASP_RX_MODE_DMA);
V! J8 i# x, Z- l- e% ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 I" c& @6 w6 _+ N. z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 e Z2 K* |& o8 A5 o7 J, B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% ?( ~: A# S& Z6 _7 `1 W; HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# d) a% U+ t/ \0 V; vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 M6 l! m& J4 C6 O) M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& Q5 j3 J$ d4 J! Z1 m/ k6 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 {+ i6 K" N) E7 h; _$ }8 E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( e* a! X3 }' _! Y L- I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ {5 k/ c$ H; V' w6 y
0x00, 0xFF); /* configure the clock for transmitter */
7 U- t' Y& M- l2 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) f4 s: e( u2 W! j0 g9 ~3 E8 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# g2 L4 S0 k4 J0 X4 {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# @, }% g* G+ Q0x00, 0xFF);
; P) H4 Z/ W Q+ G5 W# ^6 l- |4 D" H! n- N) O/ T2 k' E
/* Enable synchronization of RX and TX sections */ . f! I d7 ?$ Y' h" E/ j( |3 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: E. A+ H+ A/ a8 K! k9 d$ S1 I$ kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 C) u/ }: z3 W( j4 d @4 z, EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 K$ }4 v, M5 E/ R" g0 z$ O; U L
** Set the serializers, Currently only one serializer is set as) |0 p0 f+ ^9 Q4 H2 Z: Y7 H( \
** transmitter and one serializer as receiver.
* A4 z9 T* O1 h$ n( r# p*/
0 u% v) b$ u/ D6 t1 ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% d! y8 [" A) y1 i( g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. V) \# q; m3 Y7 @1 P$ l** Configure the McASP pins ! n8 G8 E3 w$ ~; C) {+ X/ [9 U
** Input - Frame Sync, Clock and Serializer Rx
- i0 Y7 E5 T& L; d0 C1 ~** Output - Serializer Tx is connected to the input of the codec
- P! F0 t \6 ]# B J) E5 z5 @- |*/, s C8 y# r& a, A; P' A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 c" L6 v; M2 }( X( c8 Y3 I/ CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, G" a% u) P( M: j: ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 X- n% \5 U8 f4 H! E9 O3 S
| MCASP_PIN_ACLKX
! M2 a; b; D5 J. b| MCASP_PIN_AHCLKX8 `3 h `: [, a4 I6 D* j4 Z& t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ y4 G- P2 ~! Y5 ?) F+ f+ I" J! {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 R* G: n4 x' i4 J. k4 o; K| MCASP_TX_CLKFAIL
6 K% N3 ~$ S- i! R5 L: T; J| MCASP_TX_SYNCERROR
* }5 l. i* D. F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" j6 y8 |5 s( Z. ?. Y5 e| MCASP_RX_CLKFAIL
- s+ `5 G. T0 || MCASP_RX_SYNCERROR
/ N* g1 h3 S* F: [| MCASP_RX_OVERRUN);
( }. P) |* _$ R$ j, Q1 I+ S& h} static void I2SDataTxRxActivate(void)2 Q* J6 {- I: W- J# E/ ^. Z5 f0 c
{
$ ~7 F" G$ o- b5 _( x/* Start the clocks */
+ V- p, e9 J0 @2 Y F" Z* zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' A2 C! t# b8 y+ _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' O8 a( h* Y/ t8 m/ |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( L/ a& q" y/ c. W1 w* ~* D/ S
EDMA3_TRIG_MODE_EVENT);
' A# b; v- e1 ^% G+ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# ]' a+ D: n; n+ AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ W, {- ]9 G6 V7 b3 e* {1 JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 ~' I; D3 x+ w4 D' U. w. m! m4 ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ C! `- {' y; R) r8 [, kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 X/ ]! s6 ]5 b' e, K1 cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# A3 O& f$ H* K7 g/ L1 ]& m, ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: o. }4 U5 j2 u. l4 q
}
0 {" ?' F* w( j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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