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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 r$ Y7 D8 R& x
input mcasp_ahclkx,
; y2 q/ {, X9 K+ \input mcasp_aclkx,
& i* j+ s. U: n# x3 y0 P- linput axr0,
3 X+ n0 \6 l+ `! c9 I$ |9 l# G5 E0 F' Z1 C+ q
output mcasp_afsr,4 h/ y2 _4 J- E$ p# J
output mcasp_ahclkr,
g/ Q7 C6 a# l! p4 Z. c9 k+ Loutput mcasp_aclkr,% V, o0 M+ |. G, w0 {
output axr1,
: N1 Y9 ~7 ?$ V5 Y assign mcasp_afsr = mcasp_afsx;& [( p5 A2 r& s0 U6 `* s
assign mcasp_aclkr = mcasp_aclkx;
) W1 ~2 J4 \5 l; {# qassign mcasp_ahclkr = mcasp_ahclkx;
/ C- y9 H" b# w9 q$ iassign axr1 = axr0; ; B) x9 ^1 h9 N' K
6 f! h1 R' J+ d2 B) u! H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 |% i) R8 H3 U/ |" [
static void McASPI2SConfigure(void); P1 P; a; D! C* A% V/ R
{
$ Q" g O0 |% y ~. T1 ]# LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 c# B) \, g3 {( @4 r0 L6 K, WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 w& N r. M" b! u1 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ s7 T6 O( c9 U$ ~! [: pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' j$ }( r! ?& Q' \2 u' M" ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
v3 r3 G" j2 B7 @+ V4 Q, cMCASP_RX_MODE_DMA);" O- {! o$ L8 N p& c# J" C. P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 j- d" `/ d3 K8 g4 B: P U. ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: Y7 x$ Q* _; Y; T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' m% b/ p& f' ~- r% e$ u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* j2 G8 Z4 O% _# I% MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' O9 b Q$ }! |' _5 } {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 f8 O8 p1 ?/ H5 w' F: h H: p3 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. \9 m* Q, ~% Z7 l! L( p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * J" ~. T5 f7 v& ]2 v! O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 N7 l! v8 K5 s" m. q
0x00, 0xFF); /* configure the clock for transmitter */6 ^, x, @& B' v( h- z% o* n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' j S0 m* j5 R: C' v7 t5 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 ]* [9 L9 w; ?7 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 F- h( b K" u- \' G) A
0x00, 0xFF);
6 z1 Z U" \" O9 Q/ g1 B0 Q, ^7 h" B
/* Enable synchronization of RX and TX sections */
$ b( T9 V {4 d' d: V7 a5 {( DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 x) x" {8 m' X* @' ]; Q- p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ z) }0 Q( {1 L: L/ k7 h: `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& u4 k9 p) U7 K** Set the serializers, Currently only one serializer is set as, F2 |7 L& y" p! [
** transmitter and one serializer as receiver.; u: G7 c m( F) @4 f& ~
*/
+ g, d7 [8 ^* O# [" L3 K7 _ S: wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 D7 H' i+ Z. ?2 Y9 C4 q/ B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' \" p3 R# o* V! I$ c6 v! R8 e: O** Configure the McASP pins 3 J: D* y- ^: p- s0 k7 L! v
** Input - Frame Sync, Clock and Serializer Rx) V: u8 b3 H F* s
** Output - Serializer Tx is connected to the input of the codec / k% a$ n( D+ U. {8 Y9 F4 I
*/
5 }7 b& W+ h8 d. x$ F* ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% Q6 y: v& X1 WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: ?4 M: ]; I$ T KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' f8 J. }. E- g/ s
| MCASP_PIN_ACLKX d3 l# X$ S3 K
| MCASP_PIN_AHCLKX! }4 G/ H+ W' g c3 Y$ Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: Q) h, z* s& O5 v, h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, v# V, @3 w6 S/ l& @. S, S| MCASP_TX_CLKFAIL " J3 \ z4 v9 p+ B) |
| MCASP_TX_SYNCERROR
% e' I- a4 a9 u& T: w" K9 R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & T- d6 D5 I" k; w0 P+ h! |
| MCASP_RX_CLKFAIL
; ~1 P' t1 q8 F2 p( c| MCASP_RX_SYNCERROR 5 B( C7 c6 W/ D9 H' k4 R8 L
| MCASP_RX_OVERRUN);" [9 }9 L$ j" K
} static void I2SDataTxRxActivate(void)
* r1 E3 V$ W1 G1 R{1 r2 T. g r; S
/* Start the clocks */
" B/ w6 ` ?1 t( t$ ~5 Z% X6 P! m2 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 v; m' u% H( W$ M0 f+ ?8 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 k$ V( G$ v3 x7 y& LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 Y) ~1 m8 D0 `& V7 HEDMA3_TRIG_MODE_EVENT);8 K2 Q& z+ U& p1 L) [5 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' R" h/ H p* i7 r Q2 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ }( h. z5 q* F' x( w* d) B6 y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' A5 ?+ s0 P" i7 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 I: N" e; U- f# o4 W m& lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& M- u9 \: m" }) \! f- j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, e# U1 M% f; v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); l( d6 j. w6 d: z* g
}
5 }% l+ N5 _9 F* M: r, I2 H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) s5 Z; _/ m1 r4 i3 ]
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