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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. }- O: F }- N2 g" l/ E/ iinput mcasp_ahclkx,
" U$ L* U$ Z; Q o- }! H2 m, kinput mcasp_aclkx,5 o7 S6 b% w7 x/ [- {6 p
input axr0,; d# |1 N: h6 ?0 ]
7 u- k! E) a9 q, _( c( R) ?5 [5 {! Voutput mcasp_afsr,
1 P+ R# ^& d( {output mcasp_ahclkr,
" T% m o( h4 L, X+ g9 N4 O# T+ moutput mcasp_aclkr,: s; p$ J4 \ ?7 }' z
output axr1,
; x! f8 r* B8 i! Y1 J0 p* M assign mcasp_afsr = mcasp_afsx;
7 S. r3 k( o$ u2 X4 f; Z3 H! Fassign mcasp_aclkr = mcasp_aclkx;
0 M1 n! H: Y1 E: @: @# u! Dassign mcasp_ahclkr = mcasp_ahclkx;. |$ t/ i Y$ ^# D
assign axr1 = axr0; # u2 E5 A3 M* e2 u1 E/ U
0 X; G5 r! g5 U; u9 p! M. i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 i6 X! b" A8 G8 n& m+ lstatic void McASPI2SConfigure(void)0 z% Y+ R* M3 N2 K
{
* D2 x W0 ?* m$ V5 Z) o) eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ w" [; R3 f* d1 G) Y4 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) q9 }. e+ ], y9 h- E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 y5 G1 Y) D( A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ S# X+ o6 {8 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 a$ O+ _+ _5 r% C7 Y/ Z* B- L6 q3 \
MCASP_RX_MODE_DMA);8 c% g: N2 Y' F7 K' g- ^$ j' j- Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 ?. L" M& m2 g7 F& F( d+ C1 ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' E3 F# n- n' ^6 `+ w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 @! F' r. i; R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 J& {* j% C' v0 K& w* M9 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; t% V$ m' h9 A1 u- G. L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" l2 M# p+ v, j, ?# G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. \% m, q+ H: X1 ]. r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / z$ w5 u+ }( s0 H# Y2 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 |# F% f2 X5 v* n+ F% y9 f+ l8 @! ?0x00, 0xFF); /* configure the clock for transmitter */5 u! g/ [1 ^) u+ O7 S2 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 q; C8 m5 O* a& f- ~3 |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 ]& }0 X; G) AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 ~" y% D q- g' @3 o0x00, 0xFF);9 ^! P; X, X$ f) X; T y4 Q5 g
2 q. @1 q1 b [3 r V' B' C0 |/* Enable synchronization of RX and TX sections */ # H' n5 z- B9 _/ ?: _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* N/ _+ R# { }' N8 ~6 T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. L5 l0 q! D$ K5 W0 q1 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ }* K" X$ H( b: h
** Set the serializers, Currently only one serializer is set as
3 ~9 w2 N) f3 Q9 Q }** transmitter and one serializer as receiver.% q4 f! u0 o0 e: D& E+ {
*/. f& M$ Q9 }! ]% o" A# Z. _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 S! n6 N9 D2 n' a* LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; X# h) X3 \) n6 ]5 p( q& a
** Configure the McASP pins : }3 l, k" C3 ~0 @! z
** Input - Frame Sync, Clock and Serializer Rx2 Y8 [6 T& }3 ^( E0 ]2 N
** Output - Serializer Tx is connected to the input of the codec
8 y. F: @' T7 H0 k*/
* p, k2 ^7 e# t2 e( LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ y1 [4 \: D' S& YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& n- {4 d( q* `/ G+ X: ^0 U/ ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. f/ [$ f' B$ c" k
| MCASP_PIN_ACLKX
5 n9 f; W; v+ L. m- }" W| MCASP_PIN_AHCLKX
- Q0 n4 @0 g9 A5 s3 p G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* t1 n {! o5 H; ^. ~$ L2 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: }9 h$ u0 [, D& a* Q% E0 I n) r0 H| MCASP_TX_CLKFAIL # J: `* r9 q+ A- k) D. A$ ?/ L& [
| MCASP_TX_SYNCERROR
@ K$ h% i4 d- |1 p, ?# p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . [" Y& v/ ~: L) M+ q. x' {
| MCASP_RX_CLKFAIL5 F: P0 G2 r4 |4 s, V( w1 b+ D1 T. F
| MCASP_RX_SYNCERROR
$ U: S2 R# W% y! x6 F: J: t| MCASP_RX_OVERRUN);" m9 `8 v8 y6 [2 A! u
} static void I2SDataTxRxActivate(void)
4 o8 n" s; Z* U+ O& W{% T4 {4 ?6 ^. r: O. _$ `$ |. Q1 k
/* Start the clocks */
_4 o$ j1 C! j7 t- RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 `; v8 [) P: v6 u* SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) p P* ] k& b# l! } g* D: q, YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% s: |; e: p7 A+ M E9 AEDMA3_TRIG_MODE_EVENT);
. N5 K/ U6 {5 F4 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 X0 C; [. d5 V/ J' H8 ~" X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% V% r$ } l" `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 ?! u1 \8 l/ I2 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- ~7 r5 k) p, D$ ]: ]' G, `" Z, |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- r/ T" U; y) ]! vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 P5 o: Q( T( C- p! `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& | p1 K2 g7 {. @6 N
}
( m! r& T/ n( V7 Z9 X/ E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + G$ `1 H I# y2 o* x, B7 ~
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