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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; T1 a$ U( j& F* g) X$ z. j4 X
input mcasp_ahclkx,
; N* d) B' I- r, z b! l7 dinput mcasp_aclkx,
7 X. e0 Q+ U3 ^2 _% {' w7 Ginput axr0,% I% {0 E2 O- Y0 U5 Z+ _
( }" p/ I1 l& M5 V0 \! goutput mcasp_afsr,' r' o w" `* @' f
output mcasp_ahclkr,$ ?- T5 u. m; ~; [9 G# `2 L2 ^
output mcasp_aclkr,
' h" E: j% Z4 ^/ F$ \( `# K' o( }output axr1,/ z' F4 i% Y( I" O8 t. L. _
assign mcasp_afsr = mcasp_afsx;' w/ N2 g( X2 N- w
assign mcasp_aclkr = mcasp_aclkx;
2 |, |( y; C) s3 I( fassign mcasp_ahclkr = mcasp_ahclkx;7 N9 `5 i, ?' H, L) P2 a' @/ Y ]
assign axr1 = axr0; 0 b" h' B+ n5 q, |" g \; Q' F3 h
0 H. Q* o8 ^- A/ _: f5 O; K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- e4 M! z5 `: f- R* Kstatic void McASPI2SConfigure(void)
; O6 f; o8 T$ ?- y4 q{
2 n( b9 U6 c8 a* L- s! OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 D: E; ?4 F# ^$ M. hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! p8 c. q% b( u7 a) g1 P- G8 x/ GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 }- g$ P5 I0 y9 V" t: f3 H. S' ` mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! r1 w: v* g4 m+ z; P3 P- D: S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! d! ~$ ]- I# |! k
MCASP_RX_MODE_DMA);1 r7 s# `& p' `- h4 F- n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 j8 Q% W* @- ?' m! @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 G6 W" g9 b2 [4 E8 E- B; c7 \: sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 p% C1 F, r" |9 l! M! r% [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 G; \# `/ X9 _3 _3 M% b, gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" v9 T7 d3 |; l. p mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 i5 N3 R% X8 o2 c! w1 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; ~- N* Z+ }4 J7 W/ uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 e! E4 Z1 Y" E6 p* j8 `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, g/ H- [( ]4 p0x00, 0xFF); /* configure the clock for transmitter */
+ \+ R% m& R( l( hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ c3 Z3 U5 r9 R7 K9 B" Q& ]$ v& y: jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 Z. ]+ |; s% S! t. sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, F/ l8 U; I( A: t. l8 H
0x00, 0xFF);
; b6 Z# F0 ^$ S8 i2 K+ i! Z
$ {* A: Y0 x' x. A0 K% Z/* Enable synchronization of RX and TX sections */
0 E; Q' A* n4 f3 }; t4 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ v q+ j1 c3 K9 X6 F7 V% lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% ~5 O- H& i. d( y7 y# b1 M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: V; A0 ?2 ?% U h** Set the serializers, Currently only one serializer is set as
3 _) U6 b) x0 s' p+ ]% Z. ~** transmitter and one serializer as receiver.4 S x) O' C+ l y3 R& J
*/
, K) B" P+ }8 V# RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 Z7 N* e$ l% m% _4 s; cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 l9 k; B6 ]2 K& ~** Configure the McASP pins 5 _- ?. I2 Z1 K& _
** Input - Frame Sync, Clock and Serializer Rx8 v, u' ~2 ^% p6 h, C; z6 y
** Output - Serializer Tx is connected to the input of the codec
! D$ _- \" c" U+ g2 Y0 Y*/
6 w0 ?* R1 C* k# i9 _2 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( d' ^9 V! L7 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ z. z$ U) Y1 O& A: c4 l1 B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 ?6 {9 ?$ G; [2 U) T4 H" i
| MCASP_PIN_ACLKX) G8 Y/ q: ~6 o* n
| MCASP_PIN_AHCLKX% k* |6 C; M( I" |' N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ p- |; x. P& L5 x! v' OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% T4 j7 J+ T- ^9 [+ T- @6 @3 ^( l' e| MCASP_TX_CLKFAIL
" y; [$ L' N, p4 v! U& R+ G| MCASP_TX_SYNCERROR
& v6 r+ r1 W: }! {/ _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - P9 K0 U0 C, O. D% L
| MCASP_RX_CLKFAIL
/ v0 }+ N9 _+ a% M+ Q6 j* E: w| MCASP_RX_SYNCERROR - t/ ?8 F- S& D1 t) M
| MCASP_RX_OVERRUN);
6 {: c" }- y0 a1 K. v ^} static void I2SDataTxRxActivate(void)$ r0 J( ^- N( i9 K' g- V
{
) F6 M. R0 z) P* v; R/* Start the clocks */
1 ?7 P1 l; W2 x5 U2 F! X5 pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) e( s+ r; E- K- Q' x. n5 M" z6 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. t, v( r1 r' A8 \6 }1 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 m7 x' P9 Z' Z7 ?3 h2 E% {; U
EDMA3_TRIG_MODE_EVENT);3 h6 \# X6 Y, z8 {5 m5 U7 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 G( T, a k; }9 i) |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& I7 H1 I6 B. a) FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 l% \' s" f/ I0 }9 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 z- q* I5 r% G9 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 J& ]" X" j6 j" a2 S- iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 G Y; _; w& H# j* ]7 Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' h7 ]2 Y# N. ^7 Z8 S' ~9 s% G4 Q} * R# L$ k/ F- c; S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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