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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 t, X: Y% M( m: t9 `2 m/ e5 ainput mcasp_ahclkx,5 i( z5 T* ]* Z- r% D
input mcasp_aclkx,
% H; e( z4 s9 F( M `, [input axr0,- o2 t0 @7 u7 M$ s' R/ K9 o
! |4 A; J; k) Z4 {output mcasp_afsr,
! e# a) g' O7 A7 S* N* q5 p W( `output mcasp_ahclkr,
. a& l$ ?1 L/ }* r: f; soutput mcasp_aclkr,8 M* x( [8 f3 W! K1 e I' Y
output axr1,* K+ T, h, L# F# |# m$ V$ `
assign mcasp_afsr = mcasp_afsx;
% ^' p5 z. J- |# X) W l: cassign mcasp_aclkr = mcasp_aclkx;2 C$ k* F) M& g, J2 X
assign mcasp_ahclkr = mcasp_ahclkx;0 Z% t. e% m( Q8 n% o0 p% P
assign axr1 = axr0;
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! ?6 v7 ], z2 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 {; Q" d ]3 i( O1 D4 Ostatic void McASPI2SConfigure(void)4 [& v' z& U/ c& S% ]; W; y8 G6 p
{+ `: b7 I) d. G8 O V* b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' u& N% i# y& K' }) F0 z0 q# HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# i8 N6 D# i1 t8 x) z8 [+ h6 aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! F3 H. T5 Y+ Y2 ]* o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* ~& Y3 O) a0 W- q5 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' f# ^2 i' g7 u
MCASP_RX_MODE_DMA);1 w& z- o2 K4 Q0 L+ S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 R! b' P( a5 \' H5 h- JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ O& x& v( N1 z3 }8 y9 q. t5 f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 X+ C+ H' O8 \" o% H- y. C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- Q ^* t/ t9 @) _. E( j$ X7 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % F1 R; }$ [- J. ]* s) X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 X' ?5 ~) W4 C+ C1 ?4 x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. l( C* j: J% r! B% U2 ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / U! H" U& J/ L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ l0 M& H' }& ]5 S0 j& G
0x00, 0xFF); /* configure the clock for transmitter */
' B1 D# s: s0 K0 f1 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, l! y8 v9 F6 r4 F% Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . W4 M; w; J1 u. R7 A7 k& i: T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; s% U7 y' W' K6 B9 l9 x6 r0x00, 0xFF);6 d! d- U/ f4 b. n( ^3 h9 j
5 f8 |0 N: |/ F: u' |4 }! n
/* Enable synchronization of RX and TX sections */
5 k' w) m( ?& U! }1 OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// u* z5 C5 w, p+ @2 z* Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( x1 n$ Z0 _3 S, j2 F+ E2 C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! X% h9 e8 S4 B7 p** Set the serializers, Currently only one serializer is set as
" f: I/ Z9 k A" t% x7 U** transmitter and one serializer as receiver.
# |* }7 S# k. [: h6 d; |9 E*/
! L& Q4 f2 }& E# W. PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 |/ g1 c$ I6 AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 S& L {) o5 l4 m- k, v** Configure the McASP pins
1 `- H8 B2 l1 Y4 R** Input - Frame Sync, Clock and Serializer Rx
' `1 L) r# d( J2 k' l6 r1 U** Output - Serializer Tx is connected to the input of the codec ( m" Z+ }& b* C9 o# {
*/
- ]4 x3 x' F8 Z! N( R6 R) LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 X/ a0 J0 W$ e* r. a5 I- dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 O& S7 \3 B) O' T: T: m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 Q. ~9 Q. X. K8 f/ v" Z8 O2 u
| MCASP_PIN_ACLKX
8 f! b. k, c5 o3 v* F| MCASP_PIN_AHCLKX! R7 v8 \- F o) h( c2 P( ^/ F! L, ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; F% L1 }( i, R4 X# M8 v1 [7 UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 w! T( P# p) E; Y+ a+ s2 u: |+ F
| MCASP_TX_CLKFAIL
7 g# ?8 V7 U- I+ E| MCASP_TX_SYNCERROR
& u- ]: {! E, K5 h3 f& E& \$ {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # g' E4 f1 X! J" Q, B3 ]
| MCASP_RX_CLKFAIL# I0 T2 d9 @( V& p- {# ]
| MCASP_RX_SYNCERROR
6 m* N" x% U) m" Y7 J& \| MCASP_RX_OVERRUN);
* V6 [! q$ M4 i9 g7 R% K} static void I2SDataTxRxActivate(void)/ U% x% Q a2 m) O L
{
/ }) @, ]" i+ z+ W3 H6 g4 \/* Start the clocks */$ T" H- Z4 V, y) V3 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 w( i& ^, {$ z: j' g8 e4 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' S* f) q/ P1 J# z0 d% Z/ M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 A7 @1 H3 t1 s, Q' p1 \% H5 b3 j* U
EDMA3_TRIG_MODE_EVENT);
1 S2 E/ \' `2 N" A4 Q% Z! pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 u; b# M1 j3 d' n. L. ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 R1 S' K W" K. a! ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 e2 n/ |+ s- d$ s6 u0 h8 y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 e+ w, e+ G7 _# G, vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 ?/ K6 q! k) _) t" Y! ^1 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, t# x/ M5 F* N5 y# S9 ?6 iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( _7 ]/ U' ~6 S
}
; w$ F- R! ?2 t7 ]! }' [1 }* f5 [5 M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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