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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 p2 _8 o) n6 h$ h* U, Pinput mcasp_ahclkx,
2 m8 l9 X1 M- o5 linput mcasp_aclkx,
1 e/ Z' A9 W/ }. m+ R5 Minput axr0,
0 T' X: l# e5 h( ~; m2 x5 \9 v# O- p$ @; t9 C; J
output mcasp_afsr, b' p' q, W4 B2 b0 [8 s
output mcasp_ahclkr,
: q" N! P3 n- S, v4 j5 G7 N: houtput mcasp_aclkr,
3 A( ~% E0 Z, H! [$ w( ?output axr1,' T7 x3 D9 ^7 u
assign mcasp_afsr = mcasp_afsx;2 F% g2 ~5 D! c8 O0 k% e6 ]! J6 ^
assign mcasp_aclkr = mcasp_aclkx;6 ]5 I! R0 A5 t
assign mcasp_ahclkr = mcasp_ahclkx;
- s7 B, r$ |' ~" T3 s8 d+ b' k. Lassign axr1 = axr0;
9 @% t% M7 D* G( x# h
+ j, g& `5 p. l* m( p! T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 ]9 v# n# d i0 R( [static void McASPI2SConfigure(void)
8 f# j! M& N; {3 N8 G{4 {, o) X9 z. E! K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' d2 B9 V1 d( x' q3 Q, u' RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* [" o! e# ^7 j6 T. E5 @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* W; b( n7 z9 G" \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# ]$ o" D4 X" d5 i: _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ C, m& g( F, A) J, X5 F; QMCASP_RX_MODE_DMA);
6 k. s& u* N0 qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 l; n- Q# e. K( ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) J& U% m6 C! V7 U& P3 u, oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# b9 X$ @# d* }* v! l4 D5 ]6 R( t" jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( M$ b9 h7 @2 Y" D9 @0 C' ~, pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ p8 _. ]: O; b) l% T9 z4 P3 N; fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! a. Z8 V7 i; eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; r: e0 `/ |/ S' H. e. wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 l2 `" ^# [7 m4 d1 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 q @+ K; H* t
0x00, 0xFF); /* configure the clock for transmitter */+ D0 g$ D" Q! Q3 K9 s) K+ \) M0 {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: o' a( n" w0 a+ L" W8 H& a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, H+ H$ h4 f2 H& ^7 SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 ^, @3 @/ e. R; E) k4 \+ W" Z0x00, 0xFF);
2 T7 ?; y# W0 @8 J5 w; n ^* w; W2 ?- y3 x2 m5 U" c8 D/ k" r
/* Enable synchronization of RX and TX sections */
1 i i. K" u/ d- K3 G+ g+ MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ v5 W K) L& P3 A3 D! l% s; B& uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* k$ B+ l6 s u, A. \7 u! sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 K2 m6 b4 o- N** Set the serializers, Currently only one serializer is set as
3 L( u6 f2 ?7 y0 [* a& m, H** transmitter and one serializer as receiver.! ~+ p+ T5 a( w
*/
+ N) y* ~. X$ r/ v* q7 z9 S yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ S/ Q8 A& W, h9 {+ W0 d* F; r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! D. Z1 Z U$ ?, Y** Configure the McASP pins
9 E- q% d& t$ t0 J4 z. v** Input - Frame Sync, Clock and Serializer Rx9 T) X% o. X+ k
** Output - Serializer Tx is connected to the input of the codec ) t2 @/ ~- u# P$ B+ {
*/
& L- m. v0 w$ r" c. t8 @2 RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 v' E/ a9 E: \# P+ d; aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# g7 l: C' k7 F/ T3 t: _3 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& M5 E1 T5 _* P# h* g; q
| MCASP_PIN_ACLKX, q7 r2 w% Z4 i/ J$ Q1 R# }! I. \
| MCASP_PIN_AHCLKX3 ?% f8 m2 l8 j. ~" D2 j8 V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 O+ N0 F: N: L! Y/ i: ], j0 j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; M4 |8 w0 Q5 |1 m. |) B
| MCASP_TX_CLKFAIL
+ F) m8 c7 `% v( N| MCASP_TX_SYNCERROR4 M5 h' G) ]# ]+ m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + Y0 k0 \- r8 P8 L g
| MCASP_RX_CLKFAIL% ~9 k" d- @. b1 _
| MCASP_RX_SYNCERROR + m9 v% {, a* g) F5 k
| MCASP_RX_OVERRUN);
W5 k* N; T! Y3 H} static void I2SDataTxRxActivate(void)4 }" Y$ q1 a0 v
{. x4 n/ Y+ o4 X. Z/ a; k
/* Start the clocks */& G. O; h9 C. e, X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& N$ r* r& u2 v$ p( TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 I$ f- O0 r5 a' [# SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 ^/ L' {; U3 b1 T9 ~5 kEDMA3_TRIG_MODE_EVENT);& f9 u7 P) G4 C* h* Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' W6 Y4 V% m1 f, z) H8 e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ J' z4 [, S. _2 U) q, ~+ `* FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# Q u# S4 R) BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ Z7 s0 q. i- U' {8 ` Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* V! g3 ?* H, S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 ?+ K2 [. r; l! p, d; c4 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, K0 F- L! ?; \& R}
$ D b8 s7 V6 V, N1 ]- I9 R7 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 l1 L1 `& q/ v; y0 _( `$ H
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