|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ d9 p# E- U$ q0 t4 {8 xinput mcasp_ahclkx,
+ p' i7 G, f8 i5 Z* b* Binput mcasp_aclkx,9 B+ l+ R" L0 s2 v
input axr0,8 K V% \& Z9 A2 W9 u$ { {7 H9 ?
, H% [; r5 X9 m- Z2 z
output mcasp_afsr,
+ j- Z4 R* n! Y5 V2 H1 loutput mcasp_ahclkr,
8 A) ^ P+ p$ p% E0 L2 qoutput mcasp_aclkr,# l7 N' m; L# Y: Z: _
output axr1,
3 m) N3 ?9 C- z6 S" I assign mcasp_afsr = mcasp_afsx;4 _- ?! ^; D" t( ^7 X; }
assign mcasp_aclkr = mcasp_aclkx;
% ^! O# D: q+ |" z1 `9 hassign mcasp_ahclkr = mcasp_ahclkx;% n, C( Y5 F t3 d! H8 l8 s
assign axr1 = axr0;
Y, ~' b* E8 j6 I
0 ?$ z. ?, w3 u# ~! }6 L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ }- g7 O d8 {% A5 Tstatic void McASPI2SConfigure(void)
1 `" @( G% J% ~$ G5 s{: a( \3 I7 F* W1 J3 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& Z/ w" N6 N5 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 d& r( q: R" O- t) P: f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. D7 s1 |$ e* `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- \% N2 M& V& sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 M) O* e% w- k6 x
MCASP_RX_MODE_DMA);
* }* S+ y% W3 a0 r& x3 H/ N/ AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 M! o8 [1 }! lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, ~4 w. m) e- n) ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , q$ \3 j- s, F1 C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 A; L; _0 Y% S0 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. b e2 i0 t/ E; s* j0 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 d* W) F# V3 ? F. t* @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ y& c+ T' `/ s6 [2 i: gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* I0 k/ b2 Q1 O7 r- I% JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ t# n3 K6 h3 O: u
0x00, 0xFF); /* configure the clock for transmitter */' V- q: e1 ?, x* f3 H: h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' H) U! r9 c- E) R; UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 A7 g& T1 j2 c* K8 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; p% l+ T( m1 y) A9 \# A
0x00, 0xFF);
1 d2 F8 d" \& u- W/ s- L m$ t/ v r& }" }2 a
/* Enable synchronization of RX and TX sections */ 2 J( L$ A! n& ]3 V( }) D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 [8 \ G1 M4 W" P$ h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" B7 f% h5 M( {! i7 z5 Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, {/ j7 K* M4 A: R% c% D Y
** Set the serializers, Currently only one serializer is set as; Y7 P+ h; s6 B/ Q8 o
** transmitter and one serializer as receiver.
+ r V" [+ {8 t) b+ Z7 M) B*/2 Q: A( l. o$ }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ J/ N$ M( j' a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' a- z3 ~/ d4 T& v7 E; F
** Configure the McASP pins ! }4 y0 G7 G) x2 U
** Input - Frame Sync, Clock and Serializer Rx
( f o+ |! e6 G) f* @ b* w9 n** Output - Serializer Tx is connected to the input of the codec R" j' _; u: {# S, _
*/
6 U! K! L' J/ S( v0 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 f) D4 R( P! V* r9 t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 Z0 m1 S% _. a7 L8 z! W8 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- c3 F" M! @5 @, ?| MCASP_PIN_ACLKX
' R, J; _1 b( Z& O, B8 V& @2 z| MCASP_PIN_AHCLKX
; x% \; j: K1 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- I1 [! e$ a1 ~( [6 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 V4 A. a" B% F A
| MCASP_TX_CLKFAIL " g* m+ X: f* o% O' `
| MCASP_TX_SYNCERROR* x) K- i" S$ \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( F! g3 N- N9 || MCASP_RX_CLKFAIL- T" v" {# ^% ^4 {. u n$ H
| MCASP_RX_SYNCERROR 4 ~( q: R9 i* v: }& x' }8 R
| MCASP_RX_OVERRUN);
3 {1 @) O% v5 V6 v3 u( ]} static void I2SDataTxRxActivate(void): H _7 ~' y; g9 I: e7 _9 A, j
{! s1 q4 ~; g8 |, M8 _4 o1 a! r
/* Start the clocks */& r' a9 a: q- o( n9 d( d% ]1 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, I6 M& ]5 U! h$ C) O7 ^# o+ l% aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 c3 x m2 q; ]( ~, \, U r$ q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 I8 o' g0 V* `) _7 CEDMA3_TRIG_MODE_EVENT);8 O+ L6 x O% q! K1 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 I8 Z- [7 Y Y: E/ c) l3 V. ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 @5 q3 c1 P. n2 C6 F- U. d# W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 R) a& B+ r2 w; {: f( x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ L) P4 y; k8 ~) L1 Y" Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& k$ u t3 f1 S1 L, V/ \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. m9 W) J* [( Q$ \/ ~7 ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 o( ]* M, N9 `7 ?: S}
Z: v$ w. `+ D1 |3 D5 f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% e- G; \; k8 h7 Q; A5 @ |