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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: B) t$ H: Y% B9 {5 Minput mcasp_ahclkx,
' H8 m/ _% _! t: W1 H' Y1 binput mcasp_aclkx,. |6 T5 L& N2 O8 _8 C9 [) a& \7 S
input axr0,/ x2 k, k% [( x" [* p' U: W
2 Z9 k' @' T- z: }1 ~8 @output mcasp_afsr,/ r$ T' E; O# Y- L1 X) l
output mcasp_ahclkr,
e+ i4 e5 V* B4 v$ Voutput mcasp_aclkr,3 }- x& _* K! j. v4 t
output axr1,% o( @! R% Y9 B( Q5 l) I6 L
assign mcasp_afsr = mcasp_afsx;* Y' n0 T \( }4 v, `
assign mcasp_aclkr = mcasp_aclkx;3 [, H; r2 c$ D! G; v5 K* E( i6 x
assign mcasp_ahclkr = mcasp_ahclkx;" j$ Z+ j. r/ D5 W! J. B5 d& w
assign axr1 = axr0; # J- {+ V2 v5 t8 K4 x/ O7 y; i
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 n! [2 R- |" j) ^
static void McASPI2SConfigure(void)
) h% `( {! h* z( h9 o{3 }$ r- A q4 g+ }- U4 e1 I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- }: w6 M9 G6 Q j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# m I, ]5 B+ h- C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ X4 R3 T$ a1 u* R3 HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 z) N) j9 o5 J, w! f. f) fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 [& d- ?6 _4 OMCASP_RX_MODE_DMA);) H$ Q% { _8 C/ N8 K6 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; M/ |1 |$ n4 YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ Z2 T) f2 _2 w; S5 r8 N8 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ E) s* ~8 \& `6 bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ a# F7 P V7 w- n% r6 v. J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 |7 ~7 l, {" b; J6 K, Z ^1 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ m8 A9 ~; L4 c8 X' J6 R9 S6 ], f. g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. j, h+ }1 i% }. E& eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 N# L- T; J4 y! J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
p. w- ?3 g3 z( ]0x00, 0xFF); /* configure the clock for transmitter */
8 E) j) q$ j# Q. \6 w, `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, x+ ?- }# |( X' ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( z i, w1 K' R3 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," v L7 _2 H1 l2 @
0x00, 0xFF);0 P5 a8 R% P2 g& ^/ J @
9 J1 G. l& a; l5 k+ r( R7 a/* Enable synchronization of RX and TX sections */
3 E# L3 ^" S1 ]1 | ]8 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ Q/ z' n$ d( @+ _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 W9 |; I/ n9 i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 Z& ?, \2 Z9 p+ q7 y, N2 i& m
** Set the serializers, Currently only one serializer is set as
2 Q, [* }1 E2 {! x& }1 x8 V( n** transmitter and one serializer as receiver.4 B- H5 p, `8 P+ \( B! [
*/# [8 H, j1 Y' q" O" z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( O" S' W4 {+ p, ?3 `' m( s$ FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) K8 R& `8 X+ @7 v2 z& d
** Configure the McASP pins - X! e: O! ~! U8 A$ ]4 u
** Input - Frame Sync, Clock and Serializer Rx
3 H/ W1 u! Y4 t; {** Output - Serializer Tx is connected to the input of the codec & L3 h6 \2 O* v' `
*/
& g, Q1 S$ f. K2 JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 O. _/ s3 Z& v; R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- e# ?8 j5 e& |. M& b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# p3 L! r* Q8 R; b n| MCASP_PIN_ACLKX1 ?6 G# k( W. ~* B0 u
| MCASP_PIN_AHCLKX" X$ ]+ U+ ?1 N0 [' v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& u4 N$ Y+ ^& l. d9 |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 s- j8 {9 n% G" r& Y+ z| MCASP_TX_CLKFAIL ! z' Y* M4 l _$ S C# S9 t$ R3 [
| MCASP_TX_SYNCERROR# i+ H, C* ` Y; \6 {" ~% w+ Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 D4 S7 i" v B+ z h W| MCASP_RX_CLKFAIL. I& ~# M5 y+ M) l. p/ l1 Q
| MCASP_RX_SYNCERROR ! \) n& Y! ~2 c
| MCASP_RX_OVERRUN);) v4 l: E% G6 U) n' |" Y) E1 i
} static void I2SDataTxRxActivate(void)- @4 t4 ?' k( m& _% C
{
% t. ?& n& R7 n8 G) h7 N/* Start the clocks */
+ M8 r# e& q5 fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 M1 B1 q, N: e- d* n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 C6 ]6 |9 X& l8 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 r+ t/ B' W" D5 e! c
EDMA3_TRIG_MODE_EVENT);
S4 n( h X0 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 V" P, f8 r3 Q: C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 y( C4 C2 C* S6 z3 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: u) l, e+ k9 A7 n# ]+ y; x! t7 wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
U' T- Y/ Z- [! z$ v- b9 s6 H: ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 \1 k' E4 c; x1 _2 l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 @, B" @, b; S3 T8 Q( m* A% U8 b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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