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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! g0 o( ?/ g3 a8 _1 e% ?
input mcasp_ahclkx,
# Z8 l4 r) t7 T$ P% G+ xinput mcasp_aclkx,7 k( e! C) U+ ]
input axr0,
- Y' y: u( x3 l8 o0 p1 ^ T z# F- W+ L+ |7 G" ]4 O9 {
output mcasp_afsr,
% j7 H: O7 e+ @output mcasp_ahclkr,6 Y8 Z; c0 B* L1 |9 L) o
output mcasp_aclkr,
1 O1 B! h$ `3 ^4 J4 J- _output axr1," p! f! A% M% B( c6 l/ `
assign mcasp_afsr = mcasp_afsx;( l: }$ a; W: D2 W
assign mcasp_aclkr = mcasp_aclkx;" b; e( T1 C: L. {: p( H, K
assign mcasp_ahclkr = mcasp_ahclkx;% R$ ^' t8 z- c& @6 v
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; c. k* K9 Y; V2 q2 Astatic void McASPI2SConfigure(void)
$ w+ ?% m* `0 r) U2 t6 j6 x{
7 r5 E/ p4 q1 L2 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. x/ A. a4 S( J# q0 z8 zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, C, p5 a) u2 k3 wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" j. Z* q- O3 a+ z1 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 F9 t5 @$ N r n2 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# e. u; T2 Q) `- I3 t K
MCASP_RX_MODE_DMA);
. W Y% A# w. _& S4 d p7 RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 s. _" j' `+ U7 X$ c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 ?/ c' i2 O& t N' Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ f( N& r, x$ B, C L- Z1 ^: zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( a% m& \$ W) v$ @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' N ?- ]5 Y* c+ X/ JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ Z" b9 N/ l' j% ?# ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! w$ {* J: f$ O/ i: t5 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 \6 M% x9 l4 o' JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! Z% {7 ]) W& A9 K' y/ ~( m3 i
0x00, 0xFF); /* configure the clock for transmitter */
. U1 e; Q2 L( ? `/ F! Y- H( dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' @" G& b% Q/ W0 w# v$ Q' _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; a3 b: q- x f/ K, o! `9 R( XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 G- o% d m+ z4 o7 E- b- }! ]
0x00, 0xFF);
# q( K! U3 z# l9 Q `* @' y+ J. V3 ?$ Q B, k' Y+ b
/* Enable synchronization of RX and TX sections */
3 R" M& l5 K7 k5 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, w0 A G1 Z* A I( YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; h' K2 S; d7 Q9 [- W K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 c- K6 }# }$ ?" w** Set the serializers, Currently only one serializer is set as9 F# w; ^2 b# p1 H* O1 k' O$ @* W
** transmitter and one serializer as receiver.6 \, P2 n/ e' J& C
*/. E" }" E, F, F& M) F/ h( y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ }- Y6 L' {0 |7 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 _0 x" r! I( ~4 g. @* {
** Configure the McASP pins
/ m) h: ^% F$ |$ D8 V4 K y** Input - Frame Sync, Clock and Serializer Rx+ N! r) \& \4 Z! y0 q; y
** Output - Serializer Tx is connected to the input of the codec
- \5 x: Y: d6 w*/% c& _% z/ b$ E0 X3 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% h$ v* P: K1 k3 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& p6 \& ^9 ^9 l7 l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
z4 K8 Y$ ^9 g2 z0 \) || MCASP_PIN_ACLKX
/ M0 y$ G J, E1 O| MCASP_PIN_AHCLKX- q" I1 o& K: i( E2 y) y _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% y. O. G9 d" D3 x# j/ i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 u; Y: N4 [5 F7 {5 ^9 f
| MCASP_TX_CLKFAIL 8 ^9 |* @, P- Z
| MCASP_TX_SYNCERROR) E8 {% W3 Q' B5 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) n: _! g, v4 r# K5 U
| MCASP_RX_CLKFAIL
, G5 i+ B1 i1 n; R; T1 Z% ~| MCASP_RX_SYNCERROR
0 t7 T# C7 y ]) i2 f5 R| MCASP_RX_OVERRUN);
5 l. }) ]' l2 \( I% s9 ?} static void I2SDataTxRxActivate(void); a6 D2 X4 |7 K! h
{4 L2 W' g7 e. a$ Q1 e: Q
/* Start the clocks */9 a; v/ y) |% c: [3 s: m! ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# L4 ?! d! g1 k7 H& H" L7 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ r' P% `- A0 g$ L/ V! I& y; f6 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, v2 r1 S3 F6 Y, t- _- V0 b
EDMA3_TRIG_MODE_EVENT);& r% z/ `( K: I. v+ f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 F. E6 d0 C+ Y2 C2 y& LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! z0 P. M7 x+ `4 W) [% r4 }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ g+ q$ p8 H* P* q9 qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 g( _& {- h" b$ Q3 i" D: W6 cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 b: U2 F$ ?5 I b* S6 ?: c" ?6 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ L+ V, ~( X7 e; {1 mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ y. h* p- d$ G+ q- a}
" I& h9 ~* R1 l# E; S$ c5 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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