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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 T1 S3 h' E! m% A- O& y6 V# vinput mcasp_ahclkx,8 l+ B p+ Z$ G( \% I8 n2 f$ o
input mcasp_aclkx,3 E4 O, u+ k9 _
input axr0,$ A$ d% Q0 S1 C# U. [, _5 S
, m$ G- l# I3 T I# T' J! Goutput mcasp_afsr,1 e4 K e# s2 s5 k
output mcasp_ahclkr,3 G8 P1 E' ] C+ ?" |7 k4 L! o) Q
output mcasp_aclkr,
/ \2 n, O! p( C& n) }2 soutput axr1,% \! K) y5 ~" B! e( w8 y
assign mcasp_afsr = mcasp_afsx;0 X. r$ W& Y2 o: M; P
assign mcasp_aclkr = mcasp_aclkx;
1 y8 _3 o7 m/ p) Zassign mcasp_ahclkr = mcasp_ahclkx;% d I! u% a% W
assign axr1 = axr0; |( N/ I3 h1 ]
% J; K3 | x& B0 F0 c/ v4 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / D# f |: m* p# I( v7 t" C6 f
static void McASPI2SConfigure(void)" T3 H7 k+ Y( U% A, t2 O
{$ t! }# K; U4 M( c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
v+ P c4 x# t, z% t; jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 |+ Z' d; M& G7 T% W! x7 j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 ^9 m% L" V+ T/ o# T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, O, I4 C" X- C" `# X, s3 dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, g4 H5 c5 T" [+ R
MCASP_RX_MODE_DMA);
0 p' w9 {0 ] d, }5 N. ?. Y% ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 L0 F, ]- e6 X4 T& N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& R" n: t2 k8 W1 ]2 s5 n4 |2 S% R' e+ t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - d! b# L9 H2 F) e; H/ \9 M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! L9 P) ~1 `# C. C- D3 @8 M* DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 h. N; q& A7 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! j f6 |7 d y! y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& I- A4 k& L5 y( r( ^7 C0 U7 AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + r' ~! |- w% N8 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& B4 b0 c; y8 ?8 S
0x00, 0xFF); /* configure the clock for transmitter */
( \* `. a9 N' K' x/ q) R9 oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# P4 ~0 ]4 O* V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & [( @9 A/ A- y K9 |+ J2 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 H( @5 q( y; x* w9 b! i4 D0x00, 0xFF);
+ r4 y; q# t R1 ^1 c6 N& S9 v _2 U2 |+ S$ p/ C* [
/* Enable synchronization of RX and TX sections */ 6 _$ M+ Y/ O) B7 D! r0 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 u8 l5 A+ U: {6 N5 z l- s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); g; u" `3 n- j# Q* g8 Y- B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: }& z# x5 G N8 f** Set the serializers, Currently only one serializer is set as
# ` s- Q( s% }4 A( e1 j** transmitter and one serializer as receiver.
9 m1 R R5 T- E*/3 A# ]. w5 K% I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# {, E: n" d% f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# U6 `* z9 J/ O/ q** Configure the McASP pins - n v0 V ]! s* @
** Input - Frame Sync, Clock and Serializer Rx* t: E+ X+ T2 s/ N$ `' n V- j* v
** Output - Serializer Tx is connected to the input of the codec
' R7 G' A7 ~0 n9 Q% \*/4 O# T1 }3 F3 c* A9 q/ z9 @9 Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% T- ~6 ~) r1 f: a N9 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# N8 Z/ L0 R: ]& ^, J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 d, `/ _$ _- W: \4 q9 r$ N2 B: _: F
| MCASP_PIN_ACLKX
; {) p G |$ e. `* v- l/ p$ B| MCASP_PIN_AHCLKX
3 j8 g, R3 L8 _$ _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) ]) \1 w, J+ h6 UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; E" ` E& }: F9 ]0 x8 R. N
| MCASP_TX_CLKFAIL
' _: ?% }- ^" s/ m+ E! i9 c| MCASP_TX_SYNCERROR
8 i3 A5 _. w4 e! m% p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) `. x7 s. J! ?% ^9 v
| MCASP_RX_CLKFAIL
0 B' O! V' @$ U; X% m0 B# |& R| MCASP_RX_SYNCERROR : R2 O8 U# U2 M% m
| MCASP_RX_OVERRUN);, Z, u: P( Q$ _1 I! s
} static void I2SDataTxRxActivate(void)
" q; x N' ^4 {6 D4 U: ?{/ J" R, E8 y+ X S6 w; d# y
/* Start the clocks */- d: o+ p6 X1 |) n9 y! n: k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ p) F( p* D" W) }; JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 G$ Q9 n$ I* R# I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 g- [1 M5 h- p: B, c5 r: Q) W3 nEDMA3_TRIG_MODE_EVENT);
# I( V$ \3 H6 s8 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, I% r( ]2 [# y+ Z% F/ T8 L* HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) }" k2 g+ d/ pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* ^$ M9 I1 I* Y4 Q* Y# l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ J3 E; d1 Y5 P! uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# c+ a$ O( P0 F" w: l0 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 U' S/ t1 ^ [2 l& ?3 T' v' t, |, E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! k* O! I) F3 b6 H7 X4 ?}
6 V; s7 z! ~/ s/ Z k, Y5 b7 N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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