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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! S/ n6 w$ ~, e' G3 L! H+ S# [
input mcasp_ahclkx,$ {+ U& D" w1 e6 m" `
input mcasp_aclkx,0 E0 K% X/ p: _5 R3 V
input axr0,
7 c" I5 a w& A+ a2 P
1 y* E' C4 K& D0 h) A* woutput mcasp_afsr,; V( d3 ?; s/ I
output mcasp_ahclkr,
i. Y. s' p) x1 Noutput mcasp_aclkr,* N/ Z3 g/ D9 |# V6 }6 j, H5 |
output axr1,( @: y' n; Z; k7 t1 R' R
assign mcasp_afsr = mcasp_afsx;9 B: z, G+ f4 i1 S/ F# e
assign mcasp_aclkr = mcasp_aclkx;0 m, c* q6 b9 P
assign mcasp_ahclkr = mcasp_ahclkx;* [$ X* ?& @0 L5 y$ R( _9 ?4 j
assign axr1 = axr0; 1 v) c* g+ u( u$ B7 a
; t3 A% K- u" F! h3 |1 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , I# z, f/ o+ R8 [- P# |. X8 r
static void McASPI2SConfigure(void)3 p# ~3 U* R6 r1 h0 y; \5 M( ?
{
6 \" W. I3 ^4 f+ e) w% HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% a2 V( r, Y/ V$ ^. sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' S. H$ n9 K- hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 W$ Q- \: Q+ }' D7 r! n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 K7 C X7 n2 b2 x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* A% V: \/ N- [$ z* Y3 W1 ?. aMCASP_RX_MODE_DMA);
4 Q5 p6 K( W! b$ z- SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: y) T" I0 n( o' M: a0 W ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 c# w2 c. X. o+ |' m/ |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% G" p* Z, S \0 h3 I( `! ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& S! U9 n; g) N6 d+ E& [: ]3 XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# y; w9 `% c/ i. P- K2 `; |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ w* }+ `% r0 B- N$ |/ b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ N3 g( i2 G3 Q* r5 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' J; @" `" C: A7 M3 I8 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# l ?: l* ]$ N) O2 e
0x00, 0xFF); /* configure the clock for transmitter */) j, ~- ?) b, l2 w; T$ a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( C& S9 r' `" A; S+ ]. c# V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 {2 M) c C m" G2 }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; @: Z2 r" m$ i. u7 a3 c/ M0x00, 0xFF);
\1 e5 i! }" @8 F# c2 q( ^
3 W% A+ R7 w( k" O+ B/* Enable synchronization of RX and TX sections */ 6 f/ ~4 M7 K6 R8 B% {( O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) x7 A8 v( n- L' J- K& Q$ U# q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% C& g+ X% W1 v7 b$ e$ N! O1 M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% h. ^% a9 R/ w; F2 m
** Set the serializers, Currently only one serializer is set as
4 |* h/ K6 ~7 K5 C" `** transmitter and one serializer as receiver.1 |" b8 l S/ r O2 d
*/
9 F" }( a6 Q3 M; }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 N+ I+ Z0 S# RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 m$ ?1 D" F, O4 A** Configure the McASP pins 0 y0 }; O0 b2 Y% T# o
** Input - Frame Sync, Clock and Serializer Rx9 K. k, D: C. Q' ?1 l) H$ P( Y% k
** Output - Serializer Tx is connected to the input of the codec 1 U8 z3 J1 ^# t9 Y
*/. v! j+ |+ V. K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 ?9 ]* I. L0 n! Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 D5 s1 c' T0 P7 `7 O( p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' s9 N" f- e; U9 m% h
| MCASP_PIN_ACLKX- a7 k% M a9 |% Z& v$ y8 V, E( ~
| MCASP_PIN_AHCLKX+ N2 v0 Z$ c7 h- f! Y6 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ z) y) C& z% Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / a7 J, I4 V$ Z! P" v0 i' N3 A* L
| MCASP_TX_CLKFAIL . x$ j" J0 A! q+ a/ U; ?
| MCASP_TX_SYNCERROR% Y- J, ~3 o" Z: x0 `- [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 K4 q. Q5 ~5 Y" r! U: D/ \| MCASP_RX_CLKFAIL/ a# [( T6 {! U; M
| MCASP_RX_SYNCERROR 6 y9 S, T! ~4 j- d2 |* q! `
| MCASP_RX_OVERRUN);
; C! s& H2 i8 {1 m, r3 e' M" S} static void I2SDataTxRxActivate(void)) a8 Z2 @& S/ N g" }
{2 K; `6 i4 d( M7 p
/* Start the clocks */
* @5 k& ^- R$ v1 {- O/ n. KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 s1 i1 x' K0 B6 ^& A! aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 M; |# V4 ~) P' P# ?7 X( D$ fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 v( P5 v% Z" f
EDMA3_TRIG_MODE_EVENT);
" u+ u2 u. `; ?+ o% bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 c# a9 R! F9 @: P2 \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" {1 U1 z0 o" y; s3 U) _9 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 g2 V! g# R, u0 u+ U4 p6 l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 r4 Q# Z. `) F7 U0 A4 }" j5 K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. t8 O: V3 I% Y7 E" K) P: l; _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& f! I' V4 h; VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& d9 Y u H' D. E}
3 h, X: Z1 p: q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. p* R) a% ?$ c7 r
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