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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, n) j, S) V1 `; s, N- D9 A
input mcasp_ahclkx,
' G0 q1 P. X0 s4 U" pinput mcasp_aclkx,) C8 A! a1 [3 }1 ?! Z
input axr0,$ X1 U3 l1 e$ S3 q6 [& A
( |: d C8 p3 C- A. q0 l# o
output mcasp_afsr,6 O, Y }+ C" r- |1 F5 r3 V
output mcasp_ahclkr,
/ q6 D' i! ^9 [' b7 Goutput mcasp_aclkr,
; q8 i( i/ ^( y1 S& l7 s- Y0 foutput axr1,( U- o* V5 |/ ?% ?& _2 n0 c* N
assign mcasp_afsr = mcasp_afsx;
- @6 F( B7 b' c: qassign mcasp_aclkr = mcasp_aclkx;$ ]' M& T3 ?" H1 y5 K+ o4 F7 b
assign mcasp_ahclkr = mcasp_ahclkx;, @8 ]3 Q5 K8 S
assign axr1 = axr0; 0 I9 F: ?# Q& s5 i
0 I% M# h( E& d- Y5 w$ G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 b& c& x+ \1 L2 @static void McASPI2SConfigure(void)
. d: i$ R2 _9 h/ Y2 P. m6 k6 a6 U" l{
3 o3 L+ T" E' L0 eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 G, u7 ^; B+ H: W, _/ O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 W+ R! a# ]/ U4 R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& ~% H/ A6 m( P7 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 v; A" u+ w( b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 @' ^ Y: G, h& q# S) j
MCASP_RX_MODE_DMA);
* S+ I' [; a7 W x! zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 N! [* v7 }6 n# }# }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. y- [2 }# w& E* qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 A% |& q0 L9 d$ o' d8 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# `* p c0 y/ Q7 d" a5 ?) dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 S3 x6 M- d) E, [& a; b# \! AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ G$ R% V/ U: i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ b4 I' ^" t& W& X1 DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . S4 @# |9 A" _# F+ [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) l% D: W! W j/ l" Z0x00, 0xFF); /* configure the clock for transmitter */% G0 B, C# S) ?1 f( y3 K/ V' d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ V! \5 s' o" W# l+ a+ q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' u. t' M) C7 P7 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: D3 n6 y' _+ Z8 P q7 ^
0x00, 0xFF);- v/ W9 k5 a }) U+ L( V4 v: x
; S2 H# P9 m: @: V- f, p/* Enable synchronization of RX and TX sections */
! L6 m2 ]' }3 {- C6 j& H4 PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 z+ M( s7 I. k Z# ?( [ sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 r+ q+ |5 B- t( x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) w4 |4 i( R8 n; L8 w3 k! t5 ~+ X- v** Set the serializers, Currently only one serializer is set as% s3 x- L Q$ y4 E
** transmitter and one serializer as receiver.
; ?7 C, F! d Y: ^; `" d*/
5 M4 {% V9 h7 c: h, {. KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 ~9 |2 i: r6 s0 n, F7 r F% a' g1 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 c# x9 I/ y5 @** Configure the McASP pins ; z+ a- J/ J( S! ]9 K
** Input - Frame Sync, Clock and Serializer Rx
9 c6 q* w% v+ b4 G/ K/ Z** Output - Serializer Tx is connected to the input of the codec
& Z# i# ~: V, \- E. U+ c1 A7 S*/
3 W3 l( p G7 C7 p- p/ `1 yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 |2 q" V% Q# O* I2 {4 z2 i1 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% v$ g. d% U! ~5 c( y) [7 v* D$ kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
M: c' i, L& ~" H; \| MCASP_PIN_ACLKX/ M& f7 M3 G+ I0 D
| MCASP_PIN_AHCLKX- A$ \. z7 x8 V$ \& ~8 B# ]& {' V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" s+ ^ T4 Z- n% o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# c1 N6 D/ P8 \$ G. G' b2 @| MCASP_TX_CLKFAIL
7 `5 s8 d: ?5 v; Q| MCASP_TX_SYNCERROR
# O( |1 {7 ^+ ?0 y: o7 J1 g& `7 K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& ]! B9 h% k+ c2 j; S6 H/ G/ q| MCASP_RX_CLKFAIL
! Y5 Y, V' n$ q# `* P4 L b& y. A0 ~| MCASP_RX_SYNCERROR 0 E/ W& I& g0 t* ?/ A
| MCASP_RX_OVERRUN);! v: B& y9 b$ m8 @+ w
} static void I2SDataTxRxActivate(void)
7 F, B" W5 x# I: s0 I{
R" J/ M0 L4 n6 i/ `- y+ n% M+ }/* Start the clocks */) K+ C9 n( U( I- U; u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 {& \6 U5 b, b' M( TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 z! p' X+ n8 d# H8 e- GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 B0 I* g" Z- S& n# f# F, e
EDMA3_TRIG_MODE_EVENT);
- B: T3 P! V [2 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* ~- t& X9 N1 ^1 O. E4 |) AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# x: z: l* W4 m, j) V- l6 I! c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 Z2 ]+ A0 D- }2 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% g5 D6 V" h$ n+ L" W2 ]; U$ ]5 Q7 Z5 l' n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
O6 \! F& u% ~' C1 O KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 O* @# `5 g2 u( PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 B2 B& v' s% r, z1 }} 8 e* F9 O' O. X% [9 s g1 M, _2 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / T: Y# j8 g% O- ^9 Z
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