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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 ?+ e N/ Z2 F/ V) B7 d. v# g
input mcasp_ahclkx," h3 Y/ @0 u0 ?9 S( s& z9 ~
input mcasp_aclkx,, i8 _8 F+ s6 A
input axr0,
% ]7 n5 p1 }6 y I; Z/ {1 \, v6 {' q5 N
output mcasp_afsr,
5 N7 I' ? `" O2 ]- X! aoutput mcasp_ahclkr,
# }' g2 @. b+ F, {output mcasp_aclkr,/ N4 I0 I0 y- P+ ?( \$ Z, M" M0 C
output axr1,
- l5 O8 S8 Q! Y& @" X: O assign mcasp_afsr = mcasp_afsx;6 D; O" T, O E4 L: d
assign mcasp_aclkr = mcasp_aclkx;- X4 u2 ?. V. x; y% O) b/ v; t5 X
assign mcasp_ahclkr = mcasp_ahclkx;
. b4 W% G0 g* ], o6 rassign axr1 = axr0;
0 [3 r, A) r; c7 d7 ?' Z4 N2 j
7 t5 C* w! _! B7 k O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 ?; ~- u. |: h; n7 ~/ T# M0 ?( b8 kstatic void McASPI2SConfigure(void)
* E9 P# f* L p. M6 F' Z1 h% r/ x: _{. c# d- ]. |+ N* M& U
McASPRxReset(SOC_MCASP_0_CTRL_REGS); u# R' B# L) X+ P3 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 s7 A0 g2 H8 m9 q& S. B7 @; [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& x q5 D0 _# A) z0 ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 |6 X" G' Y1 VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 |. a( y' E6 `2 ^1 X O |
MCASP_RX_MODE_DMA);3 d" }& ]/ t5 y# S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' z1 w c) z* s4 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 t9 l5 p1 ~- C% O) q4 s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 Q+ T& [' G0 v; f5 K* ~: R' mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% g+ R& B# b1 q6 D* LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / s0 m8 {# i7 N% a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 ~: I9 U. P& ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ C3 s' b" Q& y9 |5 O+ QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* Z- k; ]! o4 t% E4 X" |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% N, h. |. ~' @7 ?0x00, 0xFF); /* configure the clock for transmitter */
% E5 R% e3 _6 b9 aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 G+ _9 W8 e8 | D: v' A! W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' Q" X. D' ^; B7 C' ` wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' p2 S+ N9 ^9 ] \0x00, 0xFF);4 f' k2 x5 e. ^' |1 [, v
, C% B% c( L* ?+ i [/ f4 L/* Enable synchronization of RX and TX sections */
% k$ b7 K4 O; pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 b' ]1 x$ E& A1 N0 @( J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. g7 `+ O" m$ Y( ~* B' g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 w9 R7 H; M# \** Set the serializers, Currently only one serializer is set as
3 B! X1 J9 G+ p3 ~0 U1 ]** transmitter and one serializer as receiver.
7 l, s A/ S% ^4 S* ~*/
' p/ x* G; W1 F" v, \( p& o7 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 y y2 P2 S' h! zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* ?. q% R1 I9 C4 }: V# }
** Configure the McASP pins
$ Y- J1 k$ G' F u** Input - Frame Sync, Clock and Serializer Rx8 \' Z: F+ u9 N% S- R
** Output - Serializer Tx is connected to the input of the codec % a* V, e, w! M: _( }
*/+ X8 p6 \/ ?8 }. ?; @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 u, r! f' i; x3 XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 p, E6 a- V+ N/ dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 y8 U9 ~, f# L& O+ m! b| MCASP_PIN_ACLKX
* ?; a; Y( r9 O6 u| MCASP_PIN_AHCLKX% y) b5 H/ x; m$ o4 q5 J- n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ D! w' X# W/ U8 \8 X* c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 b! |" y, j: C4 C/ F
| MCASP_TX_CLKFAIL $ m6 b: s9 F( U
| MCASP_TX_SYNCERROR
# g7 p. i) Y# W& y! ]3 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* n4 M% \) G) l- x+ I( z1 L0 e| MCASP_RX_CLKFAIL
* o: A: T% i4 @* g+ ~, Q/ W| MCASP_RX_SYNCERROR
2 F7 a2 K' s8 ~% Q| MCASP_RX_OVERRUN);) Y1 m t# J$ }9 z1 c
} static void I2SDataTxRxActivate(void)
" E& k) ~7 ~% c2 Q( t3 a! c{
. X# n) y1 s4 `, [ |5 G/* Start the clocks */
( G. i0 h0 Q7 s$ M$ D) `2 D @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; l: I3 R* r. ~/ B- V" K4 F7 I% F& H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; o$ L7 c: z4 `; r, @( b, @( a" g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. w, \8 p% W" C- ?- W% V0 X/ D# L
EDMA3_TRIG_MODE_EVENT);( m8 t4 z6 o% Z- ^* d- _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 a3 j" [+ r- b0 r+ _( VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" X. v# T+ Q$ e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- U2 W/ t7 B S0 M1 _! V+ ^- IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' d7 w" L. S/ G" t6 v U Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 T# I* E) x6 Z2 {$ h% i9 zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* ?' M9 Q# }# h2 y# ^" [6 P- W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ d* O) l0 K8 V. T! I# s8 r* ?
} 9 L+ o, a0 Y4 d; u, V1 w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * B& J( X' J8 n8 t4 T
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