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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 | {' I4 t" zinput mcasp_ahclkx,
* e1 {# ]6 ~% b; G8 s- b2 }/ e* vinput mcasp_aclkx,7 L: h9 W* D1 Q- k5 B
input axr0,
% v" a+ Q* k7 V( L' r( l; d" A M( x- a$ w1 C3 m
output mcasp_afsr,
9 i$ r. b: ?" c$ ~output mcasp_ahclkr,5 e2 h8 t' n( h( q$ T* \
output mcasp_aclkr,
% X, S" \) D6 b( loutput axr1,
% A9 _8 q# \# N7 Z8 R assign mcasp_afsr = mcasp_afsx;% Q, B2 j& a0 r
assign mcasp_aclkr = mcasp_aclkx;% S( P" }5 H- U% _5 {0 C0 e+ }
assign mcasp_ahclkr = mcasp_ahclkx;
# l/ u( U& \: hassign axr1 = axr0; 2 M3 Y: _0 r# h4 I- N/ s. L4 g. U
' e& V* D, F- `* r) z# f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) X7 F6 F+ Z9 j" t6 nstatic void McASPI2SConfigure(void)
@1 d7 b3 D( i2 f. s{* f, f# H4 ]0 Z6 K6 G* N$ R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 g8 B* x C( vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. y' M0 c& j3 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; N$ C* ^5 D5 b8 }+ h# X) s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 [! S0 ~9 Q9 P8 i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 G2 y: i6 ^ n; p
MCASP_RX_MODE_DMA);; A& ^% d' J( {4 Q0 y% @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ S j# w1 j( Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( h! V/ W' g7 s4 p3 GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; k/ H/ Z$ _4 U! x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& m k3 K: Q! V# E2 ^# aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" A* s9 d- M, t+ zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( t1 y" |# [$ A; rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 ?$ y y: B( p. s0 s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & K* K0 k' |$ O6 n# s) m/ V7 K3 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 x0 `" e4 f' {+ O' @ v( g7 E
0x00, 0xFF); /* configure the clock for transmitter */& F, d3 c, L3 S O# z5 T; Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); u- `# M6 W+ F7 i7 ~- N5 o/ p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 V; {1 m9 `( C# s7 j3 u' s- y+ q: NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; a1 }4 j8 y7 C# r6 D0x00, 0xFF);8 k! L! C: q! |: O2 K! _9 _1 }$ t
- P' p) P* x/ E) f7 Y/* Enable synchronization of RX and TX sections */ & p' Q8 n9 i& A8 C* L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 y$ e: ?4 Y W6 k2 nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 z" y; X9 _2 U% z9 L: pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 i$ d6 ?: b( ^
** Set the serializers, Currently only one serializer is set as
" x: e7 X- T& J: C( G- d: v. h** transmitter and one serializer as receiver.
! r; m& _3 q s; E+ W*/
+ P+ q5 C! ?# X. ^+ T# SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( ] F% ^+ m0 W- T5 C0 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 ], ?* s3 m3 v/ x** Configure the McASP pins
! V! E5 H4 \8 X** Input - Frame Sync, Clock and Serializer Rx. `' Q& V" q) ~% M" @1 V( J
** Output - Serializer Tx is connected to the input of the codec & d+ r7 ^" Y0 y( A
*/, Q' r+ W0 z% L: |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 Q' ?5 d3 l" Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 T4 v' C: u7 A5 ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ _6 p- [ |$ w) d; _+ s
| MCASP_PIN_ACLKX
5 i1 ~8 S5 _, k# J| MCASP_PIN_AHCLKX1 X, r" L* {! N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 {& P5 j. |& @3 C k' d+ P* O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 i5 g) {) _5 E( q9 O6 X3 [| MCASP_TX_CLKFAIL
5 {) c, _3 D" T: t. Z; F: Y: g| MCASP_TX_SYNCERROR
' B' H$ v8 `5 z4 |0 a% F* O$ u( h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 g2 G! W h) V: Y( r| MCASP_RX_CLKFAIL
. f! s1 d$ z# U% E" K| MCASP_RX_SYNCERROR
- s1 Y3 G, T6 j' P, X| MCASP_RX_OVERRUN);
8 ~- c, e8 q6 r} static void I2SDataTxRxActivate(void): W* ~" ]3 a7 I7 C0 I! ]4 ]
{# E. d1 h: i7 ?. P1 [; y7 l' p1 N
/* Start the clocks */
% c7 A8 A: x" P* g* qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ U* @) Y0 @: i& n/ n2 fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' C5 n) r/ ?- H/ H$ P) ~6 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ j8 m2 s( L4 [' r; ?/ f, zEDMA3_TRIG_MODE_EVENT);% \6 S4 T$ f; Q* r$ K) B" K; Y. n0 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - k" @. y( u$ o1 y; ~" W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) J8 S6 w( a$ Z+ Y. O1 u7 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, V& E! [' ~8 K/ Y$ _- [! s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ U0 ]9 d; S2 vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% | o: w- l7 R0 f- _+ C% zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 g, ^3 l! G& R WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ B6 z0 w1 R5 D5 V! Z+ G} 2 n' G/ C0 Y/ u4 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + p& I z# y' w9 X ], w" S. y
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