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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ x8 t# w% V0 `$ k
input mcasp_ahclkx,/ ~6 Y5 ]7 n& X
input mcasp_aclkx,) T( K5 i1 s5 D
input axr0,
4 z8 r! \6 C; q, `" d3 P k& D& g2 e
output mcasp_afsr,+ c, f. c' k$ s
output mcasp_ahclkr,
3 X2 P+ }0 a, t/ d0 u6 c) doutput mcasp_aclkr,. M& Q: @8 W9 y9 t# h* V
output axr1,. J5 d; b& G, P! Z
assign mcasp_afsr = mcasp_afsx;! O2 g2 w0 M& y; Z# X: }
assign mcasp_aclkr = mcasp_aclkx;3 f9 H. d/ l0 i& L
assign mcasp_ahclkr = mcasp_ahclkx;7 z! M3 d9 o/ t1 S# e' ^
assign axr1 = axr0; 2 C9 W8 u @9 L7 z
) ~9 y3 O0 g4 ~* S+ i6 d$ F% r3 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, t; c5 e) Z5 R* r: W1 }5 Tstatic void McASPI2SConfigure(void)
9 [# s% m. t* q) t6 h2 z{
. N$ N8 Z- v1 U$ a3 y7 I. NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 H: e) S, k7 K2 Y% B- O4 PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 F7 C) ~9 u6 z' B5 V- o: p$ Z5 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ ~. l$ m2 m3 q7 Y O) _ M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 i/ H+ m( B& [% N! O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 ^% h6 u9 ?% _3 e4 s% I5 G
MCASP_RX_MODE_DMA);' ~; @% X# E+ @! j* q1 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 N. z" ^) h* S- _2 h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, Y$ g; \5 q, H, o/ X9 f wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: p, J; ?: y: G' K0 ~0 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 I2 h5 P5 {6 t/ O% IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * @/ J! D' c d8 y0 B5 u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 i y( k$ r2 _; pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& P; o2 @; [* B# U3 D4 x, L; MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, J# f A; l% ~3 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& `8 G0 [8 M9 [0 M' `; N+ k" {$ G' P9 H
0x00, 0xFF); /* configure the clock for transmitter */
9 Z/ r0 X, |) M- W! pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' `5 s/ e7 A) j4 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 S& X( k2 r! B' U# }, I$ T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 s6 Y, [. `2 k1 f+ j' K
0x00, 0xFF);9 t* D, c, z5 O
2 r( g( q1 a+ l8 q& D+ Q
/* Enable synchronization of RX and TX sections */ % P1 d/ Y0 U8 x# M) H! v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 Q# [- n, ^9 L) x! jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 ?2 {7 R! H+ L. sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
B. A0 i" Z6 P1 h e** Set the serializers, Currently only one serializer is set as1 K8 m* N- }: c4 L/ ]7 E R7 W# T" u
** transmitter and one serializer as receiver.
' d8 g/ m( G- J4 e6 O/ E7 e+ r*/
4 C1 g# F- y. u- jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* m# e9 p& B7 V0 V* s1 c: h' D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 D$ p5 \1 \. k# ?2 l1 ^** Configure the McASP pins
& c* b+ s2 W/ q** Input - Frame Sync, Clock and Serializer Rx
3 z- m7 t# u: N: z: u+ ]5 \/ _" P** Output - Serializer Tx is connected to the input of the codec
$ M1 Q% d& u8 b; B4 v5 P# }*/
$ D' b* A% r3 H. E+ d( pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 C: d* A+ k7 z0 Y# S0 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 i8 Z5 |7 _3 w* t( |1 Q$ f m1 Q( p& _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 u3 K# S+ f: w, L4 s( A$ k$ X| MCASP_PIN_ACLKX
% u$ w; b5 \) V2 H/ O3 f| MCASP_PIN_AHCLKX
7 @+ X3 j4 A+ u2 _# j" R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# |/ @/ H9 d) A: q" z2 R% @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: l5 x! D" B- || MCASP_TX_CLKFAIL * M" p7 j, F) E% b
| MCASP_TX_SYNCERROR
1 A) Y z5 O ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 D# C# w- O9 V0 c1 ]% _
| MCASP_RX_CLKFAIL' V+ a9 a' N `
| MCASP_RX_SYNCERROR $ J7 z8 D; b# L
| MCASP_RX_OVERRUN);
' H! D; D. d: u( A, w* G} static void I2SDataTxRxActivate(void)
! [- Z: V$ Q! _{
6 L# F) g. R; l) b* R/* Start the clocks */" t' @( W3 W4 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ g( }$ p+ {. N0 I' y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( ?" o5 V. H9 T9 Q) \+ j) p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ N8 E1 }# r% Z) q6 m/ AEDMA3_TRIG_MODE_EVENT);
, x. E6 [1 a4 _, ?: JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 [* R r ?, m3 p7 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 V V4 m, z8 h( ?( sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 C4 l& o5 G2 i( o1 a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, _' q" {' o7 o# q4 z9 l& Y+ |2 N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ ]+ ~4 _* p% s- w4 Y" V4 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ W( O. `8 c; T: m1 f8 yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 U! K' I% |2 y4 R9 [& j
}
5 Z2 m0 f* Y& E9 M `* _0 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * O7 R( m3 J8 X3 a4 ~- ?: y0 }
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