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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! F. U0 Y8 N; b: { q/ i! ninput mcasp_ahclkx,
# P, R) Q4 K% Yinput mcasp_aclkx,( o) Z' S( m: y4 n* U$ c
input axr0,
& u9 p' t8 U- \$ ]; T x# B6 x4 ^
output mcasp_afsr,
7 N5 s% Q# }* houtput mcasp_ahclkr,
, z) \7 N8 Q( l4 s; Q; S9 Q7 f7 b& ^output mcasp_aclkr,- o1 i. S' R' O
output axr1,
( J2 }: }# y! `. _, I i assign mcasp_afsr = mcasp_afsx;5 F3 |- \# J3 z+ e
assign mcasp_aclkr = mcasp_aclkx;
( s; y5 E0 {6 y, gassign mcasp_ahclkr = mcasp_ahclkx;% z$ b' _9 U7 A1 i, d t; R9 j
assign axr1 = axr0; 3 O9 n7 c7 j6 M
4 C9 W! i9 x4 q3 i. w ^4 i+ b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 U u% c9 z7 Y& vstatic void McASPI2SConfigure(void)
9 T0 k+ p1 a1 ]3 E2 X# `5 p8 r Y" e+ ]{( w# n5 l0 _4 ^2 n0 Q( C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# g: P ~/ z+ g; j) N: w' o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% y# L, G/ ?. x8 \3 T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; u, l) E# s6 P! z( S3 |8 T8 x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! O+ m+ t# P, J- _6 ~7 i$ oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 V: n/ C" ^& S3 {
MCASP_RX_MODE_DMA);
w5 _& b! i4 E; a" f! iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 }3 `* u8 |* \* ?: _) }; i8 p+ nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- P6 j; F! f+ ~, @7 n! zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( N, [9 `9 _" _+ P+ m* Q3 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: y, r+ n# S' ?# p7 x0 O- oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , V, V$ y) Z) Q+ t- S+ _$ P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, d1 O7 s# z0 G" h* @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); w6 F! Z5 N6 p. \) |" D$ V. h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# b/ m% e' @+ k3 ]0 H' f4 fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 F7 ^- D( M- {3 u7 W& V& x0x00, 0xFF); /* configure the clock for transmitter */& o5 O# s# t; p7 K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& ~8 g( t# d4 d+ d4 @& D( |# IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) I V d8 ?3 g$ X$ e9 z' _; ^7 f' j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% J8 {8 h ]" l+ P9 z& L, V
0x00, 0xFF);
: z; \. M0 Q7 t: |" k8 b: Q/ F, W# p" x3 F, y6 h' f# I' p
/* Enable synchronization of RX and TX sections */
0 M( [0 ^. q$ V2 O) E$ `1 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' q8 W" P G* E& |4 g' U8 TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 Q2 ^; I9 S, g! `7 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; d. N- Y6 k2 g3 \8 N** Set the serializers, Currently only one serializer is set as
5 h# _7 c* d% r1 Z0 u** transmitter and one serializer as receiver.
; k+ {: z/ B; i( B( T*/* J8 x: Y9 d9 r$ ~+ x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" @9 ^0 t8 f9 G& y- I- |1 t/ `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) h" `+ G! x2 k& a) T** Configure the McASP pins
3 Q: p, T& l/ [; f4 M D** Input - Frame Sync, Clock and Serializer Rx' _5 k8 n+ b9 x4 E/ |$ b* w
** Output - Serializer Tx is connected to the input of the codec
+ I$ j/ w1 ]/ g9 i9 i& ? l2 w3 \*/! ^$ q% \& {( v+ C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 k: v; O0 @9 C1 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 }$ R! K! R3 @8 j& G. |& d. {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: ^' {7 h8 U" o+ [2 M$ l- c2 s| MCASP_PIN_ACLKX
3 f% u3 @: F% A y| MCASP_PIN_AHCLKX5 W# _% @, i H; s3 N6 Z' p, O$ a3 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ d; t' I4 Z$ b- gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : K D2 _$ V$ d' t
| MCASP_TX_CLKFAIL 2 V" L% _) ]4 f7 ?9 X2 ]
| MCASP_TX_SYNCERROR ?* E1 v3 O+ H* V; s7 \0 ?6 s/ }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - T' I" y2 Y/ [6 p& x, r6 B
| MCASP_RX_CLKFAIL
F, e3 s" Q1 b. l% ?| MCASP_RX_SYNCERROR ( a& r9 r2 v) l
| MCASP_RX_OVERRUN);
8 Z$ q( E) [) b( i7 `& l2 e} static void I2SDataTxRxActivate(void)
5 ^( [$ \/ G2 Z c4 {{# s1 i2 F4 U8 E. |( c
/* Start the clocks */
/ G2 a: v4 K+ s$ S7 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 y5 h( P" z2 j; H, ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ n% u; h( f. E9 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 `* B0 e9 y Q) \7 V& E" l
EDMA3_TRIG_MODE_EVENT);1 z) T5 k" s0 |6 r" R! S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : R3 a7 H$ ?3 Z- I4 J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 A0 W& g! J) t1 s; S4 c" dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ ~& V/ d; \5 a4 p' s4 a# A4 ?7 \1 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ n M* ] i( d1 q- A; c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& `9 I" k% o( w5 [0 w5 }: cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, }1 v; K1 J6 g9 C! O2 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 i' c9 j* ~% Q* x1 W2 c
}
4 X* G7 d! z! r6 `: [0 U" R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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