MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
& ^. D: |- V/ j. j8 z- x6 Linput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
  z9 d! |& x+ A& M- }
' L9 _7 Y$ q$ H$ {output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
  j- e; ^/ S9 T3 Ooutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
! }8 N; M% L! C8 o5 L5 P  q! P5 }assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
8 k8 i: ]6 }5 i0 M/ B) w4 G{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" h7 i; g8 X8 g: G* n1 B& NMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
" [+ z, g, ]. Z, i$ B" g1 GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% B5 Z% r2 v. }; c6 y* J+ W' IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 U4 ~) ?/ a3 |$ |5 u1 TMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 W' f, s1 M/ J. m; xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 P- Z9 O2 v8 v7 s1 q. _4 @" ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ R, u6 F9 k% i0 S  f, P8 N; u$ ~0 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
' t9 O6 u: j" OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! D) j" D% F2 c& Q7 ?5 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# d4 l: [1 r) \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
: y. k9 G! f/ t( n. g; ~) \# t" ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
: T: N0 M% r' E/ L$ Q9 V8 t7 r- [
- u" ?) U5 K; L: ]/ s5 b& Q' j/* Enable synchronization of RX and TX sections */
1 H& ~6 R4 h/ ?6 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ C; I( t1 S# O' R9 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
6 u1 b1 G9 r( e' k0 M** Set the serializers, Currently only one serializer is set as
8 U" U: f" J3 K# c** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 M! }; i& f3 Y9 a. U; m. _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
( z0 J( F  ^9 i% y: e3 K* z** Configure the McASP pins
' N; G; Y+ q! I' a0 o- Y5 ^** Input - Frame Sync, Clock and Serializer Rx
) L, [( j. C9 N; H# f** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 f8 i# C  a" F6 ]% kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ J6 Q. f; a( P0 r; @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
4 `0 `: W8 x: G5 a| MCASP_PIN_AHCLKX
1 K& s* o: o5 w+ M| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) _5 R+ g5 R  p& }( f% A" ~7 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 J# i" g/ i- k  ^| MCASP_TX_CLKFAIL
9 v9 O' J: q  X+ I# k| MCASP_TX_SYNCERROR
3 j. W) m0 j, F| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 ~% A% K8 E0 @& G1 [| MCASP_RX_CLKFAIL
5 ]5 k) P( e/ h( G% C5 ~| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
8 ]5 }3 y. t/ YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# ]. r! e* c* p, _4 V7 ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
# S  H. _, b8 n/ ?: c" AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- F7 V  ?8 ?. R+ r9 s% _: c- DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

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