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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 w) z4 T/ H3 L- Q0 K) pinput mcasp_ahclkx,
. O/ J/ n# l0 W) S/ Rinput mcasp_aclkx,+ G" D; r0 ]- W
input axr0,
: b, S2 r* _% p1 C$ z! J6 b
" c5 b% Y- n$ _$ A& E! Poutput mcasp_afsr,
5 }1 W# w' g/ k/ u; |+ [; | K& koutput mcasp_ahclkr,6 g. ~9 u6 J0 W
output mcasp_aclkr,
% [* r0 O7 f" G" w p; v( R6 xoutput axr1,
8 W" Y0 k) L+ h1 v+ L* w* W assign mcasp_afsr = mcasp_afsx;
5 D R+ m% i- n1 Bassign mcasp_aclkr = mcasp_aclkx;
5 u* V4 P( v$ i' n7 b: U5 Jassign mcasp_ahclkr = mcasp_ahclkx;
% q9 K) K* U" G6 n: p/ }; q" e" p/ f" Nassign axr1 = axr0;
1 U4 y& t5 K5 K" o7 Z0 @: Q' v
" H( K; v+ k0 ^# k( ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! ~1 Z( M+ A5 f) e# d' O7 Bstatic void McASPI2SConfigure(void)
; E# e H' Z- w{: \+ m5 }5 ]: j/ }# p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: G2 o" v# g& G+ }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ M o) S. X: K) R& f ~1 U; ` l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, E" Q3 Q$ h) i5 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: v/ V/ b1 ?1 F4 [# p( XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! a8 l: l! [! _% Q. Y1 ZMCASP_RX_MODE_DMA);
( ]6 _/ U' r1 [8 s2 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! w. i9 y9 w7 D' x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# }3 o* {% B# D9 K7 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : d. V8 b; t# j$ s6 L. _. r1 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! f9 G/ z% a5 F2 v* F* HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" j {. h8 I% @5 p9 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// H" Q- W9 O8 y: o: _& I7 T0 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 j; r7 K7 d6 R T( @$ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - d% M6 y' |8 J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# b3 D& F1 c- I2 J: N# O! _9 U* V0x00, 0xFF); /* configure the clock for transmitter */$ s6 ~! Q3 P/ a$ ^4 `0 C3 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- l: f/ S# H ^1 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' x& r( r) {2 W- u( N# ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- U! r. m* @/ h/ e& n
0x00, 0xFF);
% r1 K' `& k7 N7 ?, L& C' O+ q1 p+ W4 ~
/* Enable synchronization of RX and TX sections */ & k7 D% ?; ?" J! _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 K6 `" A% f% X* a, Q" Y8 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 h, A, q6 A1 [% v, wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# ^' ~9 q" [, o6 s' [** Set the serializers, Currently only one serializer is set as
0 D) M, j1 d6 `0 u# ~, a2 Q' A** transmitter and one serializer as receiver.- n+ ]/ J# m% U/ C% M
*/
2 v- p( W5 A7 n% v) \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: h% P3 h6 Q. w7 @+ _# ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ t% U, W0 R- J0 W* o( n" c
** Configure the McASP pins
; O+ [: H% z7 @** Input - Frame Sync, Clock and Serializer Rx
4 a" ?3 v" N: w1 v, O- Z: F** Output - Serializer Tx is connected to the input of the codec
, h+ }8 K/ P0 L' j; D*/
: e3 y4 u1 T$ r( }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- w* U' r. W% DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! Z; P1 z# Z' D+ ?% w, l$ |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, y# t1 n- Y( Q4 T8 M| MCASP_PIN_ACLKX
' }& {) X+ T. V \1 P| MCASP_PIN_AHCLKX
% ~$ w3 e! T( _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 o1 \( `, K) ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 y$ ?2 [' k/ X6 U9 L, j| MCASP_TX_CLKFAIL 6 ^4 y( G, W" X, U% `- j+ ]
| MCASP_TX_SYNCERROR
3 _' {" [& X) ^3 Y5 Y2 W5 f, g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, `" d7 D, M+ A+ m7 H4 g, _& D+ A| MCASP_RX_CLKFAIL
6 p$ b* T( Y( [$ }8 R4 O& f| MCASP_RX_SYNCERROR I9 f2 d9 \3 G1 e7 y6 {8 q
| MCASP_RX_OVERRUN);! R1 J3 `0 Q4 B$ K/ ^4 y2 q
} static void I2SDataTxRxActivate(void)
' d4 D) K6 ]+ L7 C+ e E2 p{8 t) ~2 l5 l% s" [& F# x# E
/* Start the clocks */: |2 p" ~3 h8 G' m( d1 F, I( s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. I! M0 a$ f5 N& }. a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 i. C( ]+ |. p% _, D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) z9 k/ d P5 _ ^8 c2 b$ B3 JEDMA3_TRIG_MODE_EVENT);
" @& T) [8 L" C" }7 Q6 e7 Y$ I0 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 {" m4 k# @: W- V4 R' DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: r; P& @$ @* L q2 C0 ~! b' l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( u$ \' y! g3 kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' c# l5 Z( w& t" `$ U9 y9 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% t2 @2 G0 ]) n8 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 U& B: S% v: |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# ~, [( ^1 x1 r
} : {+ R" ?3 {# v% e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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