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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 X3 D! G! d+ ^% d( Z% q2 e6 t; p. Linput mcasp_ahclkx,
. B+ b- {0 t( {+ W5 Z0 {input mcasp_aclkx,
8 x, h8 n# M. q: A' ninput axr0,! R* ^4 r/ {9 Y, ]* q
4 _7 Y; t4 W; b' z3 D
output mcasp_afsr,( n6 d: M0 A D! }: g
output mcasp_ahclkr,
, l4 w! Y- ]9 ?4 R' ?" Y" Goutput mcasp_aclkr,/ b" c, S' o7 b9 `
output axr1,
* ]9 a( `* D" Y+ }# \ assign mcasp_afsr = mcasp_afsx;) I" P& d# E& }
assign mcasp_aclkr = mcasp_aclkx; s/ f" z7 k4 \# z5 t
assign mcasp_ahclkr = mcasp_ahclkx;
% }! A' C7 z, j4 g+ j4 Uassign axr1 = axr0; . a. q% S0 B& W& `' E4 t: j( C
, h) m' X2 Z ?. X7 q# Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 n1 O5 ]( ^4 _# f: Z R* e+ Xstatic void McASPI2SConfigure(void)3 r5 V N" T! z9 S
{
# q2 G3 W3 u7 I q3 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# K8 W: s: i& d( k2 [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! g) {8 M0 T0 U0 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- p- ~3 [ ^* L) h. e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( _, a: e5 V8 f$ C% q5 _, ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! W9 ]5 B/ z) S: J0 w! h# @MCASP_RX_MODE_DMA);
$ D; f- L# d+ W- ^5 ]8 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% R: m! w- }) {" k; n* {! I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 }/ w; {5 K1 U: w/ w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . x3 J& h" Q. T9 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 ?' Z8 U$ Y( eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - v1 \6 Z7 Y3 w; ] I5 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' c1 v, Y# O! |+ [1 b7 JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. C( j1 p. a1 \* } w# H$ GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 {& w3 s3 ]6 O3 Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ J" e W. g" q6 W1 x" [
0x00, 0xFF); /* configure the clock for transmitter */
4 E: o( ?% t) [' { y$ \, WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* u( M: L3 M u, v3 Q9 ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 {& h4 G1 D" q. T2 L; k3 ]* nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* R: |. |+ d" A7 U& b0x00, 0xFF);) ?6 E2 K* P0 g/ C. U4 C
# u( H+ O1 { ~( X1 G- s+ y2 m/* Enable synchronization of RX and TX sections */
# ?; ^4 I) Y* O( HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# I0 U! P2 s. T" S3 G7 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. f* |" N1 N2 h$ Q3 r9 w/ A, nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: O" l0 {7 } K1 J5 V
** Set the serializers, Currently only one serializer is set as) M- P* }5 Y# g' D+ C, y7 A
** transmitter and one serializer as receiver.6 s' |: `, O* F* I5 R; H
*/
( n* M5 i- R* B% g: a/ c3 BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 H( |" E8 F$ L- _9 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% B1 d, f1 K6 R+ }. i8 B4 b% P** Configure the McASP pins
2 _+ s- Q' ^% L5 U& [** Input - Frame Sync, Clock and Serializer Rx4 ]1 Y' D+ j B7 q
** Output - Serializer Tx is connected to the input of the codec
5 o: ~3 L. F6 U' M*/
- @: W, d+ a2 b; k1 ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 w; J% @. A- S- }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! {5 U. [& K. k3 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) A% Z! h+ i y" k+ N# i0 s4 B| MCASP_PIN_ACLKX
! j/ W# t4 O" V9 E" B: ]# b, d7 \7 h| MCASP_PIN_AHCLKX6 D' i3 [: H' \4 h- P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" [3 C* m/ k* Q2 {& J; Q$ \/ BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * a' B1 g! ~, _# O# w
| MCASP_TX_CLKFAIL 7 ~) a+ _8 ^7 J# l( M
| MCASP_TX_SYNCERROR
+ J1 O4 ^1 Q. k% }6 n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ V" W5 [% h; ?/ O( i$ g6 I" ^
| MCASP_RX_CLKFAIL# N0 G# x8 m# |7 B
| MCASP_RX_SYNCERROR
2 _3 R5 X/ n% r; {6 v# K5 h| MCASP_RX_OVERRUN);- E) b4 k4 o2 O: K7 r& u) N
} static void I2SDataTxRxActivate(void)
1 U4 v5 ?3 i9 T1 H. @{8 Q# L( K4 O: L. U
/* Start the clocks */# w( ~, a8 k2 y' G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ |* d( M. [' A7 n9 V; c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* E$ G0 q6 v1 D% L9 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 ^2 }- f& d: p& B( u5 ]# r; S0 p ^EDMA3_TRIG_MODE_EVENT);
! B( f; D; I( `. ~6 i- ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 |) w) j8 K$ O; n2 I9 M8 B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& W r, f( A- s/ ~+ Q- KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; D& l7 \7 U6 @& X o3 l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* q1 S* O. H7 L) R% a3 f! G$ W0 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 s4 s" n) w7 m6 c9 JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ m$ i4 l6 C9 m! O( BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 C8 Q: l# ^9 _' ?: B
} / D0 E8 C5 o# F, n2 G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 n! A* U6 ]5 f0 D& X. p5 h
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