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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) X/ {8 b3 r( F# P
input mcasp_ahclkx,
+ p5 ]; U& E' ]9 {- W7 Y. zinput mcasp_aclkx,
6 y- |" X* V" O) i; ^) oinput axr0,
m9 O/ K8 i/ L: R9 f5 q% Q& j' A
) K, [0 L e) h- |) ?* e/ Goutput mcasp_afsr,0 c" F5 K2 S, W
output mcasp_ahclkr,6 W5 |$ d+ A& m1 H) @
output mcasp_aclkr,3 r2 h( J. k' g8 d9 I% {
output axr1,3 \7 z3 x; X# C4 h
assign mcasp_afsr = mcasp_afsx;
1 g: N2 Q0 R9 d5 I# K1 vassign mcasp_aclkr = mcasp_aclkx;% b0 G0 I- P4 g2 ]$ {" X0 M! s
assign mcasp_ahclkr = mcasp_ahclkx;
7 ~ ^2 Z( J# X9 N$ Yassign axr1 = axr0;
G+ R1 E! c" }: a. t! b: W- ]3 I2 o l, R& E8 E2 A$ A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 ?& Z# S4 K$ s6 R8 R/ b! {$ m. X8 ]. kstatic void McASPI2SConfigure(void)- ?3 ?# {( b! X0 a
{5 Z; J8 O) C6 |7 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 P5 b: j2 y4 y' P& ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* K/ w# Y3 i( {/ ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 ?3 x- \7 i8 zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; S/ I% V% R) W3 b& G2 F. G- N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. |1 { }( Z- D& m9 s1 o
MCASP_RX_MODE_DMA);! _! X6 Z3 ~2 J! n' m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ?! S& L( C. S' OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) G: I, [0 c# B* d$ I$ w/ k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; x! k7 X1 W$ M3 S# [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 m( f8 y. h5 m8 U( Z7 B5 j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 U8 E, M1 K, i( [5 y0 @6 G0 y6 \* PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; S4 a5 o) J$ z1 sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. `! b5 D7 W& {/ y; _9 h' {* [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 }9 D* Y9 ?& E- S, b6 Y+ ]+ \9 C2 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, Q2 V" o' X v, h0 l! ]7 P
0x00, 0xFF); /* configure the clock for transmitter */
: s3 H& U4 v$ LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 {6 K4 g+ M3 d6 E" w0 x! p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' ^0 M; @4 e3 j( H# l5 n# wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) K: n( d3 b9 T1 n
0x00, 0xFF);
$ J# w: w' c. J* m: X, I% [! m7 L8 y% Y* d! b
/* Enable synchronization of RX and TX sections */ : G' D4 b: U4 l3 E0 y9 ?' u2 Y* n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( B6 t/ A# B1 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 B0 F( X9 |3 \" aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& C0 [: N v6 C* P) c) M** Set the serializers, Currently only one serializer is set as
# X' t0 f4 p4 d5 i** transmitter and one serializer as receiver.
& p% t% Q5 A8 C*/
, g7 ^% Z+ }3 v2 h& Q; H5 XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 |- e$ e, O( Z# k( q; A" gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* a; e5 v/ a7 U. \** Configure the McASP pins
- L1 }, D% N6 T+ Z# J3 N- @8 C** Input - Frame Sync, Clock and Serializer Rx& a) v( c1 n6 u* z
** Output - Serializer Tx is connected to the input of the codec + a* i6 H4 n0 N$ D
*/
, V$ m5 { @9 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% @+ C+ T) y, oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* z: q3 r: f* i, G$ y; W+ ?0 i2 sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
T1 {+ `, i, J) j) Q" }. t| MCASP_PIN_ACLKX
3 z5 r9 f. l4 g% g I; {| MCASP_PIN_AHCLKX
( A8 Y5 Y! V0 a" Q3 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& N* h- O' \! q" y" w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 u. m% v9 R* L/ Z, ]: o| MCASP_TX_CLKFAIL 0 e4 V7 k- W8 @8 \9 r! }+ U5 b
| MCASP_TX_SYNCERROR2 `0 I- E* d6 F' A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) r3 R7 f$ D4 k. x
| MCASP_RX_CLKFAIL6 T! V9 Z b$ F* M
| MCASP_RX_SYNCERROR
" R# s. U, B$ Q. @2 L- b2 r| MCASP_RX_OVERRUN);
& o _& z& c4 g0 v% @8 R} static void I2SDataTxRxActivate(void)
$ u- e9 D3 i) O" q) F3 [{, s$ y- ~! }( |1 G0 V Q6 p
/* Start the clocks */
. y: o; _7 q/ U6 Y! W, p! M4 D7 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ m: \/ u7 f+ h, `7 C1 z4 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 k1 J5 c4 Q" B: p0 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 t! c4 {/ B2 Y( ^% {EDMA3_TRIG_MODE_EVENT);
; [, C: s9 \3 | j/ B9 J7 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 L+ c/ y& u4 ?, }' d/ u5 C4 sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. J: L4 |$ W0 J5 T( \6 x7 V* DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ d3 b. o# R' j7 n- R5 A3 T. iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; X* r& \5 ~ I2 n) Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& N Y1 a6 A% G4 d& P. qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" b; y/ e+ Q& H+ ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' `$ v/ b- D1 ~" i, [: f: c} 5 _, E/ t7 O2 X+ V; [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. w3 [4 j0 J% e. G3 F+ b t7 m
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