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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" m3 N [0 L' F! \/ D3 V, X+ einput mcasp_ahclkx,
) s3 ^/ o9 C4 W: tinput mcasp_aclkx,/ M- c; o1 M) q
input axr0,: f) @; j, M% k
3 B- Z5 o( S; poutput mcasp_afsr,/ A: T( ?' m2 J: _8 E0 Q
output mcasp_ahclkr,( j: ? I( C; O! O$ {; M3 R: O
output mcasp_aclkr,
& @+ C t7 o# _! F3 g. y; Moutput axr1,
- f1 k& _/ _1 q2 F6 C assign mcasp_afsr = mcasp_afsx;
3 D9 \. p$ L4 }0 F# L. `+ o5 Passign mcasp_aclkr = mcasp_aclkx;3 Q3 M+ W2 N' Z/ Y% H4 q* }
assign mcasp_ahclkr = mcasp_ahclkx;" @- O$ {$ j1 g. y: E0 W3 j
assign axr1 = axr0; - ]! l1 y3 U- m1 B# p; Z$ A/ i
6 V3 `3 x5 Y' \7 Q# u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 c8 C; r5 s8 B& X0 R( E- Astatic void McASPI2SConfigure(void)* Q1 s- S. L+ H" f; T/ C* ]
{2 _3 M) Z% ]: }% o- A, F4 n P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' @& V. A \( [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; S/ z, l2 I! T4 U" Q, u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 }" g6 l: ?- q& V; I* y' ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, b) ?0 j3 }4 nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- s6 E. ^+ |" p( H2 E& K4 @: zMCASP_RX_MODE_DMA);# t. k; X" Z# v0 @7 B. o1 J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 _' b* f' o" l" C2 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 y" u$ H( G; @* jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 i R0 r# W$ B* r9 W( f7 B' ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( C. g8 I" M2 w4 W/ y' v2 L) ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / Y9 k! X- r2 t! ^$ r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 B, _1 b! D* a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# v3 N- H8 H! y5 o" G! z( n7 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 r2 n- D# O. `+ ^) O2 X9 O5 N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 [ g0 m; R% T* s: q! O: I
0x00, 0xFF); /* configure the clock for transmitter */& Q% n* `6 m4 p% V {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! v( P) ]2 z- J! t! X" YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 A; |$ A; H6 c6 F7 T5 H8 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ H- s: c! o. X, b( L& N) E/ l0x00, 0xFF);
% N% ^$ N* ~ f( b9 _9 _9 V' H0 t/ }* T) N$ I! s/ ]
/* Enable synchronization of RX and TX sections */ 3 [. @9 P6 r* Z. n3 \6 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; F" |' A, v* T$ \- [& c) _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ I3 z1 s+ t2 l. K, v2 m0 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 s j6 F' h3 g( H
** Set the serializers, Currently only one serializer is set as
1 N! p' V& m, T- R** transmitter and one serializer as receiver.0 m" n0 f4 d+ q' L. v: R7 W: y
*/$ {" B5 Q3 L' A+ o" y* V' Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ ^. v8 ^1 G' j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" Z# v$ J' E) t$ h# i2 g** Configure the McASP pins " J7 l' l9 U+ X s7 `' A
** Input - Frame Sync, Clock and Serializer Rx
, h# p6 b, K/ L1 ~: X2 Q U3 C** Output - Serializer Tx is connected to the input of the codec " b4 b$ W, P8 z
*/5 J1 M0 F2 \6 V6 q/ b* J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 G; \7 {- L- Q/ z. k- PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* j+ J7 ] ]1 |% t3 E/ A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: I: C9 ]- ]9 f" d
| MCASP_PIN_ACLKX
7 g0 k5 r x% E x7 d| MCASP_PIN_AHCLKX2 {% T# R5 t2 ^( ]$ I# l6 O5 X/ b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% A; ?, u5 Q+ x- LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 U m- h" z& W
| MCASP_TX_CLKFAIL : G6 o/ I$ x2 ~7 a
| MCASP_TX_SYNCERROR
6 F6 P3 P2 }( k5 n) f( V! F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" a; \+ A0 A- @' t5 @; l. Z& u| MCASP_RX_CLKFAIL5 z# _4 P$ s# H
| MCASP_RX_SYNCERROR
/ O" g E$ r9 f7 b4 [# r+ m2 f| MCASP_RX_OVERRUN);0 B/ m! x& D: e, Q: N& S4 n
} static void I2SDataTxRxActivate(void)
# N+ }- l% k: P/ ]. b8 o{4 F2 A. p+ t' R# |% t: D {
/* Start the clocks */& E( N' p4 ~4 D0 [6 n* z$ r/ e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' x0 }7 W! H" P" |' g# l! U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# r* ~* C9 z3 J/ s W8 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 p8 {; Q" p7 T4 N @& p LEDMA3_TRIG_MODE_EVENT);
2 v" F# ?8 B( ^8 r) N& `( ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Z; G0 q4 L4 p. G* Q7 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) f) ]' |3 K& p: x& U6 \2 QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ }2 j$ `5 y% p5 G/ p' a. I4 ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( f$ L4 E v% x. C% o, o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- w! H& k8 e9 {8 K: \9 Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 R! z: W8 ^9 x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ ~/ t3 n$ P$ e; u, `% p% T7 O
} 2 q9 P7 f8 h2 \8 u1 q7 \. s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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