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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
]; q/ j. j8 O }( Y5 \# m# [1 R" a+ minput mcasp_ahclkx,8 w0 M0 k+ @0 w( c
input mcasp_aclkx,
/ ?) A" c* X {$ rinput axr0,( s" R/ I5 G5 u
5 Z6 e8 p) O+ Y* routput mcasp_afsr,- x g' s0 i- u
output mcasp_ahclkr,
) Z% Z A7 N: g) O$ z- p+ Uoutput mcasp_aclkr,! [3 `* q6 D% f4 z
output axr1,
0 o" H* E5 h0 o. M4 f5 M) s assign mcasp_afsr = mcasp_afsx;9 s% d" w* M [$ P1 |
assign mcasp_aclkr = mcasp_aclkx;# X9 \# o& a- C( g6 g, f
assign mcasp_ahclkr = mcasp_ahclkx;
7 d/ G9 ?6 K# Z! f# }assign axr1 = axr0;
' A3 X, ^- M& q/ ~8 Q" C J4 `3 _2 m
' n) U. I* C6 [" n0 q0 R& m" Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / w+ o- R5 ~' M5 O( Y7 n% a5 i
static void McASPI2SConfigure(void)& f( h7 W; z. ~6 p2 D, Y" l
{0 j% p' s( I( s/ F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 e: N, O8 ^; W K1 h( g% O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- z j" l- W/ r# A3 A! IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 i2 h- R) R) a, c- K) VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" D" A. u# y) ~2 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 L: E0 Z1 N0 g1 a0 c2 {
MCASP_RX_MODE_DMA);* e. R5 n" }$ ?; D* g4 P& r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 j/ v: ^& E& h: {$ W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 A0 l) m& G1 N p5 y; `, L% q& C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ S5 T9 q; g6 B9 Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) W6 {. b( F, k+ _/ i4 }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 B9 f, j3 ~: W. g" H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! K5 j, K; o `& F6 S4 d% P' s2 DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 R4 B, t/ K; {! IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 `0 A& `1 W o1 Y* CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; U8 D0 W0 l2 P1 j
0x00, 0xFF); /* configure the clock for transmitter */: [- ^+ y, ~" q) p `2 B* |0 K1 s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); a, t* Q+ w! a; u% E2 a7 U# q5 D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 J7 [1 a- z, B+ ~/ r9 n+ l6 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* x7 {7 Z$ V+ G" W3 S6 `! R0x00, 0xFF);
) |8 w( ]3 w" \ i8 h# F6 S2 U
5 {' d8 k5 j* }6 W# V4 _/* Enable synchronization of RX and TX sections */
; A: b0 n4 X4 O- V, tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' s5 _) Y# u$ n$ P- L* t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: d% y( T5 g+ U. ~1 `3 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ H- a6 K2 B9 c3 P** Set the serializers, Currently only one serializer is set as
3 W# B! T" }# U: ^; o+ c** transmitter and one serializer as receiver./ `6 L" ` z3 N! D$ P% u: F
*/
5 b( Q- P9 M, B- m8 {" eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, G3 Y+ A8 m1 i/ x( u. x4 P( }( hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 v- {7 ~: F1 m, B( A. }
** Configure the McASP pins ) u! q5 i5 v, A. N, R
** Input - Frame Sync, Clock and Serializer Rx% x1 J$ c, x! F% A
** Output - Serializer Tx is connected to the input of the codec
+ X- Z* y) ~: v*/! I+ j' k2 d V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 e) J* g' R8 Y+ E$ hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- C" j# \4 {, aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: y, Z n; Q" S( ^4 P0 K- G" B; o/ I
| MCASP_PIN_ACLKX
6 e0 w3 T9 Q }2 q0 P' ?+ {: i+ N3 j| MCASP_PIN_AHCLKX
3 k" I. C; r6 s) q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' h8 V0 W" K S: p3 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # ~' P" M; M$ M9 \& f% s% |) R
| MCASP_TX_CLKFAIL ) G- [# f) ^; Y T4 ]0 J
| MCASP_TX_SYNCERROR
* A5 t: s8 I( n( L A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 z; l7 f2 ^& T( I* y' X! V3 N
| MCASP_RX_CLKFAIL, M1 H: k; b4 ^/ s+ C
| MCASP_RX_SYNCERROR 9 ~, O: e% ^% K' g, e( g* d- I: I( H/ j
| MCASP_RX_OVERRUN);
% J0 H" d' \8 _9 {} static void I2SDataTxRxActivate(void)0 |/ c6 J8 B0 w/ k! V' Q& y
{6 k$ O6 W. O! S% c( A8 x! y$ L
/* Start the clocks */
# N, `/ z. p2 P% F5 S; P. w4 FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# {3 A0 O, E. R6 s0 e6 j6 {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 }$ C2 i/ n0 ]% i7 N. U9 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. R" D5 ]+ J4 M! k* n2 p5 ]$ [
EDMA3_TRIG_MODE_EVENT);/ z4 y0 e$ _; h6 l5 Q# P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' A0 R/ k4 Q. H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 u4 c. _. b1 R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 D$ e1 }$ Y4 `4 C& a! H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! q1 {% Y b0 w+ E& ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. g# R( z p% a- M# d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% V/ B% t" v, d5 h0 L$ q3 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# P$ U; e% p/ l. X- w3 h% C( u
} 5 v% k, O$ E: ]" A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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