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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, x# S% @" h( `) @, U
input mcasp_ahclkx,' `( m' N# t* b
input mcasp_aclkx,* _1 Y$ M8 s5 Y+ B5 k1 M
input axr0,% q6 f1 Y5 D* g8 N) I
( m% k) ?2 _/ R' t3 U2 boutput mcasp_afsr,
4 l2 I3 X2 }+ h: E+ m5 W& Ioutput mcasp_ahclkr,. e3 ~6 e* F$ _0 L& b$ z# B+ ~4 b6 Y
output mcasp_aclkr,' b* }% g7 o# q- O0 b" s
output axr1,9 q t4 e1 i$ X
assign mcasp_afsr = mcasp_afsx;
2 j- r6 I. J7 |/ ?6 _* jassign mcasp_aclkr = mcasp_aclkx;
: y$ E5 ~0 I' f' H3 S! Jassign mcasp_ahclkr = mcasp_ahclkx;
4 ~5 {$ C0 ?+ f: K2 P' i$ A2 `assign axr1 = axr0; 6 y, [" L6 @3 e0 d& D
, |* c+ G! K+ X. L0 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, {6 m+ C' E; y2 lstatic void McASPI2SConfigure(void): g7 ?- T' L2 h, P" ~2 d! d; }2 H2 A
{
, c3 f7 H+ Y1 g) |& fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 {, y3 m! ^) J4 N: oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( `+ n2 l9 z5 Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& H% `5 Z' }6 d/ @% bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 e- s5 i# }) a4 j5 X2 v5 _, r# J3 IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. {& E0 E: T( {0 J AMCASP_RX_MODE_DMA);
3 C' ?" |8 Q$ B N6 I) o! r: mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 \4 F. a0 S/ x; E0 l. J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( e& ~/ K: h, F( m. b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 @0 i2 G0 ~5 @! W" Z2 u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! C: Z! r7 }: ^/ Z0 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / V. ^4 p) Q+ _: C( b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, y7 k' j, [0 F6 l! T) Y$ q9 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' ^( {9 d1 ?4 [' M0 H/ e' {; j! o- }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % u, g; l( f8 k( B/ W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. ~* u4 l! G, Z
0x00, 0xFF); /* configure the clock for transmitter */! [& h- D2 B* z+ k& K+ N0 G7 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* v, c. \) s/ U1 @# i4 F( AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # n7 ~ l t. z; Q) n& |" K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 ?/ x( [( B) }% B0x00, 0xFF);
8 s- `1 e4 ]0 W% W$ X$ s) v9 A; b; _) A/ E& x0 H
/* Enable synchronization of RX and TX sections */
6 v! A& n, G8 ^- X; N$ EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 R- t' g! Q, A! q* u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 n. |- g. `" X1 |! Z3 l4 n% ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* q" C8 R3 [; c+ L* {$ L. P, F
** Set the serializers, Currently only one serializer is set as
* i2 w; S/ X; e l** transmitter and one serializer as receiver.
& [4 b' C" h0 ?/ ^*/
! c. f* m y! zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, D0 w5 {/ e$ w5 w, [. jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ k) A. ], | n; ]- d6 L5 M** Configure the McASP pins
4 z5 j) I0 J, k* P$ m** Input - Frame Sync, Clock and Serializer Rx- h f' m6 h: X {7 l& e
** Output - Serializer Tx is connected to the input of the codec . f7 s+ b- o" j3 P% i) J
*/
" ^7 V& \ D- Z& m# F5 l B# OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; x5 ?) v2 u. bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 t8 |9 N% @ R+ r8 A$ @* Z$ `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 h' q3 a5 [. Z- z% u* C. Z
| MCASP_PIN_ACLKX
. H6 g; D1 D! s% [+ e| MCASP_PIN_AHCLKX' E6 A0 m9 d5 f7 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% y' P- v& O# W. l. T) [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' P4 v: R+ o6 a6 J
| MCASP_TX_CLKFAIL
4 R3 p7 o+ b' n$ z3 \| MCASP_TX_SYNCERROR
5 p9 h9 n' f# g3 w/ x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR i! z$ C) O5 E2 x: e
| MCASP_RX_CLKFAIL
/ s5 E/ p" j4 z/ k| MCASP_RX_SYNCERROR 3 j' N, o+ U1 \, C
| MCASP_RX_OVERRUN);
, |4 d: O" v5 m9 {} static void I2SDataTxRxActivate(void)
# ~6 `3 ]6 `" M9 x{/ P3 b1 @7 N; j& W9 M: Y
/* Start the clocks */7 p/ P9 x# b) |$ L: s& }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 {9 N% F5 ?$ d6 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% F. S4 C. K0 E; S+ a8 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 h0 h h! `! `, q- Z) n gEDMA3_TRIG_MODE_EVENT);
2 @9 i8 {) V2 a& p! A' GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 a" }2 g& W$ w0 b, JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, ?4 C% B2 j9 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! y3 d2 ?& K8 o( `. m6 z: nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( @( s# O$ I7 W, X- [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* s9 \7 W' d j0 o/ g' X* K. u- ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 j& I9 V9 a; {( ~& z8 XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 x. K4 o- q1 h+ C, X- `+ A' d} 9 ]$ { H2 z: M$ y& L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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