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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' U# z4 |# B4 b# u3 T% O4 Dinput mcasp_ahclkx,
5 p4 k/ J# H+ finput mcasp_aclkx,
$ } M$ `, c5 B( W0 X( s6 Minput axr0,) ^! b1 Z2 J: U2 V+ f
! ?) B5 z. c3 [7 }! Woutput mcasp_afsr,; T7 Y0 K8 R0 A* F* l4 e
output mcasp_ahclkr,
1 t0 s0 \- C2 R; p% Q2 voutput mcasp_aclkr,5 e o( b" d- R# P# c4 |8 d
output axr1,
7 V. l$ ^* W$ h0 ~. I: E5 {) i assign mcasp_afsr = mcasp_afsx;
0 {; j' W* \3 y/ y& H* d/ }assign mcasp_aclkr = mcasp_aclkx; K/ z$ e7 ]; d( e* @4 ?' ~% \, d% q
assign mcasp_ahclkr = mcasp_ahclkx;
6 u8 v' M" r% H* Q) J5 Hassign axr1 = axr0; : Q$ n$ j+ R( M3 [. _) p/ K9 h. w
9 h$ X4 o0 }9 o' e2 g) }- T! K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" Q! U' `9 P& `, j5 Lstatic void McASPI2SConfigure(void)
% ^" J/ ~3 W$ l0 c{4 F9 ~: S: Z0 k9 a0 }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 b% Y7 E6 F: KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" O4 q1 H, ^! n, @ n) b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 N; ]& K v) Y& ]' bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
\3 ?" e/ [; O. n* s! @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 c- I0 D/ }4 }) GMCASP_RX_MODE_DMA); b$ Q6 g7 T( e2 K$ O; k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 o$ t( L; V( p3 m1 d* Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 F2 x* M- N6 \! j: j1 g! xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
Q. n( o: b4 K# _8 ?: ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ W0 M4 C7 g6 t/ y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, H1 U! @* c U) n8 m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 q+ f3 x( i: P. }: F% ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& y! m/ V3 X. @$ p% |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 R/ V6 N" |4 m, D0 D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 I6 W5 J9 ?! f; s8 _, G, S% B
0x00, 0xFF); /* configure the clock for transmitter */
5 b$ m0 x3 x- x+ X. I8 zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: o$ A0 H+ }9 x) \$ l( U9 d: H* JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ G1 }' ^. ~6 o; X/ q4 l$ z) @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 e9 m6 O+ P5 a. z, C0 ?5 I0x00, 0xFF);
8 l y5 ^$ B% h/ d8 ~4 `
! \# r2 X; A* A& r- X( `' Y' J" I% R/* Enable synchronization of RX and TX sections */ + F3 G8 y) J1 @9 c1 m1 g1 X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ f; L6 D, W0 Q9 @& B+ Q+ F7 LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' `' u& `7 Z5 T. |6 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' g1 o Q5 d1 ?* U( X1 a8 u) b** Set the serializers, Currently only one serializer is set as9 j0 @. L2 _, }- s
** transmitter and one serializer as receiver.: R- }, A) q- L0 F9 V9 e1 C9 \
*/
: Z/ b6 r9 g" c% _9 x9 LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ x5 \; R) v; s- t8 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! g$ J3 K$ H4 t, B5 D4 M& u
** Configure the McASP pins
8 \) x# k% |$ k; x** Input - Frame Sync, Clock and Serializer Rx
" l5 K4 n# {4 s4 S/ M% ]** Output - Serializer Tx is connected to the input of the codec . Q6 a9 @# w3 E- J% _! R$ i
*/
9 I5 A- n; c9 WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- O0 e4 N: r! H z5 y6 m8 a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: y% V) |8 V* H7 X7 M# KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 L! T: x, j2 v* v' X/ Q3 X9 W| MCASP_PIN_ACLKX
( s; i( ]8 c1 [1 N# M' @ I| MCASP_PIN_AHCLKX/ r# @! a8 M6 u+ ^8 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 J. K, t; r/ w9 V1 y# G. S' Z" @$ u+ m" n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# }- W3 y0 {* l/ ?1 b0 r# @| MCASP_TX_CLKFAIL
6 J0 ~# \; S! o| MCASP_TX_SYNCERROR
0 E$ G- T; h9 L# i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % D8 u, H9 n; K1 i& p0 g# q
| MCASP_RX_CLKFAIL( K' z" O9 x% Y
| MCASP_RX_SYNCERROR
3 U# A7 c H* F2 `) D0 _| MCASP_RX_OVERRUN);
& Q+ X# R8 C3 L0 a" p} static void I2SDataTxRxActivate(void)$ D% ~ P K5 G2 H t
{
) B1 H# e8 o6 a2 r4 e. ^/* Start the clocks */
: M+ U; ]8 I8 n2 R( \, y( mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 V. [; Y! b3 g% e$ `2 bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% _. L4 a; F2 X$ j# V rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; g" L) v- d% ?' EEDMA3_TRIG_MODE_EVENT);- @1 n/ d, G6 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Q2 k! n( K# @. U: Y7 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
T; Y; |5 j! r" c- l/ ^+ _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 U6 r' h/ g) e; q* p$ h) dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& g& C. Q% K- ?/ D$ d, h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: F1 {' V! {+ D0 Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ X$ ]( T4 j0 S* f3 U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ h; [! y2 o+ H' V) ^# v9 ^; e( `}
6 G5 c# A! M( n% @. s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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