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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ {6 W5 q: }: l
input mcasp_ahclkx,; T$ R& U$ m1 w) p
input mcasp_aclkx,
4 T4 ?- l+ z! W: b& n2 F4 |input axr0,
3 t- s2 I! _ W4 m8 ]& \8 l% X4 _* P9 u
0 f: w0 J& @- |) {output mcasp_afsr,) P$ \; J+ G( j
output mcasp_ahclkr,
" w- Y% a' P1 h$ Qoutput mcasp_aclkr,$ q r# |" Q0 ^5 ?
output axr1,$ s$ {8 T0 ~- p! v( P" s( F
assign mcasp_afsr = mcasp_afsx;/ d# M+ |; |, `) A; e- C6 {
assign mcasp_aclkr = mcasp_aclkx;: X9 v$ [7 u4 n& O& W. A4 {
assign mcasp_ahclkr = mcasp_ahclkx;& U# a @/ W! P6 J# d
assign axr1 = axr0; 0 k! D. f5 E# v' F4 `
; F/ |/ s' k: p3 U( u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 }$ q1 I* c# l9 v: Bstatic void McASPI2SConfigure(void) u9 j8 o' t: |6 ~0 R# ^
{
2 f" t7 u; g& v1 c9 q! X# ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);! Y2 W5 b$ |! @: ?! a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( ?& R" d1 c2 r7 z9 {1 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; V# r2 K6 ?. M6 F8 A1 qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 z2 ?. u, s/ i: d. c8 Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: w( X4 M5 Q1 b8 o/ C4 A1 ?
MCASP_RX_MODE_DMA);3 J0 w3 L& Q, g: H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# A* _ }7 [' R# H1 s. YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 Y- f$ J z* s' X& B! _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 l, w: e7 A$ f$ LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 T6 z5 }& D, m* F) QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ h% E4 @3 d+ {0 y- vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& a6 z3 z4 K5 r7 e8 A( H# d4 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- x0 d6 m7 E+ ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* O3 M( R/ m7 Z8 E# c4 fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ @$ n. R: P) D
0x00, 0xFF); /* configure the clock for transmitter */
8 b! n% R- J1 v# n! v$ CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 z; e: n" |9 E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) V7 g% ?# h( \& A7 n, b. }: j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 ]( {. p8 p6 s+ Z7 p/ z4 u0x00, 0xFF);1 G5 M6 g+ W( c, X
4 m3 V& X; D+ C
/* Enable synchronization of RX and TX sections */
. M! [# A& D1 x( V9 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ P: j$ _* ^7 e$ R; a- ^" \8 g6 z. nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) k' C* q- z, E) F* L$ c; \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 V6 ^4 `9 m7 T( \
** Set the serializers, Currently only one serializer is set as
5 W2 q* L* L l' _0 T9 Q2 \** transmitter and one serializer as receiver.6 s7 b4 Y9 X0 q. B$ p- F
*/
4 P& ?# b* X/ l6 ]7 p: p3 BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ Y+ q* [/ ]: Y% |! V$ `8 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! G6 }# E. b+ Z8 M/ }4 J" _
** Configure the McASP pins
H( M) S, ~* I! i, s7 q** Input - Frame Sync, Clock and Serializer Rx
7 x, {, g1 \! ]. s1 M** Output - Serializer Tx is connected to the input of the codec
" |4 ~( R( r, w6 P+ e*/
/ v6 o5 I" p' gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# W: q/ o. d& ]) N, a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- R6 ]9 D' L' Y" }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 l( k" t. v# S
| MCASP_PIN_ACLKX c0 L5 m$ R# N1 u
| MCASP_PIN_AHCLKX
: v- _0 M5 U: D5 S% R9 F# J4 || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* h) J# D. v% D) C9 iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * Z: Z+ X3 h; g# G. O) k
| MCASP_TX_CLKFAIL
8 Y' Y5 P: H: f' n2 t. j; J8 ^| MCASP_TX_SYNCERROR* P- r* N7 b0 J) ~' @6 l! y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 w6 g$ e j0 V# D: V0 [$ x
| MCASP_RX_CLKFAIL7 x6 a- R; X% ] Z, D- h; m
| MCASP_RX_SYNCERROR 8 _+ ?3 ^" N( y" |3 t# t
| MCASP_RX_OVERRUN);
( S7 \, e2 k& o y0 U" x7 P} static void I2SDataTxRxActivate(void)
/ ^: m# c: S2 @! w0 t{4 W1 b% ~ z5 E) ?0 p: I0 H
/* Start the clocks */5 d1 [% G6 l+ g8 q8 U- D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. \9 H' Q" W- U5 l1 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ [. x; V* x# {- j- h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 g- D. _+ ^2 K' F
EDMA3_TRIG_MODE_EVENT);
: F8 B, V: U( v+ u8 l. jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ }9 ^) z$ U% H1 N# nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* i! [) S* d* T( p+ p- ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 y5 `- {- _# |. F& k" C; I- ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! y. m9 D. W; d6 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* |! _7 |9 E* S+ ?' I0 D( i9 ?2 VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); Z3 c: V+ r; ^8 o. @9 ~" }1 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: r1 |6 J! y0 @3 P: X2 `( z}
2 k5 ^- Y* i$ U6 _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , M9 b8 O5 [" k* ~0 ^7 p2 F6 y$ N3 j
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