MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

; R5 p+ e$ L# c5 q  i- {output mcasp_afsr,
output mcasp_ahclkr,
3 j/ y6 c: M% a! N; W# zoutput mcasp_aclkr,
output axr1,
3 G5 p4 \+ X, S

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
6 K/ N7 u( N' a/ `0 D  M9 Oassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
" \: r- C# Z6 @$ p% f' V{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. l- V9 D2 p8 Z( R' E6 P2 f9 LMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
5 l2 Z8 E4 x8 e' h4 ~# Z( QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 W/ J# H4 \/ e7 M+ w% eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
) Y% |! v& u/ g# T0 QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
" }7 j  m; Q7 m5 n7 q% RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) p$ u4 R2 M0 s5 U% Q  T2 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
9 C; y3 ?  Q; t$ q4 tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
$ t, e  g* A4 Q( p1 x. `. T/ B: dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 z3 `' d& z5 T. c. Z) IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# S" R. |  F0 _# xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ Y' z1 k9 N; R! Y) g: |0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
% @1 q. W2 E: i0 o9 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
* a# O+ t: S7 N6 t' _& e+ t3 D- n: zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- D# s5 u; w3 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
$ d% G" J/ T. Y& v** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
8 a: c& [* d% Q8 A8 B9 v6 w2 d6 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
/ A" I: a; v0 K- Z& Q" v** Configure the McASP pins
. E4 ^" l4 i9 A9 g# z** Input - Frame Sync, Clock and Serializer Rx
% J5 A5 o2 N8 Q7 F/ f2 {( F** Output - Serializer Tx is connected to the input of the codec
" S; w  L+ I* d*/
! @: f* ]* g8 D4 A9 F2 ]4 m, B; yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 S. }9 g# R9 _* n4 A6 j. m8 SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 ^; H6 f  E, D' p: o5 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
& L% ?" J, ~1 a/ J| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
4 W5 x! J" A: R$ p, w| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 F; c; a3 P; f  w  ^4 _1 g5 W| MCASP_RX_CLKFAIL
, X0 r' D+ P$ n+ h$ e| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
8 k5 e+ s! [9 o}

static void I2SDataTxRxActivate(void)
: ^+ h; X. z- ^- b3 t% e{
/* Start the clocks */
& c0 K- B7 c6 O& XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! F* a: u$ ~9 M9 Y; ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 ?2 K+ E# q. AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
: t$ \8 c- `; AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
4 A2 ~% c0 w  v. rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* i9 A- f% b7 D2 d% DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, q. C4 @' Q9 L9 M}

( Q6 _% H: L$ B& O! N+ H

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

( B. g6 l# k; ^7 W