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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 \. d7 Z. d q( r/ Winput mcasp_ahclkx,
9 } t: I p" ginput mcasp_aclkx,6 G6 P4 a3 d+ @! r8 L
input axr0,* {1 J+ r- Z/ a0 Y9 U j
, f) z/ H0 v8 o3 |output mcasp_afsr,: P1 B: |! C- n3 ~
output mcasp_ahclkr,
) i/ Y1 R# h9 Uoutput mcasp_aclkr,, L" |5 B' Y7 F/ q% V0 \: t
output axr1,
- C6 U% y; G! G$ m/ E" R/ G& F assign mcasp_afsr = mcasp_afsx;
: B& `3 P; h! {* Oassign mcasp_aclkr = mcasp_aclkx;
8 h2 b: K* J' n3 d& gassign mcasp_ahclkr = mcasp_ahclkx;
7 f6 O* F9 t9 gassign axr1 = axr0;
! q) D4 A$ G: y0 C* i
2 ]( S7 u( {$ ]( D4 _( q# \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ y0 F( V$ }1 P+ t8 i/ f }/ t: fstatic void McASPI2SConfigure(void)/ e" h+ X( z; g! X
{
% p( M& u- K0 q* c$ WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: d3 L+ e% j# R& L; v2 ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% X1 g) K% g+ |, C5 A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 T3 |6 Y% v$ ~6 ` p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 p. E+ ~7 u8 s4 q) nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' N% I# N) E' G3 _" o8 d6 [4 ^$ D% ^MCASP_RX_MODE_DMA);. p8 w7 ] a/ [- ~! C6 h( @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. `. D1 C, y7 x( J8 o6 s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 e5 W# u( ^: T5 l- V8 T0 b: |9 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " ?/ X9 h4 y) I+ D/ w! y V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; e( X! ^3 z/ `& T" B6 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; g# d5 g* y+ m& V, S$ S; j3 o! ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# @6 I$ s) [: A: A/ L6 Y j9 L3 qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 J: A, M c" n/ o8 ^1 l7 e2 Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( k( q5 j |# ]) o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- k1 J0 S$ g2 M# W: F% @0x00, 0xFF); /* configure the clock for transmitter */
( n/ \$ A8 ?- p: C+ mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); ~+ U. C' g4 w' r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % K9 X! j4 C9 x% Q j% W' D+ ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" {& j% V: I1 ]7 f4 q0x00, 0xFF);- N$ H/ y {: g
0 K+ z5 V( s" Q0 `/* Enable synchronization of RX and TX sections */ $ \4 ?3 g2 v: j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ \, _1 t1 e9 NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 v6 S9 X: w5 C, T) d( G" A, lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 W4 u# Z" ~' B$ q; s+ e4 w
** Set the serializers, Currently only one serializer is set as" `# O2 @. W8 T
** transmitter and one serializer as receiver.
3 j4 P5 u# n0 k! g# q- ^2 C2 x*/9 `4 B" y, x* ^5 ]" l6 X8 O; V/ M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# O# U! Q1 p5 q6 m# H" B4 S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, j% w( R8 X; c, c4 p** Configure the McASP pins
. }- }# [1 |. o** Input - Frame Sync, Clock and Serializer Rx4 ^, s, s" e2 w7 M5 ^
** Output - Serializer Tx is connected to the input of the codec & d( J- ^$ n. C/ m6 q
*/0 G* K2 y- H; s2 [+ k k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: E0 N& ?' o2 B% G3 r5 B" k9 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; P1 g0 |$ c6 z% Y+ ?$ ?" b; _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 z: y* l J: l| MCASP_PIN_ACLKX: T; R1 E" E5 p% {4 K' }' \
| MCASP_PIN_AHCLKX
8 N ~5 S, T/ ^4 C( h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( J1 Q3 ?4 o( \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 w3 m, h! O; ~* V1 G2 K| MCASP_TX_CLKFAIL
; r! j3 t5 \+ o; F5 d0 q9 b| MCASP_TX_SYNCERROR
0 s0 z! N+ u9 q' U2 s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * D+ V; s' T1 |
| MCASP_RX_CLKFAIL
/ K9 \8 i$ G/ ^! }" {| MCASP_RX_SYNCERROR 9 b h: u l* j% R# d( r" e; ^# t
| MCASP_RX_OVERRUN);) |, p' ^0 u$ E- b* p
} static void I2SDataTxRxActivate(void)+ a, B. i1 A5 w; |- h
{! Z6 \' u5 v9 Y8 y1 M# b; c1 h
/* Start the clocks */; x$ b0 h, B. L8 H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, l1 v- y) X2 C) kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 S3 `3 ]& o0 G ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, E+ g% T! J9 R6 _$ YEDMA3_TRIG_MODE_EVENT);6 O6 k4 \0 o2 P( i! @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 t) @. o" H/ k& J: V$ `. R" B4 o& dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( X) m5 k3 [/ y3 t- EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 Z6 ^6 Z" n% r) L/ O$ s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 d! A9 a( z& P; d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 L# z3 [' t, F$ y. D3 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 i- N5 R( X& S' S' b7 p' E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ d1 x& x. M$ A" m0 U" I" K I, g
} 5 N# R# f( E2 n" [7 k: s D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " J8 M* s: T+ ^/ y2 n7 J
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