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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; e& P( N0 t$ C- q; e1 b5 u4 ?* h3 qinput mcasp_ahclkx,6 v) e3 N" @, D% o' I/ K
input mcasp_aclkx,# R( b" `% O& t6 z; O( @
input axr0,) M: s! I, W( d! n: U, q
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output mcasp_afsr,$ O' E9 V T6 F" X- Y- [ ^
output mcasp_ahclkr,
9 }& J" q; I- }0 k, `# [* `/ Ooutput mcasp_aclkr,
0 b. I! Q6 ]+ d a5 [* soutput axr1,
) p% l) K8 m! k# k& N8 O assign mcasp_afsr = mcasp_afsx;7 h# \/ Q! s# h: ^2 f# A9 Y+ x
assign mcasp_aclkr = mcasp_aclkx;
6 g p0 g( K$ _8 P( iassign mcasp_ahclkr = mcasp_ahclkx;9 v$ j ]5 ~+ I: k/ E t; Z1 `& m
assign axr1 = axr0;
8 o! v# S$ E! I( Z- |* Y6 t L/ s9 z) c0 G+ x3 \' T. ~- r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 t `) y8 {& K' L" u# ]
static void McASPI2SConfigure(void)% J. |" S2 t! N3 }, m1 a
{
- [3 @4 V8 \4 w x4 O3 XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, p5 [4 V1 |7 r4 n" H$ I1 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" @; Z) T$ H# i0 e6 e2 N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) `. q* f# f: {, G( g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 O$ a, v R. S6 ~% ]% U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! A' w& f+ n& ^1 EMCASP_RX_MODE_DMA);5 i0 S& t! K( B% X+ S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ]" v9 A, T: U. sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 S8 f( e3 P# A; b6 b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 ]/ V: M$ c9 S0 q* O7 u# uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- Y( S$ d, c1 v. _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % b2 @- W8 n1 g/ W: k( z9 \. B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 k4 H& c; x+ R7 v( c3 C7 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 W4 \* F9 H5 F9 Z$ z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - T0 c- Y% S8 B- b, v" {2 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 U4 T$ B1 E. j0 ]0 R2 V0 F! N) v
0x00, 0xFF); /* configure the clock for transmitter */
5 q( z( w4 `9 g5 h" h- uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 E) `1 A7 k" u4 q* ~! I) YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 \7 U$ D0 q) I& E5 A# P9 B9 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: v1 q+ s: v" u; a- f- `$ N$ f" a0x00, 0xFF);
/ n3 `8 t7 `% _% V) S' q9 D- O8 ?* e
/* Enable synchronization of RX and TX sections */
9 }- ]- q, E; }( j9 W4 V6 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ h( }# O% y/ a8 d$ k" T [" j0 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 H& S8 a1 W2 p' j; VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** z- F; z) `5 f3 G/ h5 ~2 a& P
** Set the serializers, Currently only one serializer is set as" h9 f( t. {3 t: N
** transmitter and one serializer as receiver./ Z. u' D8 _' l, @" S
*/& i* f1 f0 d" g( H k( S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 i( i& ]) q/ ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. L8 }1 U. ]5 O2 k
** Configure the McASP pins ( Q* C" k4 o& o; l# N0 }
** Input - Frame Sync, Clock and Serializer Rx
4 e0 l0 R) ^ j6 F** Output - Serializer Tx is connected to the input of the codec
& P4 _- z6 h" o7 @# z*/
`- v6 i' q4 ?3 {' y a8 nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- K! v+ g( E+ |3 O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# T' R/ e U9 B) }8 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 ~; e6 [" N6 L3 ]$ A, ]* J
| MCASP_PIN_ACLKX5 K* `8 M9 c1 D* {8 O" c
| MCASP_PIN_AHCLKX
: r% Y6 r& v; ^) v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ `1 d! O# X5 X% J9 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 [; e% R* H( C) L; _| MCASP_TX_CLKFAIL
) o; L5 f& M: s$ {| MCASP_TX_SYNCERROR6 R& n2 ~1 X9 H- u9 a3 Q Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 M- w3 d* ~+ _5 v3 s" K4 H1 n| MCASP_RX_CLKFAIL
; f& |7 u# u3 Q- ~& t| MCASP_RX_SYNCERROR
0 g9 P& h8 T8 b4 c3 `) i| MCASP_RX_OVERRUN);
! `' I8 T) D8 P G} static void I2SDataTxRxActivate(void)! Z. e( I; c; `5 a
{
" ^6 @ D; E7 C# q5 J# k; w5 t6 S, b/* Start the clocks */
1 R" W& g$ G3 p$ ^- SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
@$ ~ V! c7 x& G1 z( RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- p8 G% m+ k2 `1 f5 \1 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! d/ o5 x% K; m: ~; Q
EDMA3_TRIG_MODE_EVENT);
+ ?- i! o( a2 }) i1 y9 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( ?% A8 j& D, x, r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, i3 F* {3 ?9 i. B9 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ {6 C5 Y: s* ^* F8 U! L% D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 L) q2 r4 E6 E% A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 W" K. c1 S2 G2 A4 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 y: z7 A! r, x, b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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5 w' L1 D7 L- U5 x. D$ d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 X8 s4 ]8 Q; ]. C
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