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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 D+ r1 \) V2 }; `# |3 |; ]9 _. sinput mcasp_ahclkx,) D o# G( z3 a/ D6 B! n7 w
input mcasp_aclkx,
' w2 u; _: T# v7 P0 _, B+ X3 Binput axr0,
( M5 {! q- }$ j* R0 T
% v! z3 _8 f5 n/ ^9 s( s2 Koutput mcasp_afsr,, D; u+ U2 Z* N/ [/ l, ]6 ~
output mcasp_ahclkr," K6 u7 H4 s1 S* v5 x
output mcasp_aclkr,: a5 T& \) e1 {1 |3 c
output axr1,8 L% W+ a J3 I K! L2 Y
assign mcasp_afsr = mcasp_afsx;( q' p6 |0 k `* w
assign mcasp_aclkr = mcasp_aclkx;
& }6 h( E, ] ?, e) ~& @assign mcasp_ahclkr = mcasp_ahclkx;% r: W! S5 E9 S: ]4 ^: L. z3 N8 R
assign axr1 = axr0; O4 A: y9 }- G2 F
) D% s! G8 Q& J! ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 @6 E( [3 B9 C9 p4 D& l* s
static void McASPI2SConfigure(void)
& k5 ]. y/ {0 ~2 W& ^! s0 _. y- }- ]{# h+ K1 k- t: I/ _. \/ Z0 @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# t. P. `6 ~" }% E" v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. _% X9 C; O5 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 s6 q- R/ w( h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ U7 x5 B$ `! c6 i+ vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 x; A9 z7 {8 nMCASP_RX_MODE_DMA);: e' r- m3 e/ [. j; \# k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
K9 J) n% I$ o5 M6 T: j& _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// ^3 D+ ^# l8 j+ @3 F" g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 b- `* k9 U2 p6 e6 M- s0 ~& E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& Q5 D* p8 |6 j. a9 F) q/ x" N* {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( W& ]" ^2 S# u* A$ AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' R3 w& i; a' f6 g9 u. m' l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ d1 a! n- }; L& b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 v% a- T4 @. ]5 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 V% }# \4 Q% O( ?! |% y+ o0x00, 0xFF); /* configure the clock for transmitter */
9 @. W5 A+ e6 f2 z9 _0 UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 a; H0 q7 n$ AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , F7 B$ e7 g( w" \: r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 V9 a( t3 s7 v# P: q% h0x00, 0xFF);
' u* a6 }6 b w: l3 \! a* t1 Q9 \% D& l. {& h8 ?
/* Enable synchronization of RX and TX sections */ 5 F% S6 {5 C8 i0 Y. h# L" z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 {1 E' e/ r# L% b3 Z8 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, i3 X6 C: [# u7 u2 {) M& {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 \4 O- h: Y% n5 W& j** Set the serializers, Currently only one serializer is set as: `/ W1 P; d) X) n% P6 O! U( x
** transmitter and one serializer as receiver.
* ]& G$ R/ V& V" k4 {4 M: k*/
4 {& z! A! d" ? P% ]1 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' a; w- n2 w% r. J; b4 Q, p0 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 U* g9 {, @( }. j8 N( X7 z
** Configure the McASP pins
2 @0 T0 S& \1 B, ~! @4 J1 R** Input - Frame Sync, Clock and Serializer Rx4 g! f0 j3 K: E' E
** Output - Serializer Tx is connected to the input of the codec $ v9 x k9 r" y! e) I: a
*/. V4 ]0 F7 L3 N3 k3 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# v" C0 y% u+ F; u( \; |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
P3 g) _# o( a8 h* c9 KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( f2 T0 F$ Q+ h( ~
| MCASP_PIN_ACLKX
: r) F; A8 d0 Z2 S- a5 u0 h| MCASP_PIN_AHCLKX$ Z4 D/ f7 e% I& K: a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// f H5 F+ I9 T! s9 |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& [( h h- {3 U3 D| MCASP_TX_CLKFAIL
. g/ D/ a2 w, ~; m0 Z2 h1 r| MCASP_TX_SYNCERROR
8 j# n4 [- z( d% i8 R; E1 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / Z, i$ [2 o: v
| MCASP_RX_CLKFAIL
4 E! S) N/ y, P* q5 G; n6 ]& w3 ?| MCASP_RX_SYNCERROR 2 n0 F+ O, |2 |6 l
| MCASP_RX_OVERRUN);
" ^$ P* T3 @( E& P} static void I2SDataTxRxActivate(void)2 D) Z/ g7 |. s" y, t
{3 R5 c N% ~+ b* Z
/* Start the clocks */: `- b* ^2 e) B' R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) H) K9 t. f- |' Z" f! s9 F9 ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& `, W5 a9 n0 o1 s7 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" H" W2 p) J n/ v2 rEDMA3_TRIG_MODE_EVENT);
. Q, S) T+ _: U+ K: {+ [( w2 ~% N: GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# X" D7 q$ B4 l% pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( \6 T" }* d- `( t, T' t+ E' V: F7 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 l* O6 q3 n, e1 ~' zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 ]( q* y. K2 D4 P% d! fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 P6 u$ ?2 t. k" D/ p# k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: E; V. W# y& m# J$ p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' J' a1 B2 z5 F' D* V! l}
( z) W- K5 i; W6 q. o+ _$ d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 ^* E6 w0 N- z+ |+ @0 v6 p
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