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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" J% X" [) e/ z5 O- g' z) Finput mcasp_ahclkx,
# x" r3 s j5 Zinput mcasp_aclkx,; n4 f |1 N- H, S
input axr0,
/ a$ c) A. p1 E( _
) b8 V, N7 G9 \ a1 z& Zoutput mcasp_afsr,
8 ]5 t& [ S2 ? Y* g' L3 w koutput mcasp_ahclkr,
/ N/ p+ m6 ~7 Z. G: [output mcasp_aclkr,7 \- V% a1 x, V! D; s- |9 h
output axr1,
, J3 ]/ c5 }- g( Y& k# m2 A8 i assign mcasp_afsr = mcasp_afsx;8 I3 }+ A2 _1 m2 W5 `+ g
assign mcasp_aclkr = mcasp_aclkx;
- ?, Y7 B$ `8 z Kassign mcasp_ahclkr = mcasp_ahclkx;% p1 F: M+ B8 U. s) R b& U& I
assign axr1 = axr0;
8 I& m, ?1 G; @; n. F5 e6 a7 ^4 C; K: J- E+ X( Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' |2 _; Q4 ~% ^
static void McASPI2SConfigure(void)
% z; @' a* L) n{
$ f8 J4 B* @: U+ v% ~/ G' mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; X) T4 H/ {. D8 X, [, \" rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 u% @9 |2 R: `, L! w& b7 c: cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ B; b6 p' g/ g( J6 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 v# j; \+ x. m' e- h$ w8 N) MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: p+ j. j; T/ Q. g; v6 M( O
MCASP_RX_MODE_DMA);
/ v& s: ~7 q1 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ o5 y2 F+ T6 T' @1 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 x, L6 ]( ]5 o) p% uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' R- G, m. T, C% N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: K# [! a$ G* P+ l; {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 y! B9 m4 p% H# ]( m, M8 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) {$ J! T$ N* |& v2 I7 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 S# Y) D- N2 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 j% W Y: E) z2 Y" AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. @4 P M& h% B# W0x00, 0xFF); /* configure the clock for transmitter */
# |0 n/ }# B9 w4 w+ V* _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 E4 ^3 Y3 s% X( I1 }+ I0 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : \8 |3 U8 B" U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% s9 |- q3 `; w! V0x00, 0xFF);
+ l" ]7 F* |' G$ s" ^2 g5 K2 ~8 N$ g$ S- \0 b% ~0 \
/* Enable synchronization of RX and TX sections */ * |5 f" b. j2 |& M5 L0 A5 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& i; h& g7 u1 [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! E% d" o* j4 I8 fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' {+ } e( }2 r3 K# [+ E
** Set the serializers, Currently only one serializer is set as% K2 H# @* F7 R/ I3 C1 y% u
** transmitter and one serializer as receiver.. d/ k( k! W m! I, \ d3 L
*/
( f6 B2 X( p X/ }+ \; p7 K! J8 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 j" s5 ~! a' O3 d% AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' S* E3 w' |6 N( ~# H( _
** Configure the McASP pins
8 M, c, f: u( l \9 U0 {** Input - Frame Sync, Clock and Serializer Rx) O5 i6 [) Z2 a2 E5 }
** Output - Serializer Tx is connected to the input of the codec
- g& M6 W3 I- O* O- f- ]4 Q: y! P7 p*/! q% D8 v- i( m5 Y, D1 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 F5 \" _: ^" z- ^8 \1 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& a M9 k6 i+ o* s0 CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! ]4 {- s' ~4 Y4 r/ L
| MCASP_PIN_ACLKX
! E7 Y7 |; i0 z8 S9 c| MCASP_PIN_AHCLKX
& {. l: g! U% |% w+ a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 s# u1 @. p- N7 a* M, ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, G& \7 E. a: O| MCASP_TX_CLKFAIL 5 a; q6 ^: ~1 m4 l; \
| MCASP_TX_SYNCERROR, f/ x, ^! N* U' B/ K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % b0 h! i# d9 ?0 G
| MCASP_RX_CLKFAIL
9 @9 K$ y2 Z+ {! G) b| MCASP_RX_SYNCERROR
2 m3 \: \/ |* y. ^% F| MCASP_RX_OVERRUN);
, s7 ]9 V: D7 M9 k} static void I2SDataTxRxActivate(void)
0 n( Z7 L2 Y! h1 _6 Z{
1 r9 Z1 z [# i; ^9 N d' U/* Start the clocks */
( n. Z: z' y) n4 [6 q) R, vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 w' n# r2 N2 z6 a$ E( JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
[/ {$ c& U0 {- G" uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 g# Q4 t$ u, ?
EDMA3_TRIG_MODE_EVENT);2 W1 D3 A5 d6 j& I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. O' B) t* c% U4 f2 D% e4 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 b- }1 E! z* ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" T8 H( r: w( V; G- |+ x" U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 u6 N8 J6 J( C3 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# E1 Q+ J3 o! D- K& r/ l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 w R( n |9 Z C% f% hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 a9 l$ V3 L: a1 P3 V
} . p; O+ H" ~( O! c2 G# ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. @8 R& A0 z' [) t1 ^7 m/ U) W
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