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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# ]: {% t/ e6 l# [) E; minput mcasp_ahclkx,
/ L* \7 S7 U5 {( ]/ E, Kinput mcasp_aclkx,
) b( c& C2 O2 {7 Vinput axr0,
7 O6 T9 b" z+ ~6 \" G, T& i4 k! P h& f& D0 r
output mcasp_afsr,
4 K! ^: v' o% i, a" i; u. Z* houtput mcasp_ahclkr,+ z/ P( @7 H% v; } D3 e
output mcasp_aclkr,
* c1 r# h6 ?2 Q4 {% eoutput axr1,$ d' Z& g+ V* ^3 \. X; |
assign mcasp_afsr = mcasp_afsx;
% Y* {% s3 M1 `% `; Qassign mcasp_aclkr = mcasp_aclkx;2 f" @9 @8 O) I1 q/ `) E
assign mcasp_ahclkr = mcasp_ahclkx;
1 X( _# a4 E: ^assign axr1 = axr0; - O* X. s9 L% u
0 I, a5 R5 M* T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ j) R! ~ k$ C2 s/ Y: n9 v5 B/ o9 `static void McASPI2SConfigure(void). `" A; p* E+ ]) b, a
{
* @( G# y1 X, E& ~$ I" `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ Z9 Q) @+ Z9 M4 ~" W; ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, R8 q* g- O* ~4 i4 r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' z* z. ^( M! s7 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ U, Q/ u3 X& L" }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 d2 r- E/ m) U
MCASP_RX_MODE_DMA); U5 f6 G, k0 I0 G+ B% X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 ~% i+ ^/ P3 X; G$ @! HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 E! G; Y t& i: ?1 M! xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 b* |2 s! z M8 L" |; B$ E' \7 iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ T' |$ Q4 y) ]" I# g5 g V; r: z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 h5 e; W& X% B& \0 w+ d4 ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 S; x. B$ B" R8 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ N0 |" J, p+ N3 D) mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * T ^) U7 J) o8 ~- Y$ y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 W7 G9 f& W' }0x00, 0xFF); /* configure the clock for transmitter */
/ E* J: X g0 ?! `) j9 `; L- MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ M/ s* R, J9 CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 a0 J" S; ^$ w' H9 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& @5 A I( v% h! x
0x00, 0xFF);* [0 f% i' n( d, i1 f w
+ W9 T2 u4 i, A
/* Enable synchronization of RX and TX sections */ 1 Y- O1 m; o: b/ Z8 w! A- Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
S7 T, K' o9 Z( [( }6 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' E5 l* M7 t I% h( b. a9 v5 _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- l( v$ p b/ ~' N: q3 v** Set the serializers, Currently only one serializer is set as
/ f+ t: E& Q$ \2 I. l- a- w' U** transmitter and one serializer as receiver.
# C6 A, F8 Y) a" F* s, s*/
?) x, c1 ]+ L% ~" _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 d$ Z& o" g- B5 m( Y. O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 D7 v* T9 B! `9 v: i6 m9 l** Configure the McASP pins 5 T) o6 q, r" `* N5 M
** Input - Frame Sync, Clock and Serializer Rx
- _% C( F2 ^5 V- n! I% G& Q, E6 I** Output - Serializer Tx is connected to the input of the codec
3 n }. S) d; E/ {. |: k# B*/
, T2 h1 E/ }1 Z1 g1 G% A' C: VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 p% I, f4 \( T( E5 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. W6 i; r4 `. K' {5 V1 xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; L: C7 D5 O9 r
| MCASP_PIN_ACLKX
5 q& A7 k% ]7 B+ V; H| MCASP_PIN_AHCLKX& P$ v# d+ R5 N2 q2 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* \$ ]% a. S3 PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 e0 b4 T9 p0 _1 o0 k/ @/ B| MCASP_TX_CLKFAIL 8 b1 h% D" J* Y
| MCASP_TX_SYNCERROR6 S! C: S% c: K2 T* }( E, a8 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* W) U0 W6 S, o7 w! P| MCASP_RX_CLKFAIL
/ L* ?( r5 Z# b% p9 z, _% [) E, S| MCASP_RX_SYNCERROR * n3 e" l& J: d; t7 v; ?
| MCASP_RX_OVERRUN);
' `3 Y0 g( g1 r& k} static void I2SDataTxRxActivate(void)6 V. u7 D$ q+ y+ _
{" b& d8 [7 _1 R
/* Start the clocks */) [8 m+ a" f# S+ m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, H/ e! k/ p2 B' P4 v/ k u+ s/ wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) t; _% J3 T* A& v# f* x) s1 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 m3 k8 T) r$ o& d0 w& Q. HEDMA3_TRIG_MODE_EVENT);1 z1 F- V U6 A7 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* k- }& l+ R8 ?( h# \" `3 [. [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 x# n$ Z$ {' O1 K# k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" y" }2 G: J! ]1 K% F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' b( m3 a p5 T% u+ \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 J- I1 K/ L5 l. q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; B0 k/ z" u/ D2 g% TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 M8 c9 U& A S- L2 W$ N} ' N. |* ] @6 e7 v" I: i: k( a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! A) j5 _2 P) ~8 I |