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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ `# @# E' s" C1 o! ~5 ?& Q
input mcasp_ahclkx,* v2 X7 z& k3 p( p: O: w
input mcasp_aclkx,! K9 T0 o7 P, e! i, E, c) Q
input axr0,6 m4 m7 R* ]+ T& o2 |/ [
# M6 v, q: {4 m: M, a4 z
output mcasp_afsr,
$ L( [3 o, d0 T# Loutput mcasp_ahclkr,! q2 E1 e' A% y8 f5 k
output mcasp_aclkr,
/ s$ t w/ ]" R8 Qoutput axr1,/ Z, [. Z/ Q" o
assign mcasp_afsr = mcasp_afsx;
6 G/ x7 R* M( D% `( P1 T/ o" y2 e7 fassign mcasp_aclkr = mcasp_aclkx;" E, ]0 }/ F3 ^7 ^; M+ y2 A
assign mcasp_ahclkr = mcasp_ahclkx;. S' @- h7 Y ]+ E. |+ T4 ~% t3 U
assign axr1 = axr0; 3 |1 }3 G6 O' h8 q
. @2 U2 {& `9 Z6 f7 S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ F' q, L$ W1 x: e# I, ^1 S. O/ ]static void McASPI2SConfigure(void)
) z8 Y1 T {; e1 b$ b0 ~0 l; }# }1 R$ Q, k{
' E/ {( C: I, B# r+ f: XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, Q7 W. N" ?8 d6 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; D3 p% @0 M# a2 k' V: lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# x! F; n3 `# L3 W/ qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 a) b) f+ V- B8 W7 y) wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 a9 J0 Z! ?2 C/ ~0 l% g4 V9 C
MCASP_RX_MODE_DMA);
3 j9 S* _& q, T: T" g' V3 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! H, u! @( i) Z5 l/ U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
m$ t7 F! S" R/ dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & c7 ~: t7 U" P. _ b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' W( n' t2 t$ ^6 d/ Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ E: ` Q% f. C; y( Y! m3 UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
@* j X |! @1 L* {) OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 G- I+ P1 w8 r9 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 Y& R% [2 V8 @) `) A* tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; M( A1 ~: S8 g# [# }0x00, 0xFF); /* configure the clock for transmitter */" s4 P- e/ Y) X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. [! O) s- u6 n4 {4 C1 n0 e- BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 I5 ?3 z3 E, W/ _/ s, i& m. {( p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" Z! Y5 a9 d/ I) V/ m0x00, 0xFF);
* {% O' F L* ?
5 g0 @& o( p1 t& @/* Enable synchronization of RX and TX sections */
" \& Q- T! w3 N0 @0 [6 EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 C9 M; g5 q' O& z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 c. M: Y. p! n2 v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 }% B. \1 {7 ~1 y** Set the serializers, Currently only one serializer is set as; M/ A8 L' {# {; W C1 L0 Z
** transmitter and one serializer as receiver.
' `. h$ X6 D$ z" Q) k: T9 ?) j*/: b' Y1 C7 Z6 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& M" w6 r' S' E: g5 P0 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 z V9 h9 w6 _; `( ? @** Configure the McASP pins
M7 d+ N9 g4 L! F+ J: L6 q& A: I( g% e** Input - Frame Sync, Clock and Serializer Rx2 S5 n, |: P1 Z& I* r
** Output - Serializer Tx is connected to the input of the codec
, ^$ q/ E" ~+ T1 {. k y( Z*/
/ D+ Z6 _0 c. D, b% K4 D: `; GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 a% c0 V) U9 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 J0 u0 S3 a& Z# U( N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 U- f; b/ _8 L2 P: q8 I! N| MCASP_PIN_ACLKX
0 d: }6 @# ^) z& T F| MCASP_PIN_AHCLKX( e7 C. [& W1 f7 \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
y) t! z* Z9 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 ^( t- R1 C! Y: m| MCASP_TX_CLKFAIL " ^ B& F8 C9 |! C: v
| MCASP_TX_SYNCERROR
7 F( ?! A p. X, E, \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* S9 ^* K* I- s, n, X| MCASP_RX_CLKFAIL
1 d2 F; V; J8 T3 k, E! U: j| MCASP_RX_SYNCERROR
" V4 j1 u' H. I$ R& ?1 p# O3 t| MCASP_RX_OVERRUN);" @% @' @; N4 j x
} static void I2SDataTxRxActivate(void)3 h8 @$ Q% |/ A) Z1 n" e9 d5 q* a
{- J! c7 w& b. n9 D' k( Z8 }
/* Start the clocks */
2 m8 O4 c8 {0 O% M0 J9 c* ?& qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 T3 f+ `' m4 r# q( Y$ d' r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
d" w% a/ _8 |( L4 T+ ?/ y0 u0 {* ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. R2 j+ l8 ^. G& r
EDMA3_TRIG_MODE_EVENT);0 H. @' u3 k% x4 r) i+ y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 E9 F+ z3 j3 T ^! E3 H# F/ l9 r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ ~' F. z$ V. @( d, a2 P$ {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ k& W! ^6 E& m# j' O9 h+ u- L1 ^5 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 S4 n6 L2 z0 D& w7 S; Y- uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) G3 c8 j, R+ {. T7 ~" N% R: T, d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- q; D% ~7 E( {( p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, B& q! j; o# ]- P; Z}
4 ?& L6 G8 k% J9 y- F5 u( V. T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : M% O: l% q9 v: W5 h; E' Y
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