|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' F7 _; g2 I& R
input mcasp_ahclkx,! r) ]5 g f5 \6 _5 @! w# j3 I2 E
input mcasp_aclkx,
5 y& j6 D( `" U. Q/ S4 W( j! J8 {7 Jinput axr0,
t: S a' ^" Q( h! x' m3 G
7 N6 o+ c# Y. E! h. ^) h2 Houtput mcasp_afsr,2 C8 B9 N4 o' F7 y) P
output mcasp_ahclkr,
0 |0 A1 H7 U6 z2 w7 Doutput mcasp_aclkr," R2 F9 @2 N; L2 v! v
output axr1,& c7 M7 j7 U$ V" j5 O2 s; n# T
assign mcasp_afsr = mcasp_afsx;5 n- F; \- K6 n; V$ t
assign mcasp_aclkr = mcasp_aclkx;
# q& z- I9 C3 j$ B ?assign mcasp_ahclkr = mcasp_ahclkx;6 b* m0 w- [+ r( @
assign axr1 = axr0;
# e( P z! L# Z; ^: a% q- h- S, s5 ~6 s9 v1 ~ N; N: B1 M& e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 H2 b" S0 w1 _; P: D! dstatic void McASPI2SConfigure(void)% u# f* D4 R# m5 G3 w
{% l. O6 `1 X* P' _: A- R& r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, J' X0 ?/ |; |+ ~, p. W* zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: }, k( L: |: [; A; W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% Y% S0 q2 r# Q$ p! ~) K. bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* K1 K" V8 f. F7 O4 P4 _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ A6 z8 d9 s- N# N+ t& i; M+ [
MCASP_RX_MODE_DMA);% j8 e* n# N5 H3 ^- [+ Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 `. s2 ?& [% u* T+ Y+ BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" \. m# A9 | V7 [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- Y! p% ]+ J6 c ^) BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 s/ R4 h; X& @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% M2 k2 \6 V" {( l$ Y2 m0 a- WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 V2 A1 u7 B2 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, i4 Z9 l4 `7 w: Z NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) u: r& u/ D8 b! ?" Y6 P' _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# _0 {' B$ d4 k0x00, 0xFF); /* configure the clock for transmitter */
2 h) F- Z+ z, X G/ tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" p/ @4 ~- r6 _. K8 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ |/ x O* {" H1 w( ~, f& [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 X: s0 B3 o$ i0x00, 0xFF);
8 t4 R# L& r. ^. B8 e) H
4 W0 }5 Y7 ]7 y; [! L/ n0 P2 B) [/* Enable synchronization of RX and TX sections */
+ O' v1 S6 E- f, HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 G& k( p5 R4 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% B% `0 S0 J# s: c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 L. i7 q3 _7 @/ ?** Set the serializers, Currently only one serializer is set as
0 G; m* K2 Y! q4 x) Q** transmitter and one serializer as receiver.
9 p; n% U c$ r; }( s* Z" H*/
7 {7 Y0 u# u/ Q7 W$ l3 G" NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 H2 P( I% Q; r$ M/ b7 P8 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( l( m1 K2 q# X# c6 J** Configure the McASP pins ( S; d5 I! l' l$ K! f; n8 @: a
** Input - Frame Sync, Clock and Serializer Rx( C/ w. E# t4 U) P1 O
** Output - Serializer Tx is connected to the input of the codec % V" r( w) _7 R$ Y/ f3 k
*/
$ A3 L) p$ ^" t0 s" nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 r# P5 n* H2 B% y6 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 J8 f( f+ w; P, D5 E6 G. |: jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% d. r4 }, j2 F# k. Y8 i" @2 F. b" h| MCASP_PIN_ACLKX
- C0 o+ A% X9 c; U5 [3 K| MCASP_PIN_AHCLKX5 r" O0 ~% E/ a3 h0 w$ I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& f* g9 o1 H- q/ F& q4 Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 R7 B5 a0 s" U2 r. ^; E
| MCASP_TX_CLKFAIL
l3 }% ~* i+ P# d( M! ^| MCASP_TX_SYNCERROR0 P1 w* v: _: c; B. F5 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 M5 q# ^0 l5 V* u) u3 y# C| MCASP_RX_CLKFAIL# y2 t* s: [1 Z/ l
| MCASP_RX_SYNCERROR 6 L$ l% I4 @4 w. J
| MCASP_RX_OVERRUN);
8 m- Y$ Z5 v5 a8 I} static void I2SDataTxRxActivate(void)
; B5 B$ c: D! \$ h2 a: C( H{# n" [6 M9 d4 `5 T
/* Start the clocks */
4 L; r. S2 j; s3 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& Y" Z3 g: o2 Y- bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, m# a( X' M, b8 a9 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* z z+ }6 E r( m* T+ ?' l* ~7 tEDMA3_TRIG_MODE_EVENT);
- A6 `) N: |; w, A! BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 n- t) u3 V) A5 R" S9 jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% A! `& Q$ m) G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( p1 T$ x. Z; z& E& W$ J3 {" |' i( yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) X; F* C: n% J3 I* C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ \ V9 n' b+ kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 o+ r, r8 \% sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ m5 O: J8 a( m0 Q4 G0 D) ^} ( M% X+ d: M o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! @3 U t' Y1 t$ ^2 C W |