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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, b, a5 V: \ M, pinput mcasp_ahclkx," N- y: F; ]+ P! L
input mcasp_aclkx,2 @ p% z) c m
input axr0,3 q4 s& y+ J q6 B1 U ?, A* m7 |
7 y2 { B2 @: D+ P
output mcasp_afsr,3 z% s8 G" a7 @) _. g. P
output mcasp_ahclkr,4 ~: ^6 s* z) A' p
output mcasp_aclkr,
3 M+ |/ R1 @( V; B# I9 t% G6 S( qoutput axr1,! @7 E+ @8 R& l
assign mcasp_afsr = mcasp_afsx;5 e# l- J3 W. L
assign mcasp_aclkr = mcasp_aclkx;
, w" G9 e# o e2 ~3 F2 Zassign mcasp_ahclkr = mcasp_ahclkx;7 ?2 E$ Z; K% b: m( U
assign axr1 = axr0; 5 [9 T0 X- ~6 B8 D
) J$ [' ~$ O: P. w; F1 \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * h) ~( _9 V6 }& x/ G2 W& Q' c
static void McASPI2SConfigure(void)
$ |0 N- Q/ @1 u1 J5 ?{
D! `5 l( |9 R5 D: {3 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 T0 q- {& O. {% V/ H3 D) l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 L4 a: k( _, c {% ]/ nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- h9 r% b1 V6 l0 z5 xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 u" x4 F4 u, _5 s% P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 w( H- w* L2 V1 d, u
MCASP_RX_MODE_DMA);
. s K4 m2 B" c: s- E/ BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ _) t7 t3 T1 X& x3 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. ^& u( ]1 E% G3 [5 H ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* d7 r) ~7 d& E& ^0 O9 vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" s& W4 v0 k3 I/ Z! bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - Z% i! ^/ Q+ P* \$ b9 N k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ L& Q2 |1 k& @9 [9 G. G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# F8 C4 \+ B, V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. ~1 s3 W, s+ @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( n) q1 j" q' P- }0x00, 0xFF); /* configure the clock for transmitter */
) m. r% i e5 ~! ]. q2 FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* G! P( r2 @1 i9 g" l* i1 i; I6 EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 S }/ P. u3 J/ h& G6 e: \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( i8 `% V5 r0 C0 a1 ^* ~/ J
0x00, 0xFF);% r$ D: ~$ D* n: r7 X& Y! y
% T; F; _& {) u- p6 i/ C R6 p/* Enable synchronization of RX and TX sections */
' q3 @: j6 q$ U/ }1 u/ n) @% c. oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 S9 X2 w& [3 G2 }+ B% k% \" r7 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. }! z" A. z `# oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 k4 b( k7 O6 o& l
** Set the serializers, Currently only one serializer is set as0 i" s2 S" b& Q/ k. P. V
** transmitter and one serializer as receiver.
; }# r" u8 p! t, B*// v9 U/ v- u/ o. V0 M6 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! W5 P4 @# G# O6 [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! G1 ]9 O2 A- d5 S; j, p. n% X
** Configure the McASP pins " Q1 S0 b* i3 z( O& ^
** Input - Frame Sync, Clock and Serializer Rx+ p8 {# E7 n- K) Q
** Output - Serializer Tx is connected to the input of the codec # k4 B) u- x9 e" E0 y
*/
* u n7 W9 `3 y9 Q: y; c) C8 C% jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( w& n5 P1 i. q4 r3 o$ r2 C; N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: f" t' r% W2 Y2 B6 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% {" i! `7 M3 _! D2 ]4 a; |4 ^/ r; O
| MCASP_PIN_ACLKX1 z+ h$ f; C# ]0 `& R2 E/ m7 x4 D
| MCASP_PIN_AHCLKX: i1 _ y1 A; A) y7 g* N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 Q# h4 a9 k& v" _% x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + |+ \( ?6 X+ J) p
| MCASP_TX_CLKFAIL
( m; }" @+ S' b| MCASP_TX_SYNCERROR
1 v- _ M3 H3 p4 N! a/ O3 n5 X, t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# {) j0 i6 q% L| MCASP_RX_CLKFAIL( V' v! W& Z. @& v- e9 C* h, O
| MCASP_RX_SYNCERROR
0 a3 s. B# K4 J$ R# @9 L| MCASP_RX_OVERRUN);: i, e+ O8 Y5 N# K
} static void I2SDataTxRxActivate(void)0 e$ v4 e {4 Q& V! F
{# ?/ l: r8 Z% b( X4 L
/* Start the clocks */
; r2 c$ ~) W+ `) {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 ^' N, n5 E6 x* ?1 I0 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, n( ^: V5 S4 i, l" x) i! y) a' [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( q( ]1 c* W; Q
EDMA3_TRIG_MODE_EVENT);
% y* o/ ^1 J( \% |# [- e. K$ b2 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
h8 Y. b4 k. t6 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ n; u. J2 Y4 C$ L0 F* _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 ]/ g0 H- ~1 K/ V kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. B+ |4 f: y/ R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 P6 }) z+ E* c4 C$ |+ c" Z- s2 q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* T* _: T1 s* p- N! u6 C. M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 ~ b# @$ e1 Q
} # G! Y$ P5 _. V- t+ `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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