|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! N7 i7 q, z7 a* K* Oinput mcasp_ahclkx,
" U' z0 i2 e% ^) ^! E3 Y5 d9 Winput mcasp_aclkx,
4 k% C. j2 k6 m( E) ^2 T% ^input axr0,% i4 w( R( k4 _- A9 o$ q N
8 W* T+ n' V1 J% ^: h- Toutput mcasp_afsr,
- x( Y0 r( t/ ?0 ?4 Z8 S voutput mcasp_ahclkr,
y' C: I0 E: coutput mcasp_aclkr,
' S, T) h3 B: d0 Coutput axr1,# u4 W" M6 |; _$ T' K! f; P
assign mcasp_afsr = mcasp_afsx;$ k/ r& _) ^# M% t: @
assign mcasp_aclkr = mcasp_aclkx;
$ U0 O6 j1 r& `8 h" R( u1 p; ?assign mcasp_ahclkr = mcasp_ahclkx;
* {8 ^ n. l9 n4 l1 p/ ]; Tassign axr1 = axr0;
; d, x/ n. P( s
$ t8 A" _: h0 C, o! ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; [4 {; X; K& m; Bstatic void McASPI2SConfigure(void)- q4 O3 ^( X2 u u
{4 v6 V, M4 a" _6 I+ P! o- O$ B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 H+ I6 T$ T" U0 j1 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& K! e' \% d8 D4 T* M; D- u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 J( t2 O" y2 V& d" t: ~8 WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
N1 Y# c" z4 ?% |0 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. @4 H+ t. N9 RMCASP_RX_MODE_DMA);( h) }9 ~5 F% q( V- f, a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# `$ |" M! Q \/ _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& k* y8 }- T: L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 G3 N2 ?9 j- x. q; M; LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, H% @ O, p% ?$ l7 U4 N; t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* d7 c* O! M) F' bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 J4 m0 |8 I# ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 s% v7 s: Q" X, X7 yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! o. U$ W: t% G0 t. c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 x6 g; Y, M3 u5 e7 m5 W/ u9 ?0x00, 0xFF); /* configure the clock for transmitter */
9 d1 G" E$ C, v LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ @ s3 m% V2 M. ]2 {% H8 w, KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - t' N& j/ m4 q. Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 x+ g/ Q8 C2 i( _- Q0x00, 0xFF);& k7 v! X: Z0 \- M1 |! w
8 w' L$ L& N$ z; `/ L2 c5 N4 A" Q
/* Enable synchronization of RX and TX sections */
. S: q4 i3 ? v9 o/ B( [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 c; ^' [$ C% | I- D9 {6 l7 o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 [7 { X* x; u0 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* _. G d" L" h8 u3 M
** Set the serializers, Currently only one serializer is set as+ x- |0 i& A; Y) B0 _
** transmitter and one serializer as receiver.
& O7 ^: T: Q9 }# [: y5 Z*/
2 _1 c2 j& f s4 F3 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- I) M+ T/ N0 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# v7 b1 Q _+ B. a
** Configure the McASP pins
# G; ]' [4 V% u) q. P7 [4 P** Input - Frame Sync, Clock and Serializer Rx
- }- u5 O) L; w3 c8 \! q** Output - Serializer Tx is connected to the input of the codec & w; G7 b3 z" O1 c- h! ^2 }* e% z9 Y
*/( j; e' g0 t& E2 f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ Y6 G6 ~, o5 f7 G% N3 }8 ]2 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 m4 T, v1 j4 v3 Y9 f* g0 YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ l" ]* I8 _6 j& u( l) z5 W| MCASP_PIN_ACLKX
2 x* `4 k3 @$ T$ b ~; [9 R! e| MCASP_PIN_AHCLKX
5 @' T* t6 x7 y3 e# k5 X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 b/ d% P- ]2 a9 O; }7 h y# ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : o; Y" _; o7 a0 W$ ^
| MCASP_TX_CLKFAIL 9 ?: D1 S' _+ |% D
| MCASP_TX_SYNCERROR
9 n" S/ F4 M* e6 Q% _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 C J: o. W( e* j! A
| MCASP_RX_CLKFAIL1 ~7 D2 H1 o7 f# R* P3 K) z/ G
| MCASP_RX_SYNCERROR * Y: X' ?9 J# R! f8 h" d1 Y" d8 D( V
| MCASP_RX_OVERRUN);
7 x; g2 p9 p9 \8 ]* X9 m; X} static void I2SDataTxRxActivate(void)% j$ o( P- {0 V2 a8 t5 L
{
% W$ q) m0 k; l6 {- v% k/* Start the clocks */2 k: ?2 j. x6 V# E( q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. q: h, y. O% A6 X9 p+ z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 d1 i. d7 z$ t% R% c3 a( \) O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 p0 Y! z( E2 O5 l p- PEDMA3_TRIG_MODE_EVENT);8 x, a. Z6 G. z2 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % N5 N& s' g7 B( V- `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
b1 g& J; I9 L9 P1 t" h, S* F& gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 L0 _0 s( I5 o) PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& O; `( M; m4 b8 R# ~% o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 I2 V" z9 G) W/ x! j1 U a2 a* ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ i$ J0 c) ?& ^! z rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( J7 \5 \ P w4 V
}
: S6 |% h2 u( N8 @# E# s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; t7 P/ F" X- @; d |