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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 Q/ n/ }8 s. o" w5 w* Linput mcasp_ahclkx,: I6 J1 O6 {% n/ P) [! b. c6 a
input mcasp_aclkx,0 r) y2 h6 S1 b. A
input axr0,1 w3 r1 g) {+ z9 M& j7 {3 p' I
) ]; b' @% e' H& q" f1 r/ J$ Q
output mcasp_afsr,
( _0 J2 o: J- v) J( d8 q) r! [: ?$ Loutput mcasp_ahclkr,. q t& [$ c# a. J4 s$ E+ h
output mcasp_aclkr,- r5 a6 h9 e$ P- A
output axr1,
# W0 i9 s9 w) V! \3 a assign mcasp_afsr = mcasp_afsx;' M$ v; @) \& U2 p! k M& ^0 J
assign mcasp_aclkr = mcasp_aclkx;/ h. l3 B/ o1 {
assign mcasp_ahclkr = mcasp_ahclkx;
/ Y; y8 e4 r, o6 Massign axr1 = axr0;
, l+ w3 [, I& I5 Q/ f: H5 }; C) n4 \" Y+ W" O- V+ o; M* V9 R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . K" o: `; P( g. r6 z# z5 L& \4 h
static void McASPI2SConfigure(void)0 x5 q* H3 x1 z( A
{# F- J5 l s3 ]( {2 b/ j$ l5 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; J! e1 e+ N2 U; ^& {; a: _' p+ j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; T7 d) o9 I* U. X% DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: U: r& B- {; wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 U" a$ A9 X# v; s+ Q! b' a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& h- o; r" s8 ?! Z, Z& @1 B Y) N
MCASP_RX_MODE_DMA);
0 P8 _+ N7 ?% k2 i4 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! x/ S3 T3 F0 R& l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* Q- z6 G2 f3 Q) W) K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 R# C$ _' e& w7 z' Y/ H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 h' ^9 q3 I; ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 m9 k- Y& L, Y: n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 `% f8 J5 j5 V( l3 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 ?* z- k8 k6 ?$ f$ i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) W2 h! e0 a& R" x6 ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) m* R" A% H3 X3 ]; K, M0x00, 0xFF); /* configure the clock for transmitter */# P+ c. D+ P- C' U7 j- Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% g' I% A+ q7 u; U( a! n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & T9 T C2 D# l4 k: [4 M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 D* }) L# ?+ r
0x00, 0xFF);
, D. Y8 K8 W7 n# r9 x' f0 q1 i9 C5 s8 W; Q
/* Enable synchronization of RX and TX sections */
% S+ y1 d& X2 r% d: a: m4 p1 e( a) [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, D9 j; x9 ^& D( q5 f5 ?+ AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) Y& i3 i; [. E9 H$ k! f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 E8 k! y+ v5 Y# D( n* G Q* f** Set the serializers, Currently only one serializer is set as
( E; `5 C% J% s- i) D. d" g** transmitter and one serializer as receiver.+ x7 `/ d7 f4 N8 G* Q: y, ]
*/
) I" J6 j! i! c! M- k$ _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! U g7 j9 m, C5 k1 M- A2 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' ~( A& T8 R% |- E! [$ _- Q** Configure the McASP pins $ i# Q ^5 p" D& U% `0 V. f E
** Input - Frame Sync, Clock and Serializer Rx& r: O& g/ d# m2 F" G# }
** Output - Serializer Tx is connected to the input of the codec 5 `2 R1 I3 y+ D% n
*/
6 ? [% x, l, e, N5 {/ \4 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( _6 h4 @ _7 i4 q' X( x- {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# R* {$ b0 e/ m6 C. t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 f4 ^7 B; b$ ]8 @/ B( K z
| MCASP_PIN_ACLKX
% |& o7 H2 V2 g# p| MCASP_PIN_AHCLKX- H* s& o+ ?% N W8 c/ m7 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 d6 ]: E- x1 B1 g& A g/ sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) a$ \5 W2 W6 |" K) e; v
| MCASP_TX_CLKFAIL & U ~ H4 h8 _
| MCASP_TX_SYNCERROR7 w; {) m" d& s; M: X# m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( ]& w/ _# v# m1 X0 W4 e; X0 i& ?
| MCASP_RX_CLKFAIL
5 ~: [2 S; g2 j* [. |+ J| MCASP_RX_SYNCERROR
% s$ Q6 e* x, R| MCASP_RX_OVERRUN);
& A4 B, Q0 b% V, r/ ~3 @} static void I2SDataTxRxActivate(void)
" W% ]7 I B2 r% G{' p) S5 }. ~9 W$ p
/* Start the clocks */
Q5 B$ H4 m! x/ qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
Y# i# I5 D7 m5 ^# X0 xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 T/ A. H& h- L1 o& w6 m- A1 i& c* y- s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, y( {/ E6 s% h; o9 P5 ~EDMA3_TRIG_MODE_EVENT);3 s7 k! H% P, ^! ~2 c$ A, ~8 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 E |5 s$ w2 f7 ?& H' q$ H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ F }1 V$ E! m) V7 k& A: LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
p6 R W1 c" l7 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 D$ p* F3 p# ?/ i2 S4 hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( m) ~- B4 L/ |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. u- o* B, ?0 k- s3 S& `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, _# \6 l4 G( H& G) w" r! J$ C7 l
} 7 g9 ~, a/ A6 L- u* \' E! w' j* v3 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : I. X4 O) l* T+ |7 j% x
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