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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 z: v# t$ ^9 ]
input mcasp_ahclkx,
) j2 @7 n# l* ~. a- }( Jinput mcasp_aclkx,
+ F- P$ ?% _! o2 t5 q+ Oinput axr0,; ]# \3 n ~0 ~9 H
* }" w5 Z5 C, T/ k
output mcasp_afsr,6 ^% C% h+ o0 I) L
output mcasp_ahclkr,
# e; z* r% G: ^/ o5 B7 toutput mcasp_aclkr,9 r- k- a% A2 a. ^+ |, Y
output axr1,( K, E' Q' @7 O6 o& N, c! C$ V
assign mcasp_afsr = mcasp_afsx;
8 r, j+ J O6 N( J5 q% `assign mcasp_aclkr = mcasp_aclkx;# U" p* g' \6 c' R) |% f
assign mcasp_ahclkr = mcasp_ahclkx;
! n2 P- N: k' `1 G% X. j& rassign axr1 = axr0;
4 v$ @+ n9 i+ b2 ]3 @$ e1 ^ ?
( L! l& Y. W( m3 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 f7 ~9 ^# K* j7 x" L. @static void McASPI2SConfigure(void)
: v8 S% Q7 g& [+ Z) I, N{
5 c: E; ^* Q m P/ Y n; NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 G: O7 W: C: H0 W0 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
}; d8 d. M j" r" W5 gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& f" e# O5 j& f0 v9 }5 ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 V2 S* D2 w) `3 B( M9 EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; d2 ?5 V* P) o- l8 J
MCASP_RX_MODE_DMA);/ o8 Y9 U2 U; ^0 y6 u% F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," k9 w" c$ F( Y$ C4 J# t# K* W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; A7 \9 P9 |0 a- h9 g5 T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 ]$ d7 A1 d8 s; F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 s6 n7 \, r. @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( C c# M# p/ X# U' a, hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- f3 E0 t; ^. g% iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' N h/ G) c: a- E9 Q% `* l# Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' X2 v0 o0 ~: \4 \0 Q) @+ ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- t( `1 p" a P2 S6 e$ p
0x00, 0xFF); /* configure the clock for transmitter */
( e/ F- ]9 B, m: O) `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, i& ^7 ~# n( h/ z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 q3 n( P* R' a" M* Z" U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) D* F- @6 i1 B, E% |
0x00, 0xFF);
" e$ U/ a2 f* P6 x, z" p ^) ^5 q0 I2 u
/* Enable synchronization of RX and TX sections */ 2 V7 B4 g! ~4 z, Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 s' h5 [ P, J. s) r. e' JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 L+ n! e) }$ r0 Q0 {& C' b! ]" LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* V, W4 j( [# |
** Set the serializers, Currently only one serializer is set as
$ v" [; t- ~( Z7 |! O! H$ l* E** transmitter and one serializer as receiver.4 J! R1 ?# G! \" [! z9 J/ p8 [7 A
*/, k5 X8 N* r/ V. Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& {8 Y! o9 ^6 Y# w' CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 E f# y. _0 q* N
** Configure the McASP pins
) E' G& w' ]/ p: ?** Input - Frame Sync, Clock and Serializer Rx5 ~+ j" G3 s: `+ {# k/ C
** Output - Serializer Tx is connected to the input of the codec ; l5 K8 S) ]! J' ?
*/0 h1 t f7 S# |) R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. z. j7 d# S* OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* F' L$ F6 }1 y; q& yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& Z# C9 H1 @ P0 J0 E' s| MCASP_PIN_ACLKX
/ p5 h8 R8 N% [: x5 }3 o* {; S| MCASP_PIN_AHCLKX
3 M' r9 C2 A+ v( }$ V& O# B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- g4 v% N, i+ i- \0 w% w( t& }) h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! i0 ?( ~2 L6 t: i2 v
| MCASP_TX_CLKFAIL
6 h' Q, D( ~/ R% L _| MCASP_TX_SYNCERROR
2 l0 k s& d1 @9 h, \% H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% }2 {8 j; L0 }2 Z& ?, P| MCASP_RX_CLKFAIL8 s- A7 {5 _1 K$ z( Y; N
| MCASP_RX_SYNCERROR
" e( `: @+ j( O' f' N l| MCASP_RX_OVERRUN);
r" I: @1 i' b K" X, g} static void I2SDataTxRxActivate(void)
8 e# Q) L9 o+ |3 n1 U{7 P: T- C5 e% ?4 a
/* Start the clocks */
/ F& @: n: H- o0 ?- _, V% WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, x6 F+ ]. Q# G" e3 ]* l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, m! o; g& A4 H9 P1 ^5 E1 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 Z6 U+ {' Z% i- B
EDMA3_TRIG_MODE_EVENT);
B6 N% b5 q- x( C/ E: dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( m+ O* ~6 w* J) J2 j- f" O, pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ \. [ |7 Q* C% ?2 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% o% s4 b1 Q5 W( G, M H9 ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" `: S3 z( j v0 e+ X/ h* }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- c( f: y6 ]6 l* n, Z/ o8 F- ^2 D% qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( B; T. D! R0 b9 }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 y: ]# p+ G9 m, r}
2 X1 F. r2 {5 f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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