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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 D) V7 E4 f9 j# |8 {- `' ^
input mcasp_ahclkx,1 f3 K+ N7 m8 m9 p
input mcasp_aclkx,
+ S0 d U2 @( s/ V+ c2 sinput axr0,
4 m' {+ X- l, G P- r H( y4 i
3 p8 k' b$ j9 X6 b" x, joutput mcasp_afsr,8 f: s' ?4 b; _5 J, G# _: r
output mcasp_ahclkr,2 R$ [6 G. k. X7 N
output mcasp_aclkr,$ T$ [5 ~- ^+ K9 u$ s4 T3 T
output axr1,* b* Y- k c) B: e
assign mcasp_afsr = mcasp_afsx;
. l9 M3 d& R- J- L+ k7 R$ Nassign mcasp_aclkr = mcasp_aclkx;& u$ v: h3 _. U) \& e
assign mcasp_ahclkr = mcasp_ahclkx;6 D& L% v, i8 x7 ~$ @% Y
assign axr1 = axr0;
- ~8 Y6 Z& W8 E" s2 a3 Z, A) p8 Q* A L- M4 P$ K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 h: n" L6 M1 e6 m& W2 S! L
static void McASPI2SConfigure(void)# { n1 L5 d" G0 r( R
{
+ T) b. R6 c. } pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 t2 S( S" G7 k, {# XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- k- p0 V" H8 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 x8 `0 v9 z v& r; A8 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% f0 p; U; y9 k( R' L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- {( C3 e3 Y& k' Z0 w
MCASP_RX_MODE_DMA);4 G) I& J5 ~2 ]: C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! L* z" P' I; U' {8 Z. YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% R# k3 h$ k& W6 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 z; H4 E" d2 a: i# d* w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 v& k; N% }- G$ B3 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 j* f2 e! N7 \* L" u. T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 t" W, o! I9 q9 ^1 d2 `5 |1 V+ ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 f5 q% M& {! {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 u$ {$ W* w% w( d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 k+ v. P& a: S: @
0x00, 0xFF); /* configure the clock for transmitter */
+ h# U8 H" A( p q. @# Z: CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& V6 M) M& n& U2 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ E: T0 ]9 ]- t# J5 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 h9 W V) ~# e7 O! I V0x00, 0xFF);/ @( Z' \! }1 }6 ~ {) a- _4 c
/ }4 y8 `$ P0 v/ X/* Enable synchronization of RX and TX sections */
1 P6 z% {& q0 f- VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* u, f! J% u& z8 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 r: L4 j* s! q L% aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
g5 `& h" u, D, X$ T- u- o** Set the serializers, Currently only one serializer is set as. h& K+ N6 i3 m
** transmitter and one serializer as receiver.
, P# A% M6 q m/ f- N*/2 _; i( p+ A5 \% ~6 o* V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( f) w' _, c! k% [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& @$ `: ?4 p( K% |/ [
** Configure the McASP pins " G0 c, n; M- s/ _: m1 `
** Input - Frame Sync, Clock and Serializer Rx
" T" W1 t: f+ }8 l3 E** Output - Serializer Tx is connected to the input of the codec & c6 @- {; W1 p6 o# o' J
*/
6 W: K$ V! G: ?! r3 U* kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( L+ x; ~+ k) e* f5 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& d% f. ~( h( L0 l6 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 @6 i3 V, c+ |& p4 Q4 S1 p+ N( B
| MCASP_PIN_ACLKX
" G3 `6 c1 [% _* h| MCASP_PIN_AHCLKX
% V, D& n, ~- m9 j: Y" |. E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 p1 L& p5 v: v8 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 m' E# } Z# e& i @- ~: p/ B4 ?: {
| MCASP_TX_CLKFAIL
' d2 B2 f+ }3 O9 `/ N5 ^| MCASP_TX_SYNCERROR
6 c; e7 B: y _$ }% ?9 Y1 h/ t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR [1 E6 Y" {# q( ]1 f' d& O2 c
| MCASP_RX_CLKFAIL
- Y; w* q, C8 N$ p1 v( O7 s) W| MCASP_RX_SYNCERROR
5 D7 U1 h& r# p4 ~0 V# c3 {| MCASP_RX_OVERRUN);
8 @1 ?9 O" x# j% K7 G+ I8 h8 ~ e$ M} static void I2SDataTxRxActivate(void)1 o% u2 S4 q" l; T
{
* D; R8 _0 J y1 Z8 R$ w/* Start the clocks */
7 {; c$ Y/ {9 fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 V1 J$ y" `7 t( V$ A( g& n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- ^ v3 @. x/ i& F: ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 d! y) l* @% W, R" sEDMA3_TRIG_MODE_EVENT);
- f3 n1 P5 X& D. {$ [5 }9 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' l+ Q3 ?# {1 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, I0 g# S1 \" E! s$ ~0 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% p/ d- N1 C# dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 V4 U! c' X0 c& j6 D5 `) {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ i# D) l) q! f0 |- e8 _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' x$ e0 m% x! L$ Z9 D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ z$ Z0 t" B$ N+ A/ z$ o
}
% z/ X" t1 i! w4 P g+ S( O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 q/ L6 |$ J. `6 o
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