|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 }& n6 w Y8 f1 G, B4 f1 q
input mcasp_ahclkx,
, r1 |/ X4 i$ S8 Ginput mcasp_aclkx,! F7 S Y6 e' r2 ^% f% F# e! U/ P
input axr0,
0 f1 s( N$ @" z- v' m8 U0 R8 \' V4 D
output mcasp_afsr,7 e9 ]5 c+ d f7 M: C8 Q0 }
output mcasp_ahclkr,% u9 f" f9 X$ Z1 B. p
output mcasp_aclkr,
' J% i+ z6 X" u4 Aoutput axr1,. N5 Q- g1 Y( K0 y1 I# m
assign mcasp_afsr = mcasp_afsx;
' O/ k. V; V/ [2 \" q2 Xassign mcasp_aclkr = mcasp_aclkx;7 Q* z! {+ y" _9 _5 i) A a& ]. q$ _' ?% T- }
assign mcasp_ahclkr = mcasp_ahclkx;5 i1 Y5 d9 @0 b/ y5 [3 {: E
assign axr1 = axr0;
+ l& a: o P& k/ A* d _ A/ u( g2 W; l i7 p& m1 i# |8 Z. m3 D1 f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 {( s6 y' z; Q& {! s7 O
static void McASPI2SConfigure(void)7 X0 l8 T% t0 e. q
{4 O8 ]" J* f" r0 M; d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' U% |5 k2 {$ I" @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 m; ^3 ^# k4 g6 k0 G {. A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 ~. n& V3 n6 S6 t4 B3 J* d& w" m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 Q+ H5 p3 H: m) g7 ?/ T" lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. [% K1 e5 g- S! Q' e, hMCASP_RX_MODE_DMA);
) f# ?4 W1 ?; P9 G4 @: ~" GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, o# W( G) A4 W/ ]( A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( r+ Y$ z) `6 R3 KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
s4 n8 G4 |4 c+ z3 c& ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( _4 R& C7 B9 ]* {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; z1 f1 O* w" Z) l3 U2 C' WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. G, X9 w, _3 @+ D3 r- f# V$ mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ V, k. I C# k. {) xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( \ K5 ~7 m. x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, a% v8 i) `4 S" ?* f3 {" G0x00, 0xFF); /* configure the clock for transmitter */
/ j0 K! y3 u* f! U# Y- N: wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( N2 y& u! s, e; w) T+ w' L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : Y$ D) V8 [! b" {4 s$ m9 S6 v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# I9 X {) W8 x, |) C
0x00, 0xFF);
, Y" n: m, a4 ?" V" c. [, y9 O8 q) G, V! a
/* Enable synchronization of RX and TX sections */
8 |& C' X$ n( s( d l3 qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 A1 G% v* W: a3 b! e% M! NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ y6 h. Y% r8 }' [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 k2 ?! V( C$ }, h- O) V9 G0 u** Set the serializers, Currently only one serializer is set as+ E5 S) ?+ C0 _2 K+ _1 `2 r* h
** transmitter and one serializer as receiver.( I; v0 x$ P ]6 L
*/
n( i5 k5 X; t/ gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" B- h8 U& d/ P3 A5 o( r) s# qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' U7 M; q9 A4 X; x
** Configure the McASP pins : [6 l( U0 K& N; M. L
** Input - Frame Sync, Clock and Serializer Rx
6 b, u% y( m& m7 m** Output - Serializer Tx is connected to the input of the codec ) c7 n2 [1 t4 e5 W- q7 C
*/" h! k# R3 ^2 `$ I6 f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ G2 K& {) |; g& Y/ V2 E% d0 x# X# MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) ?" G n% ?; d6 h; ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 I* C' d1 S7 N4 b8 Z% p& }
| MCASP_PIN_ACLKX+ n+ k K f4 X& x" ~( b
| MCASP_PIN_AHCLKX2 f; w/ L0 `$ C" \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 l. l7 }6 p) [* r) Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & T& u: s0 \5 a" y) u a" u8 _
| MCASP_TX_CLKFAIL ( a# t! j; C& n) l
| MCASP_TX_SYNCERROR
! W3 B# H1 D" }- L u' ]$ R" || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! A. B+ i* i/ s& B8 \" w$ e; w- w* G| MCASP_RX_CLKFAIL$ l( |* o- a0 Q* X4 _
| MCASP_RX_SYNCERROR
0 f) X' c+ q' ~- y5 _6 b5 z5 p8 h+ `| MCASP_RX_OVERRUN);
' d; U0 a3 n7 p# k% V. }7 ~4 {} static void I2SDataTxRxActivate(void)
: J2 k* |0 f" Q{+ j4 o* A7 Z% @/ C8 ` g" X
/* Start the clocks */% m/ K+ ~ Z; ?2 A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) \, ^: @9 ]" Q+ X4 @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 U* Z4 u0 V K- i2 z, zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ B' Z% }8 _9 v) _
EDMA3_TRIG_MODE_EVENT);
" q l6 i; f( W7 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - B" c1 t" P |5 B4 ]' ^1 `5 O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, v( ~6 @6 d1 N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 ]8 f$ [ B' p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 @. @5 r9 u$ m) J7 I9 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. O( p! h5 G( q' |* OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( ~, x6 S( ^5 d; VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. |! e$ r* N; H) P3 B}
- R' `; n% c: t6 i7 q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 K1 [& L, M9 b8 A5 G$ v+ | |