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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. q# r$ G- p Dinput mcasp_ahclkx,0 W m1 ]' P: G! A7 X+ l. `' J4 `
input mcasp_aclkx,* _: u7 e! _/ _) D, T
input axr0,
# P3 \' L( i% q% l
' P' g: L" Z; [) X e- v) Z" qoutput mcasp_afsr,( I- |" N7 y; I# n) r& ]/ c7 N
output mcasp_ahclkr,: J! F, Q' p# E, ^
output mcasp_aclkr,9 B, ~/ O& N s" r6 M" D1 J
output axr1," ?- I/ n* _4 y& ~) y
assign mcasp_afsr = mcasp_afsx;9 }0 {7 f) }3 z/ ?
assign mcasp_aclkr = mcasp_aclkx;* Z3 Y. @6 P( A1 j2 h4 b& | |0 h
assign mcasp_ahclkr = mcasp_ahclkx; t* s w. o2 A9 ~) I5 P
assign axr1 = axr0;
7 @1 k3 p+ b; Z4 M0 z' l# w+ S! x/ f8 H. q( @6 O; v- |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) p. g# ^- t4 Q) W* t0 dstatic void McASPI2SConfigure(void)
6 z1 k+ t% Y( |7 w+ H/ |4 U( [3 h{$ @) t4 M& e& r6 y% H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 U6 ^: s. o5 w! e: z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# E% s' v% \6 v. ~ |" w: f+ JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 P( D. r$ ~6 T* x, E$ @2 LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, o, y, w1 \/ a! W& Y- }0 tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 i. _+ R9 [6 S F. a3 P% n
MCASP_RX_MODE_DMA);
0 E* @0 I+ w! GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& S2 g& {& G' O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 r' F. F7 ?) \) A: n4 G$ ^8 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' @% }; a9 H# u5 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 _- O, O# T& ~* b: l1 @' eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; l5 q& v& V3 w; c/ X; ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ w% W: Q, D. r& J# g% ]. c% G( ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 @' \ P3 e5 J( [1 t- M0 `) s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 U7 |' S5 U& t! B9 e0 _, n1 M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' I6 B! O# { l; R& \0x00, 0xFF); /* configure the clock for transmitter */
4 }6 h) Q+ L( C& c: \, PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 s. W" |5 S2 [! o1 L6 T# k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( J- V4 I8 ?# E+ RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: ~7 p6 O. @% d& I% n- G- ?! z0x00, 0xFF);
. B6 r* p- R4 l( K% ?3 k( k9 A3 O8 d7 }
/* Enable synchronization of RX and TX sections */ ; Q4 z! W! K& o9 o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% L& S; \; a1 ]6 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% S6 Y1 e; C5 z+ u+ f) Q' `" y) T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 n) k/ h+ n& B( c8 c** Set the serializers, Currently only one serializer is set as
0 S/ H( l8 _( c% O5 |** transmitter and one serializer as receiver.
6 d* e7 E+ r* _7 a*/
, N7 Z6 n, W# r' Y* [5 EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 y/ i: r' g" w. s8 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& v; b9 X( u6 M: ~& z9 a b** Configure the McASP pins
+ Q$ I: z. E. \) D1 L** Input - Frame Sync, Clock and Serializer Rx
! Q/ n, @! | P: M2 |** Output - Serializer Tx is connected to the input of the codec
8 s3 p+ u7 x9 F/ K* }* N*/
, U; F1 ]8 c6 G- X4 e0 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. j; |, Q% r3 `' R6 \' l% QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 ^! m8 k' L `6 I, ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 ?( {9 F/ b1 S, K| MCASP_PIN_ACLKX/ I. b! k7 w( z6 V9 J
| MCASP_PIN_AHCLKX
$ H: o& d; \) b- P) y8 I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, r( N% |9 y1 Y' `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 a6 ]! U5 c, ~4 v( || MCASP_TX_CLKFAIL
! a d: _: R% A| MCASP_TX_SYNCERROR/ S8 R! j. I" G# Y4 u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * u) z& a" a: Q4 N" ]
| MCASP_RX_CLKFAIL
- a1 |' Y, t( T% Z9 o| MCASP_RX_SYNCERROR
* O$ A% B7 d* o9 J( d, I| MCASP_RX_OVERRUN);9 M* D0 E: u# m: E4 M: s9 Z
} static void I2SDataTxRxActivate(void)3 @( {' N- k* N( |$ F4 r& b
{
" r( Y8 c) R- x( t/* Start the clocks */
' m# ]8 O' B, o# uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. h) v) T1 V8 e/ D4 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! X6 x3 i0 u G0 G" c1 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! n5 p6 R! g% E- E% E% W
EDMA3_TRIG_MODE_EVENT);- O. B/ q6 K+ _- P, |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 z5 w& T7 |( k2 [4 f2 x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 M, T2 n" D" \; g$ b0 \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% X5 A- I; S' h5 BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) _5 z' u- O1 E/ }2 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 @7 ]* C5 e' \# }& g9 `5 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 G7 j2 `- W$ \6 K; l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. C' _1 R+ v, L
}
/ \3 V k h2 L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' q4 m6 n$ k) V1 `& M
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