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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) ?) u2 B6 v7 Z4 p
input mcasp_ahclkx,3 o. f2 h% K: C) [2 y
input mcasp_aclkx,
5 ^/ P ?4 U4 X Vinput axr0,0 }4 {; o# Y) q3 ? x9 |# n
0 Q3 D T# j) J) J5 J, Routput mcasp_afsr,9 [! x& W% B0 k
output mcasp_ahclkr,
, f1 l( c" b" K/ J. _1 Eoutput mcasp_aclkr,
4 m" K- v9 s) Z' A7 y9 G( aoutput axr1,
+ ` Y0 r8 D1 z/ B2 g( j assign mcasp_afsr = mcasp_afsx;
$ H% G: ]; S8 S; g% ]assign mcasp_aclkr = mcasp_aclkx;
8 [/ T1 j7 @" N' m* G8 `) sassign mcasp_ahclkr = mcasp_ahclkx;
2 o. z$ f: d# ^$ }' xassign axr1 = axr0; ! [2 _; o1 h( g
# J9 y1 t0 U# N6 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 k9 K. r* L- @static void McASPI2SConfigure(void)# z3 b1 O4 a4 m3 x0 s
{) I: _5 q) n: u2 j2 s" a8 y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; ?8 b) x% x1 e( TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% b& I/ _6 L+ |' p! C! v5 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, H) M" B6 h; q( g& w2 m8 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- @9 c8 y* d" V( T! r& L6 ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# r$ ^. [, `2 fMCASP_RX_MODE_DMA);" ]) ^2 c* m# }6 X, ?3 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; V/ a' K0 g/ \# ~9 u, Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* z, X0 [% G' I2 s/ M3 JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 g' M! e: x) ]6 E# dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 W. N1 q7 @# u l8 G: mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + ]3 u$ K9 }2 k5 g( \: ], H+ M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! n( T( Y/ W0 i0 S0 ~" r: x. CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 v9 |6 v6 A" I7 KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 |+ ?6 P# Y6 W+ TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% f( I; N( T8 |& w y
0x00, 0xFF); /* configure the clock for transmitter */5 U7 o4 Y# r( w& Q6 w4 v) O9 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; P2 v1 a4 ?" R$ `( ?8 m5 w/ O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + b, o2 E! |9 w' W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' }8 D) b& K8 J5 H3 T! `0x00, 0xFF);1 Z4 F5 ]9 a6 |& v( ^0 k; I `
6 k o3 m" c. `8 j* e5 S& [/* Enable synchronization of RX and TX sections */ 7 {' A+ a- N+ Q+ O, ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ }3 T, R4 W. @1 V; D! `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 h0 w. s7 w* H2 `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* f8 p+ [/ [3 G% c
** Set the serializers, Currently only one serializer is set as
1 c: z& M) h! \7 K% e6 z' T- V7 V** transmitter and one serializer as receiver. k' k3 D; Z. }: y* Z1 m+ e# [* C5 b
*/
2 p5 r' w% ~: R: RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! C; r9 O; Z' H( [: Y( ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) W6 E8 `0 e( W# |! {7 j0 N; w** Configure the McASP pins ' h, T8 I n, N% m: J( q
** Input - Frame Sync, Clock and Serializer Rx
( u8 X2 v! r$ b6 r- T7 e** Output - Serializer Tx is connected to the input of the codec / k7 l$ U: n$ y5 S
*/8 j( R w, n2 a+ x6 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( l3 z& b( U9 N7 y# {: R+ RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 U5 A& V }5 k) p. h# o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ S, q" v0 S9 W, _) k6 l! \
| MCASP_PIN_ACLKX
, R% Z5 K% j. X+ y* {| MCASP_PIN_AHCLKX9 u9 f: S7 k/ r9 D6 q1 T: G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 @+ [0 L* s) @. B* X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; N! P: e, J7 h" O
| MCASP_TX_CLKFAIL & c9 K+ ], g4 z, ?4 [
| MCASP_TX_SYNCERROR
: P' p w, m: s& Y/ s* ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, ^0 d H# U; K9 x1 y$ z5 A# L9 e| MCASP_RX_CLKFAIL/ F$ a, a4 M' b
| MCASP_RX_SYNCERROR
9 f" Y a3 S! I$ S8 O7 R7 L, ~| MCASP_RX_OVERRUN);
& _& `: a2 O# j} static void I2SDataTxRxActivate(void)+ E9 I; P4 T! T
{
# E1 U6 c' {3 K1 }; S8 g8 E: D/* Start the clocks */4 Y" l) C: R+ ]6 f' o0 _0 @9 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 y% G. ?% v7 U1 n% U, nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 M% n p1 |+ b: G8 K9 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# E+ ~$ m/ M' d8 v) S$ { A
EDMA3_TRIG_MODE_EVENT);. y! N2 n h4 M1 @/ d4 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* [6 _$ Q8 i- Q3 q. x, d% FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 w9 |. x* u- _1 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' I7 |1 j5 L. u: \! Z) M* l2 DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' _, a- [: q/ ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# Y1 Q2 f1 U( |. n/ i+ Y7 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 S+ X1 U4 V+ r( Y, `4 N8 U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ ~ {; }2 x7 y} ) J( K, r7 H$ c5 I4 }6 E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 g; ]* N1 W5 F) }8 j+ V
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