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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 H" O! D$ G8 o s! ^
input mcasp_ahclkx,
" A: O4 R3 o+ U3 Zinput mcasp_aclkx,
- `6 J6 y* B8 \1 Q( h: t( S$ tinput axr0,, b, S7 i/ j3 I. _2 I/ r
% Y& b& U" Q% B' c7 Routput mcasp_afsr,; s4 B( i% d& ]9 c+ R: b/ R; E
output mcasp_ahclkr,
: H' x2 F( B- K1 ?9 V/ s9 houtput mcasp_aclkr,
6 a6 W1 D+ T" ]! v* N. \' `9 d6 koutput axr1,$ a: P7 r2 f9 R b: y
assign mcasp_afsr = mcasp_afsx;* U' e) B5 R! {4 H6 t
assign mcasp_aclkr = mcasp_aclkx;* ~2 b8 d! {" K2 g3 B i- M- X: d( U+ q( d
assign mcasp_ahclkr = mcasp_ahclkx;
( j; h4 ?5 K5 j5 G, aassign axr1 = axr0; # d; B1 K- E9 o y6 n2 Q: f
3 h2 b; Y9 \+ L% ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 s: W( W0 m- b8 d% Dstatic void McASPI2SConfigure(void)
# G) X! _5 g; o! r) K% o{
: K5 g6 {: M2 i2 F/ K( \McASPRxReset(SOC_MCASP_0_CTRL_REGS);! K+ r7 h2 F. O }" r9 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" k! F- v0 P {# U8 m( A) HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, E6 `$ M# ^, v4 e* NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ m/ V5 \' Z, i1 o8 @ }; VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! q* e# |$ y6 zMCASP_RX_MODE_DMA);0 `# Z4 H$ R. `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ D/ _- Z7 L; F! k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% O2 {. S; t3 T- EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) x- Y% X3 Z" T3 q3 r% y) R1 bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" D0 `4 Z" ?4 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 l. [/ E8 A) c# \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ ` g6 u/ x1 E( b/ H0 W8 h* m! r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% U8 u9 I% p9 BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! y& @& Y: ^" L |; ?9 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 a& _3 y- o) g+ X! t/ v0x00, 0xFF); /* configure the clock for transmitter */" N( Q* t, S* E, O& a9 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 }& S; n5 X1 J# A0 E) r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: x* j7 X, O$ M5 |- a, d9 tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( [' t! }1 j+ u) u9 x, y( T
0x00, 0xFF);; b% m/ V, }' N7 T2 W/ N+ ^! h0 w
2 t4 k" O( w/ s. ?4 W+ }8 {
/* Enable synchronization of RX and TX sections */
8 C% W. m/ T& jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! c# q+ Q, G& ?) T8 S& o3 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, C0 h1 U4 S7 ~" H& v5 d' k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; @! r- w) Z/ x1 ?& [% A* K** Set the serializers, Currently only one serializer is set as* e% R* n! l- l5 o4 [5 X% b4 |
** transmitter and one serializer as receiver.
4 `# \! E& U8 |9 b9 \/ ?1 x$ G*/' s9 t! t4 G) x/ c: T/ [ F3 l2 E/ }! r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 a" U/ D+ A! y: o$ o. k9 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" s9 V; ~. H3 {! ~+ b
** Configure the McASP pins 0 N3 @8 \( R" F6 V. F6 U0 b
** Input - Frame Sync, Clock and Serializer Rx0 }+ p) M: n. p/ n& k
** Output - Serializer Tx is connected to the input of the codec - ]0 ]8 Z; s* Y/ a3 e4 e1 u
*/
, m2 \! j- `% l, ?6 k( [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' G I# P& Q; PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) ^" V# v! S: r. A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) E1 B: P$ w% x: L6 V! Y! F| MCASP_PIN_ACLKX' l1 K+ f4 b/ z1 b x: L
| MCASP_PIN_AHCLKX5 \/ f. }* x% v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 n0 B% p0 k# F2 A3 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 \7 m7 \7 J7 R5 G
| MCASP_TX_CLKFAIL
, p7 a4 w8 W; P1 r. Q; o. J| MCASP_TX_SYNCERROR
. i7 F7 a) ^8 A& p# d+ O# g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; M" V; [7 @+ i& D! m3 I' L| MCASP_RX_CLKFAIL5 [5 \! Y) Q' p, A' t. [
| MCASP_RX_SYNCERROR
; k0 r1 A( E5 D! t. @: `| MCASP_RX_OVERRUN);' i6 |) k1 }7 D8 r6 J6 P- C
} static void I2SDataTxRxActivate(void)
* |- [! }/ `. S% V# b2 }6 h{
" P% b3 Y. N8 D; u$ k, U/* Start the clocks */3 `& V8 r; e3 _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 R' o( s& A! O6 L& x2 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, x- o) E9 C4 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 {% L) f4 i3 X/ k! Z/ `EDMA3_TRIG_MODE_EVENT);9 I# k4 T. t4 X- @* f4 l- u9 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: X& A' w6 F' O2 L. z1 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. C9 w3 }! B) s% T; k" Q0 d$ V1 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* \- N: x' V, M2 `. G2 r+ @6 d9 `# K# m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. j! |/ M7 L. \! twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 }, y! _6 ~: o; x7 h" M. eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# N2 v) F$ v# |8 {! Y5 w2 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 i+ `3 W7 d' M m# o0 U}
4 T' l. w! l0 u4 v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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