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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 z2 e+ C! _" ~1 V; O4 ?
input mcasp_ahclkx,
* ~- i1 ]; n/ |0 [0 ?% V4 c0 H% Xinput mcasp_aclkx,3 y Z4 k- N$ A) [. `
input axr0,, A t. z1 x8 S9 a" w5 i4 i
- v9 f) _) Q) |% p
output mcasp_afsr,
7 s4 h: m( W5 m3 `( doutput mcasp_ahclkr,
0 H- d4 Q7 p# }) X; Q8 w; soutput mcasp_aclkr,
% G+ i% U$ X1 Poutput axr1, y4 Z/ X" h' x9 s* y6 z
assign mcasp_afsr = mcasp_afsx;
7 ^+ l& _; K' ~assign mcasp_aclkr = mcasp_aclkx;
$ t, c' ^: X; _# \: l1 M0 Zassign mcasp_ahclkr = mcasp_ahclkx;
" g+ L& j7 w: a" H; N8 Q' V) hassign axr1 = axr0; 2 D1 e6 S+ z- V; O/ x
- S7 p1 p0 L- k6 y3 C) [& U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & c3 E, M5 c8 {8 A: ?
static void McASPI2SConfigure(void)% M" f3 k; t }) ]
{
3 U6 ~6 u+ x2 z2 X, Z6 o" S% kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# {/ d9 {- ?- j e# d/ _; A: N: HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: ^) z! X, i$ H4 y5 y" N7 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 g5 b' L; d! e! R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# g% c% c; ]. p* ? A- SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& [0 u, `5 v4 e4 v( mMCASP_RX_MODE_DMA);6 H8 u L1 ]- {& v' O1 t' Y( B! B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) a) N/ T& L2 y: q0 n0 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ i8 x2 `) G% j' h6 Z$ `8 ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; f: i/ n% q3 g7 fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 `3 q$ W9 V# I$ B( q, M" j4 M* fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& l& H% L9 c0 L: z+ |% RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! a: z" V7 J- B* p. S" \1 MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( }! q, O( [+ j' g5 SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" D& e5 v O! y& ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: A9 [4 a5 }6 S x; I- {0x00, 0xFF); /* configure the clock for transmitter */% ]) r7 U- p% T2 |1 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 C: e1 @9 v1 _! J6 `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 w4 }: P" U1 m% \1 [) b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 x' x/ Q7 e2 p1 \2 b; k+ V4 E
0x00, 0xFF);
2 k# e' i( k8 l/ p, A* n: X/ T8 b F3 ]" A. a( F" c
/* Enable synchronization of RX and TX sections */
0 d4 U+ y! o v, s9 v, kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 J4 I. ]* P- \6 E5 U8 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* B4 k6 L% {( WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
h# N9 ?: f3 i** Set the serializers, Currently only one serializer is set as0 ^4 t( G9 i, s! T+ p
** transmitter and one serializer as receiver.
% M9 r2 e5 X: z0 Q0 Q*/
, M& |0 x: h: cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- ^) D8 ]% ^; L z6 A. WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: R, c' l) G2 T% q: S
** Configure the McASP pins
: f" c' A$ L/ g+ t9 P: b** Input - Frame Sync, Clock and Serializer Rx$ d# c, L0 C# L$ C1 m
** Output - Serializer Tx is connected to the input of the codec
: n' ?2 ?$ @" u, i, C! ]) H3 P* b*/
% }- R. E1 k1 ~3 z6 M9 e# _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" B2 K! p: D) Z2 v5 e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: N( B' K2 t, b" E" E8 a* b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 B6 E- U: d% \. H' |# l; P5 U
| MCASP_PIN_ACLKX H1 h4 \9 z7 q2 B
| MCASP_PIN_AHCLKX/ O6 e# \6 d/ ?$ R: v) E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! F! E' j* Z; Q$ q& Z5 Y1 NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # Q/ A0 M+ y& e3 e9 Z0 E+ r
| MCASP_TX_CLKFAIL " ]: n, N/ L( M9 q9 S
| MCASP_TX_SYNCERROR
8 O) Y3 X# A/ H0 s! g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 {* q ]# `% {+ [. \
| MCASP_RX_CLKFAIL F& X/ Q- c6 y
| MCASP_RX_SYNCERROR
/ G: m! @6 N: ~| MCASP_RX_OVERRUN);* }/ x7 o$ T, h) H3 F
} static void I2SDataTxRxActivate(void)* d ?. }; |% o4 q L+ c' ]; @
{
. I7 M1 ~6 h0 y/* Start the clocks */
0 |7 o) \7 {; fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 j. I7 {! q& Y2 N: OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% w: ?& i" w zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; T5 M1 s: l8 G' F' l
EDMA3_TRIG_MODE_EVENT);) I# b3 k, B' G* L z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
F. E: q9 y- {" @9 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! n# b4 w5 G) Q4 a! c- h6 J, ^$ l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) F) N' F. |7 S7 f1 b& N, H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- T6 Z/ e' m/ o/ o- O8 v+ B+ q, t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 `$ f% n5 r, y9 J8 S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 A2 b+ u2 K* jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, W7 O* C& R) y; M
}
$ r# U3 ]1 M* U; s+ U8 _ X9 C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 L! R1 g. w: H2 O" ^, n+ [4 w, { |