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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 ?9 _2 ^& I- |! }+ f% R7 \input mcasp_ahclkx,
) c1 U+ k3 q' B7 Hinput mcasp_aclkx,4 h- f+ g& J# L; L6 e$ z
input axr0," s$ T Y2 ?% W9 }9 x. X4 }
* _. v5 `# D" {; P; R' l
output mcasp_afsr,
" ^6 E2 O2 U4 l+ B3 h. a9 M8 ooutput mcasp_ahclkr,
! t5 C9 D& J5 w! woutput mcasp_aclkr,
' N; b9 s2 \. t! T' J: J" [output axr1,
6 e6 m$ D$ J% R assign mcasp_afsr = mcasp_afsx;
6 m3 P% z) {! rassign mcasp_aclkr = mcasp_aclkx;
2 e1 f0 h; H" B% _assign mcasp_ahclkr = mcasp_ahclkx;5 ]3 H2 _1 d9 C5 P
assign axr1 = axr0;
* G' o i7 ]/ K8 o
% ^8 Y" Y, Q* n, N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # l4 @+ k' ^/ v, B8 e0 n3 |$ T6 w9 l
static void McASPI2SConfigure(void)
$ J# L# s) E2 h) M{
- G* v! v' j- WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ Y# L" M! T9 L9 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 F6 b8 h( Z7 Z; j4 l! I8 U$ \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 h9 C: `0 O: }; }2 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 G, I+ p! H" K+ Q4 U$ BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" M' x0 R1 m/ u* B8 L7 x6 r# ~/ j; NMCASP_RX_MODE_DMA);3 ^! `$ {: r M! c G6 X$ ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 @, j* J9 M( \; CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ z8 E4 D! h) o3 K5 m4 W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! y; X5 d% _* n# q1 q1 e8 HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 m& x9 ~0 j8 J$ h* SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ J" |, {; _ m6 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 e/ L5 ~' Y( c2 h. F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) P& I( b8 Q0 Y; J$ ]! n3 h$ g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, x7 x' L; K O8 S! b9 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! z. G' i( I* b& b0x00, 0xFF); /* configure the clock for transmitter */( h5 l* v1 |1 w3 D) L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ j, K8 Y# @/ x' y7 d uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 t( H) e/ V1 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. q; ~: r c2 p- ]. t7 a
0x00, 0xFF);* n5 P2 ^( K( a2 {& l7 X
& [$ V) y3 x4 {4 L1 J* O
/* Enable synchronization of RX and TX sections */
6 z# V' |4 m5 ^! s% J& s- vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- @* n( u8 h, D* C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ c K, c9 R: Q. P/ |1 I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 v" _, ~5 I/ |8 Z
** Set the serializers, Currently only one serializer is set as$ o, v7 k/ a6 b/ Z
** transmitter and one serializer as receiver.
6 h0 o1 z. ~( a# @*/
: A4 c5 U( h8 g4 m9 Q1 v" n+ l- UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ z9 X4 x a K# y& ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 p Y% i' Q+ ]/ F9 Q# `** Configure the McASP pins
$ ]0 A- U0 |0 m4 T** Input - Frame Sync, Clock and Serializer Rx9 K( ?) J* r2 N) ~6 |+ Y
** Output - Serializer Tx is connected to the input of the codec
3 ^5 q; D8 i& }( Y# i*/7 K$ V" Q, @8 y9 d# [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, N6 u7 C' L, h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 O( n+ a! j2 m/ `9 sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 V- U3 J, v F# i) d* u0 y, X, u& f, c- t
| MCASP_PIN_ACLKX
8 ^* W$ B7 x, m9 C* l| MCASP_PIN_AHCLKX1 |& O" Q: a, V' S3 \" l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- B/ z# `1 M/ G* l# H' dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ S0 U/ N) `- z6 K9 _' i7 ^# c
| MCASP_TX_CLKFAIL
( _* Q( b$ L* L) s8 i- o| MCASP_TX_SYNCERROR4 K1 W4 o1 e w) Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" N; t. n1 ?( Z/ ?7 F* J| MCASP_RX_CLKFAIL6 R7 z) e7 [' c8 M4 a# [' W
| MCASP_RX_SYNCERROR
- Z' @5 J; ~3 y+ @& q# E' y| MCASP_RX_OVERRUN);) e& Q0 _. j* v
} static void I2SDataTxRxActivate(void)
8 @8 \2 A9 \- B% G5 T{ q0 e' L0 _9 I8 T
/* Start the clocks */0 w/ ?+ V: a. p1 n1 ^, ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! t& _0 Y- |" P E7 P1 h6 u$ f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 \' b% x3 p7 A$ i/ T D5 S& C" X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 J3 \ T& @7 b6 h/ D) ^EDMA3_TRIG_MODE_EVENT);# i. {7 O3 U& s r7 o- a+ S3 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! a3 C/ c9 Y# W/ D* |* @2 C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 S3 F, q7 s0 e% f. t6 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
N: d9 ?0 ], o8 Q2 a bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 H# X4 o( s$ P1 {* ^6 H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" W8 D$ t7 M9 x; ]5 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! Z8 y/ T6 p! ]0 ?6 z; q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# {3 `" D* ^( b/ ]1 c}
3 i+ l6 S ?' b, x/ e T# e9 O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " b8 K8 o/ E2 _% D. `
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