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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 w' ?+ ?% ?( P" t& Z; J b
input mcasp_ahclkx,
& r& Q) s8 R* `2 Winput mcasp_aclkx,
m3 k, w3 n* binput axr0,
8 G4 ^! K0 |! c, ^ w8 Y7 x6 J o/ y# h
output mcasp_afsr,
3 E. {# Q) y+ s7 o) ^! Eoutput mcasp_ahclkr,+ b2 p$ e: _) W1 s2 r& c% Y7 r
output mcasp_aclkr,. Z7 u: [9 Z% s7 x/ e" C1 J
output axr1,! I0 }8 D1 I' [0 ]5 j q3 X( ^
assign mcasp_afsr = mcasp_afsx;
0 N5 h, B" |9 e2 ~! K+ xassign mcasp_aclkr = mcasp_aclkx;& t+ z% P3 t0 g( {8 x% D
assign mcasp_ahclkr = mcasp_ahclkx;5 T- R. B7 l* ?. M5 B. m2 v
assign axr1 = axr0;
n4 f( b1 | S6 f1 `) E) k' A8 N9 ?$ |; H8 v2 n8 t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ m; q ^% w4 ^) Q# m1 \: Xstatic void McASPI2SConfigure(void)
6 A: D$ ^' V' U; E+ k3 G{& K, a \( {" V: h- {/ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! }4 F" r& X: b7 D0 [$ z1 Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) g; y; x, F; Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- C! r8 v( K: z, e* I2 ?) B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) I2 i6 v& r* Q. h; DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 B% U6 @ @; j8 R5 ~! @
MCASP_RX_MODE_DMA);
# k+ R6 @; p0 i- s& F; ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ E1 G% U( e: h: RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 D& @2 x+ O' A6 q C s7 K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" i; ^% @0 B4 e- m CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
k, `0 E2 X* ?9 g4 Z3 MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; ?7 w2 {+ w' a2 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( F8 n$ O: c* R4 d- b) \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 u$ \" i3 N0 U8 r( x* k9 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 _4 v: _, \. i- DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: g( t8 Q- y, S7 p' T
0x00, 0xFF); /* configure the clock for transmitter */
9 D2 r8 b. F# x" j W4 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' d7 y6 B) L7 I3 R( [( J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % ?7 e1 I/ d7 G! M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& F' V4 f0 s- o& r' s t0x00, 0xFF);
# {4 ~* [9 B* H& B% f' G m9 ?" b% ^7 B. c
/* Enable synchronization of RX and TX sections */
4 F# f' ~/ n }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- ]" z& v# A3 S5 m' m6 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ U, w6 N, w3 @/ u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 t) B: y6 j& W" t2 j* ~4 }** Set the serializers, Currently only one serializer is set as
: F2 R- g+ a& Y** transmitter and one serializer as receiver.* U0 C2 B% w# z: w
*/
, H1 I5 i9 S3 I* H. XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 r) \1 a8 j- l# X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& d T. y. f' J5 N2 z
** Configure the McASP pins ) ]; [' W* H# Y! E; V
** Input - Frame Sync, Clock and Serializer Rx
; H; L1 R0 G7 C9 d' C% b* ?6 \** Output - Serializer Tx is connected to the input of the codec
" t( A: r. t' ]8 t4 P+ ~' f" z' o4 x*/
+ z. y+ _. \2 G3 j7 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! t5 M% j6 r- s% [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 b' N: d6 c, n9 S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 O, M0 T; Q [. ^$ j| MCASP_PIN_ACLKX2 x9 a: k+ `6 H M
| MCASP_PIN_AHCLKX4 @; E0 e$ n' s( ~+ x) c" ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ V$ `4 }' c# I% M' s. c& w7 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / N% q; D9 m# ?
| MCASP_TX_CLKFAIL
, m) n4 V* n/ p8 ^" J| MCASP_TX_SYNCERROR" J; k2 F) x% y0 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 ]: B R3 ~1 d: b$ _8 y0 a| MCASP_RX_CLKFAIL: W& ~/ R6 f( z# z+ i2 p( E
| MCASP_RX_SYNCERROR # r. }8 A! f7 w
| MCASP_RX_OVERRUN);
6 \! F+ O) s9 \& k$ o1 z} static void I2SDataTxRxActivate(void)
# `0 u9 m' \6 m5 H) s" |) t* h{( }8 G, \+ e( N
/* Start the clocks */: ~) C: M! Q# o; @ J+ i4 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* u# v( I1 N- k) h$ b; XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 J' X1 x# B6 z* e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! x x! b+ |% u5 r' m2 _EDMA3_TRIG_MODE_EVENT);
% ^/ f+ g4 `# o d" M: B6 T/ V; ~" iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 l) T4 B+ D4 r6 G. h, v9 lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// x' S3 l, q; W. f8 `2 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# y3 T$ n# R7 r) M" q9 XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 n( X, [' ]: g. ^3 @8 ]3 i( n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 x t |; ^; |+ K6 H% kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% v0 ]) q* j9 `/ o) k7 G+ lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 U3 T( _9 z7 B: G+ ^4 ^
} ( b# L" c# P0 X1 Q" z8 A3 c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 I z, P( O* U' A+ ^
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