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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 R9 t5 t* h7 Z& X
input mcasp_ahclkx,
: E- r) G8 h- c) ?6 Ainput mcasp_aclkx,
2 ~9 R c4 Y0 U5 O W1 N* X. xinput axr0,3 w8 V9 `6 F, U' g6 {% a+ Q/ ^
% H C: e3 R" ?7 l( A) Q. i3 E0 X
output mcasp_afsr,/ U5 M8 W* ]0 c- m9 e4 G9 ~ o/ P9 r
output mcasp_ahclkr,
; `/ X, B6 c( Aoutput mcasp_aclkr,7 o- v% T3 H- R8 @
output axr1,
1 \2 u2 ]% E: [ assign mcasp_afsr = mcasp_afsx;- R0 J* `' d, S
assign mcasp_aclkr = mcasp_aclkx;! t: d( A: H- U7 t1 k* Z
assign mcasp_ahclkr = mcasp_ahclkx;* H, ]9 g! V/ f5 {9 k
assign axr1 = axr0; # w6 w& h3 d# i1 S+ L" c
- |2 G% F1 }; h/ e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. _' t0 a+ k& {# E& zstatic void McASPI2SConfigure(void)
. S' k+ `# p0 \: e! d" t{
# E: W/ x0 q! d) K/ mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 |/ R4 {3 u7 W1 u8 ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. @; G) a- ^( s/ ^2 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: o( K7 D6 E+ N: n; C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 k( g( M z/ ?" @$ W: D0 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: j8 p1 z+ x, _% xMCASP_RX_MODE_DMA);$ G8 |. x* S' U( C& _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, [ n0 ~5 ^; \, F. b( q! q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 N3 K, A) [2 @; W/ O9 K" g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * i8 \: t6 k+ y: O" P1 O& w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 R/ o f9 @" {$ j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' V! _; G! w) ~3 T* k# RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( q b5 v( o4 K" S2 g b7 SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 G6 `" d E1 j4 ?# x# H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 e% K0 M* Z3 u$ m$ e! ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ N: h+ ^ t& W& T
0x00, 0xFF); /* configure the clock for transmitter */4 t7 c9 B& T4 } R$ ?, E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( S7 u: X: b: P( O; ~8 Z, g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ c t+ ~& w! W+ Q2 }, ~( c" c1 |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. U# R5 _, T2 i! r% P/ y
0x00, 0xFF);4 T, j! _& a( B
/ F* o! ?, \% c2 t% R% X, G/* Enable synchronization of RX and TX sections */
7 R7 `. R3 C4 q1 {2 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// o; Q3 G8 J' n, w4 ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- o1 u1 Y1 v1 S- x FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( t. G6 A2 f" _) i- s& x
** Set the serializers, Currently only one serializer is set as4 {- h% b ~' C* J$ H8 C; o
** transmitter and one serializer as receiver.) x* N# ?. z- e# K1 q6 n! L
*/
& ^' e3 }! B) w5 VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( a( W$ _5 R% C. ^; C3 Y7 L8 m5 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** r& R9 w) H0 `4 P/ w$ o
** Configure the McASP pins ( M: P! x; t8 F
** Input - Frame Sync, Clock and Serializer Rx
" |* i, v$ L5 ?" Z7 a9 ?** Output - Serializer Tx is connected to the input of the codec
6 V" z& X/ U; L( [*/
B# Z3 i6 |5 Y. P. WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& Q$ m/ C K# s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ `% s2 t8 Y4 r0 m) F: \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; J/ _0 I. B( E( B| MCASP_PIN_ACLKX$ m3 _8 N& k5 C$ l
| MCASP_PIN_AHCLKX6 ?/ v) T$ w8 D& L9 f+ W6 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. L1 q% T+ f: _& @+ S# l( u1 O8 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! `& g7 R z( b
| MCASP_TX_CLKFAIL
/ g, J( }" X6 u4 ^$ C| MCASP_TX_SYNCERROR5 q& Q* I! [7 b6 i* D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 d8 `6 a$ }( b4 V* o
| MCASP_RX_CLKFAIL
: l, P! L/ ~+ S( e7 P: M# i+ ^| MCASP_RX_SYNCERROR - C6 t# C* M: ~- _ u' y( u
| MCASP_RX_OVERRUN);4 p1 B9 ^. c6 k' T7 V# c2 j' F
} static void I2SDataTxRxActivate(void)0 O0 I1 I `' f4 t7 C4 U+ f
{; k* [% C2 t7 `6 j" \1 n
/* Start the clocks */
9 n: q0 ^+ R0 d7 w+ KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: A& [8 w8 n) o: L4 |" [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 r6 z% e* |. c' SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. [0 Q5 C' D7 D: e0 [$ h
EDMA3_TRIG_MODE_EVENT);. y0 R+ u. h/ s. t; p8 G4 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 P. ?0 m/ j! z8 l6 v! l5 `$ oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' ]- F9 L F0 t6 D+ \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- C t4 K$ W& _4 m/ ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& `, K3 u8 c' Y/ x; }+ A: Z# {. nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 K; Y5 [! V, Q+ Z! e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 ~" h8 y( q* }( o) {8 J' @- T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- W7 U/ M4 y; y} # p+ p* d; B$ y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; {1 t8 {; l2 V, w! Y+ C ?1 ?+ ?+ T
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