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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 l2 `' a7 G5 x7 ~3 O6 O
input mcasp_ahclkx,
- p. ]& L, }( }input mcasp_aclkx,) L% }; R5 k" z8 V5 V5 h; D
input axr0,, L( n% v# Z4 p- S" u5 s
. }# ~, K9 `4 r' c/ i8 p% t
output mcasp_afsr,/ Q, A; Y& {1 k$ q) \/ s N
output mcasp_ahclkr,
' n' \; K+ I4 }& _output mcasp_aclkr,# f- s: I; x% \- V" D
output axr1,
9 k6 G4 N+ @$ v% }: i1 O7 o* Z% U assign mcasp_afsr = mcasp_afsx;# d; Y& u, |! d. T4 \- C, S
assign mcasp_aclkr = mcasp_aclkx;0 H: ^: i- c) s
assign mcasp_ahclkr = mcasp_ahclkx;
$ ?$ g6 N2 p" s5 R1 ?6 Aassign axr1 = axr0; ; X E9 b( V6 d" Y7 @
8 }7 L8 E/ T' J0 ?, r+ _) _5 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 d n, w. t/ p9 Z' P+ b) N' V
static void McASPI2SConfigure(void)
) O$ r. ^6 n: Z/ y0 P{
% p5 w7 \0 F% U5 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( q: }6 k8 v: Q6 T7 T* ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 q+ \, I6 G8 Y, H3 `+ p4 r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 C' F* i. l" c! {) ]" d( K2 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) r; z6 K9 z8 g8 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% b. O( R: Z- H) kMCASP_RX_MODE_DMA);
8 X) A8 N }- g* R! L1 E; vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 D# F% m- h8 tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 |) r4 }7 m3 \$ f, e! ]$ h: M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 G# G$ z& L @ _! T& S a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); `; p F0 C: C/ ^1 U* b8 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 a" I2 J. e* T R# M% Y8 C1 cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ a* y7 r( s' L+ `" N0 vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, w. W7 q" Z* e6 G% \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); o( z# O4 x" V2 @- o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 a# i' @4 D I
0x00, 0xFF); /* configure the clock for transmitter */% M2 J/ ]) f9 n/ U- t% T, s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! H$ s. x0 O ?; @- T H3 g4 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 J) m& L$ c- b, _: r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# s; n [9 h: }6 u
0x00, 0xFF);( ?0 S& k) I% [& |5 Y- n6 [
& V+ d' R- s9 G
/* Enable synchronization of RX and TX sections */ ( s1 H" M* s- v7 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( {5 I7 a5 q- r' d) i0 P/ G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 |& }/ Z( d3 d3 z# i' c# NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 ^2 ^' \/ {# R- b
** Set the serializers, Currently only one serializer is set as @' K& K O/ V& {
** transmitter and one serializer as receiver.
# Y: @$ |" n! S" I*/
! }9 n& z* A) Z* N; |; s' aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- I# r0 N) O+ q: W. K- s. g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. |3 }/ B; W! Z) A# |) x8 }0 s** Configure the McASP pins
- I3 y( E/ L0 n** Input - Frame Sync, Clock and Serializer Rx
, F8 V1 Z$ H8 X** Output - Serializer Tx is connected to the input of the codec
6 Q8 W2 }, R7 Y, M*/
- e) ~, h- r. q2 M- g6 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- U# V- }+ I7 M5 A7 V4 r% N, y& lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 c) M$ w; ^' e0 z9 l0 j& b4 }6 L, r0 X! R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! M7 E6 X3 C( G/ c" b8 }" I! ]
| MCASP_PIN_ACLKX
1 N P* d, x) j: i% \2 T| MCASP_PIN_AHCLKX" ~6 ^: J( M! C V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, G) i4 Q, z! s1 T3 [1 a/ L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 J6 }2 Y1 F* |- N1 i5 t
| MCASP_TX_CLKFAIL
/ S; I( c" f3 ~! q| MCASP_TX_SYNCERROR
+ b5 k+ X0 \( ^7 s" o! m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / Q; `$ ?! L- k
| MCASP_RX_CLKFAIL
9 ?, B- B& N+ Y. O( ]3 a! v& {2 P; o3 V| MCASP_RX_SYNCERROR
, H$ f: h$ C0 t5 j( F: [2 @) H| MCASP_RX_OVERRUN);
& Q* y& k- U" g5 Y( b7 j3 ?} static void I2SDataTxRxActivate(void)
+ ^7 x f7 R% e: ~{
0 N: }' s+ x; v" J1 R, C( s1 N: p5 J/* Start the clocks */
) k4 U" X. `& h; T) m# s: yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 L( f+ g8 E* SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* v9 N* u O9 o: gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% s0 [; i4 W+ j! P ]- h* [$ qEDMA3_TRIG_MODE_EVENT);
$ m2 ~( x, @- _7 F7 y" ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % A$ y" @: ?: }% W' {$ U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( j6 m+ C. z! ?5 y0 P; O, DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 s) Z1 _% k+ p2 J1 z+ H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( Z u% y& y+ u2 x0 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, w. }9 `! V( s6 H0 k O# _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
[7 b! b5 U! X, wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ a$ l! ]! W( L% O7 M. I7 R5 D} 1 {9 h2 g' R* ~# p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. y" Z, R; v- M. r1 A5 w
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