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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, G" L/ {4 p6 U$ A. w& \5 N4 B4 F7 \input mcasp_ahclkx,
. b2 p: B% d9 ~, ?& Xinput mcasp_aclkx,
1 E1 m# V) a" A0 l3 B2 N4 R. f* iinput axr0,& y, p" f- `) p3 T! E" W' X
1 ?0 h' a2 D* K4 X/ u8 e% Houtput mcasp_afsr,& w$ A% Y5 S4 ]7 ?4 m
output mcasp_ahclkr,
5 [* {* k) I2 v% i S2 Coutput mcasp_aclkr, K5 E/ o' U6 X- m
output axr1,4 m! ?* e1 `5 H
assign mcasp_afsr = mcasp_afsx;: k) c2 k- o9 ^" T$ b& i
assign mcasp_aclkr = mcasp_aclkx;
4 l. `% j8 E+ l" n" Yassign mcasp_ahclkr = mcasp_ahclkx;
4 ^" J" [5 C7 I9 [1 W# Qassign axr1 = axr0;
5 k( @9 E5 [3 T- a; @
; ]8 x' H; F* }, d" `7 M# d2 C4 A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' t# i: f0 {1 U X% ~5 S5 Z; lstatic void McASPI2SConfigure(void)
4 B4 R: a# R* E' w{
& b, C) B# b! n1 f0 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; h+ T r; H0 `! n' ?7 [ e4 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: Y% I# i' G' {2 g; l. NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 U4 y/ M' w+ u% X4 H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. [( T" a" S/ pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( ~ I, U+ i+ g' U0 K" }
MCASP_RX_MODE_DMA);
& D0 T4 U% G3 U) dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. {. |- Z+ H8 F/ ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" S8 C2 a+ u- W. ^5 N( d3 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' F- A9 y! t! S* }( F$ q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ B' x h, S1 }- u+ y* VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( \8 [/ w$ m# s2 rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 P8 E: X5 G% H9 V; }4 j- LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; F5 z# ~ ~) h' k1 @7 K4 @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 B3 S4 f6 u6 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 U# Z, O+ j+ \7 G
0x00, 0xFF); /* configure the clock for transmitter */9 v4 |9 F, [3 J: V( v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" v0 t8 N9 C, A8 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 P3 |) e& |( @& z9 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 R2 D, u, b! D7 b" `
0x00, 0xFF);) F/ S* J7 p8 }2 l5 J5 Q; \
% b( b4 F$ ^" l- L( C% M# }: O
/* Enable synchronization of RX and TX sections */ ; O ^- m9 m" I" w, D. u7 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 m: S0 M) o" d+ X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* Z9 t" y$ x( M$ QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ E5 {0 l5 E1 c. q
** Set the serializers, Currently only one serializer is set as
7 N7 A. S2 o1 T7 V** transmitter and one serializer as receiver.
1 b; I& r: ~1 R6 p- i+ T0 O*/1 E2 w) t' R- Y8 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 O; K+ C+ f) |8 aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 D8 l$ r- z2 A** Configure the McASP pins , g! Z+ V5 A2 S& y$ x
** Input - Frame Sync, Clock and Serializer Rx1 U; p0 Z# b7 ^8 R; }- e. u- s
** Output - Serializer Tx is connected to the input of the codec
1 k9 r4 d7 N4 M: e*/
- e- Q0 j. I7 ~: [+ jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 m, @, F. @/ ~4 a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
y0 k B7 V% K; ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 n# r0 c" q2 _; S1 ~' }| MCASP_PIN_ACLKX
a- D' ?# i" A3 s; Q| MCASP_PIN_AHCLKX" x" N7 b Q- m. v7 ?. X* O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 o1 Q) ?& H. @! _0 B9 ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 T% a& r- e# H: X| MCASP_TX_CLKFAIL 3 W) l4 a% Y7 {0 e# b
| MCASP_TX_SYNCERROR
b8 i- w5 x2 Q$ h! l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" h& u& C, L7 r# u* l6 U& ?1 H# ?! z6 A| MCASP_RX_CLKFAIL. ^. ^" |, C& m
| MCASP_RX_SYNCERROR
9 | ~# Z l, J$ c' o3 }6 b| MCASP_RX_OVERRUN);
1 N3 [; ?/ O7 Z+ _$ w# t} static void I2SDataTxRxActivate(void)1 h" ?9 o- r2 W3 G3 k& ?
{$ o6 H" q) |& g1 _5 P1 T6 M
/* Start the clocks */
8 P# j( i, \1 c1 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: x5 ^4 K; ^9 u( GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% K2 K! U$ N; a' NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 n% G5 \, e% R0 z7 C, G* AEDMA3_TRIG_MODE_EVENT);0 a6 L E9 T! `: Z z" |+ E7 k0 P: _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 p. n) `. V8 P& t; {/ L c, G3 REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) K, p4 v, r& L8 T3 u/ O) T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: w+ Z: e: J' o, O+ C! p/ e9 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 L# a) B: i- P! {* Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 n" I! F' h- C4 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 u. F" B9 |0 |' c4 i; W1 Z' M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- V4 h! I' k0 f& a
} 7 O& a5 z$ C. P" _/ C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # r. @4 I# p5 o3 {. T& A! Q7 z9 U
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