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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; c" e% e' U3 ]) j3 n. c; ninput mcasp_ahclkx,
+ |* R$ C' `0 ~input mcasp_aclkx,
$ B5 ^$ M0 x: Ninput axr0,
# i) x7 E! e/ I7 ]- m, e+ m
( j$ C3 g9 w9 r7 M: W( q" moutput mcasp_afsr,
1 R* a# d( @2 i9 r& S# q6 Koutput mcasp_ahclkr,
" x3 A' z$ g, n8 s U" Woutput mcasp_aclkr,
( t# x0 B6 V) b- W. i! _output axr1,
" y9 n: o6 H: t$ B( \6 V L1 I& m assign mcasp_afsr = mcasp_afsx;. u% Y5 i4 ~ Y
assign mcasp_aclkr = mcasp_aclkx;
; R. p4 Q% V0 X* P. v6 ]: U3 Rassign mcasp_ahclkr = mcasp_ahclkx;
. c6 K) a1 J' u" {1 Lassign axr1 = axr0;
5 B( h1 z# r" z! U, y" l. Y2 j
/ w$ z) L& B% m. R b8 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ V8 V9 v! M8 `7 M9 z1 A0 f- z
static void McASPI2SConfigure(void)
f& v5 Y, p- B- p{
, f, i* q% `( g' ^* n5 f2 b# AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 e& B2 e9 C! r, c3 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& S( X1 I- w+ @5 X; W6 B3 D- H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 i" L) ]3 v1 Y: j3 b/ Z& j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: H' y$ X; [' |# sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
I( Y: B/ J3 m' p1 JMCASP_RX_MODE_DMA);
# i& e) L( }( p5 `" V. lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 n+ H" ]0 U1 ]/ K% l, t+ }* bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 c! K& i1 J0 {2 |( `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 h6 ^! l- F0 H! I8 \' }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 I: |3 P7 N( ^3 X4 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: ^9 M2 N% h( W: T* fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% g! U3 z0 q0 ?! B2 ~( S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 r$ l& ?9 C F2 {' S# ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, R( Z4 E3 F8 A/ m" MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 F8 R$ r% A" T/ G/ F$ R
0x00, 0xFF); /* configure the clock for transmitter */2 P& x& X& v! d; u, [1 k0 \* ^6 ^2 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ H- w% C. L; v2 B4 a; Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; z# l7 K8 ]- d$ z+ q- {2 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: t# b/ k( M* f, s6 M
0x00, 0xFF);/ f& P8 T% v$ b* m0 P
* Z. G8 c6 m2 m$ q/* Enable synchronization of RX and TX sections */ ! f) s4 f3 p4 H* J+ l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& ~0 Z2 y( o) oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ J; c) \( s/ d. @% ]& `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. ~4 ^9 x$ c0 R& n
** Set the serializers, Currently only one serializer is set as& E# l9 a& j! F
** transmitter and one serializer as receiver.
; \3 N5 c0 p, f; X+ h, B*/
9 s$ e* Q; m) S0 H/ s; cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); P5 \+ i% U, O* a& M: ^: P' G6 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" \1 r$ `& \7 l: J" J0 I** Configure the McASP pins
$ d6 G+ H- L4 [** Input - Frame Sync, Clock and Serializer Rx
- Q1 B# |6 ^ ?' q8 Z: l! p! U** Output - Serializer Tx is connected to the input of the codec 5 }$ z) B; a! R+ {0 v
*/3 O& T8 j0 i5 h8 Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ E: R' G' Q( x8 [! IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 B/ k" B* d; K& R; cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 M* g- @3 b! C. R* V& @4 l| MCASP_PIN_ACLKX }9 h! B; m5 _. i+ L
| MCASP_PIN_AHCLKX8 p4 e7 e; n" b7 `- n! ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* i8 I# y$ m" O8 [. A: p4 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : L( c! Y# ], I% [
| MCASP_TX_CLKFAIL % o- _) L2 v5 u
| MCASP_TX_SYNCERROR: l6 ]+ W; G( Q- h) E5 {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ R7 e6 q$ e# g0 H% K5 y| MCASP_RX_CLKFAIL( G6 l& Y( b0 M& F @% g0 m
| MCASP_RX_SYNCERROR
; X$ B: M+ A( Y" c8 Z8 ~4 [) N7 \| MCASP_RX_OVERRUN);: v6 N* } d4 Y. k# y2 i
} static void I2SDataTxRxActivate(void)
- A' F) u9 h& S' g+ M, T{! H& j6 c2 [7 P7 W5 m
/* Start the clocks */* m- v$ V' Q9 ]8 a: q- {/ f8 T9 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. [; ]+ S2 d4 |1 l9 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ B. Q: t* p+ R( g$ g: h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 Y* }. w, ^, w8 N% Y- D6 EEDMA3_TRIG_MODE_EVENT);8 X5 S+ d; R- K" A. i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
B! G: M- `' h5 O1 o% {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# \6 N4 ? W+ HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, ^! H- l+ X% s! q' u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 V0 j6 Q% L$ ~! B) Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ k7 F! `! `: V* J: H3 T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# b, Q: B4 O! y: T$ W) Q( h- \- ]% T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 f) q, a7 k" ?6 I- s& {
} 3 P' G3 P9 W( B& y7 q+ M7 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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