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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ W: b- E' F6 U) g# Kinput mcasp_ahclkx,
% G9 [6 G/ I: I8 D3 |input mcasp_aclkx,- t$ m$ D3 e, N/ F) H
input axr0,. y# {; v0 F8 Q: c7 t/ O) h- \' {
6 R0 H5 m, k( {3 `" z Ioutput mcasp_afsr,
" Q) X) l1 r4 B4 i; P |output mcasp_ahclkr,
* w$ c0 y5 X! S; g# ]4 D' P* @output mcasp_aclkr,
- j8 q9 q, a, a/ [+ L/ noutput axr1,
4 J+ b! [: M/ C9 M" _1 k+ N) L assign mcasp_afsr = mcasp_afsx;
1 [4 J5 S/ P# f0 @assign mcasp_aclkr = mcasp_aclkx;8 h3 I/ h) N) n3 D' Q! N
assign mcasp_ahclkr = mcasp_ahclkx;9 g8 D: z- Q- o% B
assign axr1 = axr0;
: S q Y: X/ q+ G4 |: @
2 S9 |, A0 t( g# j. m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 F% o, c) ?4 ^- Z$ O& _ w4 Hstatic void McASPI2SConfigure(void). Y; z% c, P7 \& x
{
4 K1 A8 p. m0 ], q* X3 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; s/ a% `6 Q+ d6 W" q! wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 l' p. b8 l/ t6 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 j% u- \( M0 p3 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- \/ e+ m8 r9 k5 k4 c7 hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& h. F$ c! m* I4 T
MCASP_RX_MODE_DMA);
1 D$ l$ Y+ e$ x4 O7 w" J: O2 t! ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' \) H! _" }( A0 ~1 ~% G, J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& K8 p0 K5 Y% D9 m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% S2 }& \/ [5 C2 L# C- V" {* {1 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 ~; Q# n% s: S6 h7 t, YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
S& k2 M. [# e% i% i% x6 I: S2 P( yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' F) k6 Q1 n8 ]7 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! H5 d4 ]6 ~, Q2 x( A7 yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ T1 O- M1 n: t' |; S3 U9 {( D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
C/ B# l3 ^8 }+ z% a1 J0x00, 0xFF); /* configure the clock for transmitter */
[; l% w7 t( A$ D9 Z. F4 S* Q, XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 T& V5 U: ?/ V4 x) l2 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
p# k. n% p8 m" M5 YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: p# p* q( t- u+ ?
0x00, 0xFF);
3 G' _+ {7 n# U
8 h3 J5 \3 ?3 p; t/* Enable synchronization of RX and TX sections */ 1 r0 g. q2 @0 |% j9 a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; _+ w/ I5 t+ B& zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); u, \1 Y, D$ N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 ~% [4 G. y' R6 d! D2 k8 R** Set the serializers, Currently only one serializer is set as1 \: [" `/ @7 ^4 P
** transmitter and one serializer as receiver.& v. ^4 o3 `' a$ r$ Y3 {
*/
" Q, d7 y, g& AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* I6 R1 B: I8 l% ~$ PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# G& {6 L# O- G** Configure the McASP pins
: d- i# ?' f9 \* X( \** Input - Frame Sync, Clock and Serializer Rx
* x( ~2 {9 m+ }3 {- O+ ]9 N; c** Output - Serializer Tx is connected to the input of the codec
& h7 E/ O( S3 q*/( ~0 t7 ]/ u2 e( u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- k% v% J% X( Y$ Q1 k {. xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 H5 _; I C8 U. {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( p$ N: _! {5 v, w- @( w
| MCASP_PIN_ACLKX8 x r- H% X! q, o& M0 c0 u
| MCASP_PIN_AHCLKX/ G* d, F$ \; o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 L* j$ c$ [. Z+ {4 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* b' K4 G) i$ _$ v ]$ f) j| MCASP_TX_CLKFAIL
) x9 G5 l; I8 q4 n9 w, c: ~| MCASP_TX_SYNCERROR
, F! d: C6 K& U* g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% V* j3 G; V+ ]' k* ^| MCASP_RX_CLKFAIL3 S y% h5 S# l( Y
| MCASP_RX_SYNCERROR
) ~* w2 H0 v. d/ W+ D| MCASP_RX_OVERRUN);! x$ W \! S; N/ L/ x
} static void I2SDataTxRxActivate(void)4 P1 a3 P% y8 G2 p6 }
{
0 p$ G- k' |* u, Z4 O4 a: I/* Start the clocks */, o& S/ U5 m& ^( `- _8 r0 [( K' B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 z; I1 a6 V' @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 I8 H$ M0 w- E! u+ F* wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 i8 ]7 K/ @% I/ F8 d) o
EDMA3_TRIG_MODE_EVENT);; c. e/ L1 Y5 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 _& Y! C4 x9 u( L! J, [* NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 l; Y" h+ M/ @2 k6 u. gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* W3 Q( x# H( J6 e! B* {) V+ H6 q9 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' ?8 N( R7 E$ C2 l' @& }4 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' S* b0 F+ u3 H4 D: B" c, i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 A4 l. S/ k5 RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" D' z% P) P# u6 J}
: x! u3 i( n" s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + ^, v0 f/ A; |! i. f: X
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