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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 T; Q" t) a4 Q4 G3 b4 C
input mcasp_ahclkx,
. r4 t7 F' y9 o' {# |2 Q. v% Sinput mcasp_aclkx,
) z+ H2 e$ X1 a& Minput axr0,8 N5 h$ d d% L; ]2 i# v# D' P
! a8 a0 k$ ?5 f+ a7 a q
output mcasp_afsr,
2 c3 U) ~2 P+ A9 \8 boutput mcasp_ahclkr,* l- a' ?* d( Q/ l
output mcasp_aclkr,5 B" e/ ~7 \ V. t
output axr1,. D& R2 l, B0 y
assign mcasp_afsr = mcasp_afsx;* A% L) R. d7 p% X# {/ r
assign mcasp_aclkr = mcasp_aclkx;
. ^/ Q! ~/ D* z) c) [. }# T3 C; Sassign mcasp_ahclkr = mcasp_ahclkx;
! A4 k. {, s6 f* cassign axr1 = axr0; ) H1 r( L, G+ M1 W
" Y+ A1 `7 K8 W8 [) x) C. A& n: w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' f3 l% e. n$ v/ ^/ P+ E
static void McASPI2SConfigure(void)! `4 }; \& [8 t4 v: q& S3 P* |" L
{
" H& |7 O$ U; ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 K7 K- b: W# { A) w; ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 E. @( y, O! f1 {$ r% l/ D: @: zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: R% \ X8 r) N& W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% F/ c8 Y8 b$ E; P2 W9 Q: v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& Q. |/ J: q& `. S8 M7 s+ V
MCASP_RX_MODE_DMA);
& N8 j1 {! Q1 |& h0 Q# Z0 yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ ^+ G; g0 P- R' a/ k! i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: g4 ] L5 f( aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 H$ W& e% z" s% A/ G+ f2 L! {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- _" z6 H6 m, Q, H' {+ h4 yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * O X# x7 T3 ]. b+ B. G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 P- F% v6 a+ F0 q3 Y2 D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ `$ t& V" C$ V( x4 K$ RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * w. p1 s. h2 c- ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 J" n+ i# P/ C) ^5 v& n$ k0x00, 0xFF); /* configure the clock for transmitter */6 C. ?# u1 Y, h; m( d5 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, t& K7 Z' ~# [+ O# v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; U$ S4 n! o- y$ {) x) S0 T+ N" x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( c, m8 z5 {, [+ H0x00, 0xFF);- U" E( j( c `& r" j
- E3 F( B# u1 D3 `
/* Enable synchronization of RX and TX sections */ + @2 o2 m3 s3 e8 A6 `5 P( t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" U8 C- I7 Y! ?: u, h; E' nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, Q% {9 ~9 T# b, ?( G- g5 A5 eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) h2 u3 j t0 u. R5 L6 u6 a** Set the serializers, Currently only one serializer is set as
5 \2 G9 k; o" @! {% y* Z+ i/ p& N** transmitter and one serializer as receiver./ `6 k0 o1 ~+ v( e+ \/ e: a
*/% E( o3 @1 S7 ^+ B% f/ I, j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; ^8 J- f3 h8 M- m- e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% M2 l* M( ]1 U c2 ]( e** Configure the McASP pins , \! O0 m: m* K! \, D& [" j6 X, i
** Input - Frame Sync, Clock and Serializer Rx) Q% I) Q2 J H+ w1 g% o7 P
** Output - Serializer Tx is connected to the input of the codec ) D" j2 N" y7 y* Q+ ~
*/% x, {2 v4 g+ O S3 G" ?# e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 [) w1 f& k7 G) c: _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; ^6 s/ I+ E' i% f; P& SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ I$ a. H; r, @8 v6 @ r
| MCASP_PIN_ACLKX
, q# t4 P: m( O& T; y1 s! u3 R| MCASP_PIN_AHCLKX" W* p3 d! {) z& O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 |. e! A' Y4 l, z8 fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : }: ^3 R0 Y1 ~% h
| MCASP_TX_CLKFAIL 0 S S. A( E- C, X4 Q9 j
| MCASP_TX_SYNCERROR
1 |' e! K7 R4 ?( R- ?/ c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # c+ V0 A" j; L1 R k- i2 E$ P
| MCASP_RX_CLKFAIL0 W& H0 z& S. }8 W6 ~1 X
| MCASP_RX_SYNCERROR
" B! B! G# b) o- p; P| MCASP_RX_OVERRUN);
; k2 a: {/ j# _9 C- Y; @) @} static void I2SDataTxRxActivate(void)! l& H, o0 }" ^- o8 b, l
{# [3 Z) \! O% [, d" j
/* Start the clocks */' }6 L, d& y8 U* |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: M7 i4 R. h' x$ Q/ _ i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 T0 }5 @3 @4 I% A3 L; c5 e% m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 ~/ T+ X9 \$ o# f) G; sEDMA3_TRIG_MODE_EVENT);, w( P; T# c: e9 ~' Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; M4 R6 W: x" \. t( \9 K% cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
`# t5 s @" s$ e5 g: JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" F( v& D) w7 O* U, L3 O5 y2 x% E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- {% }% V4 o0 C3 P8 a* ]- f# Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 K/ X9 Y1 g; V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% _# z0 \* R! x5 p) W. d# L3 PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, o# o* a0 H5 L} 7 @4 P& q, v3 b( d4 j7 x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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