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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. M3 J" \$ a5 S q, p7 D- Yinput mcasp_ahclkx,+ n9 t, _* V( N8 C. t1 P
input mcasp_aclkx,
* z: d- h% @5 C- t/ b6 i7 ]input axr0,, y. Q+ A" C# b3 j+ b
+ @ P1 B2 s5 c1 ^6 _/ l
output mcasp_afsr," i! Y, X5 ?; {% G0 M
output mcasp_ahclkr,
F1 y: O7 v+ Ooutput mcasp_aclkr,
# L# \3 u( b- b+ H5 P7 N! e0 j6 Youtput axr1,, L0 \( ^' |2 u7 A
assign mcasp_afsr = mcasp_afsx;
6 R8 l- p! h1 n7 \) Gassign mcasp_aclkr = mcasp_aclkx;! v! }: `! Y$ E$ r) B8 I7 S C
assign mcasp_ahclkr = mcasp_ahclkx; _! I; B Y. ^2 y) l$ m
assign axr1 = axr0; $ z9 U% M& T1 U7 @& r L7 ^0 W# x
3 f/ K3 E6 L, h, A5 Z, ^, \+ Q- }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : }! {; x1 V( D# O9 s
static void McASPI2SConfigure(void) I) H! ~) ]# V
{
8 O f" H% n2 z% M$ h4 h' b5 g4 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 p/ |# I+ V9 g" v( ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" l9 `. _4 {& u7 p1 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 D4 Y! D3 t! M, {4 NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 o0 ^! [ I; i7 `' @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. o: j5 {" q/ w8 Z' z8 v: EMCASP_RX_MODE_DMA);2 e& [: b. a8 w. \0 O2 @2 _4 H/ P, F% M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* c; W- p9 n( d, JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 c6 ?" d. x; H+ J4 I+ Q5 G% q2 c) ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / _% p% x- G4 [# L9 p2 l+ v5 ^6 i- ]. n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) M' m/ s0 W' d6 r+ u* y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 h s9 {/ {7 w' L% e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& F9 c5 [, r! Y6 a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 S) w j' u: k) |2 `+ n. `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 n5 D2 `! }) z- F4 M2 eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
V6 o4 w6 J4 H" v" f+ ^5 u5 x0x00, 0xFF); /* configure the clock for transmitter */
0 @3 X6 e, T, Y bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 R+ `. k, K( Z* L( L3 f- s3 hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); L( |0 q# F6 g) w |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 @+ }% A3 Y) I: m! ]/ l0x00, 0xFF);
0 |- ]9 s$ c- T4 N" s+ Z
3 }0 d2 Y1 K3 y4 `+ K, N/* Enable synchronization of RX and TX sections */
6 W0 P- n' x; q2 _3 i( lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' z: ?5 u( b! f" V. g4 w! u* @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: {+ ^4 [; s) v; `; g) _9 {7 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: B! Z9 Q5 f+ v' \* u# G+ B9 k
** Set the serializers, Currently only one serializer is set as2 N+ Z0 }1 K( g3 R+ [6 z! L( s
** transmitter and one serializer as receiver./ g) t2 T# ~8 q; j b
*/" B" C! u0 T& Z! J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 I5 y7 ?* q/ \3 e5 y3 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ u9 q! d6 |* r' h( P" w** Configure the McASP pins
- O- I3 @, B8 `& Z# S% M** Input - Frame Sync, Clock and Serializer Rx0 h- P, b z5 Y: K9 c( m8 f/ V
** Output - Serializer Tx is connected to the input of the codec ; p4 v) G! `, I6 f& h7 A4 c0 w
*/
% }3 E$ Q8 E3 w* IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: Q! Z7 u" C% j( `& h( F2 @5 @; c8 RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 ?5 e4 R! n0 g( @! d& g JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ D7 h4 `$ n7 i- g% f; F( w5 H
| MCASP_PIN_ACLKX
# c3 @! h& @- ]- ^5 {7 c| MCASP_PIN_AHCLKX
/ M, n% a5 x. d# ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! U% R7 v6 }5 H, U, u$ [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % V& h# ]' ^2 {7 j, h) t; V) D& I
| MCASP_TX_CLKFAIL 9 q1 _$ ]% ^: @
| MCASP_TX_SYNCERROR
' F& `' ?% Z! o: d. _) t. {% Q2 ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . h2 s5 e' T4 `+ R* Y3 l ]( R
| MCASP_RX_CLKFAIL
/ g% [+ K; k! g7 q- U# g! U* q; o$ x. S4 Z| MCASP_RX_SYNCERROR
: d9 W& O8 g. V' c7 D. b9 @| MCASP_RX_OVERRUN);0 A$ ^6 w( z5 \6 H
} static void I2SDataTxRxActivate(void)
8 _) F- l1 k% u4 M" ^- L, |, S{
/ F2 S3 s4 `) l' U5 w9 K* I/* Start the clocks */+ Y8 D) U6 f! g' P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- h9 ^, Z! {- V& gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! Q1 w% |4 B/ t, T3 |+ ?+ ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ H( L% ^8 l3 q* xEDMA3_TRIG_MODE_EVENT);
( H0 N7 C) H$ r0 ?1 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# C8 V0 s0 e8 Z5 n7 X% ^# X2 [! zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 b$ F, X) I$ y$ w+ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 H! f% f q9 k# GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 I1 O3 g8 r$ ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 l2 V( _" M4 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' z1 v G8 R: P f! B/ K4 n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 _5 g* Q( \+ J( f, ~* ]" Y2 C/ g}
$ Q: B7 B# M- ]: k: V( X# p8 h9 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 \% Q X8 Z" l. r
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