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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' V0 ?, I1 ]: }5 Q/ a+ I! X: U+ T7 Binput mcasp_ahclkx,
. F$ W: z: [/ G# E. }2 b) \( @input mcasp_aclkx, ^8 b F- s: P6 {8 D
input axr0,* ^* q+ Y, u) ^- {% \+ x
5 f! f- ]) z6 Z
output mcasp_afsr,
8 ^& `0 u4 k! C) R" Doutput mcasp_ahclkr,
$ m" n( U; Z; houtput mcasp_aclkr,; K( Y, K p6 O K2 q
output axr1,' h/ |/ U+ G" ?( Q+ R3 J5 o" m
assign mcasp_afsr = mcasp_afsx;
' A: Y! O, O* h% Kassign mcasp_aclkr = mcasp_aclkx;7 b2 A& z- I8 `4 V h
assign mcasp_ahclkr = mcasp_ahclkx;. f0 P: j' ^& L; x. P
assign axr1 = axr0; 5 b5 a5 o3 j) |
3 R1 C- g# L* Z& x3 p( K* F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 V% V5 n( L$ j E" ~static void McASPI2SConfigure(void)
' G: R: f& V9 P! Y3 Y7 G C* T3 z9 ]{2 t) @$ j* f& N% O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 W ], }; j+ @; l" e0 h5 A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 Y. R2 K( B" M, Q2 R8 W3 f* p$ e4 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ L* y' T0 R; H6 V2 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 _0 {3 f$ d2 N3 ]+ I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, t* m# w; s. x& k# zMCASP_RX_MODE_DMA);
6 q& s( R: R! m, A1 z& m9 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: x* u6 Z! _* ?+ z# b1 L; v. w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, Y9 | e! L* W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. U0 `# k; x7 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 o( W7 O: E( j. o" m9 J2 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 r* d( s9 O: R. iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; n) u9 I1 R. |$ C" V6 j4 {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. x5 `3 p# R4 K) j4 O, e' C5 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 e/ g8 O* f7 I' q2 V2 ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 k/ Y3 D7 @0 ^( {5 ~( f5 M& j0x00, 0xFF); /* configure the clock for transmitter */' X, b' z2 s: Y$ R* \7 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; C) L. B# O/ I: uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. e7 T9 v0 _" `9 i, zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" J' x6 m; x. n- t' k9 ]0x00, 0xFF);
# w7 F# @, l" O7 C) U* ^) o
, o$ _0 M% n/ b, `( H! j8 p/* Enable synchronization of RX and TX sections */ : a! J! u' x4 u0 t/ u* w8 {$ E9 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* P% M3 E% f/ O$ @. R3 [6 H6 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' v, J6 z# x/ f- p) u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 h& N N$ h% v' S7 E
** Set the serializers, Currently only one serializer is set as# ]; P8 V2 C, J e5 z& h
** transmitter and one serializer as receiver./ m7 J$ E2 G% I; j# G
*/
7 u! V H& Y9 \* GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ Y+ j) G; R( m [+ E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 ~' p! A% ]5 ^' p3 n/ U% Z' k: r
** Configure the McASP pins
, B; G3 N; N0 C f8 B7 c2 ]** Input - Frame Sync, Clock and Serializer Rx! Y5 k' {5 r1 a+ Q% B( ~9 a8 _
** Output - Serializer Tx is connected to the input of the codec
8 S4 M+ J3 `! K*/
* P& k# S& d& P- ?6 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 t# S' ?" M G* D, L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 u( k, \# {1 h; d9 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 Q/ J. x0 W/ k/ ^: q; ?
| MCASP_PIN_ACLKX& W$ ^( Y* ?0 L2 ~
| MCASP_PIN_AHCLKX$ d+ ]5 S2 a- N; G: Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! p K1 _ }; ~- ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % D% m2 u$ F& S1 |, D% U g
| MCASP_TX_CLKFAIL 9 {- G& d. E E9 u$ {$ Z- f( O
| MCASP_TX_SYNCERROR9 I3 F, H0 ~" ]) n; o h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 ]" u: S0 N8 Z* i3 Q# f| MCASP_RX_CLKFAIL
! X9 F' a$ }/ s, h+ J9 P| MCASP_RX_SYNCERROR
2 X' |3 Y; V* A% y" X# f| MCASP_RX_OVERRUN);
V' Z" E; p) W* S6 \- K& y} static void I2SDataTxRxActivate(void)7 s; Y" i, j: H. k; x, n- u
{
3 u$ g5 q7 f2 X/* Start the clocks */
4 \" {- s# c3 T: S0 e6 D" H/ {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" K8 A* E. n" r, ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# Z. |7 z& ^8 i) q/ n7 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: b5 e* I8 g2 \, y9 ~
EDMA3_TRIG_MODE_EVENT);
7 {3 {2 C% P! r" W3 x& PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) M3 ~2 W: I) }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 s! N7 W8 A& o& l/ f5 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 l' O2 e/ {8 [2 [; h2 N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 \$ O: \4 w; V& I& t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) z4 c4 O( f5 m1 y8 O+ `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 a4 t. T7 @0 c, ^: b7 D) s# L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) b0 H; K3 r) M9 n1 f( c}
* L1 F1 M" b& @$ h* S6 K$ A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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