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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 w) v, Z4 j: n5 y+ g, Jinput mcasp_ahclkx,- T- M, f' x" l2 J. F+ R6 C
input mcasp_aclkx,, |3 u/ K0 J% U! s' k& Q
input axr0,
: t; G# d/ m6 W( n. a# x. u+ [& j" y# B( n% |- ^+ L5 g3 g
output mcasp_afsr,6 K, @4 O! n" _8 A( X1 ]
output mcasp_ahclkr,
5 f \5 f: G: E, S+ M+ noutput mcasp_aclkr,
" G. B7 ?3 U2 y" qoutput axr1,
# z+ E9 i4 {+ X$ q4 Z assign mcasp_afsr = mcasp_afsx;7 t; d; L( y. ^
assign mcasp_aclkr = mcasp_aclkx;
/ _5 e1 }: ~3 e4 ^3 E8 m. |9 dassign mcasp_ahclkr = mcasp_ahclkx;* ^! r" v* _6 S1 j' H1 c9 R
assign axr1 = axr0;
' Y5 K t9 O+ r& w1 U2 k2 O# p: h& f2 s6 s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 }4 j. k2 i: R9 E! W
static void McASPI2SConfigure(void)
: A5 m+ h, \, Q- |{% h8 v S% X$ f( c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: Z2 Q: Z# l- Q* `- L: O" e( vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) ~# N F2 n" W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 U. P3 n' U* @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ [( R" F; L/ G1 ^. Y* P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ X3 _- j% |/ k/ y, M q E$ P1 A
MCASP_RX_MODE_DMA);- m+ r: L& D3 U0 Q( r. Q4 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: `& N0 O& w9 P3 ~9 L/ n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 w+ @) E' |9 z* D3 K; T, B8 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* U- O/ Z* P" p+ H+ {0 o+ W+ h# {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: K8 n( k. s% B) Q: j; \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ v, C7 h! r. Z* A1 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. e! T4 U" ~& l6 H2 `' PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; `% Y( t) Y6 a7 b0 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# c- D" `$ B. c1 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* d9 W3 _6 F5 i7 Q
0x00, 0xFF); /* configure the clock for transmitter */
- J( J. {, ]/ t. K3 PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ W& l. `& I" i0 s; ^, W' d3 c+ R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 I! v0 K0 i5 \5 V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' B7 }) x% ~ {- C0x00, 0xFF);+ B2 U1 [% ?! r4 b' W3 S# V
( T' p9 J6 p. V( h. ^
/* Enable synchronization of RX and TX sections */
# z9 V+ [: X( E' Q. ?- xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 q% L# ^% o m) r1 v. c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 W% E* L; d, U; ~6 A& R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ L: B4 v) X# V2 z! o
** Set the serializers, Currently only one serializer is set as6 D# Y' L* _; q, J. X) ?
** transmitter and one serializer as receiver.
$ b1 |. v" Z" W$ A# L*/
. _3 \9 I. `0 c( k" r2 u8 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& T7 J1 M) c+ W- r# t# ?" z" w* mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 J9 t3 m, T, X- F l. M$ R** Configure the McASP pins 9 z7 H& n7 Q3 w9 `$ o9 Z+ X) p7 E
** Input - Frame Sync, Clock and Serializer Rx) o' G; e6 ]) A: {/ q: |, j
** Output - Serializer Tx is connected to the input of the codec 6 e- z: D; q3 f8 T7 v/ B5 Y. w1 Y
*/; z3 h: _4 @* K+ |& \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: ?. W* r9 `( g6 A5 J1 o9 w% q+ o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, G! S& p% h. F/ V! a% V- ^* TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ R, O3 ^* W1 H; k" [| MCASP_PIN_ACLKX* l" J7 X: K9 C0 a3 w
| MCASP_PIN_AHCLKX: M/ J# b. B# p4 q- v8 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: v+ C2 B e5 S& R i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( W( z: Z5 o+ d| MCASP_TX_CLKFAIL
& I* J" _- R, S+ B& i% y' w4 {2 g| MCASP_TX_SYNCERROR
8 S7 [) X* v! h2 T" j& O* k/ j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 G7 a3 n. T+ f4 ]% M- F| MCASP_RX_CLKFAIL
8 J1 Q4 @* u, r" O& {9 }1 D% B| MCASP_RX_SYNCERROR ! Y; u- u+ }4 Z
| MCASP_RX_OVERRUN);- E. ]% w' Q' @6 b- V4 Y, h* J
} static void I2SDataTxRxActivate(void)8 O: U; t1 S2 _- }( Z. |7 H
{3 T; h: v1 U2 [ {
/* Start the clocks */! O3 V$ L$ }* x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 ~1 x" [: b0 J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ a# X7 G* u, `8 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ |7 W! S9 k7 N: W
EDMA3_TRIG_MODE_EVENT);
% a3 }9 z% n+ s+ t( x4 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - Y0 Y7 ^) b6 {6 m: ]- X- C# f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 m# e3 t( a. o+ y3 f' bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( T5 z8 G: K$ I0 }4 @ O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( \9 {# X5 V3 V2 @" a& I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' i# K# B' x6 Q3 mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ e" ?# z$ s3 h8 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) n# Y* [& A) Z0 x) O) _
}
% e/ k- j! q) a& k4 r$ O! F/ p0 N( X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! X9 i% R- p" l) ?7 E
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