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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ \# d! D1 j" J# M$ a; P0 v6 `; Jinput mcasp_ahclkx,$ S! r7 i/ ]. S% r$ e: Z
input mcasp_aclkx,
* | x. z9 |5 |: S# t. ainput axr0,2 l# X" V; A& O& f9 a1 P: N: h0 Z5 f
* ~# T, ?* V3 z* g* o& }
output mcasp_afsr,3 I5 ^7 G& n0 i% p
output mcasp_ahclkr,- Y+ ]5 b6 r. E% l3 @" v ^
output mcasp_aclkr,
- q1 T8 p- J R0 \, routput axr1,
# u4 J) F5 U7 l: N* ~ assign mcasp_afsr = mcasp_afsx;# p, ]0 ]# n% N( O4 Y1 z
assign mcasp_aclkr = mcasp_aclkx;3 c( @% A) H4 ?- z8 ^" e2 S
assign mcasp_ahclkr = mcasp_ahclkx;
1 Y% Y, D: @, b Z, ?. ]7 U2 Bassign axr1 = axr0;
% f; d/ z0 \& G3 _) ]% J: W3 |; C$ E2 P% p; o+ A/ A, ~+ t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 i3 B8 p! f3 n* l! R
static void McASPI2SConfigure(void)
' l8 \) J8 q5 u1 V{
3 V# }) M, r5 B: ?4 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: d5 [- W, K5 D4 o$ ~ |, ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 G3 D# _& _# H. c- C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& @$ U' r* L0 H7 r7 ?& uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! o4 F) `- J5 ]# X1 rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ m( G7 I' y" K. u4 c! j) l8 kMCASP_RX_MODE_DMA);+ O& b+ r7 B+ q6 _8 ]7 Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 B5 q# [5 o0 z6 }# O# x# H m/ eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 s% a7 H# K6 E9 q0 F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# b( ~6 w {) K& {( Z5 DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: O; g4 O! v. Q2 J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& ~5 |; @, J; d W" F9 D: tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% A" C$ ?, i. K# {0 m& d8 lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ Y( e- E- L! D$ M$ `" K3 x* mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# ?4 q3 Q* h/ D+ hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" u5 s3 S5 q$ B. C6 ?$ J2 x0x00, 0xFF); /* configure the clock for transmitter */; J2 h3 I W6 w: c9 J% U6 g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" p& X+ N* w5 g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" U0 b& Y1 O* O% BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: ?* e; ?+ |9 B
0x00, 0xFF);
9 a; L- D& s+ _! v, k& ?0 Q# v4 [) V! x E" N/ c3 z6 S
/* Enable synchronization of RX and TX sections */ $ w) N/ M8 j. I3 d8 s0 @+ I& g- Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: f; w0 _/ M* F8 p1 ^- x; \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! f U5 u: ^" C& T0 L+ ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- Y9 j) [% I/ X/ R1 ], q# ~
** Set the serializers, Currently only one serializer is set as
2 X4 [/ r% r; O: Y3 w' @1 Y** transmitter and one serializer as receiver./ y2 u/ V6 J; S9 i* z
*/
. i n& J: Q( c' q7 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 P6 Y9 k! x; j( Q ^" ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. y5 z4 M h) w L! n
** Configure the McASP pins
" _: ]7 ?* e4 z# S ?** Input - Frame Sync, Clock and Serializer Rx: b: h+ F1 h0 { c
** Output - Serializer Tx is connected to the input of the codec 6 w) ^1 X+ c9 V0 _% G* ^
*/# S+ E$ ?+ R& l+ Y0 d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- K& r5 G6 |, g! h/ A$ tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 w5 I: D. V6 N0 ]" N9 q: AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% b, q/ {. o6 U4 G8 j j
| MCASP_PIN_ACLKX
1 _" X( M* d4 W& G2 ?1 l| MCASP_PIN_AHCLKX
3 N+ r) ~& p, V- s3 I: Y! i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 B+ K4 k$ p3 B( r5 V- n% f; C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 n! z' V% z q* k* }
| MCASP_TX_CLKFAIL
% @# c! D0 k4 [. Q' C. e) \: t| MCASP_TX_SYNCERROR# p' C0 [, E' J# c) u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 B( e- A$ r3 T9 B8 `8 c
| MCASP_RX_CLKFAIL( m1 z( k. _% P# P3 i y0 K
| MCASP_RX_SYNCERROR 0 t' c; t3 y9 W! n$ i9 h
| MCASP_RX_OVERRUN);
6 P6 _: a& m# u4 x ]} static void I2SDataTxRxActivate(void)
' U5 z" T6 x @+ Z+ d4 R! U! p( h{
. n+ x4 S `) C% n/* Start the clocks */2 [* E( P' B2 D; B& \- ]- ]1 L* y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; U; f2 `- {* M$ ~9 c# k0 J& d; RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ P- i) D4 g0 T" S+ s, n' l$ j0 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! b- c+ _) s9 k( k* c) ?
EDMA3_TRIG_MODE_EVENT);+ f: ]/ E0 I9 P- Y, R1 l4 F( D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) S* y& K+ S0 s7 D; l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 E. D, R# `- w$ v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 ~6 U3 s5 G5 L* |+ x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. l- T3 X e) g5 b! [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 z j) {0 g7 `5 ~! C, X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 L4 v4 x+ H+ B1 q* e4 \% L# U' S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! S( }, O% u( k# W4 I5 |
} & f* N; x1 \) f- Y2 ~4 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 y" A6 k' A+ U. V1 u
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