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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% O2 V2 c$ A4 b3 j/ h* T5 }9 g
input mcasp_ahclkx,
7 |8 L% U7 t0 j5 O+ b- c1 [input mcasp_aclkx,
% q7 ~, v& U1 S/ X m2 ]& ginput axr0,& V1 I8 K4 R6 U$ Z1 @
7 ^" A: y. i5 @. m) x- G9 Goutput mcasp_afsr,0 j7 w# K7 p- ^# N* K
output mcasp_ahclkr,
9 F* V% E0 y: O2 Youtput mcasp_aclkr,* t# Y5 S. Q0 v) N* _9 _+ _
output axr1,2 J. |2 [8 l5 F. C
assign mcasp_afsr = mcasp_afsx;
3 l1 V1 m( f' v/ d4 h6 @" ~assign mcasp_aclkr = mcasp_aclkx;
6 E0 f# D0 M5 [- t% n8 wassign mcasp_ahclkr = mcasp_ahclkx; H& [+ K. s( e$ ]
assign axr1 = axr0;
$ M Y+ F2 [/ x5 A) K( f3 d W
& C. l' _/ R9 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 v% W/ |9 Q) j3 D) G% P8 P# [static void McASPI2SConfigure(void). g$ f3 J8 z c+ w, f
{
9 F% a3 r5 m6 h# u) A6 @0 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 V4 D/ \2 I6 u, G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% w2 V$ z: T* W7 T0 [' u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: W' o" I3 Q! c" mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% f1 Y4 i( {0 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 z0 r: G6 ~3 H" m' z; l
MCASP_RX_MODE_DMA);9 G3 Z1 _% p8 e, J4 B' r* e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 U) |) t9 }' A: |5 q0 r' l) z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- f& M" q2 ^- U0 EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, {) I& t0 D' D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 V3 n& Y7 a8 ?# u2 BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 S) d( I8 X+ EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 e* g4 S9 _; X: M+ e( iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( I# R2 o, S$ }9 f( }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " x# x% H9 ~" \4 n3 ]- H0 T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" m% [ m5 f- [! k" _' l2 n0x00, 0xFF); /* configure the clock for transmitter *// b$ ~4 F, p2 w& ~5 ?) Z& I2 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# W* A1 _/ }- X4 Z* Q8 G$ y9 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + I4 S- F1 C# K/ I/ Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, w' ]) T) P* K7 W9 |
0x00, 0xFF);0 Q- ]% m$ Q! d1 t, ?$ l
e6 d4 H$ {0 q& H$ }/* Enable synchronization of RX and TX sections */ * h/ b% _8 y n. e7 K6 n( H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) v0 d7 ^/ }. H8 H9 ^! `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) l% C1 C ~$ \$ U" w9 |& [! DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ E- m, A. i% Z: b2 ]3 |
** Set the serializers, Currently only one serializer is set as. ^4 N1 }) z$ c) [( i
** transmitter and one serializer as receiver., n4 v; H- P4 D! A2 q; z
*/1 g- I, P9 \% j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ c, t- H- \" s# p5 Y$ hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 E) ?+ L0 @3 x( p, `( b
** Configure the McASP pins
0 j5 [3 [& x' o q/ s** Input - Frame Sync, Clock and Serializer Rx
- Y8 u7 m, d0 E** Output - Serializer Tx is connected to the input of the codec
# Z/ a) ^- \& F* q6 T* j*// f; w" d1 s7 W3 D) s# m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' b; S$ S& n a2 H+ VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) i% f8 j: R o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& w- ^6 _% y' H
| MCASP_PIN_ACLKX
" r' `. {/ r, p& C0 ]* y9 z2 O$ M8 o$ a| MCASP_PIN_AHCLKX
" ` {- T9 n4 {+ C$ D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- }6 [# m7 \4 x5 K5 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 t' c6 T. Y+ n# z9 }2 d% g
| MCASP_TX_CLKFAIL
( m8 {" t' L9 L- v# j| MCASP_TX_SYNCERROR
6 u8 Y; F! E( w: \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, d" h7 b- X* P0 Y| MCASP_RX_CLKFAIL% l2 C( V+ _" E+ `6 L C
| MCASP_RX_SYNCERROR
/ K0 \ ]; Z' ~4 G| MCASP_RX_OVERRUN);! H. a( n0 q' I. E) H" y! ~' u
} static void I2SDataTxRxActivate(void)6 r; p3 u; @* B( U' s3 [
{
1 ?2 `( a& r4 ?- L& ]/* Start the clocks */
5 ]9 ]2 a1 B j' _0 [# I+ V. h. hMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: o: j2 n- ? W, Q5 o E# iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 f* I, m t* T2 E' GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 Z; E8 J# p5 fEDMA3_TRIG_MODE_EVENT);
* f1 D% i( T& N. fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , \& j4 N1 S/ d- ` Y B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- m. ^2 y& h) `8 L$ _9 p9 Q- _# u- QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# r( m1 O$ j) {0 }. e4 X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! `, S- R( x/ M9 Z2 twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" P3 t& K: e0 g( X6 b2 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. o9 r! J1 Q- C, ^! }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" @, M) @" D1 K. J0 S0 m" e% \} / }. q' g" R S) K' D ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 Z6 O* D8 V' p/ O( m0 g
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