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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# V I! K' G+ f$ K" _/ R' pinput mcasp_ahclkx,
1 h; I: e+ [0 j# |& o: `input mcasp_aclkx,. T% U, _' K4 f$ v, R* W* f2 w- f4 M
input axr0,- j$ i/ T5 S! |
@* O/ }4 k1 p
output mcasp_afsr,
& \; @4 H7 B! A# W+ q1 toutput mcasp_ahclkr, n! U0 x3 O! }" w, y& ]% V
output mcasp_aclkr,
% P6 J: _% J5 C: C4 |4 Uoutput axr1,
+ i) J4 F$ U$ N assign mcasp_afsr = mcasp_afsx;
7 z/ y5 t+ k: n1 `assign mcasp_aclkr = mcasp_aclkx;$ W* Z* j! _) ] e4 x8 a7 N# @" L7 a# H
assign mcasp_ahclkr = mcasp_ahclkx;
9 X! ?' R5 o" [" m+ Tassign axr1 = axr0;
; q6 x7 }( `, Q) @. z# l
. ?8 {8 o5 F- Y; J& n$ B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ t# S# w2 z: K* lstatic void McASPI2SConfigure(void)
% O' r( E9 ~8 d/ [{
# [+ {* m+ N4 |" mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" |* F; J, n5 H2 G- g, c+ h: wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 i% a0 E/ F- B# L; j5 Y6 ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 Y2 j( g' J& O' e5 k) q& yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 x- X& ~# O' A9 U) @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( e) ~6 w. |2 m; j& q) \4 |- AMCASP_RX_MODE_DMA);
3 ~% |1 g- q: o8 X# wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- H) A/ o- L, ], vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' j4 @" ?. ]9 L! w' O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! W* W% \1 [/ e& x5 z- R, D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; G3 s: X' R# k0 t( _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 ?1 S% {. B+ h! e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 `/ p5 o2 `& @& r# o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( v: q& a! `2 M; V& @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 `% m, B& n! M. z# a( @3 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! f3 N$ ]; g2 v5 b1 i5 w0x00, 0xFF); /* configure the clock for transmitter */
9 L+ q/ r2 ^( d' U7 K$ }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 y3 i/ B5 } Z) [6 sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 J4 V8 l0 z. ]& ?) F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 J/ i+ ~/ B: X9 g& F4 K$ `
0x00, 0xFF);
" U$ o/ W. f' `( Q v' {) A* R) p7 w* g) @) ]* W& L
/* Enable synchronization of RX and TX sections */
8 Q, ?6 b& [# ^2 \# EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; v& T! |6 q7 U- lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 o+ C) b& ^% ~/ ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- B" L7 X2 I1 Z* j( R
** Set the serializers, Currently only one serializer is set as
- j" Y E0 {% b2 [( r. S- h- H% @** transmitter and one serializer as receiver.5 m8 a1 Z) X; e
*/6 q' n+ z- B; V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, I& Y; ^3 I6 X7 S) ?% m4 ^; PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% G) b; a& J, X1 P" B** Configure the McASP pins
4 k' C! m N3 }* x( e** Input - Frame Sync, Clock and Serializer Rx
) T1 C1 z. p7 Q** Output - Serializer Tx is connected to the input of the codec
; v1 y4 @# L0 @! c, b*/% T: \/ g* b* r* {$ o9 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! q* \1 {1 W' T u7 Q' C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 t+ v- q9 T3 h# q. [# N0 K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, L* A; \3 Q# B) D4 ~' N5 c
| MCASP_PIN_ACLKX3 h( I9 j6 }! D6 z5 J% U6 m' X' K
| MCASP_PIN_AHCLKX) l1 u9 m$ S- G7 z' X3 K4 ^) S7 r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 t4 P5 ?/ F1 Y: d- }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 Z8 O8 }4 \8 w| MCASP_TX_CLKFAIL
V) b6 v5 L8 @' n# a| MCASP_TX_SYNCERROR0 M' m; V1 Q" s& B9 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 e" l2 E4 b2 i: u: [4 P/ i| MCASP_RX_CLKFAIL Q- M" J& c! C! i6 W/ }
| MCASP_RX_SYNCERROR ' s" n. U* ?$ _$ o
| MCASP_RX_OVERRUN);* M% I {/ X/ h+ C/ A) s
} static void I2SDataTxRxActivate(void)
6 A/ V1 ?9 H, a4 g0 I/ I{
, `1 F* s* c8 [7 u/* Start the clocks */* Q; Y! s7 ?- S8 c& a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 d4 o. j& P0 _, W5 X N) k; `4 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& z9 b; A- z! d: a& l/ s5 i+ d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! c- r2 N2 W; [- l0 v) J: B* t, t- K; d" MEDMA3_TRIG_MODE_EVENT);
( U! ~4 F. _. N" k1 W2 x& U3 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( I- x5 X5 m! D' MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ y3 K$ c7 S8 A6 Y% e/ f, LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 B- C9 M( j9 HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; }) B; h7 k; A3 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. H1 o* C. _. Y3 J- W+ u3 U- c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, u4 W3 l) S( o" C& Q* h' C# v- q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" Q2 ^' Y2 \' x9 p# x} ' [5 M% ^4 N7 h) N" \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 M [& |* W% U1 M
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