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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ z$ X3 G# g+ V/ Q. Z9 F5 A5 p
input mcasp_ahclkx,% D& j: f6 o: T& J2 G+ Z9 `
input mcasp_aclkx,7 U" d& n1 |4 B: u. d
input axr0,
2 u& s4 K! x4 ~* W
2 l9 [* A$ v9 q7 boutput mcasp_afsr,: f5 t& P3 A1 n! c. k
output mcasp_ahclkr,3 g+ M W* c2 S' B0 h* l
output mcasp_aclkr,
' |! D- b4 u0 T( c! y- N5 ^3 Ooutput axr1,
/ ^2 H, _7 I% [5 S assign mcasp_afsr = mcasp_afsx;" b- b; d+ Q9 f" v
assign mcasp_aclkr = mcasp_aclkx;* [2 f( w! e0 T+ ?+ T0 ~2 x7 N
assign mcasp_ahclkr = mcasp_ahclkx;
, K5 W3 M1 [; a9 n P, \. sassign axr1 = axr0; : v. r* p+ R' w) t# _9 G( e- ^
; ~" z* _, u4 ]' V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . d. C2 t2 @, g1 f/ b7 U
static void McASPI2SConfigure(void)* E3 o0 I" _& o& `& y0 o
{- d1 n9 N5 M3 B* |2 K, U. f/ {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& ^8 G$ R( i* v: fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 \9 e) O+ _" j, D0 d6 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 I; x2 \" ]4 b# v+ p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 l6 H( J$ K0 T' g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 ~2 X' p* m" ?$ U" q6 vMCASP_RX_MODE_DMA);- |" T% s% P- W. U. |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ]$ V% N7 b$ K1 M" a9 s1 K+ C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ X5 y5 K8 L5 P' z& v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 J, J3 E* I# ]/ l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- z. T- V5 O: S# `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, M6 W0 Z. t/ e3 Y1 ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 J } g) ?: H* K, @: vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# q2 W5 o9 M) j- W; }1 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & b' v$ R2 f( T8 n, j5 m" _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 ]7 [' s+ j* w6 P
0x00, 0xFF); /* configure the clock for transmitter */# v- P& Z" J3 W. V3 m. h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 [0 a7 l1 j8 F# d8 nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 x& B* L2 x3 S* }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' d" D- N, o4 A0 Z7 S& W5 P* P0x00, 0xFF);! M3 s& n$ h6 O3 m
- N* G5 O1 ?+ A/ r9 q* G$ X+ ~6 j# ~/* Enable synchronization of RX and TX sections */ ; J ]) E+ e9 E% k; x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; W6 c( \4 ?! X0 `8 ^( ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 G7 Q' p3 y$ ~& e3 f. d9 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 c6 I! \$ p% n+ E, w
** Set the serializers, Currently only one serializer is set as
1 ?3 ]! S3 U# Z* W6 V** transmitter and one serializer as receiver.& \/ ]' q6 c1 U' G) x
*/
% O' _3 _7 F0 {* P$ \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 Z# }; y/ ~* w/ y0 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& ?9 z- o' U8 C. N4 Q+ Q5 v
** Configure the McASP pins * z3 _% D: U9 `4 e, [7 I
** Input - Frame Sync, Clock and Serializer Rx
( N& L5 l" h) [- ]$ c# }8 F% C9 `** Output - Serializer Tx is connected to the input of the codec
! ]9 t( Y# O: F6 o! o*/, a% V4 C7 ?, O u& e# C% {# M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* m6 M1 S7 O. R, QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- t1 |$ ], @8 f, HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; }2 O# \4 j% c% k- {, E| MCASP_PIN_ACLKX
6 @0 q9 ]8 Q: `6 M! r0 P$ R| MCASP_PIN_AHCLKX
/ y. F$ z' K9 _" W% i- [ A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ U4 I0 C$ g5 G+ C2 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) K4 l* V3 F) \6 D: n/ z5 w1 x| MCASP_TX_CLKFAIL % c) b, N4 B: \: `2 [8 F7 {4 h
| MCASP_TX_SYNCERROR
4 G M1 o% F0 M" @5 o# R* Z& F, B# I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 A/ F7 h2 o: e2 Y
| MCASP_RX_CLKFAIL
$ s$ ~* G# Y' K* g. U| MCASP_RX_SYNCERROR
$ W$ J7 ]% l. S1 B% m5 t| MCASP_RX_OVERRUN);/ @; ?7 j9 F9 n2 s/ y; h- L
} static void I2SDataTxRxActivate(void)6 d0 y* x4 C+ s1 [' g
{1 i4 B$ R- K2 t. j. R5 x
/* Start the clocks */
; M* _$ C p# `; @; L) Z( H1 \2 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% k' S4 ]( j% t* U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; E! X0 Z4 D8 i) q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 q3 }* O. e* T0 o, i0 g: a; Q5 S
EDMA3_TRIG_MODE_EVENT);4 z x! g4 }6 S, s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, F) u' n2 M! [0 d0 O& r/ c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" x: {' |% N' E' D+ KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ H: N* z$ s' e( E* A! ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ Z2 j8 P5 R0 b! B/ ]/ dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; N1 ~# s, ?6 O7 m q0 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& y3 g- x! K0 f6 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ h( c7 L5 |" G: J3 R} . D& M# c" n+ q: ~! A5 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 y2 B' H7 y* ~4 v% k, m( }& L |