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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 T1 Q6 l( Y8 Cinput mcasp_ahclkx,
2 L' X; w! {% e/ xinput mcasp_aclkx,/ U* r* z$ @6 ?$ |+ n# b* Z
input axr0,
7 T9 u. v9 h& C# ~, x8 Y' |# O# n/ f- ]$ }
output mcasp_afsr,
1 l3 K: D, z$ B/ G. D _( woutput mcasp_ahclkr,
3 Y' c: y: A* L6 G" j& ~output mcasp_aclkr,; j1 d0 H+ ^$ W
output axr1,
8 L# S ~5 {- o. a8 q4 q assign mcasp_afsr = mcasp_afsx;" Q4 x- h/ v7 K1 \( x
assign mcasp_aclkr = mcasp_aclkx;# B0 J5 ~9 [% b; H) G
assign mcasp_ahclkr = mcasp_ahclkx;, L* o" w) K7 B* Q! P
assign axr1 = axr0; 0 x" [0 q9 [1 @# L
# v+ e% w1 n& y4 j' G3 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 x: v3 P' V9 \- Y9 @
static void McASPI2SConfigure(void)
# n" a P' i, K! U5 }{
* Q! [/ K6 h6 c5 l, ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ h" r* f' z: O0 F( S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 T- b, v% N0 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: F9 z5 ?& N9 h7 }* A! T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 q* C; ]1 I5 _- OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ g0 Q' O$ X, [! `
MCASP_RX_MODE_DMA);; I6 @" W' v7 L" [6 O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
P# G2 w% p+ ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ }! L" {9 l: `' H0 S8 V1 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . h- T4 K' |+ L: E. @7 x3 i4 s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 o+ N0 B! v' r! A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, a7 a* S5 S4 v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% V& I; O- y: @( }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* r5 p) f6 ]: s( \. }, V- {2 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) v; Z! k+ k2 @1 E3 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, O, y' r0 t3 W. a! I- z5 r
0x00, 0xFF); /* configure the clock for transmitter */# E. g! z' z( ~; M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 V2 [. ^" H" L# r, k$ CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 c1 ^1 T$ m" A6 ? r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 t# f! d- ?( h# E2 d
0x00, 0xFF);
4 w& _+ I- S2 f* K1 G; w0 L( h$ C8 d7 R8 F( [( W
/* Enable synchronization of RX and TX sections */
^7 T; p0 S5 E- VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. y0 N2 X$ _; K; n1 E# D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 _0 o) M+ A- k6 _9 C, t' o% TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; K& o, \8 B Z** Set the serializers, Currently only one serializer is set as( Z- O+ q! B0 k1 J+ }$ i9 |: i \" q
** transmitter and one serializer as receiver.
1 r2 Y; ~$ \$ z0 E6 m5 w*/
; H( F# c* p7 b# ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. d' V7 [8 \1 A$ [* e RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' c+ Z* _8 A' |2 n% F1 N1 V
** Configure the McASP pins % w' M6 ^/ y0 C9 X# P
** Input - Frame Sync, Clock and Serializer Rx
2 _* X2 _0 J# U* _& g( E1 `$ @6 f9 D** Output - Serializer Tx is connected to the input of the codec + X! [4 q) e* u _5 A0 t
*/1 g1 R. G, {1 W% f0 p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; R& s+ M% K+ H& n6 Q/ g9 V# ^9 lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! O9 \! u% a1 m' Y! XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% C$ ~) I5 o4 m3 B$ r| MCASP_PIN_ACLKX
4 i n: x% w9 D) Y| MCASP_PIN_AHCLKX" ?$ Q0 H6 w% V) `7 x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; G9 f5 J ?. @6 O. J' d) ~2 c6 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 |& N( `/ I: @3 j! q& F( i| MCASP_TX_CLKFAIL
4 I O0 P7 }8 r* q2 |7 i% I| MCASP_TX_SYNCERROR8 a8 ?: J0 v+ l! L% T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 U! {" c, t2 z6 K; r! _' C
| MCASP_RX_CLKFAIL @1 h6 @' i" U1 M, \+ y
| MCASP_RX_SYNCERROR
# C7 f+ m4 s. N) A- ~1 H1 p| MCASP_RX_OVERRUN);
0 ~* L) P* q k% Z6 O- K} static void I2SDataTxRxActivate(void)7 c) Z+ Q8 m" T9 o" t8 m, `( O
{
( E6 h7 S& r" `6 V' F* i/* Start the clocks */7 d# M9 W5 y* \# F0 X! \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 K, ~4 _; ~& N; G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- w/ x" z9 _- @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 S4 z2 S- _# X( _9 K0 C2 r
EDMA3_TRIG_MODE_EVENT);
0 C8 Q3 G, X. L! K1 f7 [1 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! k+ s9 i, Z5 V) P8 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! @% B, R9 p4 _$ }! X/ C/ l" C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 w$ d6 O5 \+ ?" ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 m m! y9 |/ u* H4 @9 ^& pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* V; u1 p- d1 C+ G# o+ `5 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. U" ?3 ?' f" U$ r: ^* M' H& xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* \' t; z: C, V/ o) x% g} # I% M3 `$ M0 W, T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 q: i- A9 ^* C) U% d! o I
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