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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 X. r3 ?8 z7 n" P
input mcasp_ahclkx,/ e" a) T' K2 g7 Q- u$ Q
input mcasp_aclkx,
& O5 L8 X+ W' ]6 g" Y% y& dinput axr0,- v- w S, f' x9 y# ^; V
/ c9 ~% i2 A* woutput mcasp_afsr,; s. t) ^ K" w% M8 k3 _) n
output mcasp_ahclkr,
" \3 m1 c8 o) R$ ooutput mcasp_aclkr,( o! w- H* l0 f5 `6 q
output axr1,. L( v' `3 z# r7 K' F3 |
assign mcasp_afsr = mcasp_afsx;: U: N9 [* P& V2 Y- J+ U; t
assign mcasp_aclkr = mcasp_aclkx;
! @$ }- D# J: o4 Jassign mcasp_ahclkr = mcasp_ahclkx;6 k2 l1 P$ l9 z6 r: d
assign axr1 = axr0; 6 M0 ?* g- { c0 P
0 t! v1 l! j, ^$ \7 D0 b* C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; ?( o7 H" d: K `. W6 H/ r
static void McASPI2SConfigure(void)5 s, k% y4 z* q
{
; B9 j* Q! y$ }$ i8 G/ {McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 w1 n- E! @1 D' S; K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. Z) _: R* X5 C5 bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' \. \1 _9 d" \3 IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 M. R7 e5 W5 s4 g5 u$ ?" Z0 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. w9 e# ]0 G# y
MCASP_RX_MODE_DMA);( B7 w# l2 r2 P' d( O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 E6 g; N% ~- q0 W* O: C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 \, N2 L5 c- K( I# t1 VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' I& p: a5 I/ ]- L/ S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 J1 y5 ~* {" ^. @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 `7 k# ] E L1 J! x- q9 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 L, H( o+ f# m x+ @; D# E0 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* T1 n) ^ r v. R9 b8 hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + a& M- o3 s9 `0 |5 p" A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 p/ f! q$ ?1 W: t1 @' P0x00, 0xFF); /* configure the clock for transmitter */$ D) G( m2 q l8 N% U+ \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 ?7 k* G# F Q( e' w7 y0 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' D0 |9 ^, C# s' i: g6 M/ f$ D9 O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 Y8 c: ~, {( }' _" {5 H0x00, 0xFF);
% A! R, x2 \( ~& P/ l; H# K
+ }) N4 M+ h2 Z5 y% a& Z/* Enable synchronization of RX and TX sections */
f. M2 c2 X: [' I7 Q& i7 cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 z$ k/ `% P& c4 {7 A: M2 D& vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# Q6 J7 o" Q0 C* p$ D. ~. s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- K/ w# {% y; ], l+ i% H0 e
** Set the serializers, Currently only one serializer is set as
, {( f2 @- t% d: } x7 p: d |** transmitter and one serializer as receiver.+ |5 L% w* _$ Q2 g0 F
*/
2 f8 j. a! s1 v( uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ f; R5 Y$ f+ m9 k) i- v) WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 [% |: D: J# s' [
** Configure the McASP pins
# k5 V! @: j- P; N/ N7 y0 Q** Input - Frame Sync, Clock and Serializer Rx
3 I6 A( K& i0 c9 E3 f** Output - Serializer Tx is connected to the input of the codec - \9 S5 N$ Z1 w" E
*/9 e5 G& i2 N* Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ l& \9 O, h2 l* n: A( J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 N" V* c/ i% bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; k7 v% K" T X, i" Q| MCASP_PIN_ACLKX
3 A4 B. a1 S+ W" F| MCASP_PIN_AHCLKX6 x/ T$ `$ P5 C, R% A4 e+ I4 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, ~6 x+ {; B9 {" e2 fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 u3 z; o# G8 ?6 p* a: N% C: ~
| MCASP_TX_CLKFAIL
* p {. z5 t% F| MCASP_TX_SYNCERROR. H. N& ]! n: V$ U$ ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ ^0 U. x* p, o5 H1 u- t% n| MCASP_RX_CLKFAIL
/ e+ _3 I+ ?5 l/ f8 l* u& w| MCASP_RX_SYNCERROR 8 l: @# E2 `' F, P6 d7 ~
| MCASP_RX_OVERRUN);3 Q; y8 E4 I1 [- @. V2 Y R0 k
} static void I2SDataTxRxActivate(void)' `9 R- A6 _( g) Z
{
! y' e5 p+ P6 ~$ ^1 I8 J9 S/* Start the clocks */
" z' t8 T! i2 K& D0 tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 x" ]( {) @( y* n* MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 C1 f3 Q5 E& } N) N3 x- N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ ?/ ]7 ~2 o; r2 c3 x# b' x( ?
EDMA3_TRIG_MODE_EVENT);
. c6 E" Y8 c( s, M- H. EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 L! ^5 ]; N/ ^( z" B; IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 p7 [/ A+ \- r* C$ J% X" @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ Q9 N8 E ]4 `. i% b+ e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- h4 a( n$ S- d C' |. H6 z7 i3 Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 g( Q7 Z9 j% Q) ?5 O. r5 n& o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ l3 Q( R' x9 l: s* Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, f: M ~, V. D- T K
}
+ F5 `3 b# w0 \1 d+ `3 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 W. Y- Y' M a1 h$ F$ l1 D1 A2 n
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