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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) F9 { y# V6 G$ O
input mcasp_ahclkx,# J7 G K" N% f( d7 d; b
input mcasp_aclkx,
0 Q9 [. V7 s- jinput axr0," A" I) x B& `4 b
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output mcasp_afsr,
8 Q3 b5 y& h6 b% Zoutput mcasp_ahclkr,6 G8 U9 t6 S5 y6 w" q( n
output mcasp_aclkr,# F+ u& {$ @* H, E
output axr1,
/ V0 E* w$ S3 K& ]! k a7 A u# L4 R* @ assign mcasp_afsr = mcasp_afsx;
: _2 D# P- Y4 H+ Eassign mcasp_aclkr = mcasp_aclkx;
/ O; L# ?5 p/ `+ T) J* `assign mcasp_ahclkr = mcasp_ahclkx;
9 b* P8 }" h) fassign axr1 = axr0; + M9 c8 b3 M6 B8 m% V( ?
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& R+ b9 `- O: [! Cstatic void McASPI2SConfigure(void)2 G T, L0 }0 ^; L1 T+ f
{
- f$ B- E3 U* E- @) K, \" Y8 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; {$ h1 S/ b# M0 v3 Y/ X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# f Z; x) T* l) u; l$ s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 p' U' F1 Z$ DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 [& w/ x# {$ p2 r# D8 B; y; Y1 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# a5 w0 J5 m- I' }& Y8 J+ k7 V
MCASP_RX_MODE_DMA);
. \5 g( q* f- h- @! rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; Z! }: S: Q& T4 L$ v# D+ |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) o8 U6 k$ Y8 _( r/ Y8 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) d3 d9 x: J; G4 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 W$ s( h) y) o# c. m" A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 n1 n" r }$ i, I2 P0 H$ qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( }9 o2 }% _. CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ p4 t1 y0 v9 W! X6 X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- L, Y ~6 s, K2 j: }& |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," B; t1 B: K i3 p& @$ k1 v, x
0x00, 0xFF); /* configure the clock for transmitter */
6 q: c: {" v1 [: AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 e& R0 w# ^" a% U- w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 U9 ~" l2 b3 M; K: dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 M3 n" C: x8 \6 K9 f& M
0x00, 0xFF);: [* N4 f( |* d" F% k8 [; c
, i% l W- W" e/ m6 s
/* Enable synchronization of RX and TX sections */ 6 H* F2 i3 F9 ?, z. X; M9 i7 u8 N; b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 o2 L- H+ N9 Q6 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ {7 }3 a+ X; b. D- Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 g* Y: {1 k, H8 n( y** Set the serializers, Currently only one serializer is set as
5 _1 Q) x' B V- {$ l1 {** transmitter and one serializer as receiver.
( @. i' L$ L9 p$ w5 F0 T# t% k8 D2 ^! z*/, R b z5 d* v4 }, L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" x3 s, x3 P% A3 o- `$ gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' ~5 B* a- c3 }- H$ {7 t5 O* t
** Configure the McASP pins
/ Q- R3 e& I+ U** Input - Frame Sync, Clock and Serializer Rx
5 G2 C1 N% x4 h4 t' R** Output - Serializer Tx is connected to the input of the codec
8 ]; [+ i- s# G( b*/
) ?. W5 q% @7 Y( N* M$ P4 D: E5 s; UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) ?' \* \+ v$ v% c# |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. R% G: H2 D; M( W, z) C: d' qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# ]% \. x5 {# E& P8 U2 ]
| MCASP_PIN_ACLKX4 i7 e0 ^; J) l X& z9 K: v
| MCASP_PIN_AHCLKX
' U: v" V2 B& |3 ^* P8 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
H. l( A; A$ I0 B1 ^* ?2 PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR n7 E& E6 ?7 _3 `4 a
| MCASP_TX_CLKFAIL
A4 c+ w; s. t| MCASP_TX_SYNCERROR
; _4 a- U+ w" [ i. Z0 f( n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ G9 b9 A1 K0 C1 }' Z| MCASP_RX_CLKFAIL }8 [4 N& O4 {* ^- G7 c' d; x
| MCASP_RX_SYNCERROR
# l! k" [* o& } ?) c| MCASP_RX_OVERRUN);0 E" F$ S' N; o1 d7 J; o0 H/ a6 b
} static void I2SDataTxRxActivate(void)+ U. X3 x% ^0 b( l# m8 ?
{7 S) ]! L) y2 w! D# O8 w$ r
/* Start the clocks */
1 }% `1 P; ~3 `9 e4 |5 h% ]! DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' A) Q( V: A7 C) s! ^; q, y/ H, @4 UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: }% e) S7 M! G: e( b) e/ \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# R4 Z/ \& {, M/ TEDMA3_TRIG_MODE_EVENT);
* @6 n8 a0 G5 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 r) w' Z" O8 ~6 Y2 \/ `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: l. Q4 [' i+ `4 ]6 W$ y5 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 X; g/ M; `" c3 p3 I) T& v. H# K, v. N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 P4 ]: n2 u1 H! Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 ]: P) B) z/ ?6 d1 p9 n' dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# t% E. [ ]# D7 d- Z9 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. `0 V1 n9 [* n- D}
0 l$ g( ^9 T/ Z; |3 q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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