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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- s2 n/ v6 ? p8 Einput mcasp_ahclkx,( q$ J4 A* ]% ~1 r" L
input mcasp_aclkx,' a: v! S" S0 ~
input axr0,8 d: I7 E8 a a& ^+ A. b w: x
7 T, M- P8 e! Z; H2 u: j" L3 N3 Qoutput mcasp_afsr,1 c% q" F$ R) |# @' j
output mcasp_ahclkr,
2 r( o; j) O3 Joutput mcasp_aclkr,
$ [3 L/ n, U3 L" xoutput axr1,8 [0 Q. @6 }0 w1 L8 I
assign mcasp_afsr = mcasp_afsx;
' G: M0 x+ G3 ?2 {- k/ q5 Oassign mcasp_aclkr = mcasp_aclkx;
& h) ^: Y P5 x& ^# Cassign mcasp_ahclkr = mcasp_ahclkx;. P0 Z& f4 K: _& P% ^- c
assign axr1 = axr0; & o; V% b5 a0 V% ^" t- }
$ N- p& w* B' v8 ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 k) A- @% J& s- x
static void McASPI2SConfigure(void); \6 @% r/ H# Y) i6 P
{2 |8 q- E& r+ Z! u2 s% h( s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) t, U( _/ F+ y8 [( Y- V& xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# F9 W( H" @5 R, @* x. {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 ~6 E" c: a1 `# A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" B6 T9 W% i% H* A* u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
V+ x- C1 S0 Z/ ]# sMCASP_RX_MODE_DMA);
% Y6 G0 K3 L H" JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! }# n0 K0 {2 `6 A0 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: W, B7 t1 }) w4 F5 @0 L* D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 n8 Y: d! j* G# B8 M( _. _& w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( O# {" b0 i. ~5 c6 m5 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' j3 S# Z5 I. I; o5 ]6 w; n' b, oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; U& k. k' }! I& m1 D" EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 [+ X# l/ M5 Z, NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " l1 V, X5 E# X7 q( E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, `/ J( R s% S, U
0x00, 0xFF); /* configure the clock for transmitter */$ N# ^( d5 q* q( W" y+ z! L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 F$ U' n! T/ e3 ], G" i' G7 CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , c8 m' D6 G/ {* s% [4 N' y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 b# ]4 [! K2 o/ ~9 U! q
0x00, 0xFF);; x. x& e! c q7 \0 K8 q
t+ T1 k! G5 b- I( I/* Enable synchronization of RX and TX sections */
% r2 U8 D0 o! j+ ?% X0 X. j2 |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 ~+ O6 _" t0 j ?3 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% F# i1 m" F$ X" Q6 S9 r- N& `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* J, T! O& j" u0 G# k
** Set the serializers, Currently only one serializer is set as# o, v( j3 S% s) ^# I0 R7 `- D
** transmitter and one serializer as receiver.* _& L+ x( y6 Y$ m. l* ~
*/1 P+ c: }6 K! A+ h9 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- m3 S3 Q, z6 U* z/ P6 dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 t* J# l( G( Q/ j. t** Configure the McASP pins
# e( w$ K! B" I+ a0 x** Input - Frame Sync, Clock and Serializer Rx
; q" }$ Q4 `/ d' L# T% ?% u** Output - Serializer Tx is connected to the input of the codec # a) H1 o ^& n* G
*/
( R7 M2 k" I0 m* N( H3 X SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 O/ G" @7 m* `' x8 i' }; ~) bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! \# e" Q: _2 y( @5 V" NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 y; D! f; ?. R3 m( B| MCASP_PIN_ACLKX1 ^, {1 }- o$ ~
| MCASP_PIN_AHCLKX
5 F: M3 F6 c5 J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; j n0 ^! F' l( _* [0 AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 B9 t. G9 w1 g* G| MCASP_TX_CLKFAIL
, A* h+ b" R' v1 }* L# D, ^| MCASP_TX_SYNCERROR
: V7 P+ h$ h' C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 J4 M" w4 b! B- [+ `) z
| MCASP_RX_CLKFAIL. e: r7 x5 S% s0 b' o) M/ s! z
| MCASP_RX_SYNCERROR
! \3 ^( {7 f3 p3 G| MCASP_RX_OVERRUN);
0 d/ U- W9 t, J& J- e8 j5 H5 R} static void I2SDataTxRxActivate(void)$ O' h) Q# u _& y* l
{
- z8 r# L" e- ^; o! Z2 ~, r/* Start the clocks */
8 c! b/ w! V* l) ], uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( k# G# K5 o2 }9 V% B# GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 `2 o' q& k9 v f* C3 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 R v6 O# k2 B. o) qEDMA3_TRIG_MODE_EVENT);
& P; B! j/ u4 Q+ Q. x8 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 R j- G" B9 c% ~; e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ X% J1 H) ^; L, w1 J/ T& {8 L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, r' j; I4 O: _- D# u4 y! I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 n7 {: ^. J# Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& m3 n3 i0 K% h! d) J0 eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 [2 y& Y7 Q' e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! w w. B" K3 ]/ K* r( \
} 6 g; v. n% P* S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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