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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% o" W7 u! ]% ~5 S3 b9 l# S& ninput mcasp_ahclkx,
3 H# V3 D! U) A- l1 n2 ginput mcasp_aclkx,
# Q* |8 p U2 l2 [ R- o! oinput axr0,
0 L& N# e; |9 @5 l( j
' W* w' x, N) T8 U" A3 woutput mcasp_afsr,
3 z' D# ~$ I3 g# Moutput mcasp_ahclkr,
. ~8 {2 l" D( B+ ^9 g/ ?output mcasp_aclkr,
+ @8 Y2 R: {, R2 i/ n5 poutput axr1,
" O: B7 x, ^6 |- E assign mcasp_afsr = mcasp_afsx;
" {" i2 h* U* ` @4 r3 i7 fassign mcasp_aclkr = mcasp_aclkx;+ |0 W5 u: e! o0 v7 m
assign mcasp_ahclkr = mcasp_ahclkx;( ^3 s( r1 G, T. [/ t- o
assign axr1 = axr0; 1 B* _+ U+ s* C6 b- K$ Q
0 X- P2 a! x' d' |7 m2 T4 S3 ?; h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ }3 z, X4 E3 q* N3 `# z" astatic void McASPI2SConfigure(void)& p, Z' ~7 z3 Z# r \ [
{9 h: i5 a5 O/ K1 i- g! I4 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. y1 `* Z/ ^) {1 d! c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, I h; h3 C. B( G: |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 g# U' U( [, i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% u. L' U. @3 ?2 @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' f) c3 s+ m, w6 `! G/ `& I- ^
MCASP_RX_MODE_DMA);
5 L! Y5 e4 E9 [6 ~4 H* WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 d, V1 z' E4 c) P$ NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 P q# n; f/ ?, ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 ?, d8 \: {- d* X- ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) A; b- {: @0 A& R& { w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 @( O0 b5 v$ D. WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 i1 J; S) m) s+ r l, }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 N! I! B! n5 X- |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * c. B! V& I: V4 f6 C b G7 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( a7 h% N, r$ {& F B& N0x00, 0xFF); /* configure the clock for transmitter */; A" `/ j/ k+ `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# ~4 v# W q9 b- {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . v U6 n! z- ^: g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," \5 R! P7 }! u" Z" ~% t, m6 G
0x00, 0xFF);
4 C+ I5 G$ |3 y/ @' ~1 Y
2 Z5 a+ [9 G4 H, n) `/* Enable synchronization of RX and TX sections */ , p6 M& J4 P% c; o I1 e6 j" P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, l- ?' l2 D7 H" Z& o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" G3 m( @: q2 p( b! e/ H- K: sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% S$ v6 y( E0 h! O. ?5 W** Set the serializers, Currently only one serializer is set as
3 ?' v- k F2 f# a: [0 B3 b: a** transmitter and one serializer as receiver.9 z7 O* x6 r6 u' l. T6 |3 t
*/% O" |9 J! T5 n, O: S2 u! l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
X" [2 V3 V* B8 i9 mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 @! ~. B# s$ A( \1 ]** Configure the McASP pins
6 N. }0 x# c/ w' g8 M1 L** Input - Frame Sync, Clock and Serializer Rx
: ^ S8 L$ j7 ^** Output - Serializer Tx is connected to the input of the codec
' G7 T( v1 o* ?8 q3 l*/
, q# i3 d+ X3 ^9 f9 A# yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* d: s) R% C) N, p- b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' e9 T- z3 N& f% r' YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 S9 O0 A+ O! D# y# I& }1 A| MCASP_PIN_ACLKX
3 y- F: d( B0 N& U0 j# @. B( O' x| MCASP_PIN_AHCLKX* F) i2 h6 j9 @) j) x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* J. @+ B) S' I3 C. M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * R) _4 B b4 {8 `- L6 x. v3 F
| MCASP_TX_CLKFAIL 9 \6 E, W% p. |# J# r7 K; ]1 F/ q3 o
| MCASP_TX_SYNCERROR8 p* w$ N$ c q' I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 k- I# B; U8 \+ J| MCASP_RX_CLKFAIL
- ^7 K( I4 J' G6 i/ T8 {3 J2 A; y| MCASP_RX_SYNCERROR 9 d8 X2 p' z; L2 e& Q
| MCASP_RX_OVERRUN);
& p& a5 L- \( \7 r2 [8 G0 V' U} static void I2SDataTxRxActivate(void)6 l5 w% X7 z" y7 D8 ?* J
{
1 \) X2 B" ?" ?! v/* Start the clocks */
" c0 |4 i4 y1 ^8 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, B% G1 W: k# W; G7 U) O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& B6 _" v3 @. ^: D: |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: T3 S( e- S* O3 G/ VEDMA3_TRIG_MODE_EVENT);
# R5 B3 H3 |: K+ ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 D! W) e/ \" A$ a( C, u. F- N5 r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 X4 Q) y" v% z! ^; d. j q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! M4 ?9 V' K( z+ c; U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" K, \" _6 [, wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 g G k1 O& S5 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
P8 h7 ^( X* f; T4 p5 K3 K& NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 g8 H/ L) w0 h) |
} , A" a4 Z5 l) L' }& Y3 N& V: p& W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% A) ]$ v1 U# i7 k/ i5 ^* S2 P# b' J |