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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ P* j$ X( h5 T' G4 z7 }; Oinput mcasp_ahclkx,, x# o! I/ @' {2 a5 ^2 \
input mcasp_aclkx,$ E% l$ H4 ?, l) e( _* |. Q
input axr0,- `4 K y2 o4 R3 L% z1 z- B: ]+ B
3 l; [0 d" }9 A& M- loutput mcasp_afsr,3 O; Q- C! V4 Z7 G7 D. V
output mcasp_ahclkr,
) J& a& I7 h8 ]" w- s: o, l0 _output mcasp_aclkr,; V. [& X4 m6 l
output axr1,/ ?: W9 {! Y2 L/ a# J' \7 a7 r
assign mcasp_afsr = mcasp_afsx;
2 L* ^0 s! W2 d" \. Massign mcasp_aclkr = mcasp_aclkx;" o( @, C$ ]) F! k6 y$ e
assign mcasp_ahclkr = mcasp_ahclkx;
. m! c3 O8 s9 F& K8 D+ h: Tassign axr1 = axr0;
- o- E9 ?, D% P: G! R8 E% V6 A5 l% Q! O4 m( o) o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' h" m! S; X7 M
static void McASPI2SConfigure(void)( a( Q; y: V8 G/ t- d$ C
{
0 @0 [" p: }2 y( cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& Z5 \# k& I/ B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ |+ ^5 f, {8 z; O2 V, n& d, sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" b; B: a9 P" jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 A3 K) H3 w0 c! VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, P3 o* B3 j7 B2 _& i0 l4 BMCASP_RX_MODE_DMA);7 T3 p' }* i1 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, S y6 o& w- l$ k5 [* e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# r! U3 q4 s6 V9 b- p; B9 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ n1 u# h2 A5 w% g. l0 N( i. i" D# kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 l5 S6 z: Q1 A, S0 h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& W# t* @. G# p1 h* p7 u4 G7 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% \, v( J# y7 ?9 B4 ?' TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* r; h% i' H" W1 w) N" h) i" Y' m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 D# @5 b3 U) XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. [+ C1 a2 L7 ~ n+ k J0x00, 0xFF); /* configure the clock for transmitter */' e2 F% w# b2 h8 Y. E3 f Q: m7 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: o1 b! L* P# ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * M3 j( R/ _6 n9 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 ?- p' j- U5 d5 O2 Y
0x00, 0xFF);7 Y$ f, b$ b2 g; ?% P" Z
. c2 G( L5 `' ]/* Enable synchronization of RX and TX sections */
4 a0 W$ W# c- I' aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) r' b" V8 H3 z. p5 }3 l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& h3 R5 A3 U* k- w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( c5 T% R9 p. K' P0 C** Set the serializers, Currently only one serializer is set as0 }9 E7 X; C% _! g( L7 v) ~
** transmitter and one serializer as receiver.
$ s7 ^: b3 z9 T% l4 p" H*/% Z' ?" i: s7 s8 ?% L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- I" _* c# g: {8 M) J7 J" z7 Z# k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 e# J7 D# Z0 N4 |1 I9 m1 }! l** Configure the McASP pins ( p+ j" H* L! C' n. w6 y
** Input - Frame Sync, Clock and Serializer Rx
. y6 a; P) Q" Z+ t, h* s** Output - Serializer Tx is connected to the input of the codec
) V3 E# R! `. s, B. V4 c*/
* A6 B! H) l+ i" V; I- DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 t0 g: k8 D. \8 Q0 X* b3 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 F! f9 L0 U/ J/ eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. F! U* A1 o5 P, B6 i| MCASP_PIN_ACLKX* W# \' ]( Q V! W6 M
| MCASP_PIN_AHCLKX
8 h- a2 e1 W7 D- L" O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( |* `* f+ Y. h8 f+ zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & v% J4 D8 `* l: E/ x0 z
| MCASP_TX_CLKFAIL
* T( z' R: i$ O; I| MCASP_TX_SYNCERROR
: v6 `1 ^7 z% S- J' ] Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* m+ u2 Q3 f( t8 t J7 M( Q| MCASP_RX_CLKFAIL3 z2 U+ e/ a4 n0 u% `: l" b
| MCASP_RX_SYNCERROR
; Q" g" l0 D" q6 h+ E8 l| MCASP_RX_OVERRUN);
% W( T' r0 m- I* P: ~5 M- t} static void I2SDataTxRxActivate(void)
; f" Y; \* n7 g" S. l8 A{, ^- ~# k# n9 ?* G" v& x
/* Start the clocks */9 Q1 q- K3 X4 ?! F" ]- h; P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ o/ p1 M$ h7 V, f# ?$ OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ h4 A2 {1 x# ^3 U8 Z2 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) O- M9 p# X/ j J3 g
EDMA3_TRIG_MODE_EVENT);
5 f# G# }2 }/ d$ b. v. V! fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 |6 S0 O5 O$ {) l* ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 b4 R8 W, J$ D; f. I2 A4 J2 VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 M0 T/ a0 S8 V) A0 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 b( W: @$ u+ }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: i0 z3 f5 b6 w, L1 j& rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' E0 G) o% B. e6 y; W( m+ EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 f- j! e6 e; W: E; e& c} + h4 ~. ?2 T/ B5 ?& M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 g! Q3 z w+ y, m
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