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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# P1 W5 N' M6 [0 {, C7 H8 Yinput mcasp_ahclkx,
; I) D3 u9 X7 t4 J1 {3 Yinput mcasp_aclkx,3 W/ i" Y% J6 ^3 G0 {0 G6 X( W
input axr0,( U$ [2 d2 j" L8 Y4 s: F
* M6 A! w7 v- Q0 P! m. L6 g( g
output mcasp_afsr,2 R- a' W, N K
output mcasp_ahclkr,5 d5 `. }0 ?2 H
output mcasp_aclkr,; X! _- Q# j2 w9 I6 b. x
output axr1,( ?! Q5 m2 P+ ^
assign mcasp_afsr = mcasp_afsx;8 ^; N5 V7 s. B
assign mcasp_aclkr = mcasp_aclkx;& H2 ]) c1 D) }: K# w% X# l
assign mcasp_ahclkr = mcasp_ahclkx;
# w; m, z2 I: B ^; P! j) x) g0 iassign axr1 = axr0;
' E. V5 i! |. h9 L3 j6 @8 a) v
9 o2 N, U! K* Q7 N# D7 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 O; ?+ K3 a9 U7 `static void McASPI2SConfigure(void)
, \. f) c8 H3 H{
- l8 u6 i( S7 h4 H. T8 W1 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- B- i1 y0 |. q. uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 q* D, M8 o- uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; `2 z* Z8 |3 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 [% R# j% B1 X4 L4 J9 {- fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 U, y, L3 ^) nMCASP_RX_MODE_DMA);; F9 E3 K+ W5 w3 m; O \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! N% l+ o, a ^* q9 R! X0 \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% d C- ]+ V0 b: Z& Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , H& W* V- Z& @8 x s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 B- M: Q% o: _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & c1 C- z) S7 C) d- ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* j& j0 G! N$ I2 [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* o1 C& P, o2 l! y. E7 B& pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); \2 Q3 A- D- e7 V u! e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 i6 r8 P7 | ]6 S; {
0x00, 0xFF); /* configure the clock for transmitter */
, }$ y) Z. X Y; F) I4 oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 E# V6 h: h5 t( m# T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / |1 Y$ ?- K* n- p7 l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; H( U! \6 e, e! q z& `! Y
0x00, 0xFF);! `8 d' X4 \5 n( L: u
8 u7 | _4 W3 F
/* Enable synchronization of RX and TX sections */ + _ I) \5 n6 S4 a+ Q# S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: a# B$ z" Z& Q: h3 [# n; j9 NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( v1 N0 C( K6 Q; I, c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** d" W u# [# e6 c3 ]# R
** Set the serializers, Currently only one serializer is set as7 }0 J& i. a' R& m3 A* ]9 I) W
** transmitter and one serializer as receiver.
& f- u: T* w7 |6 V1 v6 Z1 w! C*/
- {9 ?8 A# @% k4 T* GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 K+ p6 p" r2 W1 q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; g# m7 n0 X( x) ^& u
** Configure the McASP pins 6 J5 G' c" [ S2 Q V! S
** Input - Frame Sync, Clock and Serializer Rx6 c- x* E( A' H1 {% J' X
** Output - Serializer Tx is connected to the input of the codec ; d4 k( S0 k! S" f
*/( B2 ]0 Q1 G2 k0 L! q/ b J- E3 z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 U P' S/ m0 H; ?: }" LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 o- H: B! ^2 |. c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 F/ |7 w4 A. j4 p| MCASP_PIN_ACLKX
* b1 U9 J4 M: {( k0 ?| MCASP_PIN_AHCLKX" K3 r- j. C! H+ ?- T6 B+ [! A/ H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# d8 N3 T5 _. @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( ~- Y/ _% R6 u0 l* I# E6 |6 J
| MCASP_TX_CLKFAIL
+ ~7 R6 f" ?: E2 t( f' ?# n| MCASP_TX_SYNCERROR
, k" I: h+ t: A5 J! o0 w2 y/ F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 c+ f/ C* n) f| MCASP_RX_CLKFAIL' |/ t( R( X, i/ T
| MCASP_RX_SYNCERROR 9 e* R( l! _3 F3 f8 S& @. h( h$ d
| MCASP_RX_OVERRUN);
' s/ U( B8 Z5 Q6 ^' [} static void I2SDataTxRxActivate(void)
. h8 @6 Z8 d' j6 u$ _5 J1 U{ Z1 k8 L w, ?6 [3 H
/* Start the clocks */* k1 K: Z+ q! O. A* E3 L. S6 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" t3 }7 h* i- d) c) e, Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" O ]2 P9 h6 ?. P! w( i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 U" U2 U7 O8 g3 {: C/ F. \* V+ MEDMA3_TRIG_MODE_EVENT);0 i m6 F& ?% B# E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" H3 P- L$ m! @* kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 {& x+ f# {: G- x# K8 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" w; _* X3 r! n- K4 {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! |) A) h3 X9 Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; b7 I3 c+ _; t0 vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% G |8 e. Z1 M: A; ~ L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 t: n; |& H& s% f( s" |# E5 `
} 9 H- {+ R1 g, f) z5 ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + \. F* Q p9 y1 ~$ R% ?8 A
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