MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
" J% X" [) e/ z5 O- g' z) Finput mcasp_ahclkx,
# x" r3 s  j5 Zinput mcasp_aclkx,
input axr0,
/ a$ c) A. p1 E( _
) b8 V, N7 G9 \  a1 z& Zoutput mcasp_afsr,
8 ]5 t& [  S2 ?  Y* g' L3 w  koutput mcasp_ahclkr,
/ N/ p+ m6 ~7 Z. G: [output mcasp_aclkr,
output axr1,
, J3 ]/ c5 }- g( Y& k# m2 A8 i

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
- ?, Y7 B$ `8 z  Kassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

8 I& m, ?1 G; @; n. F

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
% z; @' a* L) n{
$ f8 J4 B* @: U+ v% ~/ G' mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; X) T4 H/ {. D8 X, [, \" rMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
2 u% @9 |2 R: `, L! w& b7 c: cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
3 v# j; \+ x. m' e- h$ w8 N) MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
/ v& s: ~7 q1 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ o5 y2 F+ T6 T' @1 QMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 x, L6 ]( ]5 o) p% uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 S# Y) D- N2 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 j% W  Y: E) z2 Y" AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. @4 P  M& h% B# W0x00, 0xFF);

/* configure the clock for transmitter */
# |0 n/ }# B9 w4 w+ V* _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% s9 |- q3 `; w! V0x00, 0xFF);
+ l" ]7 F* |' G$ s" ^2 g
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! E% d" o* j4 I8 fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
( f6 B2 X( p  X/ }+ \; p7 K! J8 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 j" s5 ~! a' O3 d% AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
8 M, c, f: u( l  \9 U0 {** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
- g& M6 W3 I- O* O- f- ]4 Q: y! P7 p*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& a  M9 k6 i+ o* s0 CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
! E7 Y7 |; i0 z8 S9 c| MCASP_PIN_AHCLKX
& {. l: g! U% |% w+ a| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
5 s# u1 @. p- N7 a* M, ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, G& \7 E. a: O| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
9 @9 K$ y2 Z+ {! G) b| MCASP_RX_SYNCERROR
2 m3 \: \/ |* y. ^% F| MCASP_RX_OVERRUN);
, s7 ]9 V: D7 M9 k}

static void I2SDataTxRxActivate(void)
0 n( Z7 L2 Y! h1 _6 Z{
1 r9 Z1 z  [# i; ^9 N  d' U/* Start the clocks */
( n. Z: z' y) n4 [6 q) R, vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 w' n# r2 N2 z6 a$ E( JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
  [/ {$ c& U0 {- G" uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. O' B) t* c% U4 f2 D% e4 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
7 b- }1 E! z* ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 w  R( n  |9 Z  C% f% hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.