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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* I7 C" G" h2 P# n3 o; yinput mcasp_ahclkx,
. d8 V3 ]/ i, j9 m& S0 h1 j( A+ Ginput mcasp_aclkx,2 x% [# |' @: z/ d
input axr0,
+ f( ^8 v& Q1 a% e- u. O% j
( o$ J& t0 k$ _* [' Loutput mcasp_afsr,; z4 d' X0 i! o; @& p& l
output mcasp_ahclkr,
# K- a/ @: P9 u! V# F" }output mcasp_aclkr,
2 [* M- w9 L9 [5 A3 }% xoutput axr1,
* n4 K6 v8 D4 v: H/ l6 o5 g# ~ assign mcasp_afsr = mcasp_afsx;
u! T; n, y, massign mcasp_aclkr = mcasp_aclkx;
" S% J6 `8 [) N" @) V sassign mcasp_ahclkr = mcasp_ahclkx;# a( U: e7 ~8 I0 q
assign axr1 = axr0; % D6 Y3 @; Y* L I% e
8 H/ p1 z- d( W& _ h- F) m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& v/ v8 m) l: i# k+ j jstatic void McASPI2SConfigure(void) `! N8 I) S: q+ A) Q# m3 d9 i
{( x) _5 _* }* t6 c) g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 O. f9 Y* [1 Y0 r8 r# x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' u& @" O& [+ ]. Q! Q3 e8 A$ U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) a E7 _8 A% H" _1 }$ p5 I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 X* d! l/ Q2 H4 y4 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: v( o8 a* m6 c& n6 t. A# w/ w% g
MCASP_RX_MODE_DMA);* V/ m T7 j2 g6 s! g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 X7 n6 T- F3 |3 ^0 g# {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 U2 Y3 P7 j" |. ?) V4 g8 s, P' A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, J8 r9 [" @/ M4 a& b4 i3 R U8 A8 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 Q6 s1 j0 P( G* ^* t- D8 m& n/ j8 w- y6 x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 l5 K7 t1 w- `" Z% e0 m- n; XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 p7 [; @* l* g; v" a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 C) F1 @1 W5 v- LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- {7 |0 F6 m# M0 Y! M) wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, o ~# u V* A6 P. \0x00, 0xFF); /* configure the clock for transmitter */6 h4 v2 G0 W' L9 }9 ]- w+ H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- `5 F# V; D8 [) a# R9 oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) Q, \ P+ J- Z/ @. O% s& U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% [: b0 I, P5 F1 ~5 q. \
0x00, 0xFF);9 t8 g4 \( N0 Z; `: h' ~' t
$ g9 T7 S& Z) ]2 n( `4 Q
/* Enable synchronization of RX and TX sections */ 2 H, A, h0 D& Z6 U7 S- S# r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' }2 z1 y" ^* d) g- i; g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ G- u+ b! A1 o) y5 h1 HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- J8 j1 Y' T8 B' f, }% i
** Set the serializers, Currently only one serializer is set as
7 K! F! h' q# G8 n% j. K** transmitter and one serializer as receiver.: ]6 ?. V2 F9 B/ `1 v
*/9 b7 [8 Q2 r3 e; ` s4 s$ k u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 E# L9 Z- g+ I+ t4 aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ }$ I& w1 K; D4 _$ b( Z** Configure the McASP pins 3 D# _6 n3 Y. t; K( @* V6 @
** Input - Frame Sync, Clock and Serializer Rx5 }3 d$ |( p* b: N! x3 \
** Output - Serializer Tx is connected to the input of the codec + M8 Y9 u' X1 P. m
*/$ G% q! Y# _5 c% r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# G* c& M5 T& F+ H0 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; p$ |6 \5 d+ u# @+ `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 Y2 X! E) x7 }( j9 `$ o9 G| MCASP_PIN_ACLKX) A+ n2 w) B& F% O6 }5 D# p$ r9 N H
| MCASP_PIN_AHCLKX
& z8 c* b+ v& E3 n4 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: r2 o# ]7 ^: E0 B' o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% f( Q$ O4 o% Q| MCASP_TX_CLKFAIL
# }- ~3 B5 N, [. V| MCASP_TX_SYNCERROR
I2 Q. ?4 E0 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. Z* X7 N3 f1 H| MCASP_RX_CLKFAIL
6 ]& s7 F9 ? f) `8 N2 ~1 c7 E/ f| MCASP_RX_SYNCERROR
6 f: W7 b1 i! D$ F7 n: N, X| MCASP_RX_OVERRUN);# G2 N! F: |) U) ^, A
} static void I2SDataTxRxActivate(void)3 f p, X, P- P5 M/ Q- {
{
4 T2 ~# n& U9 o( D/* Start the clocks */
, ^2 `. b( }# zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# O* ~+ @) W8 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: a9 e+ o: R2 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# r) s0 o9 _: `! |EDMA3_TRIG_MODE_EVENT);
) \& ~5 i. k: K" fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 J' T, }4 I% j8 }2 @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ Q5 D( W9 w; d& N$ M/ l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# B8 s. Q: }8 N! h$ PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. e0 C5 G! ?( |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 p n8 {% {9 k# [2 \' e( {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; g o& q( i' q* X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 r5 Q3 D' J8 p# d' }} 4 C1 \$ b' E3 J% i% X3 n: `% h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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