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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," O4 U$ l5 C( L1 r# }
input mcasp_ahclkx,! w5 N$ g* Y% |. D% Y+ d
input mcasp_aclkx,
' z$ b+ K f$ J) s# einput axr0,/ b; {7 [1 [/ m0 b# d# L" |3 K
+ O- F% G1 [8 S' A
output mcasp_afsr,
2 ~ k% p& U9 J. O2 }' Soutput mcasp_ahclkr,- ]! f) F8 F, e* i- X4 X: v1 x( q
output mcasp_aclkr, y) q6 U0 s( H2 i
output axr1,/ u( w# d$ y- d, i
assign mcasp_afsr = mcasp_afsx;! `6 }; B( K3 U7 K# l2 [4 @7 u
assign mcasp_aclkr = mcasp_aclkx;7 i" I) P4 R/ l5 z7 u
assign mcasp_ahclkr = mcasp_ahclkx;: M7 c# `% j# ]( a# K4 Q$ J/ U
assign axr1 = axr0;
0 s/ H" v: z+ P1 m+ b! {+ ?/ @- ?
3 l. r" V+ q- q/ }( Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . R) r5 A* `# e
static void McASPI2SConfigure(void)
% H5 r- t0 X) ^* f: M; v, M# }6 F{
. F$ Q, R7 ?* |( i2 n jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( T5 v( @8 b, ^% s6 L; y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 A1 [ d1 N8 YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
j. P5 W* N, x+ c7 I2 b1 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 d) J+ _: Q4 Q, F+ FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 {+ P1 D' h: R, CMCASP_RX_MODE_DMA);
7 b6 e" w6 g7 l0 o8 _! ?5 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 X+ U( l F8 `4 A; X0 ]$ _% e/ j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# G n8 `5 o" i& ]: v I7 c! |7 }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ V, m4 V Q: G, w* Z7 f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 x" i4 O' F( |8 w0 n, b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: ~* p8 F; v4 M8 P1 w# IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 \ v* ?5 I: I# [) L. WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; N/ V$ ?1 b& Z5 g+ |5 R% i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 f0 L) r+ M5 p- A7 YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 V1 c+ d; h3 R# t/ o7 _3 F& [0x00, 0xFF); /* configure the clock for transmitter */
5 p: k" w B* u) m& `+ T3 u4 iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. {% K# }% |! V# w. K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& T7 h) o% ?' ?7 m `/ qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 g4 S( h% O9 l
0x00, 0xFF);
! F. ]9 V( u0 O& o2 K
- Z4 w5 {6 Y6 Y4 X/* Enable synchronization of RX and TX sections */ : F) i# W: h3 m" j. I8 q, q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 ?, m4 @/ v. r1 [' U& p7 A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ U7 d$ ]& l: @. M" [2 U, ?4 ?( vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; X$ _0 i; r4 R4 J5 ^ o! s- X** Set the serializers, Currently only one serializer is set as! q8 u. J4 j9 w, V! u& K' w# S
** transmitter and one serializer as receiver.
. T2 \) j+ R1 Z8 G5 c% w7 p*/
X! _& F, z7 G! S1 a7 J. p# Y3 \0 z* cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 `8 z1 d, b" c" A7 h; A9 O) g, F9 U6 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) S* d; c' u/ \1 q: N9 [. X% o** Configure the McASP pins
0 Z: |& M( i9 w; g6 n7 _** Input - Frame Sync, Clock and Serializer Rx
: k. S) R0 d4 N- \; ?5 \2 Y** Output - Serializer Tx is connected to the input of the codec : i# J, F3 E3 P7 Q4 R Y6 J
*/$ I4 A0 }5 o6 k5 `. N# ]. r8 @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 j# G4 c; W6 z) t2 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! `9 j3 S) D4 E! j% h7 [/ Y( ?( MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 I: x' f* b, P, K R# e
| MCASP_PIN_ACLKX
5 v( Q- m& U3 y& N1 ]| MCASP_PIN_AHCLKX! e: E7 \2 n2 B0 ^- o! V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 x% }! ~# x' k$ Q8 U S- w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: ]* v1 h, Q4 G' G5 K4 k, p3 |" [| MCASP_TX_CLKFAIL
- y6 B) ^$ q! j8 [; i6 v| MCASP_TX_SYNCERROR
( g( U q" T p! H. Q* A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" s! n% K# ]7 B: A9 J| MCASP_RX_CLKFAIL
) S7 [, q& T, c& v| MCASP_RX_SYNCERROR ( F: `5 q8 E8 M; L8 {7 d/ q% q
| MCASP_RX_OVERRUN);
/ I) N( _) J; @* @& }} static void I2SDataTxRxActivate(void)5 e+ M" B6 Z# j/ f( _
{
& }" c- j- G! @/* Start the clocks */" {6 T5 \9 s* H, o( ?* @0 _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* r$ I; }7 F& nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
p3 F" w$ {) S" t/ f( rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% D) g" I: m* Q! J9 d
EDMA3_TRIG_MODE_EVENT);" z) K. {/ P) o# K( a& Z3 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ ^& n F# N! O) l nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" B, A5 b6 n- n+ qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ K: J% a6 Q8 f3 T# m/ v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 U3 d1 e2 O8 P8 R& t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" r$ e3 P4 E4 }6 C0 O+ E9 @1 V! \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* W5 ?- j* i ]% SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) o( g! P* R0 x& x" v
}
/ X8 u( n/ I' F% v2 ?9 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " A$ m' a; X" w
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