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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 ], S$ y, C; U# ]! |input mcasp_ahclkx,, [0 o, I$ x5 T: v6 h
input mcasp_aclkx,' O- g8 s6 x( M0 m7 W
input axr0,( C& {/ K. D+ r: ]
: e5 b1 y7 x" j; G3 poutput mcasp_afsr,
$ }2 J3 F6 j# D6 L( ^' ~output mcasp_ahclkr,
3 g& Q, N# u5 _3 w7 ~output mcasp_aclkr,
( v* g, F) \' ~output axr1,
6 H4 o( k5 Y( J! |0 V/ P# w' `. t- y assign mcasp_afsr = mcasp_afsx;
# ^4 ` M* \5 m) E8 Xassign mcasp_aclkr = mcasp_aclkx;
9 `" x _* @, G3 Y. w1 W7 _assign mcasp_ahclkr = mcasp_ahclkx;
- K* \2 |, X; F. m/ Y/ k Tassign axr1 = axr0;
! [' j0 b0 @/ `0 R7 ?: H& D0 }4 X( {+ M6 e9 B/ y: q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! A" Z3 z3 c: f4 x7 t4 O
static void McASPI2SConfigure(void)2 e) K( C8 L: R) e" z/ E4 R5 O
{
- [# \" j% X. ?" S; m" n; aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& h! T$ E. a( |, x1 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: ]0 j# ^: D( {; k2 ?9 ^' h2 J( n. ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. ~( f' u# X0 G) U9 X. F BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- s4 D) a* q/ o. W0 W. z5 IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( J- P% T" a0 {! ^7 q/ _
MCASP_RX_MODE_DMA);, N1 `5 F1 x! a8 ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 C- M( P1 j; B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 b1 X) `9 E( C0 a% _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 X9 Z9 l, S( Y/ ~9 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, s v# l8 T" \6 ]. g ]$ D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( e* C, m2 s, q# {& ^" |8 YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* U, ]/ J/ N8 }( g! A$ x# UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# E3 b5 `5 Q5 P/ L$ r/ JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " P" }! v3 |4 @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 @( {0 F! V/ m0 v0 ]0x00, 0xFF); /* configure the clock for transmitter */3 }, c. q, \! s9 u: h* p# \' ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ N7 G2 r- {+ L9 A* x# T% X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ r9 c# v6 t9 d, B- T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ |7 a! o: `) T6 S+ a6 Q0x00, 0xFF);3 u/ v5 @; ^4 q. v) s, H6 T9 d
/ W$ _# J: R, }
/* Enable synchronization of RX and TX sections */
( f+ S) t# y8 i) a% M* [9 G3 PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, c4 V8 W H; Y8 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: a |4 |& D, BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, e$ O' R6 o- |7 A* K5 A$ q& X
** Set the serializers, Currently only one serializer is set as+ ~9 w: D+ B- }6 H
** transmitter and one serializer as receiver.
0 h+ r" G3 n/ h5 F+ p*/9 K( T- b! h, Q) b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 ]( ], L3 H6 t& T: n$ FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( I& R! T; x4 S, X6 i** Configure the McASP pins 0 i9 f o3 j0 L
** Input - Frame Sync, Clock and Serializer Rx. J% [4 _! o* l; { q8 G# u/ u% B6 z
** Output - Serializer Tx is connected to the input of the codec 2 F( p" i! N2 ]' D1 J$ C
*/" H' p" `! Q4 Z4 ^: m2 N$ q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, D% p8 g3 o H3 j. a; U! ^5 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 m: h m: k" I& ~1 J5 _7 p" G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( G5 U# r' p% u% f; p| MCASP_PIN_ACLKX
" S7 J% y3 P* B! E9 J* E# [1 w/ l| MCASP_PIN_AHCLKX
. F D k) V! C: _9 v1 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( t% g! N. b1 N0 t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ p' t3 a3 D; W4 @: n2 I9 y4 g F| MCASP_TX_CLKFAIL
/ {' S* Z1 t. L6 K: |1 I| MCASP_TX_SYNCERROR
/ D$ q( ^- Z/ T. || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 a6 J* S5 J; Z- H8 x5 @7 E| MCASP_RX_CLKFAIL
. j) H! ^, o V6 ^! B| MCASP_RX_SYNCERROR % ^; g0 }0 ?' w5 T$ X
| MCASP_RX_OVERRUN);% p( q; y$ P9 S8 A6 o
} static void I2SDataTxRxActivate(void)
3 E5 P5 F: a) ?& W9 Y: m% S{7 A. p" K! `& ]$ U2 P/ k
/* Start the clocks */
t6 z- ^' K0 n* p6 W/ |; i- Z, M+ dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 D& e/ B6 D5 p7 r9 t- @0 G! @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 b8 L% F+ {2 |) w" h- z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: ~+ \" ^! _, ?8 X, h. h
EDMA3_TRIG_MODE_EVENT);9 p; N# {! ?1 X3 }: l/ L- k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
C) d: L9 m! Y7 j( k. M" u- lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" b0 C% }. y( @/ O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) w& x3 E( F8 ]4 D; sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" `; y$ l- b# i3 Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" E3 t4 O) m; t7 v- }- s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 x7 F. V8 Z7 y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 N' W+ C& L1 f3 ?4 y" a" ?}
% ~* [3 v. E5 O! R- s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * H" I4 W' a6 N3 J& [6 g
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