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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* ^( C+ V6 m! B- M# k9 F4 a
input mcasp_ahclkx,4 d+ k8 v! ]% C" P* t
input mcasp_aclkx,
0 K: h$ h2 Q: o; M. A) {" finput axr0,
: ~6 D! x+ O8 O, K+ ]$ |8 o' W+ R& p$ r) q8 m: @, T
output mcasp_afsr,
- _& Z" |7 Q8 N$ R8 coutput mcasp_ahclkr,
) Z! |, k4 g, Doutput mcasp_aclkr,
- L% i1 `) |8 _- w) p1 C; H. Doutput axr1,: o5 Y, C% E0 `5 x$ }0 C( }
assign mcasp_afsr = mcasp_afsx;
( _5 b: [* T, S1 i3 T% l) iassign mcasp_aclkr = mcasp_aclkx;
' N3 {- X) `6 t# P/ ^5 K/ uassign mcasp_ahclkr = mcasp_ahclkx;
8 N' ^( U O/ ^0 t Qassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 i* p3 e8 N, ?' X) b0 T; }9 w
static void McASPI2SConfigure(void)
3 N5 F; z' C+ u4 C" S7 B ^{
. C3 X5 p7 U; f1 A% eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 X! l: m1 q0 C# B4 h% G) W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 Q( Y! g- B# sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. F: R% z: Q& L" q* qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 v& g3 i$ H ^0 [" Y, N; hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 L: w* ], @, V7 S0 a$ `
MCASP_RX_MODE_DMA);
) Z2 e8 L5 I5 P0 S9 j, OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 E: p, W- s/ {8 n9 u, @4 G, pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 I \* J2 ~! ^( rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 d) E7 H! Q; [+ v% ]$ Y) J) R6 W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* a) o1 S' S# m. J O; kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 u- D4 p; v/ V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( S( G7 X# ?7 y$ o* x, {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 K3 L1 ]5 {0 e7 p: |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # d# q H$ u" p" W- u1 B1 A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: l. Q6 f+ i' c% O2 f7 r* P
0x00, 0xFF); /* configure the clock for transmitter */) ^# F/ ]8 E% ~9 X, \2 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( L: Z* y0 z* R9 J3 TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 ~; u9 j% s6 R& s; W Z( p2 ~6 g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 L# ]; f* P! X- q
0x00, 0xFF);5 Q7 e" N' n7 l: }" n
( X' r" Y3 u9 B( Z2 b! } |/* Enable synchronization of RX and TX sections */ ( M! b& ~; J( T5 u+ }- t# h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( J: F& e' n, q; E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 y5 f6 J1 B, ~7 q8 Q" G7 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 y, `$ @, {8 i8 }) t** Set the serializers, Currently only one serializer is set as9 H$ r% H% p a* O
** transmitter and one serializer as receiver./ g" b+ U) }' [- F# U# ^8 w
*/
9 Y& e3 {; o) l! i( _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' m; v+ L9 q. xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. q2 D3 b7 x2 y5 t9 A
** Configure the McASP pins $ ?# C, h$ u+ Y3 U0 J
** Input - Frame Sync, Clock and Serializer Rx
! x- p# K' _& G3 J/ H9 z3 \# X% g** Output - Serializer Tx is connected to the input of the codec
/ D! k% V6 F, N7 Y*/
& L5 k& @7 ~5 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( C2 ?5 c& l2 T& MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) L' b; g) q. {1 K; W1 tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, c; L: z+ Q( J, m! L
| MCASP_PIN_ACLKX
6 ]; N# O4 L3 A8 y; b9 L5 D, r| MCASP_PIN_AHCLKX
# \9 E' [# e E+ Z3 Z/ ? R2 ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 o6 Y, V' T3 ?1 g& `" t& T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: z, u- E" u* [/ L% k% w| MCASP_TX_CLKFAIL * |+ k* O9 k j
| MCASP_TX_SYNCERROR, A) t& z3 `0 O2 y8 H8 C _: C0 l( U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) Y! U' t0 ?6 \ Q| MCASP_RX_CLKFAIL
4 e) m; q) B4 ^7 Q| MCASP_RX_SYNCERROR
: a. M' F s; _! T) a| MCASP_RX_OVERRUN);
' B" T4 p1 D; O' h} static void I2SDataTxRxActivate(void)
& ?. {& |4 C9 d- Z, h3 z9 J' p- p! D7 r{3 P3 P& l, L. H& B
/* Start the clocks */
; p- S3 W+ Y- s$ H" b; t! k1 n5 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. _" a/ x: a2 Q' eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# n9 ]6 o7 {5 \2 @% o" s! W% Q& E6 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& z/ Y' c; B# w. x4 H4 @8 Q2 L0 v! HEDMA3_TRIG_MODE_EVENT);8 Y( R' ?* Y8 e ?& j! ~5 o& U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, N6 m4 x5 u9 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ q; G. P; i& G% Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) ?! i; R7 ~# N# w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; ?7 {+ Q$ J- r/ kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! O, U0 {" q% u* N: _0 R8 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 \* c5 Y2 p8 `7 D+ X+ [1 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 A8 F8 k2 _ S/ W
} 1 `5 E" T" z* \/ |. I1 a4 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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