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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 j2 A7 X/ q6 D# E& r! m% x9 {/ T
input mcasp_ahclkx,7 b1 T4 b$ K" j! @4 `& r
input mcasp_aclkx,
& D( }/ _3 ]: o6 k& j) [input axr0,
" R4 K: r* A3 M
: S6 s4 e( x7 S* w3 Goutput mcasp_afsr,, w$ ]$ e; T( ]# _
output mcasp_ahclkr,
( a K$ j! m& Z! ~4 g% Foutput mcasp_aclkr,
9 }+ ?8 \( i1 [6 j& O; toutput axr1,% B: W: J: }0 }
assign mcasp_afsr = mcasp_afsx;
) `0 M( q9 @1 O. S @assign mcasp_aclkr = mcasp_aclkx;# E" k" G% } Y) b, O( N+ q* w8 g
assign mcasp_ahclkr = mcasp_ahclkx;- k& J! {+ v& l4 ^( M) O( g
assign axr1 = axr0; $ f6 s" g/ _: D5 X7 [" D
% j' S( y# X: J$ K: b. }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 G( T) B: g2 L$ V% I
static void McASPI2SConfigure(void): ?. a" i( W5 m; @4 [2 W# O" Q
{/ A+ r, w, p( @/ y( R* ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 y5 S1 k: r; ]: GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 _) J! w' M) ^, X. K7 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( G' x# J& @* L) B) B8 M& N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, M$ B6 r- {& h2 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 M9 f8 j0 K/ Q0 ~: q; V5 X, }
MCASP_RX_MODE_DMA);$ N0 G, t3 @' p2 p+ k# a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 E: d; d+ G- J# c0 H F. T* }7 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& I# z7 ?5 Y% v' d- }% k+ N* iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 r% _( h7 S# o, \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! m4 R- \5 k' s! ~; U. v4 ~9 YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
j8 } W* X" ?6 P. |3 cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! f! D5 {0 |4 p3 w8 BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ x E/ P: R' H1 o' `# t% l' e* Z' A& d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & s4 ~- o4 J# y5 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 G W& Q2 \2 I9 _0x00, 0xFF); /* configure the clock for transmitter */
2 s) i0 x3 H9 n$ j' tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ o% a9 K4 u. ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ u. l9 J; T k: }. h0 d7 \. ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 O% |! D; k& S( V0 B* F3 S" x
0x00, 0xFF);8 ?; L! g, [. H2 b1 ~2 V
4 {7 I# }- A4 f: @5 ^. i0 b/ O
/* Enable synchronization of RX and TX sections */
7 c+ R! z( p" r3 l6 KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* j2 R0 h9 {1 ~- c `! i dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# R: t, {' \+ U" N5 L5 z$ F/ ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 N/ s3 |# K4 t3 t; A
** Set the serializers, Currently only one serializer is set as
- W6 q0 w+ C: B. B2 n% T% h: c** transmitter and one serializer as receiver.
; @; r, P6 V' y* e; M*/
& X- }/ y& S0 y4 M% H% sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 s( o+ h( d- z! _8 w# Q3 i9 v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- M5 h- ^; \, t% J* Y8 U6 X( ?& E** Configure the McASP pins
/ m6 {7 q6 z; k' J, F. O: p, F** Input - Frame Sync, Clock and Serializer Rx& ~9 q7 M8 T$ w3 q& K7 z5 `% T
** Output - Serializer Tx is connected to the input of the codec . l, q* u! O) o% O
*/1 B# z6 l6 c; i! e( C% L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ E" _6 Z) X- B9 i/ m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 B9 E4 {7 p9 y; a6 |; T& _" K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# e/ p8 V" m7 Q| MCASP_PIN_ACLKX
7 E. u! X3 J5 f6 p| MCASP_PIN_AHCLKX( g* U% d: O- T( H& \) n) J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 z' l# C- g# V/ O$ ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ x0 J8 `4 F6 D+ a, |1 x: S| MCASP_TX_CLKFAIL
+ l' _7 x2 Y7 ]0 T| MCASP_TX_SYNCERROR
, ?8 [) `8 Q2 a1 I( u$ n5 M N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 t: ]( ?: ?9 h/ @- s6 m
| MCASP_RX_CLKFAIL
% X/ ~6 q5 X: Z+ x, G( T| MCASP_RX_SYNCERROR
$ p3 i8 F1 s2 [9 A8 g1 A- Q| MCASP_RX_OVERRUN);
1 y n) ~0 r8 }+ M3 [} static void I2SDataTxRxActivate(void)
& t9 n9 q: _$ Q; e{, j ?) `9 E( m) L/ l; O- p, Y
/* Start the clocks */
% H$ t6 A( p. D' K% J0 s, bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& t; J, v4 _* Z- z. P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) W3 q) C; E9 \) x0 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 g" \' w' e5 K4 w( V H
EDMA3_TRIG_MODE_EVENT);
, k: P8 a; N) ~" jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 P% c1 t6 s5 W( n; f6 I! QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( x" @' \( `& d5 @) t' NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# b( ^5 h8 N* }+ ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 G. @9 s2 s5 v! iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 B! Q8 O2 |$ h6 N# g1 b7 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 V3 u; b3 b" E( M9 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& \7 B# D) ], A* ~7 a" ? A
}
- I- G9 v, z- |) q/ v6 E: Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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