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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 T) Q9 I' ]. Z9 b5 d! B3 t. z: v
input mcasp_ahclkx,3 x5 v9 L$ n& k
input mcasp_aclkx,
0 r% a) O; }3 I1 Q: tinput axr0,
- ]7 V, k5 ^3 u- x# Q5 ?% x; g5 B5 [4 x, v9 ` B0 F3 \
output mcasp_afsr,
3 V. I9 l& O! h8 Routput mcasp_ahclkr,# L: s' }: `$ _ V6 J( c3 A
output mcasp_aclkr,
3 U6 Z8 C) R6 j5 b4 @5 toutput axr1,, [/ c" H5 P3 K: h) n& B
assign mcasp_afsr = mcasp_afsx;1 f6 W ^+ A& q8 K' d* Y
assign mcasp_aclkr = mcasp_aclkx;
0 G* `- W& A. @7 C1 l' X" ?assign mcasp_ahclkr = mcasp_ahclkx;! ^9 M) ?) p3 W2 M; @: B& s0 H
assign axr1 = axr0;
' D3 a" y) z" w8 w" j' y$ X8 [+ g v* ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , \4 _% |0 n+ j: {
static void McASPI2SConfigure(void)3 R+ C( K0 [7 w [5 A
{; c2 G/ r$ k! d' N [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 P2 ]! @/ o. u4 ?' E* o( W% pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ @# ]; Z1 i: @; Q6 L' d. Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# K, z8 _: J, w' FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 E. j* O6 u" ~$ y; ~, l" MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 A5 D3 M' o: v' eMCASP_RX_MODE_DMA);- I- r* j$ K, I& b8 L' F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) Q! f/ I) d6 ^2 s5 SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
e% Y7 @/ b6 X SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) ] p0 a: I, B: G% ?9 w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# u$ w5 A7 K" K% _/ A [: c* YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, [. d4 K7 S z% d& t0 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* x. Y& P X! e+ M, r8 u/ LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* e K3 @1 F ?7 Q; a' @6 h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . z0 s" j. ]* C/ w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 t8 _3 ]' ?$ B1 c3 X8 L/ u8 t
0x00, 0xFF); /* configure the clock for transmitter */# Q- ?- o" G$ I) h' R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 D- l! b8 g0 ^# I+ W+ ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ y# Q" b- C- _! \" V; V8 \8 d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( O& {2 P+ V5 N' J, X5 q
0x00, 0xFF);2 m+ T6 F/ J+ W6 x/ {* f
$ ^) {2 |1 _ t0 a/* Enable synchronization of RX and TX sections */ / L: ]2 B5 O3 [" C% Q J9 i5 n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 E4 |4 p% w" u. mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
o1 S0 W- h! I6 P1 E8 A& y; [4 P& \- zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! y; w- O9 }9 k7 R% b** Set the serializers, Currently only one serializer is set as1 M0 e2 q; F$ p2 n3 Z
** transmitter and one serializer as receiver.* P3 g7 w' a L U* L
*/4 J+ U. j+ u- O$ S; X# }# b. M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% t! N: P) d3 ?+ X; d; K7 QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 u/ Z8 P; }7 g# G }$ r& P( g0 E** Configure the McASP pins 0 X8 N0 `3 M0 j- z
** Input - Frame Sync, Clock and Serializer Rx# V* Y- U% t3 |; @- j
** Output - Serializer Tx is connected to the input of the codec
o# }9 l$ ~# c1 y( r*/+ P1 ^7 |5 c; I" C, }; q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# B" T7 O' R9 Q: l. d2 s2 dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# j7 @" h; S; K; V6 I% EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 i, T; p. B& [; }. W7 i. T
| MCASP_PIN_ACLKX
- h: q6 l7 Z" O5 T| MCASP_PIN_AHCLKX
% i* S7 N$ B- U* j$ W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' q8 G2 B9 j$ r/ x. vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! O% ~+ q# g' Q, Y
| MCASP_TX_CLKFAIL
" b4 \ ] E3 t9 R; L| MCASP_TX_SYNCERROR
% e* b: B: G* t3 G& R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& T C2 ~5 {& w) R! q# r| MCASP_RX_CLKFAIL
7 P2 ?! b/ A/ H# g7 g( m| MCASP_RX_SYNCERROR % R. ~; G% `0 X2 t
| MCASP_RX_OVERRUN);
4 t" c C* z; k* f) Q} static void I2SDataTxRxActivate(void): L. U$ _$ A2 O' Z
{
. I9 |0 O6 a7 Z" K6 O' `. V/* Start the clocks */
1 b( `" n( e" |) jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- w% M9 d0 Y8 ^& Z- x8 b+ PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: p7 f9 Z* s# a; Y0 M- i5 Y3 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* }7 J$ t9 W7 J# {EDMA3_TRIG_MODE_EVENT);
$ }, B$ D6 f; uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( v( g6 n; f7 ^# R; o S" v) y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 T5 U) R% q, DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 D6 g2 r7 W) a/ f0 H! a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, p& t9 `% g3 R6 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" b1 g: P3 s7 v: u; R0 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 `* |5 L4 C+ D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" i; b4 A. \4 w
}
: l8 P- U$ R7 [( `- l7 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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