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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, q& \ c( Q* K7 E: ^8 |9 |# h# U5 G
input mcasp_ahclkx,
3 T1 ? D8 U5 ?) c6 m( K) finput mcasp_aclkx,
0 c8 N9 ]; m! C* h! Z/ a# _input axr0,
+ g T4 j, l \) c {+ m3 W; U, Z
8 X+ `/ t& N7 l: A! l# s( toutput mcasp_afsr,5 ]: }4 Y/ g7 x6 l1 A# a( a* C; |
output mcasp_ahclkr,
$ d5 w8 c( F) {1 ^ ~/ voutput mcasp_aclkr,' `: O J% ~+ p* q
output axr1,
9 E" D( {! g# }3 q: o assign mcasp_afsr = mcasp_afsx;4 V( M& x5 t0 [: E5 m5 O( f# }
assign mcasp_aclkr = mcasp_aclkx;
4 S5 ?8 P5 j. `/ a `assign mcasp_ahclkr = mcasp_ahclkx;
; h+ I6 g" |2 m( xassign axr1 = axr0;
2 C3 j1 R, b- c4 p% a9 j5 Q
! t) e9 M; F8 P5 |% d/ [ H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 v, _* h- z: w; \9 M
static void McASPI2SConfigure(void)1 o; h q, W$ Z% I0 \
{
5 B) q/ w" n3 dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: n6 N/ I) j1 W- j; N1 k0 `! UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 u; C# }$ U/ W% [7 m, o) E! _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 |7 `2 Y* O$ H( a5 |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 S) O( Q2 a UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 U: t4 i0 @' B: X7 G2 `9 E* c7 AMCASP_RX_MODE_DMA);8 p( C% v4 [$ \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: T/ A, i; y# Q' J( W* @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& k7 \. A' j; G6 C9 R3 m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. o3 K6 c. I5 q. P! H# [( lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 j0 \7 W( h* ~8 F% I. c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * Q, O; Y1 [$ w: m, o$ h4 v# ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 |) ] @% i7 C5 C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 X) b6 R& K1 F/ r9 YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- R9 S5 [: Y+ t8 l9 {3 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) K9 s2 V3 d/ v
0x00, 0xFF); /* configure the clock for transmitter *// @4 N; L( B$ j$ V, y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# I* q$ \* O# x* ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 ^% A+ g' ?, F! ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; c% E$ ]% X. D( t: d8 d& t
0x00, 0xFF);1 C1 y! @ `0 {5 v, ~
/ {: G& `: r! P& J" V: n/* Enable synchronization of RX and TX sections */
3 V8 b- z4 c6 P7 kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, g; u7 Z% n) x8 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ o6 N& C: d/ t4 Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% P* u; N# Q9 _( B5 O: u! v2 u
** Set the serializers, Currently only one serializer is set as# [' ?4 ~1 [- Z( y. ]9 P
** transmitter and one serializer as receiver.
/ U- k6 r* J9 _4 H1 F w$ D# ~*/6 P! A. g5 M) z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# h7 v+ K' ]7 d' D8 q' Y6 Q2 Z! r7 D% `9 S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 e8 Q. L: O( w' S** Configure the McASP pins / s7 e5 D1 p4 |! v- k. V# w+ `
** Input - Frame Sync, Clock and Serializer Rx
9 E+ i' A6 Q6 i B, \; I** Output - Serializer Tx is connected to the input of the codec ; E" O7 a9 i9 x: y
*/
' ]! }& M, {: n% \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); T q/ {4 }0 I0 Q% D7 T( V( r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 q7 `; N5 s2 E/ U9 b9 n: [2 e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ n9 t4 ~2 \+ \) |9 g
| MCASP_PIN_ACLKX
% H* T* b. o4 R* k2 S9 O| MCASP_PIN_AHCLKX$ r. G. F# p6 l" T2 W8 I; {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& P1 p% c9 Z/ R( J% w. kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # \0 V9 i! m& }
| MCASP_TX_CLKFAIL
- w. a/ D/ d S' F- ?- l* ^| MCASP_TX_SYNCERROR; f$ d# V; h9 s( o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 m" O% X2 @( n) g! \
| MCASP_RX_CLKFAIL9 A7 v7 G: A4 C# ^+ b
| MCASP_RX_SYNCERROR
" L/ m- l7 o+ S$ s| MCASP_RX_OVERRUN);0 P, z. t W1 J8 k5 X% l ]1 ?
} static void I2SDataTxRxActivate(void)
: c! J& c; _( k{
( Q4 S/ ^: a$ H/* Start the clocks */+ V E1 D) s4 \1 K5 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- P6 k0 X0 o) e- Z; @* Z1 s: ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- h* k! g' R9 ?7 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 ?- ~ L+ n/ n7 _# c4 BEDMA3_TRIG_MODE_EVENT);7 Z2 y3 R! O, e; h+ Y; x6 W; {6 o4 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ u/ D1 g5 U. L. R! ?2 P' O3 KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( q. m$ B( y* n, H* kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 `% g- i& [; T- v3 H4 ]- U; DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// u- f" K1 X+ y9 n# |9 P, y& i6 J' z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! W, n* b5 E8 F- [$ p# K6 u: }3 K% ^0 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, q: q" ^3 N) R# rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 q' P8 E5 w: ^9 S9 m& B0 }}
: p/ Y6 i6 V8 h2 A: i( H6 g0 c3 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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