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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 b; Y7 o0 k( u$ b
input mcasp_ahclkx,5 u$ v' E, R3 Q8 S' |" @# ?
input mcasp_aclkx,( c/ a" J8 M. @" W- p- A- V0 n
input axr0,( T- s8 [0 t( C' V5 K- `
2 ~& r2 X L8 p" m% n
output mcasp_afsr,
* |: y( ]' ~- C6 x! n5 L3 }output mcasp_ahclkr,
" p" w( a% E4 o- M3 }output mcasp_aclkr,
6 ~( q: c0 o; g5 o/ H9 w8 M# Aoutput axr1,6 Y a$ h1 j% p$ W% J# D2 t
assign mcasp_afsr = mcasp_afsx;
. [( }( z. t$ G8 c: Fassign mcasp_aclkr = mcasp_aclkx;7 P; R9 i3 q8 Y+ u8 R6 [3 }
assign mcasp_ahclkr = mcasp_ahclkx; O9 [9 J* p& ~ X( m* f5 A! n
assign axr1 = axr0;
4 f8 {% B' O1 n) f, z- H0 m7 v1 F5 p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 I" Z$ u6 I: c* u4 {; L' C3 Ustatic void McASPI2SConfigure(void)
* s0 u/ ]4 P. c7 P9 Y{
3 q1 _9 x0 I! zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: w. Z( s6 f1 `2 [2 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 L4 H% n5 x! d" rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 u4 Y _. k. U! `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' j S/ g; |: m% ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ?. X' _! K+ ~MCASP_RX_MODE_DMA);0 P) n9 M+ O' i, \+ k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ a* Q- o9 a8 m+ x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# D# T: P6 @& G# k/ j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 b4 L1 G3 {4 |- O8 v" s' W8 u, H4 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 w2 V6 L, u* _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 f, b) {" n/ M0 M0 [5 n4 Q: fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& n- e9 l# d8 D4 D5 m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 g( _( d, w* Z% R; }- Z& ~+ m' L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* ~, q, J; N/ y2 g' \- cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ ^2 i/ [/ v. `* \
0x00, 0xFF); /* configure the clock for transmitter */
. r' w0 f Q: Z$ U: v2 k2 lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" Y" f! G# u6 n5 N- BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! S) o6 ~# `9 [! ]6 p" i' r+ UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ |% f! F1 C/ X0x00, 0xFF);
7 z# ?/ l! N& H. u4 t* G4 G: z' ~8 K
6 o6 j0 Y/ t1 x9 z$ K/* Enable synchronization of RX and TX sections */
* W% ~% h/ P! a# k( y1 H# gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// J3 T. ^- D6 ^) g+ i/ \; D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 S n2 ^/ i* B |7 G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ \4 f/ ~; V- V+ d# o** Set the serializers, Currently only one serializer is set as
3 _( N) p, M: I9 h/ m; ^) Q5 W7 I** transmitter and one serializer as receiver.
! Q$ G4 d' r' p! S. b) \*/. m# N1 w$ a# V6 z( ?# J& L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 }/ \8 J K! y& y4 Q, t& j6 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ R# Z& U6 e5 H3 H) B9 T
** Configure the McASP pins - m* a$ E" _& D B
** Input - Frame Sync, Clock and Serializer Rx
+ v, z: l6 g" t0 |: U** Output - Serializer Tx is connected to the input of the codec 8 P6 M1 R( I- M! F @: j
*/
. l, ?; {1 x' V3 ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ x/ Z) X- w4 O" JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 V, U" [8 w H' Y( D! @' @2 \' u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& E7 Q0 \3 K; d) U1 {+ s| MCASP_PIN_ACLKX
8 }$ S0 e) F' U5 h/ ^% Y4 M& K- S| MCASP_PIN_AHCLKX) R3 p p. w) G8 M' Z1 V9 N, L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% K8 p' w6 q2 j/ E) x, U$ bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! y8 j& b- r# J( V3 W0 C) b+ i
| MCASP_TX_CLKFAIL 2 I" ?8 Y' A9 z7 R
| MCASP_TX_SYNCERROR/ E. {$ f# `) Z4 x1 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 K: {' g+ G3 n4 {- E, \. j; n: }- H
| MCASP_RX_CLKFAIL
4 N# _3 \# d" \4 Q/ a| MCASP_RX_SYNCERROR
8 G( V4 R6 S3 o% e* P| MCASP_RX_OVERRUN);
$ @* C1 S3 `6 b/ x5 {} static void I2SDataTxRxActivate(void)
$ B7 Q. K- G1 r3 y% C/ [4 r" r% U{6 W5 J+ b. l% o' y0 k4 B
/* Start the clocks */
* O$ K9 N1 e) uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 n) X& i B; w4 P5 W8 E# ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) v1 y/ q# g5 C! K, W9 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) ]7 I5 E5 p' fEDMA3_TRIG_MODE_EVENT);
+ ^; ~! M, [3 |, J5 X/ G# q2 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , j, C5 ]7 o* j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 x) A. G0 ?( |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( U1 l$ ]8 b4 I6 v fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ x5 i4 ]" L2 vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( F3 |0 D0 n, I6 w7 B# ]& BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 S0 P/ b' c6 }9 X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& T/ ^: ^3 V. {! \
}
+ }( k6 i, j- w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * L' C+ C; o: X3 m- [
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