MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
' \2 J) ^0 Q  [8 j4 M/ w$ E7 l1 r9 Ainput mcasp_ahclkx,
input mcasp_aclkx,
8 N) ^! m9 w( Sinput axr0,
* W. h, {# V4 i( G
% o9 e2 b6 j# W% U7 ^* Youtput mcasp_afsr,
' J1 ^& @; v& i, S* A! _5 moutput mcasp_ahclkr,
output mcasp_aclkr,
" N8 E/ Z0 V: A% i' Woutput axr1,
4 o' R9 }5 X, f( ~- ^

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
6 e6 T; j& `4 A9 _+ n  bassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

1 {. ]8 w& C5 a  V: P+ g( z

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

$ N2 g7 X/ ]( m- V- D5 y* \- i2 g4 [' O

static void McASPI2SConfigure(void)
+ m, c: ~3 k& r* s1 _, e. V: X{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 ^5 f8 q$ R! `9 Q: u: HMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
9 h  k* K) d5 F- mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% C7 ]# d% b- V; g9 _MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- g1 j4 }# |4 V! q$ G0 Z* N; ], \" {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ \- Y; _' z. X" jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 |5 a! L$ }1 v: nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( k' e* d  I: [4 LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
  U; K0 x# u# A1 H% G5 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: ^9 g9 J7 t2 Y! X+ p: }0x00, 0xFF);

/* configure the clock for transmitter */
' Q* O; k! j; J5 \/ Z6 D; pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 ]/ P7 Z- u4 h8 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 Q3 M. g2 ^6 u5 A# `6 _9 n* ^  Y' s0x00, 0xFF);
9 d) S2 g1 N( o0 M1 c. G
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ m( L; [5 p1 v, }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
; k7 T# q" ]9 U& Z& B$ h1 e) Y** transmitter and one serializer as receiver.
/ g2 m% d0 L4 I, a*/
2 w# k- H' s+ }% V8 V/ c% UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 z) ?, {) x9 q. q% p! ~, bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
7 k% H5 O4 u2 L0 X! ^** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
! A) F' a6 C* d$ O7 x) y** Output - Serializer Tx is connected to the input of the codec
5 b+ l5 P: N; \( e; S3 v3 h4 u% {" G*/
$ {& v# g/ s* Z2 R& D/ ?7 a/ [( U" k3 ?( KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* s0 k' ?+ h4 u3 q, ~0 L% FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' E2 p: m3 q6 R$ J1 y% d| MCASP_PIN_ACLKX
, D/ P  l, h" R- `| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* ^1 E. I/ X  k# B! z, s| MCASP_TX_CLKFAIL
" x' i+ n- o0 T| MCASP_TX_SYNCERROR
" v9 p2 ~2 N6 O| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
- f2 m# {1 c% S0 a/ B{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
0 g, p: i& a- Z4 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
* D8 H" }; C8 x/ G6 h8 N. T) g: lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 F! I. a  O1 @3 V# \) _+ VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

( D% ~7 |5 o# p  y+ `2 d2 Y

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

8 a# p/ \, F; s# d! P