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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 Y0 D' U/ v0 `, H. ^
input mcasp_ahclkx,1 _0 j }7 Q5 }2 O3 y. \3 g
input mcasp_aclkx,8 o `* ?: m, \& R6 g9 {* `: w
input axr0,. i! T6 q2 T# ]& P- ]% r
$ ]8 p: [ O- woutput mcasp_afsr,
1 @; X* q2 k1 g- P: eoutput mcasp_ahclkr,
' `; x) F9 N: ~- f; o- houtput mcasp_aclkr,
3 U# B% A4 h6 b; Youtput axr1,: J, Z5 I/ a: e
assign mcasp_afsr = mcasp_afsx;# W) X% T5 m& x: m
assign mcasp_aclkr = mcasp_aclkx;2 l: ~* N- i7 \9 e6 I+ K
assign mcasp_ahclkr = mcasp_ahclkx;
& ?/ E* @0 ]; B' s' T wassign axr1 = axr0; ! x/ c( b+ o) R* n7 p, H' t
" f- F8 F Y k3 j; g. m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ I/ }/ c0 H; o# pstatic void McASPI2SConfigure(void)
$ ^1 M1 {0 P8 V/ n3 a{8 T- e% q9 o0 g- Z9 z. I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 ^9 Q1 o+ i U, q7 LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; Q- L, | P# m4 d+ h$ P" k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( f6 h( F5 |7 N7 ~; t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, E- p V4 `! `+ b0 H+ {+ L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 g3 W. M- V7 S6 T6 rMCASP_RX_MODE_DMA);0 V5 n' X$ O7 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' a2 a% T, ^9 h3 Z3 P% M" rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 q3 h2 P$ D) c. Q: ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
a! d5 Y* n( W( n& S. \' u% s0 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% Q9 Z" I4 W1 V( x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " d. Y" W" g D" b0 U9 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 o/ s U) ~: @7 F R; {* E- XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 |. z+ N+ ^* c& \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 J0 e; C3 }7 m$ FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 z( Z) b/ O+ Y$ C+ p1 O+ @, Q0x00, 0xFF); /* configure the clock for transmitter */
* r& ]1 u9 E$ A6 E$ {. OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; D& ~1 P/ ^% c3 h- B4 j# q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! Z% U" m$ N! o, B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ z0 f j6 P+ _2 l6 N; l0x00, 0xFF);
' l: A3 U% q0 S8 z; l% d1 P0 I* \' m- F* |6 P
/* Enable synchronization of RX and TX sections */ : \, D9 A, j( c8 ?' }1 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' E6 k& C1 y! Q$ B4 a* j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% r/ L v2 M; D6 P( E$ t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 B7 c: T& h( q2 i/ Y6 C
** Set the serializers, Currently only one serializer is set as/ X, J, L9 |' x6 e4 g; O
** transmitter and one serializer as receiver.8 r* ~, f7 N8 f8 G. j' T, f% I) j* j& Y
*/2 j9 R! V' s2 Q5 o' V2 \+ T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); L' ~2 t6 {& y9 }. ~; Q$ o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 W# h$ K' V8 r' w5 C
** Configure the McASP pins ( I6 A+ b H' k$ {& t
** Input - Frame Sync, Clock and Serializer Rx
! ^) A( u M7 }5 n1 f4 W** Output - Serializer Tx is connected to the input of the codec % q: ^# x9 b9 S7 k+ M" }. Q
*/7 m: I7 _7 z2 e- B4 w1 {' {. Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 y# A& I7 m; K" R+ {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) x# i% v" r$ o- Q$ w4 tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 `+ h9 ]0 n) Z/ l6 I
| MCASP_PIN_ACLKX
4 c8 d# k0 E* K7 w8 f" A" d$ v| MCASP_PIN_AHCLKX9 A/ l, R4 x& @0 q! m3 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ n( c) K2 V1 [1 [% {9 ^: m$ yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" s! Y2 H* k4 x* D8 ]| MCASP_TX_CLKFAIL ) ?7 R3 b: m3 \7 D6 q
| MCASP_TX_SYNCERROR3 n7 ] l$ t7 Z1 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 I! O3 h! J2 f4 R& @4 Z| MCASP_RX_CLKFAIL
4 X. j( R' c& o| MCASP_RX_SYNCERROR , D" R. k: w2 W' H
| MCASP_RX_OVERRUN);2 b" P7 V' d; E/ C) S" F5 ~; D
} static void I2SDataTxRxActivate(void)
) ~% G* [/ j D$ d{6 U: y/ U0 u6 C5 ~. K- G" \
/* Start the clocks */6 M( U. f& u# f+ ~% e0 W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) X i) f. f; M' N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. b) O, A# {, A2 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 m) k. ?+ Q8 z8 ~: [9 i) |' P) w
EDMA3_TRIG_MODE_EVENT);
9 J$ v. n& r% yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" ?, v5 ~ |; H A& {" a+ X- u' VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' H- n r. \7 x. N4 o, D I7 b1 s9 PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, Q: ?/ A+ S2 Y% c& {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 s/ P% T: V/ |7 {& k# J6 b9 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ z `6 z% C! O! ^% y9 ~: H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ P% U( j& l' v2 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* f- }8 C$ ^9 n7 j5 F7 k4 s
} 6 r5 f7 q0 I3 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / K! N- G' t! q, F/ r
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