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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ N) }, G6 w; d% V4 l; d" `! cinput mcasp_ahclkx,+ f9 z2 s+ u/ U
input mcasp_aclkx,1 b# ~7 f( l7 }! g/ D7 x
input axr0,
3 d! j8 z( I5 O R7 x% O" _. E6 _; r. N# }1 Q/ Z3 u5 R
output mcasp_afsr,2 g/ F+ s$ _! G% c* T
output mcasp_ahclkr,
2 u- Y7 n$ B! G. Y) coutput mcasp_aclkr,
3 ^* H3 O1 L) @; m$ woutput axr1,
& ^! z1 y) e4 k: B assign mcasp_afsr = mcasp_afsx;
7 K- l3 B* W/ U/ C9 E4 n# w( Fassign mcasp_aclkr = mcasp_aclkx;2 H0 Q, U2 h( h8 j, t. I4 G
assign mcasp_ahclkr = mcasp_ahclkx;) a C' i( m& K2 ]
assign axr1 = axr0;
3 @' Z2 ?0 C- o( X8 L
" t% @% J9 e) h n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . H1 _7 B2 h* d% E# {
static void McASPI2SConfigure(void)
' L- ?3 V- y g6 J4 [3 P{
7 ]5 g9 t! p `+ T5 ~0 CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 `% c& M3 a+ T, s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// N3 x- M& V1 g) b' k* e: P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- w' w8 p$ C4 i9 v% h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( l/ i1 F2 z2 |( v3 X! I! M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 O: P4 L5 r% L; n* h# p8 JMCASP_RX_MODE_DMA);
! M; Z E* k b9 D. SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 f8 ?9 E k/ g; X( p) b* wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 N9 E% a# q, g c3 z% [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % {5 `3 g- J! s( T) C8 Z9 Z, O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" H8 P1 N+ R, s: q2 T; s8 d X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 }0 t" r+ Q1 N$ r% [* C/ qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ P* \9 W/ x- h( [# vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ O( r; P, ^0 \8 v5 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % J# ~. u- [9 t) P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," m( A. s. g! B$ L2 `2 F
0x00, 0xFF); /* configure the clock for transmitter */: V9 E9 q4 W( j4 t3 r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 X& W4 h6 n" `0 y0 W8 b3 t+ y8 i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . J1 F7 ^9 C3 M6 K( b3 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) e2 D1 |; w0 f0x00, 0xFF);- {+ K5 \, O; _3 Y/ O C
W) A) [% u3 ^2 V/* Enable synchronization of RX and TX sections */ 2 e' v2 A/ _: I8 }7 j4 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 D0 f9 h2 \" r+ W, n" J& q9 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' X5 h/ L5 y* x* @; T% `3 G9 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ ^ Q* b% @+ v. U, C. Q& j i3 ]** Set the serializers, Currently only one serializer is set as1 n% q3 t9 g# p: F S
** transmitter and one serializer as receiver.
I5 W7 K- [* E6 v* O! I5 ~*/
* B0 I' d! y( NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 | c5 W6 L) d+ G4 Y- _. w2 ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 ^0 B6 x' k& ?: u1 f** Configure the McASP pins 8 [- L X; k. {6 i1 t: {, _. ~
** Input - Frame Sync, Clock and Serializer Rx S' z- N8 K; k5 k! w" n; v; x
** Output - Serializer Tx is connected to the input of the codec 9 L5 M3 p& y2 ?) J- d
*/
( o' h3 f# B5 a4 D( R: ]3 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, F$ J6 Q9 C- p0 G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ W* q( P+ `4 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 k2 n4 v# b' X* Q% h7 X* H| MCASP_PIN_ACLKX6 }; \4 u# ]% l
| MCASP_PIN_AHCLKX8 F/ ?' N. E( Y0 E" L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& d# J6 N1 V; C" O3 U3 ^/ Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 I2 z1 b) d }$ j' F
| MCASP_TX_CLKFAIL z1 t9 Q$ \7 s Y, q
| MCASP_TX_SYNCERROR/ T. q7 m/ g C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) G' S' W8 b+ r* M4 D; Q
| MCASP_RX_CLKFAIL
+ S6 k" E; W4 G" j$ ]* J) P! p| MCASP_RX_SYNCERROR
. U$ K3 m! |6 m( S| MCASP_RX_OVERRUN);
S% x3 D2 j; u _( K3 B: y} static void I2SDataTxRxActivate(void). m9 C0 z/ K: |9 a5 r* [5 n
{
1 ]7 V- }1 d9 u/* Start the clocks */2 G9 H L" \- m: B4 ]$ M/ e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# E7 P. H, D9 q. t h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" \! D3 ~2 @, p. Q( q2 V3 L) YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- m5 K$ T9 [4 q" Y$ JEDMA3_TRIG_MODE_EVENT);
3 o. _4 J# R4 {- `' F$ |; pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 f6 E6 D$ s! M A8 U JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; Y) _2 n1 H3 j) Q# A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" U$ s+ t) w# b# s4 A& d8 X! Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 a. B% |* @9 A, k$ |8 h5 e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ z8 {" d) f* {+ n) q c3 U; l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; J* g% f0 q2 ?! gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 ]& D. X6 b! r( m3 e7 q
} : G% v! \( s, v/ F- N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , P# o! l! L1 F! R% C% w9 y8 l' F
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