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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 n1 ]5 l4 z% t# r. b/ [- v8 G1 m# dinput mcasp_ahclkx,# b' a0 b& b* T" i8 c
input mcasp_aclkx,
7 J2 p" C' W A1 C4 O& s' qinput axr0,
1 w4 b7 R7 S1 v; \
$ B' f# e6 _& Z9 R0 _5 v9 woutput mcasp_afsr,& c4 ^3 N6 p- X+ V3 F, o
output mcasp_ahclkr,
+ Z, i9 m4 f# y! c6 ?output mcasp_aclkr,( D0 v v, ]" \: J( l, O+ l! k1 q
output axr1,6 x* g/ l) m! J
assign mcasp_afsr = mcasp_afsx;
" X* ]; F3 |0 K) W) r E* M qassign mcasp_aclkr = mcasp_aclkx;
3 c/ i C7 [' }6 p0 {assign mcasp_ahclkr = mcasp_ahclkx;, x& D- l0 |9 D& n( l- w- I" K
assign axr1 = axr0;
1 K( |$ V7 U7 H. m/ U/ p$ F! D5 E! f7 f5 s7 H& V7 w4 A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) U; v+ c* Q' h! z) q2 E, D: t: v
static void McASPI2SConfigure(void)
3 i5 m7 C1 K4 ]& o3 A{8 v2 `; `5 f* J# r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 b& b' Z5 `# n6 U7 [$ i; XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 X2 z/ h) Q" x: O( P5 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# [ s' `4 X- O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) z5 x& [2 F- |. l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& d0 R6 b7 h. c# a2 S, J
MCASP_RX_MODE_DMA);
0 v! X/ a8 A3 wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ X' a6 |1 R3 _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 J& z! c5 a. nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
y# n+ [. v: h5 ^, p! BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 x4 \/ j6 ^! @0 V" A# v' \ AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 O4 f; p5 Y; U' A( ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 p4 P4 x9 j0 c' X4 ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 k6 V1 i5 p, `4 B. ]3 H, L$ q% K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& j `+ e+ n; S9 \0 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 t1 J/ W) g& U* k) P# [/ M1 R
0x00, 0xFF); /* configure the clock for transmitter */
8 n! g* Y8 v N5 |) j; mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: P6 G! G4 Z# r5 V& [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 J6 t- V0 W: s6 Y# n f* ~" _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, l* [# m6 K8 t' d
0x00, 0xFF);+ z4 K, H K: f5 N% @
2 x0 j6 N( U- A# }4 L/* Enable synchronization of RX and TX sections */ & `) q6 B' O! A1 {" l( M/ B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. _6 [7 f& C2 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% `. `; Y! R" S1 M! e2 g- J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 U6 q. k, ]8 {& j' x7 q: |** Set the serializers, Currently only one serializer is set as
$ y' T& [+ z8 W6 G. s2 E** transmitter and one serializer as receiver.
% S* `8 B ]# q) \( A% o; [! u*/
g; w4 ], T! R! [$ {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 {+ D0 w: q i G& o6 v8 Y" W6 o, @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; F9 y. ~+ C0 K( T0 T** Configure the McASP pins
9 d6 r, E Z/ E% o. o** Input - Frame Sync, Clock and Serializer Rx. [+ G, Q8 f( Q1 j8 n: o
** Output - Serializer Tx is connected to the input of the codec
" ~- b; t; ?( V8 f' C) s, }*/
( _( z6 N! t1 WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# M, D3 {5 @/ d4 y* e" X+ KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- j/ A p! c; u3 ~% C7 D8 B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
v% g+ n' O' Y- X# || MCASP_PIN_ACLKX0 f6 d: J2 s7 V+ k* k4 W8 _5 S6 O
| MCASP_PIN_AHCLKX
) G, W5 f- c5 l4 Z4 R' c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 ~. C( m1 D; C* ^9 i5 Y$ H5 UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 L- D3 H/ z2 O| MCASP_TX_CLKFAIL
0 e8 G6 b! b6 X% ]7 G| MCASP_TX_SYNCERROR0 K3 v3 w1 I4 X6 D% N: K1 {6 R- S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 I, F% }$ t* j- o4 ?6 b- x( p$ ^# C
| MCASP_RX_CLKFAIL8 M! ?2 F+ a+ Y* O1 X" w
| MCASP_RX_SYNCERROR
1 X5 B& m" q+ L( r1 r. a| MCASP_RX_OVERRUN);
8 ]9 ^ O" ~" w4 B/ H} static void I2SDataTxRxActivate(void); y% N1 f& S$ B! X; r5 K
{. D' n6 V7 Y6 f8 O0 A+ C }1 A! L+ X6 Y
/* Start the clocks */
1 _0 Y, h$ T1 _1 ?- L4 OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 r8 t' A+ a' L) D* o* SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ Y$ t- u. Q5 `* s% s8 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 Q1 o+ }6 b& z
EDMA3_TRIG_MODE_EVENT);
/ O0 k! [9 E' vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 ?# G! t) e" f: ~4 |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) J. G. [7 Z7 Z" c5 u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 L7 P+ K3 X% v- J5 t9 u6 D- U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* H! a5 ]" D' Q, @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 P! ^3 n0 r" S: BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( U& b; ~: m, y, D+ I: [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: w! M+ c; b/ r. T z, T; U) Q6 L
} ! b6 U: N# m/ x% C$ b" J! x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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