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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
}3 P( L( l# \, ]. d0 ?input mcasp_ahclkx,
, }( W' Y/ f& |3 V, j: g& o* {- xinput mcasp_aclkx,7 C3 r; v% c4 k
input axr0,: d* E9 ^( ^- z$ `/ E$ x! Y
, J \! N* O& Q, {9 Soutput mcasp_afsr,
. f8 i- X% K$ C6 Zoutput mcasp_ahclkr,
2 [% V8 D9 |' f# Poutput mcasp_aclkr,0 a. I( U m* H& q u1 X
output axr1,
5 L( @2 B. L. p- Y T; z assign mcasp_afsr = mcasp_afsx;8 t8 F8 d- M. e; U0 K
assign mcasp_aclkr = mcasp_aclkx;" g9 n$ O: C* B; J# d* d0 [
assign mcasp_ahclkr = mcasp_ahclkx;
; d% L( I* a: ?+ b1 ?7 H" N: w# p; |assign axr1 = axr0; ! C, {, L9 K0 g
( x; J, @, j% E' V! ^ ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 y) M* `, m8 \! b+ }$ r+ Y% d
static void McASPI2SConfigure(void)
5 F# {+ Y+ Y8 h{/ |. f" ~! ^$ ^8 s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* z! J% t K0 H; y2 S, n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 f5 n! O/ o' q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. D; r4 Z" k8 L* b# _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! Y' z: |. u4 H+ `7 D& W' t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 C! Y- y9 z# D9 M
MCASP_RX_MODE_DMA);- C; ~; Z: B. V: m) A9 V" R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ V: G+ I6 i! Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- i( k, `' O' o4 ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ ?) s- y; h( \9 q+ R5 P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 c2 |0 T' u, k# _/ d- [1 F" {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * y- J) X5 E& C% m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ `) y: ]3 O$ V8 l& m% x# PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* B |2 C; G/ h# MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; f7 I) @" l: mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 M' C8 [' ~ S5 G+ m% i0x00, 0xFF); /* configure the clock for transmitter */% D' {0 G$ q* I! C' y' ?- H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ S3 d+ T' ]" C |* \' D$ F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, J% _9 `- k) F) n8 kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 j% z4 |( Q3 a$ O6 y0x00, 0xFF);
# [, T% ?, A8 [3 c8 x2 G: J% N7 d0 R: g5 @
/* Enable synchronization of RX and TX sections */ 6 o3 g- K, ~$ s) Q* M; O; L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 o# f; k. a& T+ _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ l: y. c* W2 d- U. u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- g2 W# L7 h3 B K, f8 L. \0 i1 L
** Set the serializers, Currently only one serializer is set as, P- @3 V2 V* P, H/ P$ w
** transmitter and one serializer as receiver.$ i2 b- {+ v- M2 Y4 C M8 x; m
*/9 x& V! v0 T! Q+ d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) {2 W- p/ i- z( H$ z3 b) GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 R" @* q/ D/ C* ]/ f** Configure the McASP pins - x# p) R I5 v, \8 L. T1 \
** Input - Frame Sync, Clock and Serializer Rx
4 o- `: x- r8 P** Output - Serializer Tx is connected to the input of the codec
& C3 Y" B3 u- F9 [* R6 V3 Y*/
4 h: W' y- ^ {4 W* fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 T3 ?7 L5 ]/ M! P; d# gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! j0 Z4 N; i" [* ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ t+ r3 _( j, @ x, Q7 ]
| MCASP_PIN_ACLKX
7 s; u' T; }0 O, f. m| MCASP_PIN_AHCLKX
$ F% J$ x, j4 r) h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// g, ?; y' A# P @$ s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 m: V" W% s7 {1 g1 e( C| MCASP_TX_CLKFAIL
, F: t8 A7 e! F$ d( B$ K| MCASP_TX_SYNCERROR
6 e; {7 q* C# C- X) p5 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - l4 o/ x! d# W& e% f% N
| MCASP_RX_CLKFAIL, U6 H- E# {8 p8 ~( i
| MCASP_RX_SYNCERROR % `: K% E! w# G" r8 l, C
| MCASP_RX_OVERRUN);
$ j, R# s0 @" x} static void I2SDataTxRxActivate(void)
. z6 k( s0 _' j{
6 F& H% n! h, u! N9 h/* Start the clocks */
+ c3 m- J5 [! qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 Y, _3 F Y& h+ y3 k8 F& J" w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. w! @6 H/ @8 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 P" `. w; L" u2 n( j5 d8 T) DEDMA3_TRIG_MODE_EVENT);
% N6 \5 |; e# ~0 U8 U6 [' T+ @8 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) z+ E [/ K% N$ d/ e& A# ?5 WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% o( c( F4 M/ cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: p/ C" F- O. @, Y- V9 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) h4 W' e. u. r* f9 H; _ @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 y) P1 [- K( S) K) u* d# k% e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 X+ n& ~( |! E7 [5 I( d+ |" h7 CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ a4 {% Y6 w h, B
}
% `7 Q& }- l& @ a- _# C" k' n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 Q2 p G4 p. C. ?5 H* l( T
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