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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 m4 e& i( [0 X# `, i8 g; z) u: Finput mcasp_ahclkx,! B5 S; r/ O' e* O7 B
input mcasp_aclkx,% _! D: b7 O/ e0 t$ X/ ^# Q
input axr0,
+ G$ u3 w- S, x6 r
" v7 b! m, o- youtput mcasp_afsr,3 A* X. O- ~8 S4 w
output mcasp_ahclkr,8 p% x/ x6 h+ ]' x. h$ b0 @6 R8 M/ ]
output mcasp_aclkr,* M/ v2 B1 _% Z% t2 Q, U) ?3 W
output axr1,# ^1 |0 V, z4 N
assign mcasp_afsr = mcasp_afsx;
2 W \( D C _+ u+ tassign mcasp_aclkr = mcasp_aclkx;
& O/ r5 B6 G4 I. @3 X, `0 J4 |6 {assign mcasp_ahclkr = mcasp_ahclkx;6 R1 {' }5 o; ?' d2 o
assign axr1 = axr0;
8 K" b5 h! Z& ~/ X# d7 N2 Z) x) P3 M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 _# }7 |) ?% W4 [+ f
static void McASPI2SConfigure(void)
, Z+ W3 H# @& ]8 j9 e% M7 @{
+ ~0 L2 l8 G& ^$ jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! o2 F* r$ s+ ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* z1 L. h2 A" F9 b3 Q4 M' n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ u9 n( a; O. p! b" i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( e; m+ L+ B+ {0 |9 l KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 [1 z: }6 b5 m5 S8 z5 k' {MCASP_RX_MODE_DMA);* d) d4 B6 C5 ], L9 S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. y& {* W/ ?/ F/ Q/ UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" _ h6 ~4 z3 B% TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 D$ u& Z# u/ w6 q9 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 R: F' L/ N! p5 S" b0 y- `. t9 p7 MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , X7 z0 d- w" C; e. g% X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* J- y/ L# M% a2 N1 i5 k, u. y9 jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 `, X# x! U" C+ W% l5 t# e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# [+ z/ N$ \ B( _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 q' b. R# Q* z3 u/ d* a, u( V
0x00, 0xFF); /* configure the clock for transmitter */* y3 d; B, o% `: K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 ?/ k9 m! s1 u3 ~# {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) b$ R! @6 [& _4 r2 c8 p0 R! N5 N7 I- k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' O" ?% w5 M/ s* y: D$ F& H2 H0x00, 0xFF);0 }" t- e( b. r/ R8 J4 n
' ~( }+ ^) C0 @: a/ x, a- d/* Enable synchronization of RX and TX sections */
7 o6 `) ^& \. B) Y; o4 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 E# ~$ f: P/ ?0 f$ X9 j3 H9 xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- l2 G E% S" p) _ d; A" p+ tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& _/ P m+ _; g/ q. E# n- |
** Set the serializers, Currently only one serializer is set as# W: A4 n7 k7 c2 s
** transmitter and one serializer as receiver.
) W, t6 u) ~* q: m" {: q; N8 `*/: x J1 R% q7 i" K$ O* B4 R8 P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ u: Z' A. I( Z3 t& x& XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; [3 h2 B7 e! A& D1 F8 A" _
** Configure the McASP pins ( n8 }+ U6 |3 t
** Input - Frame Sync, Clock and Serializer Rx
- Z r% e5 z6 X( a0 Y$ r' o; V** Output - Serializer Tx is connected to the input of the codec & W+ A, ^% H7 ^( x; T1 [
*/
' X# d/ b' W+ [3 V! d) D jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( @% w6 D9 k4 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- m8 u) ?4 Y9 S: SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& z; ]5 X* ?5 E& F6 k& i| MCASP_PIN_ACLKX3 b$ B& l1 D( d
| MCASP_PIN_AHCLKX
9 V- O3 N+ A5 }0 x6 q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" [3 g5 a3 z- z8 F; U0 t# f4 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: P4 B% B% J- f I; w3 n| MCASP_TX_CLKFAIL
6 s; L0 a/ f: m0 Y6 W$ }| MCASP_TX_SYNCERROR
' M6 y9 Y) b0 h: q2 V+ ~% D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 u! p9 ?: @$ Y I9 t, [| MCASP_RX_CLKFAIL3 a8 a- w* o6 ]8 \% w9 z. P) z9 N
| MCASP_RX_SYNCERROR
+ g* ? i( \3 @7 B! c| MCASP_RX_OVERRUN);
7 ~* d, A+ _( X} static void I2SDataTxRxActivate(void)" [" H$ O: L7 c! s7 F! Q" L9 ?
{
. ]3 M3 E5 r8 t/* Start the clocks */
( d# W7 M3 M3 B p: D$ dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& n" ~9 }' u5 b/ O: B4 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! h# i7 [6 z) D* m5 I& b# [9 L. r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ b0 v0 z8 Z3 M) S& n1 xEDMA3_TRIG_MODE_EVENT);
$ E4 v* R5 n5 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - q; U/ Y5 e, o' `* J6 |" {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// L" U/ r: t2 p/ s# w, C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' t/ M+ K" u/ W1 v' D! p, P% r8 A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' A( W8 L+ x4 A4 {0 _* a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. `4 X6 _7 S* K4 @+ `! \: O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 A/ q7 }8 k$ V: ?' @& L8 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 r- }& A5 @' [2 \( a
}
* \- E& Y; e% `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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