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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 b! _% Q% k! ^
input mcasp_ahclkx, u$ U3 n% |" Y& Y
input mcasp_aclkx,
' `5 x4 F4 f) g0 o1 Z. Yinput axr0,) t8 T7 A; X/ {+ o/ m- U9 E
, R4 b2 o# L$ m+ e/ X0 ioutput mcasp_afsr,0 p% g9 u" U( U+ r0 `* |; [5 f3 k
output mcasp_ahclkr,* k* C" J& n w: E. J
output mcasp_aclkr,6 s6 x1 [. U8 p8 K- I
output axr1,0 a8 N; R+ Q* w6 v* f( @7 Q
assign mcasp_afsr = mcasp_afsx;
9 I- A/ W( S# Massign mcasp_aclkr = mcasp_aclkx;
& \: c0 F* D# E" bassign mcasp_ahclkr = mcasp_ahclkx;
7 Z7 \6 p9 r9 m) V Yassign axr1 = axr0; 8 S& p8 K5 g4 y. v
/ R! \& k. q9 _5 r& ^9 J* @) {2 C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 [9 k. w) {( _
static void McASPI2SConfigure(void)
- w4 \) z- Z6 ~+ w/ b7 x- u{+ Q$ h+ v# ~6 N C3 Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% a" _) S+ O8 s4 [* ? S* p4 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. v8 U1 G' Y9 e' |3 m: o# l4 }- vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: f, E+ M8 ^- U- ^! XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 G) ]& U. s$ n3 T& p0 w0 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 l0 e% N/ m& A* |/ K0 Q1 g. LMCASP_RX_MODE_DMA);8 e4 P( g6 C% f: P& h' b1 r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% j. Z5 U) W3 _. m$ w5 EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& ~3 K) u9 F; X7 h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ f+ v# r% c1 U+ n7 w/ r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- o" w- q2 x& k( ]" C" F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 ~/ N3 h* J' oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' M: m2 Q. @, v$ G( UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ U- E# U* L, X' r5 }5 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , w( |; i- s0 n+ {. r7 @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; n( R5 P F! \1 L0x00, 0xFF); /* configure the clock for transmitter */
$ {* I9 p! ?# D6 `1 _; @6 a, \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 D* S* p4 r) c: q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& ]7 S- {& |4 D p) r; qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% Y/ ~7 H6 |4 t8 j6 W0x00, 0xFF);1 }3 \. X) s0 n1 R" {4 b; Z
, U4 E+ t. Z) }# Q
/* Enable synchronization of RX and TX sections */ ' h4 B4 V4 I1 @ j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; B# Z8 O8 b& E- l; C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! M C7 ] B& vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; d7 M' n0 [% [& w8 i** Set the serializers, Currently only one serializer is set as
- a" n; x8 n4 J3 d& D: \3 ?** transmitter and one serializer as receiver.2 Y5 X `( Z* _! J" i- d9 A/ y
*/
, y" ?. f7 r9 p$ q3 h0 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" Q) g" @' |3 i: r- M( u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 K8 C" @8 U( }8 z8 U# W
** Configure the McASP pins
2 y% S/ t* V( B+ e** Input - Frame Sync, Clock and Serializer Rx E9 [5 t, W) Q/ ?3 s
** Output - Serializer Tx is connected to the input of the codec
% T: q$ t( E& r. E*/2 W# i9 L4 y7 f+ y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& E% g( y' X) R1 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 i. S) c1 _% gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ g0 S# I( V8 w! F& Q* D
| MCASP_PIN_ACLKX
1 m; x# y q9 V+ t: d1 v- m0 ^% n| MCASP_PIN_AHCLKX9 e1 {- \0 n/ U o$ _) o5 d! l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 J9 F) I1 n$ i; \' R. nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 u/ B0 N4 W3 \0 i| MCASP_TX_CLKFAIL
, s1 R# |# _" |6 x7 T| MCASP_TX_SYNCERROR
( v7 S, B, w3 e: F, ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR `: R% W* Z G% w
| MCASP_RX_CLKFAIL1 L3 Y" G, L+ k. K$ r7 E
| MCASP_RX_SYNCERROR & P. R8 J. ~, I0 P* y A
| MCASP_RX_OVERRUN);0 c, z/ a/ F4 {3 L; }! P& w
} static void I2SDataTxRxActivate(void)7 J- B6 j( k" a: Z1 l7 e7 C
{1 o1 Y/ Y+ }: s$ C
/* Start the clocks */
( P. l; B, a8 Q% {' f: X5 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); i5 p$ e- \0 ^7 P+ @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 D0 r- @ \9 X. w) f9 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% g- T9 n, H6 g2 z$ N" J Z' [
EDMA3_TRIG_MODE_EVENT);& w# G7 M6 H6 \* y2 V `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
w3 C+ t& q) a( U6 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 O) {4 ]: }' a1 E0 A! _# HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: A+ z9 {7 J( VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% P [/ h8 X6 H# j9 K% c6 s" Y. ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& A1 U$ K( M. M: S+ g( @9 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 G0 i5 ^" @& v7 V3 t" m0 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& {3 e/ P% b( I( K5 t5 }5 b
}
0 }3 C4 s+ g1 h9 M' U$ p! E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & j2 L/ o3 }1 m% x% t8 H
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