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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 { N- e( d3 ^8 s$ X. P: H* a8 D. m# N
input mcasp_ahclkx,$ }. H% i! P3 p$ Z6 x' m! e* `/ J( Q+ E
input mcasp_aclkx,% _0 w4 ]6 {0 l0 z4 i
input axr0,) q; k( ~# Z" }- u/ {# |5 S, ^ F; j
( h% r5 Q! V, R& X3 n3 Doutput mcasp_afsr,
, ?( e! j. }4 y% H" U$ qoutput mcasp_ahclkr,: Z; b" e5 G( h+ ]0 t5 Q
output mcasp_aclkr,
. t; X4 w# a7 e Youtput axr1,
7 k8 S1 e+ g x& q$ ^3 \* v assign mcasp_afsr = mcasp_afsx;) H8 }- y* ?3 Q" M. G
assign mcasp_aclkr = mcasp_aclkx;
7 R& A, Q! i9 C$ z% r t, S5 zassign mcasp_ahclkr = mcasp_ahclkx;
; j' L1 s& u; s8 Y& J$ zassign axr1 = axr0; 5 b* b7 g6 {2 q/ N; I
* X+ K7 Z1 J0 {) M' E- T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
}/ A8 r0 t" @0 e' `; c" X lstatic void McASPI2SConfigure(void)
& I9 ]. ^4 B! M{/ H: }8 y2 s) Y$ z3 N0 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 }% r8 P5 R# ^; D# _) g0 q1 H+ e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ J+ @5 u# k5 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& `7 T$ q7 p/ m9 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 C! I8 H6 y1 h0 q0 uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* h" D3 R0 l: W9 ~0 O2 o5 oMCASP_RX_MODE_DMA);' |7 h( I5 m. X8 U9 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! l# h g+ V. i& a9 c& ?4 P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' m7 L! p" S+ h G; oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& m2 v+ P3 k# J8 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' ~, M# t8 I& D+ Z4 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# D, c! D5 W% ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, U3 Q5 t9 D( D% @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% T# ]- O6 I3 J- c6 a) p2 v3 c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : U6 u( `1 c/ N6 z7 s4 K) P, Y/ A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( P" N1 T6 H' _# L0x00, 0xFF); /* configure the clock for transmitter */
" S: N8 J6 ^4 X5 m1 S& eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: ^' |. E# N7 Q7 X4 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 P! P, e' g2 G, y7 M' j6 |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. D9 w, ?& r5 G4 |0x00, 0xFF);1 V& Z' d: w N1 A ?1 u
) w: X$ O/ g: r. h( b4 @
/* Enable synchronization of RX and TX sections */ 8 i+ z" m. n" p/ [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 k8 Z/ ^7 ?* l0 ^) C2 `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ l f! H) q/ S" j% _) P# D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 O# w! Y M' H** Set the serializers, Currently only one serializer is set as
$ A: o0 a2 P% P** transmitter and one serializer as receiver.
* T' A" r* C, d! E" b*/
* B2 ?; x! ~2 v ~( C' qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. `) T7 s0 q" q- s' L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' k' I$ h$ g" M6 M: x9 s** Configure the McASP pins
4 _1 @ _) f$ B9 m** Input - Frame Sync, Clock and Serializer Rx
6 Z2 M6 H. q4 c w** Output - Serializer Tx is connected to the input of the codec % ^0 N2 `9 t, F- J" V; p: E8 x
*/2 Q. A8 \9 Y* k0 n* q7 B( P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" E& z1 ~# x$ s- {# x: g7 N% X" D YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: R0 q8 W* J: ~. G$ |' PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! k- w W" Y1 H2 }| MCASP_PIN_ACLKX
: M; h/ U& ~+ u2 o7 p4 _) f| MCASP_PIN_AHCLKX
; P; D, {" D6 T& A1 C9 w& G* s: m. i$ N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% h D& U8 i3 D: [" S& cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! b" H. ^2 g2 i3 b& I| MCASP_TX_CLKFAIL
' ~8 _" B% ]: c. t" _| MCASP_TX_SYNCERROR( h! c# `5 a& @) }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 ]8 h: v W7 K& v| MCASP_RX_CLKFAIL
+ H$ n* `6 H. F| MCASP_RX_SYNCERROR . I4 C' _4 H) G4 ]5 N
| MCASP_RX_OVERRUN);
z5 _. q9 p& ?- D: X0 R& T' e} static void I2SDataTxRxActivate(void)4 m( `% u* Z$ J" j$ i5 \; }
{
9 Q! t) M& Y' ?/ R2 H2 i5 ~" E5 @* O" s/* Start the clocks */
; k% f# d- R2 @# QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 W0 E+ f; K$ G! N9 q4 H! \. D% x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 _( b5 B& `6 A' @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' ]% Z8 c+ `7 nEDMA3_TRIG_MODE_EVENT);; v7 J* K0 F9 A% C- Q' t7 ~$ t$ v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 g" m% X" X9 \8 l5 a8 iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* m( T7 O: J$ K) Y q' i2 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# g1 t0 k9 `' M6 f+ }- ? I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; \& H% o. h5 T3 A! k- ] U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% ^: }/ q1 m) X% o) q+ o" @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: ?2 T/ s- y- S8 K2 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ V' q& w+ k7 ]: }4 a
} * `2 `# o: s) r2 Y) r6 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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