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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" [- p) _: }7 H0 b/ k1 [# O: finput mcasp_ahclkx,3 }' i- k7 F, a* s( v4 F" ]$ R
input mcasp_aclkx,
5 F- D+ z k2 |; rinput axr0,; n& V6 ?9 d8 b8 Y @) Y
6 Q; p9 }# V) l# B) Z* K, ^output mcasp_afsr,3 K1 }7 Z! H) f( H/ c0 C2 s, p
output mcasp_ahclkr,
/ K& A1 t8 a/ K$ f$ D& S. moutput mcasp_aclkr,) m5 j; o2 E. X. G! g% B& h# X
output axr1,8 ]5 A( C% ~( y
assign mcasp_afsr = mcasp_afsx;0 }' G6 _5 ? Y M! [
assign mcasp_aclkr = mcasp_aclkx;
2 }9 }- |; j- c1 \0 gassign mcasp_ahclkr = mcasp_ahclkx;
5 l" ~7 b- T* t: m4 X' I$ q% [assign axr1 = axr0; 0 a' {1 L) t7 J9 |2 ^
' w7 A6 R, ^' `) D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 V0 d' {" _& G6 [+ nstatic void McASPI2SConfigure(void)
4 j% c7 b8 f$ j2 h. s' i/ T- } S$ i2 A{
0 w; n _1 s- c/ {6 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, O1 ?% b7 o- s) n8 u2 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# T" L, e! V: v7 P0 Z/ w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! x' t6 X! g# W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, w) @0 L& v# t( ]( a1 z. q- v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 {7 Q+ I+ G# }& h! WMCASP_RX_MODE_DMA);% o% R) Z8 i$ g2 y& y; i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
e& |7 i& u5 @7 ]( }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) Y; }+ M; Q0 `3 L8 ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, K% @& U( u+ f0 X4 }: [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& c" T, h6 G7 u- p) qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 V4 i" z9 q# @4 H; V! w; N0 i2 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% `; w- V2 T9 F2 i0 |* V# g. T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& K1 y9 h/ A, Y; TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , r1 N3 A; `8 \7 z8 b2 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 K$ P H4 H8 r, }* P
0x00, 0xFF); /* configure the clock for transmitter */
) o( z# S9 |5 Q1 aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* ^% g$ @% C; ?9 M% ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # V9 K* s" s, }/ ?& p+ K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! O! M1 S* ]7 N$ g0 E& Z: G0 M
0x00, 0xFF);0 }. s4 l% ~( w8 B
w- l' C+ c' B7 A: P/* Enable synchronization of RX and TX sections */
% R$ p8 ?& K4 h* fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 e: V4 U& f% B( f+ wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# w) x: Y; x \/ }! e; N" f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 a0 A; `+ t' c' ]+ d, i4 ? ?
** Set the serializers, Currently only one serializer is set as7 ]- {+ y. `: h" x5 x/ E p' J v4 s
** transmitter and one serializer as receiver.
: i$ B& w" e7 z |! F*/
2 m8 \" j4 G9 n0 v) sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" s3 G6 V% h/ g* v5 i+ k/ ?+ H- O. G9 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. U4 N- [$ A% ?# D
** Configure the McASP pins
; D3 u8 p3 q! Q; ~1 L) [** Input - Frame Sync, Clock and Serializer Rx
% Z/ |2 W- l, e" k, Z** Output - Serializer Tx is connected to the input of the codec C$ g7 K" Y# P* ^. z
*/
/ R" p2 `4 ^2 r8 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 y1 w" S+ e: {. n) m1 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. K9 ^) s& P2 B: q- |# P8 fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ h$ U% I ~* \" u. ^| MCASP_PIN_ACLKX
1 d# `5 g! ?' C| MCASP_PIN_AHCLKX+ j$ W% x$ z' m! K6 I Q3 v$ T" `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( e9 S0 K& N* a) w3 C6 R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 N% `& _% Q, s
| MCASP_TX_CLKFAIL ' t- p! r6 ^' T7 e' y/ t" ]1 W
| MCASP_TX_SYNCERROR& L. m; ]7 o4 D- }- }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 k0 o5 u: N" N7 Q1 c2 y| MCASP_RX_CLKFAIL% L2 m0 G, O0 f: d: u5 y: M
| MCASP_RX_SYNCERROR
# o: z! b. _) _. |1 o+ j0 R$ C| MCASP_RX_OVERRUN);2 l+ E$ h4 {3 W V9 h3 y& w( J
} static void I2SDataTxRxActivate(void)
( C1 i) ^( C3 }5 @{0 [) |0 x( x |3 V1 [& A
/* Start the clocks *// X$ a3 M2 i! F5 ~4 d! [5 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. a/ H) }) i# IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 @. e( A f: `! P2 P1 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 ` V" P0 k" v9 F% _+ Z4 s
EDMA3_TRIG_MODE_EVENT);
7 @ l0 r$ {" Y, OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% `* k- [- ?, M1 w* K+ BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 i. |6 C6 g% l6 Y! sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 o% F6 o+ T) O9 S8 y; U; W/ J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# @$ M' G' j6 d- mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ j2 l( v' k7 x7 A, f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; v7 |# W# R( y3 s- i6 L. kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 |( A, X! f5 j- j% y
} : ~7 l* {/ R4 \8 {5 a& k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - T4 f7 T' n' Q4 z$ n* D
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