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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 [, E) A# r4 W
input mcasp_ahclkx,4 X/ R0 e+ S9 s$ V) ?/ O
input mcasp_aclkx,
7 j6 U5 E" ?0 @! z6 winput axr0,5 B9 [' t5 ?! J. ?% E
3 P$ p0 Q$ m0 _7 ]8 Poutput mcasp_afsr,
; G7 U: u. w1 ]( F! K, h, Youtput mcasp_ahclkr,( r2 ~2 r3 Y* B+ X, V2 D3 g
output mcasp_aclkr,
3 h# Y$ ]( ^; F) h. F4 L% r3 qoutput axr1,
+ W/ m+ `/ S9 L% w: }$ E6 Z$ j assign mcasp_afsr = mcasp_afsx;
9 z/ ?5 E! W# S! }6 Sassign mcasp_aclkr = mcasp_aclkx;0 R- S$ Q% R9 o) e8 m# k9 R* b
assign mcasp_ahclkr = mcasp_ahclkx;: `( ?6 A/ n) ^2 U6 }
assign axr1 = axr0;
. {- n3 ?% n. ?* s3 \
n8 r& p& \2 k$ x& q# t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" z0 p# D" ^* I* E' Vstatic void McASPI2SConfigure(void)% g5 {' j2 Q: U, J! s# a
{
% H* i( S3 S7 g$ J& | ^$ iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 S% b4 d h( I7 |# ?6 |* z E7 T4 X. e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ k" Y1 {, l7 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); g/ N+ t- x0 M6 a; N: b# T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ p( b' x0 f q7 [. C- F; F+ D' L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; n% g/ n+ p: _% ~ g
MCASP_RX_MODE_DMA);- K4 n7 ]) t, E7 w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 T6 k6 m, I! uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: [/ C& i3 a/ \# B' T5 l* s, a* a9 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # \( G- E0 c4 e `. g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 F8 Q* j% A# D4 i7 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, e' U- s8 ]$ f. m" S6 \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* |# n+ f6 b$ e* [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- S7 m7 A% T1 v- eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 S4 z& a' r# Z' W* D1 C) w* T8 cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 g: t8 ?5 i+ b, [
0x00, 0xFF); /* configure the clock for transmitter */
2 y& S0 \# ^& v' zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' r1 W, R$ R% f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 j0 Y+ c8 O1 U& g) O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. f H1 }6 P7 o' g4 e) H5 I
0x00, 0xFF);
& Z) W" f0 \9 t2 O% |) m' q: C2 V+ m! P1 N, k
/* Enable synchronization of RX and TX sections */ / k6 A; `/ s" k; a- _. o1 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) Z3 F" F; `( I: n9 K9 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 o3 w' T9 C$ Z( y4 ]5 _: ^& a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 `1 s+ b% S0 o4 w
** Set the serializers, Currently only one serializer is set as
9 k* `3 a: M% U" @) i% P** transmitter and one serializer as receiver.9 A+ ?: ^, v% @+ g+ O
*/; S- X$ _0 u' V3 z8 D" R/ e: @; g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' {2 X, M3 H" v1 E7 Q- U6 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; }4 |. I; M, d, @5 O** Configure the McASP pins
( h! p) j# }$ p$ H/ u9 @- d% h e** Input - Frame Sync, Clock and Serializer Rx' T+ O! _ [" ~7 K0 r2 C, ^3 \& K
** Output - Serializer Tx is connected to the input of the codec
: u$ B3 W8 O9 |+ Z) A*/
6 K/ B$ |0 p$ ?- C GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; a5 q+ [2 C9 C* ~8 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 \! H; w6 V. d- F1 F$ l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. Q" ^# x& v6 j$ o3 Y| MCASP_PIN_ACLKX
+ w/ w( O. s3 n! a| MCASP_PIN_AHCLKX3 }0 }% |1 a4 Y4 R% S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% g7 A& w* X# T5 k0 B, W6 N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 ~' ^3 X6 X; ]- R3 i+ k
| MCASP_TX_CLKFAIL
% n1 }; T2 p( U6 @1 ?% N+ s| MCASP_TX_SYNCERROR
2 J* p7 q+ y( u) T3 E' e' [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' I( @2 P, ]' r5 N% N' u| MCASP_RX_CLKFAIL. ^- T) n! x+ f) u! E
| MCASP_RX_SYNCERROR
0 e3 C. z- ]$ d& A/ v% B| MCASP_RX_OVERRUN);
9 R: @! X; ~2 V. \ B} static void I2SDataTxRxActivate(void)7 A k+ d" V7 B% F
{* q9 A* h* f, r# F: R
/* Start the clocks */
* O: o2 _, z/ H rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 x6 f4 `) E! g/ q+ lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' Q4 _: g4 q' s7 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, m9 y: p8 b4 b
EDMA3_TRIG_MODE_EVENT);
/ C- f7 R: b s3 ~1 g% DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 c. }2 O0 t, a4 d/ Z) u- j8 q* [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ R" v- k) M, i% x; U" U5 J) nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 m) v) W9 s" [' z' {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 c: F9 \4 i# vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
H2 ]% J. g& V7 C, s2 IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 m+ |. ~1 F! |/ N& q: b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 Y' q/ G; W8 S) X} 8 r: l. o; h6 P8 G4 ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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