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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ c+ R6 o' [3 binput mcasp_ahclkx,
* S+ ` u! z: J- u( c+ G( Jinput mcasp_aclkx,! e6 f; @2 A' p% W' ~
input axr0,7 c" K. J5 n- L8 T" k, r/ |4 y, ]7 k
; f7 q9 a# Q5 V) G9 i
output mcasp_afsr,
3 x/ Z' U6 q2 r9 r Qoutput mcasp_ahclkr,
+ L- h3 |. V& L5 b2 v& O xoutput mcasp_aclkr,% W* Z) b# Q. O: T) {) Q* O3 u2 B* X
output axr1,
- f& X: |3 j! i* n% q& I/ a$ w2 |; i assign mcasp_afsr = mcasp_afsx;# l$ S# z6 ^* N) u; X/ p8 S
assign mcasp_aclkr = mcasp_aclkx;
. Z0 n9 h. _: O0 i* Dassign mcasp_ahclkr = mcasp_ahclkx;3 }2 r; [3 c+ v3 F. k- W" y( C1 o: C
assign axr1 = axr0; \3 x1 }- v) w" O" Z" S% ?3 c
& }' X6 D4 b" e5 M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" @+ |! x( |" L/ cstatic void McASPI2SConfigure(void)9 b' x7 P- |8 y6 Y5 _; u, @
{
2 u( d5 f% a3 L/ KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' ?8 g& d% s) N$ s% zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' }% C5 [9 [! b: X _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, c; l( L- Q6 s6 ]4 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ d4 O- h* |. j: Q1 V( gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. o5 L Z6 T7 g% ^6 t) P/ E+ ]MCASP_RX_MODE_DMA);+ W2 w! @3 m; t J; y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. e, l% A4 }* z9 Y5 YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% P- y1 z! Z m N% b- Y" X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ }3 Y0 z5 l. e8 w2 L$ P! ?+ k% _2 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! E$ H! r5 ?* [) X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 E/ _& O2 b, W* J; z, F6 e" HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 O/ u. B/ \, J) Y7 \8 G/ b! pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 {" T+ M, }, S# Q: I2 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # c0 p! |; @8 t' O, [* S; Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 F; j Y2 T* c9 a, W0x00, 0xFF); /* configure the clock for transmitter */
1 r1 ~3 |: x0 Y* w" Y& _$ TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- J5 Q4 H5 a+ `5 ]+ G# EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( e/ g4 B2 [/ A0 U. Q" K7 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% n9 s0 \& L2 J; B! ]. C
0x00, 0xFF);
" A4 K1 ?$ c5 j: ^) P) l* ]0 N
' P5 z. G* x# N8 l/ c4 ^: a/* Enable synchronization of RX and TX sections */
+ f0 h# v8 s4 m! Z, W1 ?- e dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// f1 r; C" P+ D& e/ u5 q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ P6 N; n( v& {6 d- a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 T' h, s* t# ~! S# R; W: S** Set the serializers, Currently only one serializer is set as! H) Z3 z+ G) X0 f C
** transmitter and one serializer as receiver.
! h9 i& l6 f( g- g# b4 f*/% F& h' X0 }; R$ x i) w2 K* G5 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; Y% M4 P7 u! B! n& Z y& K! c1 L( @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% \- |$ \4 S" i0 O** Configure the McASP pins
+ w$ ?5 \% @. Z& u; W7 t& ~** Input - Frame Sync, Clock and Serializer Rx
) y7 x1 R* P& C9 e7 W6 }** Output - Serializer Tx is connected to the input of the codec 5 b; ~' H& `. v$ r
*/
' F" k2 H g4 F% h. L8 c: dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 j; d0 Q. v+ o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: w, }* o5 u" h. {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 [6 ~" b* N8 C% O/ Y, k' y| MCASP_PIN_ACLKX1 P) K) Z) ]; D! _: e
| MCASP_PIN_AHCLKX& ~( ~5 E8 v' Z' |" n/ P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 C1 Y. V h3 G0 V, m6 v. z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : s8 v& H6 K" J. ^% ?' z3 Y
| MCASP_TX_CLKFAIL
5 U3 N, e, _* s/ _, W| MCASP_TX_SYNCERROR. x- V2 g; c2 @# I5 F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& g; ]" ~$ P* k9 i( u2 |/ f/ _| MCASP_RX_CLKFAIL- ~- g3 X8 \7 s9 g. V
| MCASP_RX_SYNCERROR
8 ~! |2 @9 V G5 \( U| MCASP_RX_OVERRUN);
8 H8 k/ o9 ^4 d) I! M( J- q% `9 T9 d} static void I2SDataTxRxActivate(void)
0 }- y/ \, I1 Y{0 v+ Q) p4 | `# M# h* x* p
/* Start the clocks */1 s4 {4 w+ Y$ O/ y7 B9 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) h; Q/ S( K- g. g9 p' b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// c9 _. d- ?& _# v2 Y1 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. i) w5 G9 X6 Q
EDMA3_TRIG_MODE_EVENT);/ [8 f8 G& h# H w0 a6 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! P! d' h- W. E" B& Y8 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ N' w: g9 P1 Q6 g5 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* I% {; U( v& YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. x4 ~/ k8 E; Z" k! e* c. q" r# @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. T( V- Y9 R$ d. k# }. t$ G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# {/ m0 A/ J6 \. a3 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 B" K: N w$ j4 c- G8 p} 2 E6 q8 X. }' j, i2 g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * `6 y( M6 \0 B6 z
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