|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- G1 M p# P J' W" r) O0 Z
input mcasp_ahclkx,& T* _1 o3 a$ B# l% C: d
input mcasp_aclkx,
, S* w7 S2 o+ Y2 F' s: A; L/ ^input axr0,
" i: ^8 H0 X* _! \% C
7 O: V/ J( O# P/ u y. ]. toutput mcasp_afsr,- h2 b- T, y& h# u2 e) k
output mcasp_ahclkr,
5 u+ q7 e& i0 H* J! g% g2 doutput mcasp_aclkr,
% X. Z" ~0 Y$ E* F! C+ [output axr1,* m: d: [% N. U2 h2 y" x
assign mcasp_afsr = mcasp_afsx;$ r q! H! ^* q+ p9 T% T" w
assign mcasp_aclkr = mcasp_aclkx;0 K# t$ U5 m- Z7 V
assign mcasp_ahclkr = mcasp_ahclkx;
/ J5 k4 ]) k5 E, N+ @8 ^$ massign axr1 = axr0;
" p, z2 G4 N: T/ @; a
. j" d: v9 u( c9 F1 i3 p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / O' E3 ]( X* B2 a
static void McASPI2SConfigure(void)* n/ t6 h' }8 |8 O7 \
{
* T5 Z2 M' |$ d; D- U7 R3 K" iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' T) B' l- D. F* P5 D* I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, U4 W, d9 m+ d8 J1 n' u6 z$ J* f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 f7 Z3 N8 g p. ]6 G3 {9 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' a _* c8 j- Q7 bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ f+ ]: M' S" AMCASP_RX_MODE_DMA);1 e! w6 ]5 m1 w9 K0 l. q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; |7 G, ]3 T `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 Q! o6 J, j9 n( s% Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, u/ W! d: q* e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ l# f: p3 D4 B/ S- k4 z+ |4 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ t5 X( A |- ~- W, I* t; B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ u! @8 n4 u3 }0 e( `8 HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ f3 }) z6 X" J! ~, r" v# MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , W2 @" R- O4 q8 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 _% ]+ a* H9 p6 U0x00, 0xFF); /* configure the clock for transmitter */! g0 y3 B2 E* y0 G8 U2 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 V) o* w. ]% r* k4 c9 L7 ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 r$ ~3 f8 c* {0 {/ v3 j, gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
?. _" L$ H, g+ `8 h0x00, 0xFF);
; f/ o6 a' k; ~5 Z U7 p* S
9 a- |5 O& {: ^! v: L- k* x4 l7 J4 _/* Enable synchronization of RX and TX sections */
; n$ w2 |# z _! u$ i. c7 t+ p' @! VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& \+ C7 S. y! v+ f0 p D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- \3 G9 M4 W$ y7 R3 S0 pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: `9 T$ }( \* r4 l6 u1 l( O9 B** Set the serializers, Currently only one serializer is set as
. q$ T0 g7 G4 k+ M** transmitter and one serializer as receiver.
) ~8 i; R# X! Z" I( I9 b2 K. k*/1 {$ Z9 ?8 A! w7 y ~3 G) M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
x$ }+ C) d1 g( F0 _1 f2 qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 y+ v( B4 A/ Z" \9 ]: t
** Configure the McASP pins
: \4 B l: `9 y/ j: [4 W3 Q** Input - Frame Sync, Clock and Serializer Rx6 {' ?4 g S f. r) e, U& z Q' D
** Output - Serializer Tx is connected to the input of the codec
! K$ y& | j" U/ m4 C3 ^*/
8 O. f9 L) ^. H0 T9 W! A4 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: o+ M' {6 t/ y* [: e6 x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 m g6 I( ?& ^% ]' O$ u; i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) k/ m$ _. F' y% ~/ ^( C, G0 e
| MCASP_PIN_ACLKX
! b1 ?- X7 w$ B; K4 X| MCASP_PIN_AHCLKX
* K3 }+ m/ a! l1 ]2 N- r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) c) x. Q- z3 o% _; l3 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 m* T0 i8 G! t' |4 _* b
| MCASP_TX_CLKFAIL : C% r0 D9 q& U8 d4 Q( f
| MCASP_TX_SYNCERROR+ F" T( Q% h- q! z7 E0 U% k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 Z; H+ A7 Q8 _ {: m, D4 Y7 W# V( H
| MCASP_RX_CLKFAIL
' F" ~- P8 v% N, ]) a" i$ @& T| MCASP_RX_SYNCERROR : x" X ~. @0 R) a
| MCASP_RX_OVERRUN);9 @+ H& y" R. E
} static void I2SDataTxRxActivate(void)
$ `# C) S I, X7 d* H) l{
5 T4 u8 x! ?' n8 b/* Start the clocks */0 _' G; K, q+ N: }4 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: J9 g) _$ _. X/ ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% g/ `$ |( S. K p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; `* v/ Y# f( z, B EEDMA3_TRIG_MODE_EVENT);& o9 S* q; V& t4 G! b/ \9 ~: e# H( F, f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " E2 _4 A$ `1 D4 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! k6 Q N! _$ y" }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 X3 C, r) N; ?2 M9 g ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 L( w( |, I3 a3 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: X4 J o" i9 K! {% |, `6 V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 F& M. q; Z1 M+ N$ A3 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. _/ N, e- H# ?) O
}
/ N* @8 V' k* @ O! Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) ^; P4 m9 P+ f" I/ X |