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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: A* i. [. t5 Z2 k) ginput mcasp_ahclkx,
3 d+ ~% y7 H8 V! Kinput mcasp_aclkx,& Q, r! J# s4 Q; B
input axr0,
! q/ z& ?, a+ Z* X/ M- y. ?3 F- s+ z) F- L% W) f8 g' b# |8 n
output mcasp_afsr,
/ J3 _. T! b) n2 s: Youtput mcasp_ahclkr,4 F# q( j. V3 [% P/ _5 U
output mcasp_aclkr,
$ |+ m1 z1 q% t' f# j0 P% U2 uoutput axr1,+ [) ?8 r; M+ E; {! d4 S
assign mcasp_afsr = mcasp_afsx;$ r1 e8 ^# W1 g" v$ A" A
assign mcasp_aclkr = mcasp_aclkx;
" i- B3 x6 E8 V7 x: _assign mcasp_ahclkr = mcasp_ahclkx;
: X' p# u7 F& Z. v Aassign axr1 = axr0; - m+ F/ M2 i% Z) _
# j2 [- ^: ]# h. c* z! y" N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) Q& R6 i) j3 t7 ~) i4 q
static void McASPI2SConfigure(void) o/ [4 p+ h. p& ^+ O5 O' ^# Y' K
{
) _" Z) w/ ]" Y9 D3 h8 e% GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( n9 X4 e) K" b% I, C; ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- Y% i' W6 w; y4 ?( h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 v R) g9 m" U: K: s$ c9 V( k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: ?6 e- ?8 b9 R, J, X& v: HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 S' P& }5 a. { w& @& h' H. ]
MCASP_RX_MODE_DMA);
9 U9 h9 d. Y/ o- E* l lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 b% y; F" n$ B/ k& G6 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 `# W$ T2 x0 W+ j4 \: I6 g& v" [# Q* WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& N% A4 f) c) a- Y- v' D1 w3 oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' V, X% }$ h; k, ]! O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , x, T. q0 V, j; n( O" i7 p% D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, Z4 v2 K0 e! Y& {: E( V) p' G2 Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, }; G! q5 Z9 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / Q- h; A; X: y- `; i2 P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ E4 \) S7 \- L
0x00, 0xFF); /* configure the clock for transmitter */
" h5 y1 V: ^3 g1 X' N5 Y6 l$ B- ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, L# S, K* I# C$ r( N# Q. aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 c, l, H( D# R- e7 C1 U" ?$ K6 n7 O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 @& ~ ] u7 ^) o
0x00, 0xFF);, Z; J# b4 D+ F+ W0 i
7 x9 h6 v* |3 L5 F3 L
/* Enable synchronization of RX and TX sections */ 2 d9 [' m) ~0 E) m5 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ Y5 ~7 L9 H3 lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ A7 a. q/ H# C4 b, {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* d% S s+ A/ l
** Set the serializers, Currently only one serializer is set as
! O. ^0 |( h5 y8 |1 G1 S** transmitter and one serializer as receiver.
8 p" s& w. J0 a; _6 {9 L3 t*/
) Y1 U; z1 Z( r ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ z8 Y, M! \7 K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 B% g: v f+ }8 T** Configure the McASP pins
* I H) i% L. Z** Input - Frame Sync, Clock and Serializer Rx* Z! D5 s- n( e+ G, [
** Output - Serializer Tx is connected to the input of the codec 7 p% n8 {* r. Q6 _( q+ ^* J
*/$ m+ P, m: [! U9 {1 I* ~! B7 B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 a9 e: z# ?$ v) ^! EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" O' h4 r' ^) UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 m. Q. n. e- X. D/ ] s- I$ i
| MCASP_PIN_ACLKX* Q2 F( O& y: G& G. W0 Y
| MCASP_PIN_AHCLKX; r" T' I4 ^+ Z8 k. y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ Q* J: H- W8 g/ \+ O, R' M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( _, R) X1 l8 x( x" I" W! d
| MCASP_TX_CLKFAIL 7 i% E4 _) D( b# ]% @/ Q8 ?
| MCASP_TX_SYNCERROR
; l* i" n/ J, E. G S% Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( j$ A2 J/ ?' e0 V4 e$ m R| MCASP_RX_CLKFAIL; p9 P: N% F/ K9 I! I& u2 {3 \
| MCASP_RX_SYNCERROR & ~$ t; ]1 k+ q; @3 |$ R
| MCASP_RX_OVERRUN);/ a% R2 r1 r( \3 d+ l# x5 J: D
} static void I2SDataTxRxActivate(void): h; R) J6 C# |8 K' o
{ y) O, n# S' _6 \+ O+ ^
/* Start the clocks */. t- L8 N- e9 }( U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ o+ b; z0 I1 X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- X/ A- q0 Z& Z5 x n' [, jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! i$ D3 j7 Q# y6 a3 Q
EDMA3_TRIG_MODE_EVENT);
* d2 D- c3 U- }5 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + S( s5 k% |# E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ Z# L& {9 ~4 b3 z. EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 ~) |# |$ t. L' ~$ Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- n: V% x5 H7 u7 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' t* s i5 m& bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" r5 K3 I$ j8 M' g( ?4 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 a" W) P& y) m+ a
} P9 T+ M7 R7 F7 B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - {: J& g" G7 I
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