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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 {1 P3 i8 E, S) c: i) uinput mcasp_ahclkx,
: V! a4 K }5 ^* _( H& a# Binput mcasp_aclkx,
- H9 ~& p9 X8 T# Dinput axr0,
+ g6 ]% W. G- `1 W# w
" h' |, ?* {( S6 S2 {output mcasp_afsr,
5 f# W3 ~$ x0 x' }2 p: houtput mcasp_ahclkr,
$ q* `! k( I' H+ o3 j$ joutput mcasp_aclkr,0 @0 Y# b: n9 x9 Q: { R
output axr1,. Y6 U" @# q4 `; H- a' U$ `
assign mcasp_afsr = mcasp_afsx;& m: I( y7 u/ ]3 r
assign mcasp_aclkr = mcasp_aclkx;
" f9 R% O& q# V/ ~4 jassign mcasp_ahclkr = mcasp_ahclkx;
4 O4 I5 X" P G( U5 R0 L9 {assign axr1 = axr0;
% _ ?1 z& V* R1 n4 `0 R6 `
9 B3 b7 p0 R, M! f* d: w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 }4 @: w( ]! o1 V& x, e& x# l1 k7 ?
static void McASPI2SConfigure(void)
+ j3 N9 C3 `( c; \* E{
) Z- K$ x8 x" c$ N5 l. R$ ?7 K( s/ @McASPRxReset(SOC_MCASP_0_CTRL_REGS);) J/ A4 p1 f& A8 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// F% Z: J8 t5 O+ W: K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# v( L- f. f$ H* G2 |' Z5 u9 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" u; ^% [" R1 h6 H4 z6 J. jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ O. ]+ F3 i/ W1 i
MCASP_RX_MODE_DMA);4 ~: I: F" c f# K/ I& a8 r, O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# n; }; ]4 |* D) K- ~1 D! [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 l, }( e3 U( F" x2 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % V& T1 o$ ?' l/ S' w; E, h" }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- N2 k( [! \" s6 F. S# p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' `4 z6 n2 g' |7 s$ u8 D3 N9 f0 cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( } p+ W, g3 O0 e UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" f" u; N- y. h1 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( F& {) [5 }6 f3 S% L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 [# I) R! m! `4 i. p0 _0x00, 0xFF); /* configure the clock for transmitter */
' {/ f! w2 n2 V/ P9 s$ BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ l; n! h0 Z) W& m3 ~8 u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 [6 X; L }+ u2 e/ d6 S! X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, U3 \1 |' I9 K& B- ]
0x00, 0xFF);7 f4 r; N2 `/ Y5 N$ q' k/ C
, q2 ~7 m: v2 @* E/* Enable synchronization of RX and TX sections */
& A7 R4 z8 L8 a* n8 \5 y v6 HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) X) H- @5 i. x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: i8 e( w5 U5 ^2 }" R# x3 P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 E! O0 Q0 v( `
** Set the serializers, Currently only one serializer is set as2 n0 j+ e1 r0 a% I2 ~- r( G4 ]- j
** transmitter and one serializer as receiver.
7 {" k' m* Z! |" d$ N3 M# O" D*/
2 i, e. o' Y* WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 M0 E7 D9 v* J. g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, L5 z1 M0 h; @& g6 G** Configure the McASP pins
`4 k! g! @ F. Z8 |% y** Input - Frame Sync, Clock and Serializer Rx
1 w, H0 b5 r- g q% X/ e9 U& U6 k+ S% F** Output - Serializer Tx is connected to the input of the codec
9 B1 J2 P) ^- v. [; E4 _5 J*/
3 ?3 J3 G" [1 @* I7 v0 h* a# W8 aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 e5 J, t2 N) I* ]6 u9 lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, `' ^) U. F" @) JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 O5 W9 Q' U, D$ T6 d| MCASP_PIN_ACLKX# u. I* L3 Q9 W
| MCASP_PIN_AHCLKX2 D2 x. ?$ z& Z$ K# Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( w9 ^. r& r# M: B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - J# r& U7 g0 |% b2 T: c4 v& D
| MCASP_TX_CLKFAIL $ t7 V6 x/ J: j6 h, U- ^: w' ~
| MCASP_TX_SYNCERROR
9 ]8 n4 O* D, {6 r! I8 S) S( U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 b% E, l6 U; |" `: w [( m| MCASP_RX_CLKFAIL/ H3 G) r( F; {$ [; @1 X4 H, }
| MCASP_RX_SYNCERROR
' I) r! T# D( G1 E' \8 e1 B| MCASP_RX_OVERRUN);
, D# W0 c* i+ k/ N2 f+ Z} static void I2SDataTxRxActivate(void)
; T8 A- }* H) F; W. M" w) K{1 p) Q, e9 u) g6 N7 ]
/* Start the clocks */
* @+ e. }; ]7 E% mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 A" L2 K g" M% W! `) l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( e; ]1 l* M% M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( d0 |% G1 G) N
EDMA3_TRIG_MODE_EVENT);/ j+ S8 I* l+ H4 E- t, Z5 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 I' `( t- b+ G1 v: C# V" y# DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' h- X2 ^& O& b( \+ _" M8 C T6 VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- d9 ]. ^2 y$ h7 K' K. i) B1 x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 ]+ ?6 n$ p# i4 u4 B: a) z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: z0 I% K/ R7 B+ k, J7 u4 }7 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 X; Y M f' L; v) V/ x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: r0 Z( g2 m. _. K" b$ ?' _( F} - A7 T; s; @3 d& K/ ^8 C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 W. |, U: M5 `! m. A9 C+ M" `
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