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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 N; m @+ N' f- ~& L
input mcasp_ahclkx,, {/ L J' U8 t7 w
input mcasp_aclkx,
, a8 |2 t/ f1 p( |0 w" Minput axr0,+ [% v- H8 f5 p# A
- a( K* j, b2 W9 ]+ |output mcasp_afsr,
" N! m7 W E4 Soutput mcasp_ahclkr,0 z2 S# |5 a: I8 K" @! S; w: _
output mcasp_aclkr,) z, H: e) s2 ^4 k; J. A
output axr1,
9 q; [3 S) I- R) e, ^/ f; Y assign mcasp_afsr = mcasp_afsx;
; |3 q$ r {) o& U) x6 c; Tassign mcasp_aclkr = mcasp_aclkx;
) z; p X3 X7 N# p2 w4 d0 uassign mcasp_ahclkr = mcasp_ahclkx;
5 }' ~% b4 m# J: Vassign axr1 = axr0;
* ~$ j" z+ e$ n( r: Z7 H
3 F6 L' x. s( O! {- a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! c9 U. Q* B: @1 L7 g# x
static void McASPI2SConfigure(void)1 H6 I8 p8 K9 |# P. B4 z* s/ }
{
2 n4 p) ~0 f/ g! x) eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( O* a5 ?3 k- DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 m- a) u1 |4 V, i) WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 R' m% {" Y! t9 Y) d7 x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 \3 _9 W( Q9 _" X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. f( @$ ]/ j: ^
MCASP_RX_MODE_DMA);
+ M" g; r8 m/ G! {) I3 GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 U& _! o4 `6 ^ _" OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ X. G0 ]" p! \% _" M4 @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 O/ x. W! F5 N& g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 I9 K% V( N$ T, d2 V1 k4 E* EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) A/ N! C2 E7 L: e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 u6 `) h- [2 d; e4 `- oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- ]5 V; {! V! h! P6 v; i) [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 D. O4 p4 U5 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! M% J+ {; a% q3 |9 M0 B0x00, 0xFF); /* configure the clock for transmitter */
8 \9 }- v0 S* U( g$ I& ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* }" i& j3 |9 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ n, ?3 d ~6 R; q0 y) Y Y6 W* E3 _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 p( }# p- Z+ A. K/ \: p; R& L! ^9 k
0x00, 0xFF);
6 \7 z4 U; X: R( h- Y. X/ V# K" _- E- N
/* Enable synchronization of RX and TX sections */
4 x8 S8 s: b5 L( {9 n6 a& [* dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 T$ W+ b8 [$ H% J2 t4 ~+ H, JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, ~' y4 S: |% |) d4 j$ lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: R6 V4 j5 x# B: m& _** Set the serializers, Currently only one serializer is set as4 T4 R S* `. N
** transmitter and one serializer as receiver.2 W8 S+ {8 L, l, _* q$ F/ J
*/# ^' \7 ~& J3 O. }/ J' A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); f! S( T1 O1 P4 v3 k3 B% I1 J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. n: H s: }5 N** Configure the McASP pins
& Z+ K" W+ S6 ]$ k- a9 p+ ]! A! p** Input - Frame Sync, Clock and Serializer Rx% P& G3 [8 E' @+ v- Q) f+ A: E3 i
** Output - Serializer Tx is connected to the input of the codec
4 P& S8 {; `, @3 W' Y6 a# |3 T7 j N*/; {) R4 e* d" N! l- Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 @5 D8 a+ u5 r# CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 ^8 o0 X6 Z, e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' y& _6 X; L3 [| MCASP_PIN_ACLKX
& z6 F8 h. ~1 Q. @3 n8 z| MCASP_PIN_AHCLKX
- p* u* Z2 C w8 L) v6 C7 I$ U3 p* L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 u6 b2 ]2 t) H" `- UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 i% v- }- b6 L3 h8 T3 I
| MCASP_TX_CLKFAIL
7 d8 k. |. Z/ I+ o0 |' J$ [8 l| MCASP_TX_SYNCERROR( y5 u; I2 D/ }0 q. P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 v1 [! |/ G" e, i) w
| MCASP_RX_CLKFAIL
1 Z& d8 {5 g8 z5 T) X6 l) l| MCASP_RX_SYNCERROR ) j- D8 b; q4 i& p% A {6 J4 k H
| MCASP_RX_OVERRUN);8 m4 T4 [6 H4 u1 W: |2 O# C/ ?
} static void I2SDataTxRxActivate(void)3 c. A0 ?, i' b7 c# s
{/ p3 W: p' m* O' N, G& \+ Z- v
/* Start the clocks */& u* m* [$ d X; @0 i) y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' F6 ]0 D+ \; S% ^6 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 K: Z3 S, j c- q3 E7 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 e/ h3 I3 t/ h& c/ d, HEDMA3_TRIG_MODE_EVENT);$ @5 M$ U. p! C1 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- k- ?* u8 l5 e, k/ iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 e% z$ y, R ~0 }% p- @ pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ ] ~6 w# ], a! h6 Y" i$ cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 c* D. [5 B6 O3 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 x. W. s4 M) n* y# e; X# I* M. u- Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% A; r- {! e$ B5 |9 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% `7 h: B. ~9 d5 t, z$ ~}
# G o4 F+ s3 Z, C. Q% M0 G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 p4 k1 K& k s( e4 \+ D, v
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