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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 @8 W/ m6 L1 Rinput mcasp_ahclkx,0 f$ D9 z! {/ [2 J( V1 I; o) f+ H
input mcasp_aclkx,
, |2 U- R/ b+ h3 J; Z6 R j; ]/ @: jinput axr0,
) a N4 W+ M7 Z5 q8 V$ \
: N+ }4 k& A' S! }7 m% eoutput mcasp_afsr,
, d% T. [( j7 c, K, |8 Uoutput mcasp_ahclkr,. A+ }( ^2 u5 H @5 _
output mcasp_aclkr,3 {, k' F! `% o
output axr1,4 ?% [% O' [! |' f/ h3 Q
assign mcasp_afsr = mcasp_afsx;
, {; \. ~' b1 U5 } o, sassign mcasp_aclkr = mcasp_aclkx;
0 }9 L4 `) B' d$ H& S/ H3 rassign mcasp_ahclkr = mcasp_ahclkx;" N8 X3 [/ d6 X& @- H# k0 K, V% U! O
assign axr1 = axr0;
; b1 r* ?4 g% I! U, o+ s
) M; z; w7 s/ l4 J" o) ~8 l" ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # F) s3 e4 Z4 g) G6 A
static void McASPI2SConfigure(void)9 t4 `9 z& I5 t( X+ N
{
) e! O [9 r3 \. r6 h1 ^4 T8 mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 A. {$ }1 [2 `. h. T8 p4 L( ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ J- K0 B. U9 u- |2 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 {: J% b1 u1 W- H( U3 \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( _" O! ?2 K/ D$ O N; P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( K: }& V3 E6 w* V$ \) [7 |
MCASP_RX_MODE_DMA);* D' D) B, x( j# O6 A0 ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# h u+ ^* a/ i* n1 l3 z9 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& a9 J% G* K7 F9 n/ hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# u' T5 X/ m' M4 K- g0 I# OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* T- x/ X$ o$ f9 x2 g1 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 C1 h' k& Y1 G& p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' F; ?; B( B$ T& t) L0 ^& e! BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ H, N8 ?) R2 e0 a" E$ G" u0 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 Z0 A, y g. L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- E& y( P0 @5 q7 Y2 w( a0x00, 0xFF); /* configure the clock for transmitter *// |1 e* x2 M- [4 C) t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ _1 Q" @, U! P, j- jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! K" b3 `6 u* `! PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! a2 c+ E1 z. P( R2 h/ H
0x00, 0xFF);
1 F* d0 Y& |) F9 V! r0 R* f
( n; g: w ~9 J5 }( ~) R" N/* Enable synchronization of RX and TX sections */ . E3 ~$ |) g2 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; B, O& N7 x; X2 w& b7 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 n/ B0 h, i# QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ C- p; L/ ~4 G! k' `** Set the serializers, Currently only one serializer is set as! {4 f8 G6 f/ n. Q7 q) d0 e" a; f' l
** transmitter and one serializer as receiver.
3 l3 u2 z2 |; J$ w( Q' {*/
8 n: y$ t. X0 l' bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% `" \$ f& |) R- N6 B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 y) k9 g* J: `1 ?1 a** Configure the McASP pins
; w' G' ^( z8 a** Input - Frame Sync, Clock and Serializer Rx
. c, v) j5 {% g5 U" G% K4 H j" {** Output - Serializer Tx is connected to the input of the codec
X. t0 P [* I' z: ^. q" T*/
# K. M2 w \' U% }' E' G; Z' YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ e' q. H" ]7 ]- r% W5 V2 ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 B1 N6 e# B! X! m( dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 W/ t- K+ ]4 y3 |; U# H) W; Q
| MCASP_PIN_ACLKX* I, n4 _9 z. ^$ t* T
| MCASP_PIN_AHCLKX
" h1 h! q# ~9 Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% U1 b; K- m7 ~ l9 C: n* e! h2 h% `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 h- f Y. X9 K| MCASP_TX_CLKFAIL - C+ P/ m. j# y1 a
| MCASP_TX_SYNCERROR
2 y! O: o- r% j( r2 S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ I) v" z: k* _* u4 _| MCASP_RX_CLKFAIL. I) W) v K/ O
| MCASP_RX_SYNCERROR " b. Z' |+ A& r" j. h
| MCASP_RX_OVERRUN);8 w3 n+ i: l7 A8 k7 F2 b
} static void I2SDataTxRxActivate(void)
" I, E1 X& l# h{
+ Y ^ V" o, S: k/* Start the clocks */, h+ S. g1 d2 N' O& }" U6 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 g2 T* K, j0 @, UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; n' a# Y$ e6 T6 S; g! A0 ?6 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 k9 n6 x$ B @3 ] x3 S5 VEDMA3_TRIG_MODE_EVENT);
$ A6 F" s" C& P& VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, i4 C/ p* R. X* z) ?6 {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# @; y9 k$ E" s4 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); Z3 G! R! ]& ^- {" j$ {) c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 O( n2 z0 Z) t" j4 K: {1 v( I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# T* d& F8 X$ A$ ~, x* eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* d/ ?! ?, Y4 @$ Q9 Q# k( f/ o: BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, W& ^2 ?; `! A6 B
}
& Z( m" i8 O3 u. W- o8 i( `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 ?/ k* G1 x' q$ R
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