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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( u2 v% s7 E, Z% \2 G- S) y
input mcasp_ahclkx,8 O% h4 N; l& [
input mcasp_aclkx,+ M) g( w8 U8 x
input axr0,$ t& t# v; q: e# p% x1 K! i
$ _" K8 y/ y! c, `+ Loutput mcasp_afsr,
/ x8 Y& g% u$ M" ]: U6 r1 z3 foutput mcasp_ahclkr,
% R9 z% Y8 Z% `* noutput mcasp_aclkr,
6 a0 y/ U. O1 m' e moutput axr1,# ]- _. P" A' ~' [/ o9 A
assign mcasp_afsr = mcasp_afsx;
& V; v; r# U4 g% m- bassign mcasp_aclkr = mcasp_aclkx;
* H L; m0 R. z. k% jassign mcasp_ahclkr = mcasp_ahclkx;
1 `. j U W/ y( Y8 Massign axr1 = axr0; - o# N1 d, q1 _; c
) _6 ], _" g* F* R% R C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * k: A6 K+ A# C
static void McASPI2SConfigure(void)6 h2 B: F8 R' H! r: \
{. W2 ~6 u7 K* B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ D, n3 X8 W9 Z4 g7 J, G3 M" @, OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" P5 C" y$ b0 u, E9 R9 ?/ R1 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ P! g8 j1 i6 i! f, n. u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 j" `+ U4 f+ N4 ?1 W2 L' d. GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 y9 y( b$ n# ]/ X
MCASP_RX_MODE_DMA);8 a: \+ E* s* f% n9 {3 F" o# ]# Q2 i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# B; X2 e! E6 d6 B: XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 X5 e0 o- _% z9 R B- e. F2 j, o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" p6 F/ d) `& R5 `6 |# EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 @5 |: L* Z, q$ p' H4 c% W0 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" R, z: R# T F& Y/ e5 U9 N" MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// \& h3 B" h1 k( [' P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ A( ^6 ]; T) C) A% S& I$ A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 G. @' k( M1 M, o) W6 f1 o! ]. oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# p, q' g. U% \; O+ m' P+ e" v
0x00, 0xFF); /* configure the clock for transmitter */8 j6 C0 C% z# M/ C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% n2 g& B: H0 z* hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, H: ~3 J1 Y5 OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! B$ q# g. o3 b# \# U0x00, 0xFF);
- J+ a5 d9 g5 F* `! X& x, e9 I( P# M3 `9 r) k. S
/* Enable synchronization of RX and TX sections */
2 q4 c# x& K# S% W+ S3 WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ {$ L* Y- }3 F3 ]" k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, p; s: T: l3 U; J! A' t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 i z; u- Q/ f3 L3 R** Set the serializers, Currently only one serializer is set as
M3 B' ?4 w- M: _9 |, O2 i** transmitter and one serializer as receiver.
7 W5 p. F% _6 l' e' Z- g2 Y6 x*/
* l0 j6 c3 t6 L) ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 Y- {( H C6 e6 r9 h4 E& RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! c- m+ ^1 `; K- N9 ^
** Configure the McASP pins - T. _! D! v4 M* |
** Input - Frame Sync, Clock and Serializer Rx( q9 W7 n% p& J
** Output - Serializer Tx is connected to the input of the codec
% R5 B. Y0 [- R, Y*/
: {* l. \* S. `1 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) {% Z) q$ |1 a+ Y5 @ E' a- |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 O2 g) x7 h( K( @6 X5 f3 r; n* v$ cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 l( A& M* h c
| MCASP_PIN_ACLKX+ @! Z2 J1 a+ i7 m" N2 r& E
| MCASP_PIN_AHCLKX( D- M5 p: s. l# b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; V& Q3 L. |- J( q& B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# x) \2 o0 U+ z4 R| MCASP_TX_CLKFAIL 0 K; M" f1 M/ c. Q1 ? C
| MCASP_TX_SYNCERROR. g- P& M. ], q2 n. j4 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ D) p5 |( |. j| MCASP_RX_CLKFAIL* \/ [& t3 ?" ] a
| MCASP_RX_SYNCERROR
' ~" Q* K- \' _6 W& H0 n| MCASP_RX_OVERRUN);! ]+ H7 C+ P D$ G, X, W
} static void I2SDataTxRxActivate(void)
" W; B4 `# |% c- g. V9 h{1 g4 V. h( O' G1 @/ R
/* Start the clocks */3 V( G8 C8 Q% _) C$ W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 T# p+ o. f: I8 J, |, p6 Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& {7 g+ D! I7 L0 Z( m A0 u- ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ k$ x- P9 Q6 h/ B
EDMA3_TRIG_MODE_EVENT);( l. f2 y( [' F1 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* a- K! @4 b% A5 B$ VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! D) s" Y, f+ W9 G* u* [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; X0 a) c$ \7 l3 Q4 z& nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, U: j+ o/ g$ X- G: D+ @6 K3 u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 k. i9 K3 X! [3 c' ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& Y1 ?! Q) R/ W' S q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 i6 s1 B, j% I* u, _, Z. `}
* \" b; ~4 q7 J5 ^* ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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