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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# T. M A4 \/ R$ ~% g
input mcasp_ahclkx,* ^! ?2 R% J3 |' r+ _7 U
input mcasp_aclkx,
; o% M! `( G/ R' {input axr0,1 n" J1 T5 s+ p. b2 s5 j
7 f3 y) h8 B/ G) Ioutput mcasp_afsr,! Y" I% I/ Z+ E2 W
output mcasp_ahclkr,
+ T' F( [6 g5 G; w7 r% k4 goutput mcasp_aclkr,
8 p# L% k" }1 g. f. X5 J: Coutput axr1,7 k( a, [! J3 i" l# j( [
assign mcasp_afsr = mcasp_afsx;
4 Y4 F+ g: b R4 }( qassign mcasp_aclkr = mcasp_aclkx;
3 j) E% |1 l e2 }* I5 aassign mcasp_ahclkr = mcasp_ahclkx;( Z" F0 a8 C$ Q8 P t4 Q1 ~
assign axr1 = axr0;
4 I1 F3 n: X/ b
, i/ m5 k5 c8 t, y8 |! R' u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- o( u, K- T( i2 F9 Kstatic void McASPI2SConfigure(void)
, k* B* K# r, v0 v) g1 e% P{
y# v! e) h$ D+ uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; y& g! c: R, F8 ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* i& C" u/ R( F% G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& g7 H: @' `$ |; z1 i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 d6 e- h5 b6 R) IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 p: W4 [9 z0 r1 ~8 J* A) K
MCASP_RX_MODE_DMA);# Y3 c! B3 a Y- k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 j, x- Q0 T7 YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
|# n# W6 I2 e4 l6 t0 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 m' X1 I, L3 V) ], l* eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ `6 W2 u7 L( cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- V% G2 z4 M0 ~# H( V$ F5 k- S) NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# T/ B! _% I$ \$ P+ ^5 K0 QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& P4 V9 E' P) @4 f8 N2 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, }) t9 ^9 W+ Y. E% _% B( ?2 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; i+ z: P! u' L0x00, 0xFF); /* configure the clock for transmitter */' o% P: x5 K" Z. G# _# O4 f7 f5 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# h/ A. ~3 _* a. Y& F/ [9 _7 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * c [- R! v+ W, I) c- p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 ^7 W8 Z, V+ a% I( y; i
0x00, 0xFF);
4 Z. H4 t# }# o0 u A. ?; e
+ R' \4 v9 \' r7 V/ B! @2 _- x/* Enable synchronization of RX and TX sections */ , Z; v2 X* {( i1 O& I$ U4 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 o" n6 p( W1 F1 w1 s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); g7 h6 `5 ~% h+ f+ v5 c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* p( @5 d& P9 r& N
** Set the serializers, Currently only one serializer is set as$ h# I; \* k. Q$ N D' A
** transmitter and one serializer as receiver., k- U3 S8 n' Z1 m F
*/
& W* |0 w/ W, aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 m: a% V* H) z7 N& E# [: g: [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* D. \/ b( m" U3 }; [4 z2 F7 S** Configure the McASP pins " F9 b4 L G, J
** Input - Frame Sync, Clock and Serializer Rx
+ y$ P6 y2 w# n5 e1 X** Output - Serializer Tx is connected to the input of the codec
; O, n. _& I! q& h*/
8 T# T8 j# `+ }# |3 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) q1 h, g1 S2 c/ K# c4 T+ L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 A1 ]* ^8 _: \/ x2 R: u/ J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# |0 ^7 h* F- f S) \' j
| MCASP_PIN_ACLKX, u6 T% D3 S I* m- W
| MCASP_PIN_AHCLKX
{8 E8 h* R( Z- T R) K6 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# N* n8 O- Z' ~( M% fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) r" ~1 R% Z, T0 v( f4 U| MCASP_TX_CLKFAIL
' S* Z+ M# X% L9 t1 || MCASP_TX_SYNCERROR5 H9 t' `# N% _5 H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ w: ~7 S8 S" R/ x| MCASP_RX_CLKFAIL
1 A( Q2 ?7 b8 ]/ W5 H| MCASP_RX_SYNCERROR
7 Q- I3 ~1 ^6 U| MCASP_RX_OVERRUN);
! M. f. O2 n8 Y! l4 }} static void I2SDataTxRxActivate(void)
7 p) L! a9 y- ?3 l J{
r G+ x5 Q- W3 k, a/* Start the clocks */
5 E5 w, U4 E& Z# C% W% a3 s/ mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' Z s. w2 O$ b0 T9 [4 \% n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// S) `4 R" g, a) ?' J" s- z& l ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 O9 C- s6 F: \$ g6 wEDMA3_TRIG_MODE_EVENT);
# }" T0 j& h7 c3 [9 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( t" L8 j( b6 r4 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( t% a' Y* Z( o9 T! n: u( h8 U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. r" c3 T9 I6 z( A+ S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 M4 }+ C2 j- G0 Z" O" m3 C% J( |; H) P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" ~2 w% y* B5 K' ^+ EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 O4 p7 ?& j( l6 Q" w2 q0 H4 CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 q+ S5 I: `2 ?
}
/ `& U! p7 U( l" w! J* }/ S0 A. c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 s7 e$ M( x' R+ d n
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