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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 g7 w8 y o/ d8 B& L4 Q7 ]! Z
input mcasp_ahclkx,. c+ i0 t. G1 k% K* A$ n8 C$ Y
input mcasp_aclkx,0 _7 \7 U. ^$ E: G
input axr0,
l2 K' f- t K$ }# R& q( @ R/ r; G# A! ]
output mcasp_afsr,
1 u- C6 {- R! O1 w& d+ S* T% S% moutput mcasp_ahclkr,
7 I" d2 n+ y6 I7 s4 p- X' `& Boutput mcasp_aclkr,
! x! L7 n; {9 d Woutput axr1,
4 t+ x+ C% M' g6 B9 j7 C7 W assign mcasp_afsr = mcasp_afsx;/ |7 e0 W7 W) f7 t
assign mcasp_aclkr = mcasp_aclkx;
. ^0 @3 ] f8 K" Lassign mcasp_ahclkr = mcasp_ahclkx;- |5 a) s& H! r3 |
assign axr1 = axr0;
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/ T! B" y1 ?0 e1 C ~, a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. x/ Q/ U. I2 e! q& j \$ qstatic void McASPI2SConfigure(void)
6 F( T8 b* W% r* n{/ v5 h% ?1 ~( q0 c9 s9 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 t# \3 j- b$ C; fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 a2 G2 ~: w$ _* _8 A4 t2 [& l7 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 y2 C& z3 N' A& Z! ?5 V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 O7 @) T7 u% t+ g Q7 Y- }0 I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 g6 G5 W: r3 \ M/ FMCASP_RX_MODE_DMA);2 o: `! S6 h$ O' J) M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 f d: o/ e0 f' f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& R2 `2 K2 B# z" a7 f) @' L: P. z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; U1 P3 e" |. G g0 v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 o9 Y8 J( f- w( J1 c- n! D' eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 a: g7 _( Z* v9 \* p3 p7 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 E" X! |" ^" `4 A4 K) F% P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& W$ [3 N" @9 ?& S# {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : J( q' n& H# M6 ~' _6 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% T6 J. a9 F6 [" r6 T( d( l0x00, 0xFF); /* configure the clock for transmitter */; U& E4 p1 C* `! s2 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. r o8 ]5 q$ X0 q" Q4 M" h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 W! j5 n( B* |( U) E7 YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% s4 _& S: S4 i9 Y& ]
0x00, 0xFF);+ a6 B3 |$ _+ C/ @! [# ] v1 o' y
8 k7 @. w0 x* e; [" V, H
/* Enable synchronization of RX and TX sections */
) \* m5 ^& G, I# v- T& LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* _% L) a) d4 j# L: H K" C9 YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( a3 B# Q0 \4 i% \% K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: D& G: K2 }2 T' y! u8 Y- g5 J$ p7 m
** Set the serializers, Currently only one serializer is set as
. Q( A" I5 v; B; i% j** transmitter and one serializer as receiver.8 u1 a2 @! Q# F
*/
: k, c) O. y6 D5 J0 ]) O8 ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 J; f1 J+ n, AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" ~% n% L6 y4 v* r* y( ~** Configure the McASP pins + R' u5 S: f8 z
** Input - Frame Sync, Clock and Serializer Rx: e: i% q6 d% V
** Output - Serializer Tx is connected to the input of the codec * x6 H3 D+ A' e7 }+ q
*/; I' m. \+ c6 s) u# B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' u% e/ A- J& H* e/ F# DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 z, z; u9 P6 Z$ O" KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( V' j K0 j3 I9 ^4 ~& J
| MCASP_PIN_ACLKX0 i7 W( q; _+ T% Q
| MCASP_PIN_AHCLKX2 d- o w: d* z: V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: E% p4 e8 X/ k R; ~0 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' o' E* u9 d- X* g) f
| MCASP_TX_CLKFAIL * B2 q& g" r9 [7 v
| MCASP_TX_SYNCERROR
, P! B% C8 L6 b3 f# ]) v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 M) t) x5 ? b' z0 E8 U
| MCASP_RX_CLKFAIL
. \, s* H, P( B6 ^1 J2 X| MCASP_RX_SYNCERROR / D. B0 b9 U8 s2 i: b
| MCASP_RX_OVERRUN);
" G" R# S1 E9 d8 I+ F} static void I2SDataTxRxActivate(void)
( J- Q) R! M/ S1 h8 v5 G! N; E. a1 v{
+ x) `- ?$ m( @+ O/* Start the clocks */
+ m) d* O/ j, d) cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. G' W, _9 t+ n. m1 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ g. x4 k" Y9 V: W+ L8 E5 B6 z, EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, X/ \: E8 T: mEDMA3_TRIG_MODE_EVENT);. c0 O }8 ^) `2 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ B6 C/ ]8 J, L6 j6 R' @! Z1 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 C# U; I" A5 M5 i( e# fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 ^5 g! T. v9 I8 a/ p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 `6 j; F `' a& n6 d1 {" w! R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 O/ ^2 S# y7 N6 R$ c6 K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 k. J, p# o p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% `. V- w- C. U: q9 V6 i) Y} + C& l4 ]+ z$ ]+ m7 i8 X( D2 |4 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; H' w1 `0 |7 I i# Y; y- \
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