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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' B. u) T2 w0 v% i5 b& A1 Pinput mcasp_ahclkx,! p" X( H8 Y3 ?2 U
input mcasp_aclkx,
3 M% c, M7 U3 b+ Q8 H3 l2 |# d% z7 binput axr0,7 Z$ ?& @! G/ d3 O" J2 z1 S
" w+ F! N9 R0 A$ z D
output mcasp_afsr,, a3 b: c8 r0 c1 a! B3 Y$ a
output mcasp_ahclkr,2 A* \8 c' w. n0 I
output mcasp_aclkr,: C) o5 Q& w: i" I2 {
output axr1,5 { s; Z- H( |+ ?
assign mcasp_afsr = mcasp_afsx;
* R8 i) w) p$ ~! e K! N# Y' Uassign mcasp_aclkr = mcasp_aclkx;' F: u. F/ r) o: D; {
assign mcasp_ahclkr = mcasp_ahclkx;0 w+ h' ]9 c7 n7 H3 Z
assign axr1 = axr0; , A% ]- l" Y+ n* N$ g% U# S n7 [$ Q! ]
3 K; A* K6 s0 D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! M( G0 Z6 T& r9 ~2 |0 g/ _' \3 H4 Fstatic void McASPI2SConfigure(void)
2 d# T4 f# r1 k{- H2 o! `3 Y% {% r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 {) {& D4 j& {7 ?( ~, A# J9 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* _! c, A1 @7 `; f$ e$ f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 A. R6 A# _5 o: V3 w/ w. r, t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ ^ o1 s- j( j. B! t. |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: _, K c p& j
MCASP_RX_MODE_DMA);
6 r6 F! i( M! N2 q* S6 _; Q: |& fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ z; X" B( T: ~' a5 R$ pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 D5 ]9 [ A. ^6 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' l: S3 N& H5 _! D, pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( ]3 b1 O9 N+ s4 s6 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ n% N( e" K2 @$ {6 i* wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 [* R, B2 J/ a# _/ @" e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); P& @- _' o$ ^& Z' M+ Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' X$ V9 a- Y7 R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) j4 S+ p2 j$ P0x00, 0xFF); /* configure the clock for transmitter */
$ I' i" _+ S# y% e# ] Q+ iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( H! ~% ^6 [% f" T+ u# mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 l! }$ m' f! ^$ ] m1 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( g+ p4 U& `* J/ J5 ?1 ?0 h2 G; ]* _0x00, 0xFF);% @" M7 t) U- Y2 o; e& Q
: X: h- Z" i/ n3 ?* n8 V
/* Enable synchronization of RX and TX sections */ & |$ y& x6 {1 U) A$ O1 g. \( J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' j* q- V! H4 K' v4 o# \2 X$ ~5 AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- F% s" O; G; b" i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ S5 b) u$ W) |
** Set the serializers, Currently only one serializer is set as
1 Y% \& r* M8 q' G4 k0 S** transmitter and one serializer as receiver.
) p# {3 Z# y3 O% _*/0 c' C p, ^2 ^* H' e) T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 ~+ N% M! u" u: L" GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 \ S, v5 b2 i3 x1 ?3 G** Configure the McASP pins 2 `0 R: Q* |$ Z; Y/ m
** Input - Frame Sync, Clock and Serializer Rx' ~* @5 M: t3 V
** Output - Serializer Tx is connected to the input of the codec 2 C, Y5 p. u# H8 @" M
*/
: X; k7 s. f) ~7 n- Q0 u# zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; ^) t H/ A/ h9 { W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 ]: a9 N5 C3 @; R# c+ _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 i; A h: ~& P, D8 s3 z1 Y- ?| MCASP_PIN_ACLKX: p4 _$ t8 W6 D* e# {
| MCASP_PIN_AHCLKX2 V& W4 i0 N* w( W, z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# T5 ~5 F& _9 j& B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) v, R1 b/ P( z
| MCASP_TX_CLKFAIL
. S* \# G5 y9 `/ z- \$ M| MCASP_TX_SYNCERROR
" O, |( A4 L* j7 M+ j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- P2 ^* @: J' D. }8 X| MCASP_RX_CLKFAIL
/ q6 |$ K2 w$ q! ~" h| MCASP_RX_SYNCERROR
* c' t5 \3 H- d d- [| MCASP_RX_OVERRUN);2 W% K' r% o: F: u/ ]; l: o! _, o8 p
} static void I2SDataTxRxActivate(void) G/ _$ c. q1 b0 H. k
{
; t) r) w$ I/ F) I/* Start the clocks */
9 C9 g k* U' Y" D5 k2 OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 v5 z. a' K6 N! c6 F RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 P( [# t4 S1 j# UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ P0 ] e$ X1 h% P3 s, v7 B1 H7 }
EDMA3_TRIG_MODE_EVENT);6 U1 u: E6 w/ X* k' ]& t5 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 x. i/ i8 F6 [9 j* ~6 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 _( C0 l/ s9 S: D5 G1 `. ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! L! b6 C8 d3 m) p# p8 x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) [ O& V6 y& D: i: B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 v# Q3 Y+ k. L/ E- p% r4 R# i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. Z! E5 U1 I' k( s( @5 `8 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) j# b( b1 J: Y- U- c}
: K/ ^9 e) w8 h7 ~/ Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( c8 f6 m" b, u- d( S
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