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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) E& D/ S+ F0 [8 K: N
input mcasp_ahclkx,
8 g) J( k% u2 a$ einput mcasp_aclkx,$ N: n/ L$ F+ Z$ \1 ^
input axr0,6 Z( D1 F M+ e4 W0 ?8 U
/ y% I& o7 n2 c3 d6 O2 a
output mcasp_afsr,0 o1 F; b M @; u2 L, V
output mcasp_ahclkr,
. A* _3 N E6 S( Youtput mcasp_aclkr,& z# Y; H7 t7 D4 z, u$ g
output axr1,
3 @, Z( g; x# s0 ?6 ?, G$ s7 r assign mcasp_afsr = mcasp_afsx;
! P$ \! E g; J; Passign mcasp_aclkr = mcasp_aclkx;
+ Y7 h( u4 t3 U# vassign mcasp_ahclkr = mcasp_ahclkx;- g. ^: f6 p- |' i# g \' J
assign axr1 = axr0;
' X1 H% Q0 U q+ C( K+ h( {( n" n- x* _& }* b6 V- z5 u8 V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 f: R% I3 c% D* N G, b8 r
static void McASPI2SConfigure(void): g% Q6 q9 q. h$ V, D, h. N3 A
{
' g% Q# C& Q9 x4 N1 V2 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);; B! y; {# H, D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! r9 ^, v# k u" pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ A" V6 ?8 z3 f0 q+ ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// F/ o9 @! O% y3 q( g; x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 v( o' M( _! K0 f) j& P& PMCASP_RX_MODE_DMA);
# w5 k- T( N; ]7 y8 W3 u% hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; F6 ^# T& s5 P! d/ L1 x$ E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* p7 t% f# p, I& j; {# Z4 N: y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 U1 g, ~' ?6 n; M3 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, L$ c' j5 j& }. |6 N" e$ `4 @4 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( k& [5 _* Q, m6 Y: F* s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 _8 P' O; Z+ h4 qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 Z% [- V5 @+ t) H8 J: Q4 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " v `7 J2 ^. `5 c4 d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( b1 P) N' G' d' j k/ Y0x00, 0xFF); /* configure the clock for transmitter */
0 Y& [) z. H5 S8 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* K4 I3 p* F) DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 s- ^, G* O8 a P5 i. p+ C. QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: v' w, O# B- n+ O
0x00, 0xFF);
% d5 C; V$ Y ?5 e* V6 y6 v! p: c- N9 y6 N
/* Enable synchronization of RX and TX sections */ - I6 Q: S% s1 y2 \# E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 m/ J) R' ]4 \. [& F1 X& r) p. \, W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' ]4 k) w) P% V) i) x* o3 l8 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ F6 V% Y; r7 G( m+ m** Set the serializers, Currently only one serializer is set as2 \# o# N1 ?& Z7 n
** transmitter and one serializer as receiver.8 O, c4 N/ Y) _7 c( }- A' u
*/
0 Q3 a, M* d# O8 D0 u% g/ u( N# tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" ~5 Y: I) o3 L0 f) M, _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: Q0 i' n3 A& f/ t% p5 G** Configure the McASP pins
' p/ k: O- v" K9 N9 n+ `** Input - Frame Sync, Clock and Serializer Rx
* ?& h9 m3 F4 r: [0 ]! P** Output - Serializer Tx is connected to the input of the codec ( Y; B. q) f, v) n4 w7 `
*/
{) E* c( V3 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# B* Q8 o8 d9 @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ M! k4 w: f7 u2 R6 S3 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) z U' Y& p- h1 Y" F* G& u6 o
| MCASP_PIN_ACLKX) X7 }4 A3 I( L# \: I. b( O
| MCASP_PIN_AHCLKX
# m+ e# F' T6 c- U( `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
H7 {/ v- F6 N8 r4 v- @! wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # ?( Y+ p) U* ^0 w$ l
| MCASP_TX_CLKFAIL
1 w& l8 Q' E$ _+ k4 z3 f; l| MCASP_TX_SYNCERROR4 t( L3 s: U) ^$ f% Q- b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ ]+ K5 W0 t8 p/ a9 {8 O) h) ?| MCASP_RX_CLKFAIL
1 ?) r3 H4 g& Y# `) g. F6 M* J| MCASP_RX_SYNCERROR
8 p( l% i4 I" G: ~. ?# }! H0 d| MCASP_RX_OVERRUN);
; P: u4 X7 G* q: I} static void I2SDataTxRxActivate(void)( @. p2 g1 {! P! M
{
: U# _5 N* B8 K* \) ?8 C/* Start the clocks */8 G2 d% |5 @& U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 o& z) B7 D/ A/ p! HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& G: ?# y* y: S4 N, KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 w/ F H. I+ B3 y% F& b
EDMA3_TRIG_MODE_EVENT);
9 ^3 L6 x; N0 s; q% L B% EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " y' h. ]; }1 J, C& N8 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) _! F ^! e% X1 _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 d8 E; U3 F" g/ BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. X- t9 E6 [" L3 _2 K$ H! h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' O1 d/ O S+ G) W; ^6 _; L+ Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 @; o; X5 f% V c+ S; OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 {: W5 D; b. M* ?( \
}
: U* C7 L: c; u7 `7 b7 ?$ a1 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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