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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! X& D5 B _! y
input mcasp_ahclkx,: Q; T o# N0 r5 T
input mcasp_aclkx,
1 C! \5 x* Q, S5 ~# F' Ainput axr0,
9 S- S/ x9 c8 |; [" U6 f
# I, @; `3 I# c. d: Aoutput mcasp_afsr,: @1 |+ v5 B, d7 D: q
output mcasp_ahclkr,
5 {/ R/ l) \, ^0 r% routput mcasp_aclkr,
6 k* z9 L T* t. Routput axr1,
* {* a$ ]' J% [/ ^1 A assign mcasp_afsr = mcasp_afsx;3 g J, z. u( T8 U$ z5 @" I* S
assign mcasp_aclkr = mcasp_aclkx;" V) P7 H' ?- i* |% y) A
assign mcasp_ahclkr = mcasp_ahclkx;+ p% d# ]/ z, ~+ n6 z2 A g
assign axr1 = axr0;
# M9 K2 c! x' H8 S# k$ x
/ A7 m$ C# W* s5 L/ G" r- J. A$ m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + [/ K2 u2 b" y
static void McASPI2SConfigure(void)
1 ?8 H8 v+ c8 I7 z/ r{
4 {! P4 v/ N. G8 @McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 A, r8 i. a: P* q" n: I5 [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' L7 K4 y1 H+ a) KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* A5 `( M& I3 E* z4 Q7 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ W; z& P* j8 s1 f; \7 M; A8 KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 k/ E C: y X/ y: I6 z4 x
MCASP_RX_MODE_DMA);- T3 L( u( |8 l7 ?- M! T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* s P8 T# I8 M' v/ C \: K! c$ h1 {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ R2 X4 y2 A4 {# P4 c D( r, W) SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* q+ q5 A; Q3 I# f* A4 r" p! _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 }" n+ |( B& y- i" h: j' ~. oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ H+ A2 S8 d7 b4 x0 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 `" x/ ~+ Z2 }. G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); `* v: Q2 @0 ?( i9 {) X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 r7 H+ c- s) j3 I6 P+ hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ T6 r- U' w" f6 T+ g( J% D
0x00, 0xFF); /* configure the clock for transmitter */- g0 b" j) U3 Q$ ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ o7 o6 u: M4 k+ @; `& r3 @* |: dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - [( i8 L& w5 ]# v& \6 y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- b" O3 x5 O% B( ] Y; t0x00, 0xFF);7 P9 p0 ]' e) \" D0 k; A" y$ h
@& o [. b+ _) I
/* Enable synchronization of RX and TX sections */
8 i; g7 r4 M+ P: O( ^, y( W0 PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ \+ u, a* `7 A4 Z) l% [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! b, b- r. o& W0 P$ R" F2 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ X1 i: W8 s9 T6 {6 u' }
** Set the serializers, Currently only one serializer is set as$ p' i2 E3 s7 D9 U( v5 |( S
** transmitter and one serializer as receiver.3 j U+ r& O( c. i+ G
*/
m* ~- J! E6 b) o4 s( xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ j6 g% s6 u: ?9 g1 E3 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ D) Q. |1 C/ P1 L6 G# s** Configure the McASP pins # U1 ]6 j: a4 l9 T# z7 \% t
** Input - Frame Sync, Clock and Serializer Rx2 b. |1 y* V; d4 B
** Output - Serializer Tx is connected to the input of the codec 7 P# s. Z5 O' f& q* Q( |4 A
*/% f4 Q3 r0 I% v# L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 {4 I0 C/ P3 A! C: [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 ]1 t9 q, z) ~; o( {9 H5 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; F8 l, _5 J7 N( {+ y; Z& }$ \
| MCASP_PIN_ACLKX" s) o; o2 L, v2 `6 g
| MCASP_PIN_AHCLKX" @- ~' F: u* T' `! C$ O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 n" t$ e" A8 I# T4 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, H t8 y, C( ?! q6 Y| MCASP_TX_CLKFAIL $ F5 ]) T1 j1 `3 i& \4 F) ^
| MCASP_TX_SYNCERROR
a. W, @6 f- v$ D A0 D/ d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " ?$ `2 u: Y- h5 x* k
| MCASP_RX_CLKFAIL
* M$ ~/ D. |+ s C" o8 D0 y5 n| MCASP_RX_SYNCERROR
+ j. @- @2 y! \+ [- w. B- z, [| MCASP_RX_OVERRUN);
I$ V6 S4 D. o* t. i6 Q [} static void I2SDataTxRxActivate(void)! E- S$ y. g9 j
{6 L" ]* `6 X) k0 v
/* Start the clocks */
! v! d6 t7 G: f# Q# f' QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ l* J& v0 f+ a; F( k1 _ r: K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. K* T y' z. V/ z; @& K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 W3 i6 W5 I! r& B1 w m$ u
EDMA3_TRIG_MODE_EVENT);
, U9 ~# ]! S% \. wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ o) T1 S% T O$ V5 m. |; WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( h# g: V" F1 Y6 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 n' f. b$ y; Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 w6 P3 x7 f8 J5 f8 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 F( ]# c4 r1 y9 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# _9 z4 U4 J# A }3 p Y- j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. C! k8 r. [/ j3 X1 ]; M}
3 V5 V1 u1 h$ }! K- X: k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 V9 k- H) w- G
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