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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! O0 K. ^1 H2 r7 m1 N G
input mcasp_ahclkx,8 q6 i) A) v2 ?! V6 B
input mcasp_aclkx,
/ T& g7 S. J" x3 y% Q O1 tinput axr0,3 c$ R0 ^ d* _1 ]4 v3 v
) h y5 |& G) T) n1 R" m
output mcasp_afsr,
: \' g$ f9 @. }1 ooutput mcasp_ahclkr,0 ^, [6 }) D( [
output mcasp_aclkr,6 A3 H5 ]6 t, G5 E4 W, U3 |
output axr1,6 ?% W, q4 u+ ~& O3 D+ K5 N1 d0 W
assign mcasp_afsr = mcasp_afsx;
0 i! m: r. @6 [% }# c+ Yassign mcasp_aclkr = mcasp_aclkx;/ j- U, \0 D$ c1 F# M9 M7 Q( L
assign mcasp_ahclkr = mcasp_ahclkx;* \, t# M+ c! t6 i$ M" O# u K
assign axr1 = axr0;
) L3 w, R6 n2 |, w% ?
: m- @# p5 h, |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 Q1 M5 z( b9 k, e8 t+ I1 [static void McASPI2SConfigure(void)
! P: Y4 G( t( k1 R% ]{
- G3 [/ o" i! c* w' f' V3 hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 g# ~( V& i% E4 D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 y# v2 E" c& K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 e, ^' a5 d0 ~ y1 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* V5 X; g; W8 {7 |1 X& K. p+ G! fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
\ m$ n# w/ j& Q* m1 j- ~* ?/ lMCASP_RX_MODE_DMA);2 M/ q, g" F* \7 _0 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," X* m8 J: _/ i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ D1 t' d3 B0 _% j+ eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! o4 e: _* R% S$ X0 ~( u. R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: U0 h1 _2 B) h# h6 R' o$ c: ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* d/ F4 ~$ T2 r$ ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 z9 q! z* w# H8 k6 j1 a6 y7 ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) m9 @- A/ N, Z( F, O: M4 Z, u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 Y* y( g1 l3 \# M# S* t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% M9 D4 M; l( A& t, |, h0x00, 0xFF); /* configure the clock for transmitter */: }, @; G5 f! T* d$ H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. ~( S( Q2 G2 s9 ~/ _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # E/ E6 Y5 D( u2 g) `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& t9 c8 c0 ?) g' K% B
0x00, 0xFF);# A# [4 m6 H1 V* E
2 r4 ~7 P/ r( ~4 ], m1 j2 \: {
/* Enable synchronization of RX and TX sections */
$ c8 z& p3 i6 S% I6 }( n3 MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 `6 W9 e7 U! O+ m9 IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 N. C! Y# p% o% u. Q" t. T6 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ g1 c& d) S4 D. P* X( E; I- l( I p** Set the serializers, Currently only one serializer is set as1 M0 M; t7 N. L0 T- o# F
** transmitter and one serializer as receiver.9 B' V- G6 r2 h t8 X( }0 h
*/. @' }" Z( L8 C' G, p- E g: f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ m6 U5 e8 w! y o; x$ k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 o+ J1 ?2 |$ Q4 o
** Configure the McASP pins 9 F7 r9 e2 W$ l
** Input - Frame Sync, Clock and Serializer Rx
( r# u* T4 h4 t* n# B7 G, \** Output - Serializer Tx is connected to the input of the codec 8 }1 K4 e: d+ Q0 Y3 Z) z) ]& r2 X6 d
*/
3 b- p4 T0 A2 H/ ~! {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- p7 V; `4 v L2 S3 O9 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ t7 n8 o4 n9 X# L8 w4 t, U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 I9 X/ W5 D6 b3 H# R2 v3 o9 ~5 O
| MCASP_PIN_ACLKX
. n% u4 j' a$ \9 [4 I| MCASP_PIN_AHCLKX
9 F9 w7 Q8 k( R% X4 c; W* h2 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 p) m! J: w2 pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * O# b9 H |! a8 e8 w
| MCASP_TX_CLKFAIL , m" A9 ?8 h( E( |. x; l$ q
| MCASP_TX_SYNCERROR) H/ J1 V* z. E ]# e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( J' Q) x+ u/ l6 w# p, [( }| MCASP_RX_CLKFAIL
5 Q) d! G( g/ C; M9 _% X* k7 z| MCASP_RX_SYNCERROR
X) a3 L* Y. T7 O5 {| MCASP_RX_OVERRUN);, g; ?0 }# v% l# a; ~
} static void I2SDataTxRxActivate(void)
/ d2 P! k* x2 e' C{9 C2 P2 M! f; r$ {8 ~9 F$ j
/* Start the clocks */% f- }# n1 J( i# D n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; w! Y7 N# i, X- Z- B& U/ P4 |6 |. _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 L: `2 H) B* v* dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 a+ F! l) b7 `$ K6 p# v- |* T5 X, [, Z- C
EDMA3_TRIG_MODE_EVENT);
# |! a- x2 [0 v+ }+ [9 k, X' kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : t1 `$ e5 b% L& {; [. Z E7 I+ c8 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% f5 K1 Q$ s6 O) rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) D& v( @. Z1 R' Y0 t7 c, ^; l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. P- w' y+ h* i, U0 }5 rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 ^8 I" t+ L9 ]; @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% T8 F. M% I; F! IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. ?# z- r3 n0 G @}
2 j1 _1 @" g; L+ T* O$ ?1 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " x. Z- c9 M9 }+ R: e% U4 S
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