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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 Q& c' s+ u8 | \' M3 n7 e
input mcasp_ahclkx,
a% @2 I2 |* l* u Q" Sinput mcasp_aclkx,
: z/ ^: H( L& R7 c% A- dinput axr0,
$ A" K7 b: c7 X# S; B, G
/ |. ]; ~; i! R9 b J: r( Routput mcasp_afsr,
: j: T6 K7 _) z q( ^/ q4 G; youtput mcasp_ahclkr,+ k/ S+ ?" K6 X& D I1 c
output mcasp_aclkr,
u/ n. O" ? n: houtput axr1,7 W6 }5 ]8 F) {1 h3 H! S2 J
assign mcasp_afsr = mcasp_afsx;
- D- @6 U8 z5 zassign mcasp_aclkr = mcasp_aclkx;
; x% ^2 j+ z* f5 e U4 x: R+ Q0 Iassign mcasp_ahclkr = mcasp_ahclkx;
( s) J! d( k2 N6 d Y6 N4 v) lassign axr1 = axr0; 2 f& x9 x5 n2 Q
5 x. u9 P( `1 O" L/ ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ G1 J2 L p3 Estatic void McASPI2SConfigure(void)
1 b; c, p. h# D L% n{
! }5 v! D; K( |5 dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ m: `9 e' T) x4 t$ z' b% u: S' P' t1 _* UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 r0 c& ^0 a% O, k5 v* [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& K1 s5 c: u- X7 }' TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 x6 H' T5 _, vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) k4 x8 K; l' R8 \) R" |, zMCASP_RX_MODE_DMA);
$ z! o# I& R! i0 }* ^# ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" x) V2 G- F: ]/ O1 \1 j1 oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# L" @( J* A% B& y n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - V- o7 w7 y! @" d+ }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, i7 b1 d% r9 o: T$ w, N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( w, N& i6 Y8 @ ` ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 z& S4 [- y8 E: t' z" K$ P$ x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
a# X6 Z. w' B: Y" c- m4 J* ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 k) y! j0 o0 Y- x+ N/ I* N/ o4 d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) w6 n; F7 Z( Y
0x00, 0xFF); /* configure the clock for transmitter */, |1 v f4 P4 {3 Q, U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) h8 a5 _; q8 n0 w3 L8 q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 _/ Z o% o% V1 E6 x3 O) T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 ?3 x. i A/ s {, r" F; @2 E9 t0x00, 0xFF);' d( t7 |9 c6 z. s2 k" A6 B; U; A+ z
4 i' ^& b1 A( d: R/* Enable synchronization of RX and TX sections */ 9 V: h n2 U3 t* S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" g( C! P2 X2 Z( ~0 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( I/ j7 b ]; m) u6 t6 ?* H* rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 u+ M1 Y* N/ D, c5 k) c) L+ G# v
** Set the serializers, Currently only one serializer is set as' `' K5 r3 i8 f3 }$ S9 ~
** transmitter and one serializer as receiver.
5 m) }+ x4 s# U: W: o$ x" ^*/" e% P3 w, x- a D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 {2 m& G7 R1 |& R1 M0 h7 W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; D( `, {' c3 e! T$ v
** Configure the McASP pins
1 V1 Z2 L$ w( l/ r* Y0 e* `** Input - Frame Sync, Clock and Serializer Rx
( d" J/ M, C* x9 ~** Output - Serializer Tx is connected to the input of the codec
% B' r4 C, W# c*// K ]- x. ]9 S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& `( ?5 W+ {, N8 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 G9 c) F0 ?4 {( O8 u! ~' ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 L4 O" Q; G5 t6 G$ D6 E
| MCASP_PIN_ACLKX
5 b, d! E$ D' a9 C| MCASP_PIN_AHCLKX% U$ h2 C) z* n8 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ M3 J1 \2 o- B/ | FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ N4 Z) K {9 {! e' n, A7 G6 d F
| MCASP_TX_CLKFAIL
( \, l9 k5 `1 { k" h. z| MCASP_TX_SYNCERROR/ t! `9 e) y# e1 ^7 z K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # Z+ w8 W6 L+ ?4 f5 x& N* |
| MCASP_RX_CLKFAIL
, }4 @0 y* H+ q9 h% Z: v; q: N7 w) _| MCASP_RX_SYNCERROR , M# R I: d# j* s: D" t4 G5 t
| MCASP_RX_OVERRUN);: E* u- t$ U/ y9 Y5 t/ ?; j
} static void I2SDataTxRxActivate(void)
( [& o( S7 e. V# Z5 Z; O{- i7 Z, Q( I# P' c' Z$ F
/* Start the clocks */' c W2 [2 `+ X" z2 \! t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% t d8 O8 V* ?8 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// l$ [, Z z- _. N# C2 {. x/ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- v8 l; U k1 x8 ]7 `5 MEDMA3_TRIG_MODE_EVENT);) S- t1 E& X" [! }$ \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 M& e% @0 a7 k" x7 }- k2 i+ {2 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 }7 }$ g! {) C) L& @) MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ ~8 O9 D5 O# D1 L) XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" q& K# |/ A4 C! u3 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) j; Q( ?2 h& L! LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* F8 [- g/ Z* g1 n+ Z( n) mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 O, }6 V* [( [$ E5 B' p, m
} + K) I. S6 B2 _: l( L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 ?5 q& e) `9 @: y6 N7 o+ `, D; y
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