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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
]( L( f: l& w& r1 u, b( Winput mcasp_ahclkx,* i- b- X1 ]/ T4 J4 |$ @
input mcasp_aclkx,
) ^, c {; M4 |+ d- [input axr0,
& e& V0 e1 I" }9 Z. h/ v8 _- N0 F; `! l8 h5 G+ M- Z; M
output mcasp_afsr,1 e. F/ O* ?' U' G% j' \" O4 y
output mcasp_ahclkr,
. [% I6 X, r" a1 A$ noutput mcasp_aclkr,
. `& F; ]2 s6 s* eoutput axr1,4 S5 M' }6 ?' r! M+ C5 g0 h8 z
assign mcasp_afsr = mcasp_afsx;; c$ ]7 o1 ]) d8 c( Z+ I' k
assign mcasp_aclkr = mcasp_aclkx;
* w& Z+ X1 p2 P: vassign mcasp_ahclkr = mcasp_ahclkx;9 j. g$ a6 _ k7 D0 V# `
assign axr1 = axr0;
1 \) x" L1 A9 |: C7 N) }, ~
- T4 ]( J5 o5 E4 l$ p! o" _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / @8 V2 \9 `4 F/ ?0 m6 J9 U
static void McASPI2SConfigure(void)# R' K' N* ?9 v2 C
{7 U8 S) i4 l7 l# g5 n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# N' Z0 I. x9 B# a3 I% G( u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 V n( b" E% y" x4 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 j' Y4 k# j. W' {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" Y# F, s+ k: k! \+ B. y0 D$ M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
Y5 l6 c2 R) L- \MCASP_RX_MODE_DMA);
4 a# I4 P* ?8 B c1 q7 c6 YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* U1 U y$ Y8 U! UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. x9 S" a1 W0 J9 l8 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 P, J8 e! l2 ^1 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 J4 X) f8 B$ n+ @; [1 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; Z8 C0 D5 y# V3 Z! |9 N8 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 q: t8 ^, M& p l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, d! i3 Y! \) t" l5 R4 G' s) VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, _( H1 s4 z2 `: BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 {, @% I2 m% q2 b7 v, ]
0x00, 0xFF); /* configure the clock for transmitter */
0 E" F6 l5 B4 ?3 Q5 gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
y# P8 W: @' ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 _+ @) B( T6 U/ S! k; e! P7 pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& M, W1 {* y. ?! _* h. ~( L
0x00, 0xFF);
2 j3 _! k( V; F& m- _. p, Q# m
. a! u* n% C, y4 x; i/ L E/* Enable synchronization of RX and TX sections */ 3 F) D: \, `2 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ ?6 x6 K5 g$ P+ aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, m2 ?! Y! o# p s p7 x) ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( T! G! T( H% J: r** Set the serializers, Currently only one serializer is set as# [2 \5 H) g& W& _- f4 g6 k7 S' E) T
** transmitter and one serializer as receiver.
$ G# a% S& Q0 T# B7 e4 D( N2 ^ z: b*/& p" N9 j0 Y) h* n; S: q6 q2 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 {* X, |& p- W# L9 E4 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! }; L1 N* A8 A5 ^2 Q2 u
** Configure the McASP pins " R7 t; k: ]- Q' r
** Input - Frame Sync, Clock and Serializer Rx2 H2 o3 S \" j# I$ s
** Output - Serializer Tx is connected to the input of the codec " `8 `* C% O J3 @6 d0 a
*/& z/ W! g0 S: c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 f' r9 b3 M3 } CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
|# I+ @. M& S8 e, x& g& }9 [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 C( w/ y4 \# W% F: O- V
| MCASP_PIN_ACLKX; @3 H; l( A3 Y, q4 J$ Y+ b
| MCASP_PIN_AHCLKX
' w5 D% s* t+ G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( e. d% K1 G8 d( L# RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % t' Y! s: _4 r0 f/ T
| MCASP_TX_CLKFAIL
5 {5 [' T( D# m( _7 U1 ^| MCASP_TX_SYNCERROR/ [1 j, \3 `: s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; ]6 a$ a$ T$ M| MCASP_RX_CLKFAIL
9 s" F+ F) j2 B/ P* p| MCASP_RX_SYNCERROR
8 f. T* t% S3 Q2 ~! l+ \/ |& z8 D| MCASP_RX_OVERRUN);
# P5 I- y/ e& |1 ^6 _2 T# Y} static void I2SDataTxRxActivate(void)' U; D+ ^. Z, [! p$ a' f7 n
{/ `$ }! m' w' n5 B( A8 ^
/* Start the clocks */
" R) d; {6 Q$ }- ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
^8 q) ^+ g( y2 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// g; z' u) O; W7 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 i4 J" h! q3 u+ c1 K+ c5 tEDMA3_TRIG_MODE_EVENT);
( x, @# [; L: f$ oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% n) b3 E% x4 [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, y# q5 I, M5 B! [3 `) rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 j' d. g$ z8 E, A) h' U0 f4 M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( u4 _* o% {2 P- z! E" bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# L, e) J1 Y Y h* G) e GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' ~7 t: n0 c6 q7 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! S* H3 W9 q( E5 W}
5 i1 \( H3 \4 N. u) J$ d+ j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - B i$ ^+ f; r$ |8 z* c5 Z
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