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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( M5 m! u; O2 Winput mcasp_ahclkx,- e8 s( c. Z q6 `( `. k
input mcasp_aclkx,( O* b; E/ l7 [6 s' d* |2 t/ v
input axr0,
5 A, i B! r$ I0 A: t; i d5 `2 S y
output mcasp_afsr,( _8 }7 l7 v- a7 j6 g4 H
output mcasp_ahclkr,8 c3 X; J {5 C0 A
output mcasp_aclkr,0 U) K! f7 X' f* p% i) W6 e/ L3 A
output axr1,
6 j% h- l- Y! ]: D* \$ t assign mcasp_afsr = mcasp_afsx;
4 u5 I3 G1 }7 n" }7 [. n( |assign mcasp_aclkr = mcasp_aclkx;3 y5 _! r8 u/ J
assign mcasp_ahclkr = mcasp_ahclkx;
$ h2 Q* r; V( N# Jassign axr1 = axr0; " b i7 T1 ^* S( y
" X3 N* P! ^8 ^/ y8 Z& ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% `6 Z+ }7 |- C, O* n4 v4 l4 vstatic void McASPI2SConfigure(void)! R' W, f7 Y. I' Y+ v( ^
{- X' j1 K' O" a! n& x4 I0 h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 N& ? H9 Y! @/ kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 m" W; }/ Y) x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* \) R# H0 g+ J& {& } M$ q# S" `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 U9 X0 |6 Q5 G0 @; ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 S" J/ ?# ?5 `7 \6 K3 m4 _
MCASP_RX_MODE_DMA);7 R3 G+ T0 V+ I* ^! W& O0 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 v7 q" ^& O# i0 N! R4 a3 q6 u4 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 z6 Z2 {! b$ n8 K s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 n6 E. |/ B! A# L: X9 @# T1 M$ s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& G9 V: B" ~6 _3 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , n3 B2 }6 W/ o& s# a) K- ]7 V' ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 H M9 `2 F/ H3 IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 X0 z- H* s* K/ ~" J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& j0 y+ ]6 A& \5 ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' T/ \5 I: A$ K1 E, S. m0 n0x00, 0xFF); /* configure the clock for transmitter */- K! j$ b' W0 n# r( B$ m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' I5 j7 ]( l& J3 M! hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: p' {. ~5 G8 m3 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 M0 v7 @1 V! m& {+ X: V H. B5 h8 \1 e
0x00, 0xFF);/ w# F+ Z4 O7 I8 J8 Z# l: |
1 R2 N( ]# O% a+ E7 P, D
/* Enable synchronization of RX and TX sections */ # Z1 m- O7 [4 Z$ T* {) U7 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// x8 {- m/ a6 W6 w: _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; R& M! s1 D: q! n- e3 e( T+ T( S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, V3 M [* W8 |2 F- {$ ^
** Set the serializers, Currently only one serializer is set as
1 a% T" k% l3 b& ]- Q: Q9 ^# @** transmitter and one serializer as receiver.
* ?6 |$ R7 b }/ a1 G& X( ?*/
p* Y9 ^0 l% O. Y5 c R8 n. {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 K% ?. V1 D% x( @/ D) d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 y2 D, H8 P# u& s- m
** Configure the McASP pins
- x7 M3 g k8 }& b+ f1 p** Input - Frame Sync, Clock and Serializer Rx
! [, j5 p. T6 I! c2 e. x** Output - Serializer Tx is connected to the input of the codec + j+ T0 i' K, F( e5 i
*/5 N& W# f4 b2 P* y: c! y9 D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ ^4 N8 G' {; r w: _$ q4 E7 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ ]# J' n9 H! _# @$ UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 t# d3 L! b6 I- o$ C* k/ S1 \| MCASP_PIN_ACLKX
8 F7 y3 f" s6 r6 d. ?1 `! X| MCASP_PIN_AHCLKX+ y) Z d! q6 y1 s7 ^7 a/ e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& E! c$ {$ K" z! kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; A1 |" [# h) U4 S& w
| MCASP_TX_CLKFAIL 3 w s9 v" x8 U( r) c' U
| MCASP_TX_SYNCERROR
. t% V# t% f, q7 G, V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( T7 q1 [" I, F/ m$ H- Y E4 J| MCASP_RX_CLKFAIL
; _# C! w4 D+ }+ L0 ~) r0 ?6 v| MCASP_RX_SYNCERROR % O; b7 i. w/ \; x5 a% [; N; L. Z: U5 T
| MCASP_RX_OVERRUN);( r5 Z1 ]( a1 o) E+ v
} static void I2SDataTxRxActivate(void)3 y# a! E& ^$ h V+ m, _" o4 I; A5 o
{9 @3 p+ u$ s$ H: e
/* Start the clocks */
& m4 b! P' h! {6 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# d( R% r6 H- n. u6 k4 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 }# L$ F7 L$ E/ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' @) i0 B j) z# E* vEDMA3_TRIG_MODE_EVENT);8 x: j- N+ }/ S% s0 W' @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 P0 a1 m) s# {( A3 ]4 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, p( l2 X& b6 b' h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# [+ [$ B8 b0 j0 o$ ^7 E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. q3 N) k B2 v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 ^0 @$ }$ S/ z) s2 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 w. K6 \- K' \' {5 w, ^4 x$ E' ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: E8 Z# K3 i. z, }
}
) k; c6 Z) } [7 g9 [- d+ f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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