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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 `/ S0 C/ N8 D$ d0 m5 L! z' Jinput mcasp_ahclkx,
+ U# Q. }: K( s; |input mcasp_aclkx,
7 F, w7 _: \# _5 S3 V& J% Z3 o/ h+ j% Jinput axr0,; f: t1 k7 @2 x& v( x
1 n" x: i( s% p& D
output mcasp_afsr,
0 [% E$ Q) b3 _8 C$ I3 E1 routput mcasp_ahclkr,$ s4 V! ?/ c/ g; l p
output mcasp_aclkr,) }; p W% N! @/ v2 X: y
output axr1,1 Y. u* D1 I! o y, a
assign mcasp_afsr = mcasp_afsx;' E( F1 ^$ n7 P: C! v$ z
assign mcasp_aclkr = mcasp_aclkx;
7 e1 P6 A2 a3 ]* Rassign mcasp_ahclkr = mcasp_ahclkx;
* u5 R; L* s. l3 qassign axr1 = axr0;
: `8 t6 K0 h# Y! k
0 \7 V* _& a0 f) p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( v/ W. O" U3 A/ F8 Q$ S+ s x
static void McASPI2SConfigure(void)
- c7 E/ P& M' A/ l+ L{# U$ F) X9 O: K( j0 ]6 i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 L8 [5 s2 l- f9 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 x6 P8 w% {1 T0 m5 S) ]: EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. V9 B& ?1 y0 t& H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# C' h5 V! {8 I8 Y, pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" j! z) r d& YMCASP_RX_MODE_DMA);2 I7 E( `# N( [+ [0 ?1 ?1 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," R$ e9 _7 V( Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ I; \: Q4 c( D: \1 ]$ X; W, q0 f' }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' m- M2 J8 G2 A) i {& J$ R& {" r; bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" _+ T% C$ I% x2 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 K' T/ i; K9 V4 k* G# {+ rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% b( F, Q/ `. P8 {" qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ k( E/ H. }2 a# Z, S% NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( E9 z9 h/ z% v2 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; w5 p! T; l0 D- m+ z0x00, 0xFF); /* configure the clock for transmitter */9 A2 l% n0 s; ~' T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( H1 ?; s. I1 }) J+ l* B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( i+ {6 g9 W- {1 Y: J4 Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 g9 V& q& g3 M
0x00, 0xFF);: |" s* `& a9 O( F
' Y' \4 u: v9 |" o( O: O( D
/* Enable synchronization of RX and TX sections */ 7 s$ v, ?! b9 S% `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* X/ E- ~8 Z& l. M5 q$ o4 A0 K: l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) [& e8 E M" N) P% X3 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** n& i! Z) a: L; C: ~# @) k
** Set the serializers, Currently only one serializer is set as
+ E0 y1 o" Q! @) y** transmitter and one serializer as receiver.
% j) f. M9 i( W6 H6 t*/8 m. Z0 @1 [. F5 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 v+ D0 R" a8 e! X/ {) JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; j) @4 e; c5 S, t( ~: `
** Configure the McASP pins + g3 @* M/ T2 d: i# Z3 Y
** Input - Frame Sync, Clock and Serializer Rx D4 L3 Y0 P2 k6 W; W0 J
** Output - Serializer Tx is connected to the input of the codec ) M; I) I6 m+ f, Z3 P% Q
*/8 a$ w" l. ]6 w2 |* z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: }) j1 a2 I! b- }* p& ~; R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" E q5 L3 p. ?- P# ~4 m* ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) o9 D4 Q0 p/ Z" a" C+ E, {* f7 L
| MCASP_PIN_ACLKX1 z( |1 g0 [9 o6 t
| MCASP_PIN_AHCLKX
# c, @, f" d% V: u, [5 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( f' S4 M$ I7 L( m* v4 o* u5 yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 y' X; T2 W7 v u# l6 Q
| MCASP_TX_CLKFAIL
0 o) R# q) b5 Y+ J3 i \| MCASP_TX_SYNCERROR
2 T5 M. _% T1 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 `* T6 V3 ^6 ?# o+ X
| MCASP_RX_CLKFAIL7 }5 e+ ~$ h8 ^* ^' |: S
| MCASP_RX_SYNCERROR
) D) v" T2 F( x| MCASP_RX_OVERRUN);
. d8 }. ^- k+ W2 V$ f& w0 O} static void I2SDataTxRxActivate(void)
1 t$ @- J |5 C{1 V- e+ \9 e9 @+ F0 g* Y5 g1 V) _
/* Start the clocks */
4 t& m* \% c$ s# a. q" Z$ ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- N: A5 Q- s; K1 ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, M, K* ?: q; g0 E2 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: f# h+ w y- o7 N* I5 v1 T
EDMA3_TRIG_MODE_EVENT);( ]; t0 f1 N( B" R% s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 T* }( }% m! p2 x8 Q5 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// F6 X- _; z/ r9 r4 G, e# J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* Z7 P2 \. L3 r/ O5 s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 A' T; f% L3 ~* k, \/ qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& S2 s* c5 W& l+ R7 y3 U4 AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& U# w+ A3 d# C' [( u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 ~, W: w4 J& C7 Y- S( A& [1 V# T) f M
}
3 j( W3 {7 c4 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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