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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: [2 ]& S1 a1 k1 o4 Q
input mcasp_ahclkx,2 ^) a; o* ~( n, j+ r) \/ H
input mcasp_aclkx,' w% F) a+ {+ Z0 m; M
input axr0,
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output mcasp_afsr,
& C. g( C' c& L. b6 [output mcasp_ahclkr,( m8 L/ w, c4 I( f% s0 R' m% ?
output mcasp_aclkr,
, @4 n' M L6 D4 {% h3 Zoutput axr1,
# G; u7 m! U( P4 ?& E assign mcasp_afsr = mcasp_afsx;
- ] h6 B$ s% O/ J+ ]3 Aassign mcasp_aclkr = mcasp_aclkx;) }8 z9 a% {9 Y. o1 A
assign mcasp_ahclkr = mcasp_ahclkx;
5 ]1 t: V6 H8 e- y; N' @( B, B- `assign axr1 = axr0;
- q& K$ X5 |, l; H! v2 N& s/ f3 y# E% \9 `* }& l2 ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 r1 w; H: U, Y' @" V2 Gstatic void McASPI2SConfigure(void)
* v+ d. j% r( G; u, i8 \% q{0 b; y9 N0 D: p7 Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! T: H- r1 ]- \$ eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ j$ `6 R# n6 KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* o- N4 Z( T6 |9 X- N* wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 f% `! i- U/ C+ W+ I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( O7 O! l* m/ S) ^2 A
MCASP_RX_MODE_DMA);4 `5 U) A0 H& ?. V) k8 V9 b# t8 z# t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 r7 Y" N' Y c; ~) X/ A5 C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% S- c, q/ K* `) T8 B5 |3 OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) v% [- C6 {% E4 X' CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 a G; u- \& Z2 D8 S, u. q7 q, JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 G7 Z" ~ A+ V& r" i" jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) I) p5 b0 u I1 y! X3 i* l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. d6 g8 ]+ A! k/ \! e8 }0 DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) g# E0 N% p9 E! uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ b# M0 X4 y! e0x00, 0xFF); /* configure the clock for transmitter */
! G5 ], ]& k/ [* A- JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 i. j9 B7 Y1 M9 x- y, Y% p6 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
T5 L% `' q3 W% jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% x" W( H; n3 c7 L% V$ L; B
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ 4 ]1 x" g o m: s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" f# V) C$ d+ pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ F, z1 q" F) C% Z4 p7 u2 x, LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* H9 Y3 V1 H! X" a
** Set the serializers, Currently only one serializer is set as
: W6 w1 A) W! R2 P; V) |. j** transmitter and one serializer as receiver.8 \: S$ @. c2 G4 |( f% J. A0 ^
*/& u3 N4 j" q) G8 _# |/ J4 A3 {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 D+ l+ ~2 [0 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 Z$ F: t d" H
** Configure the McASP pins
$ H7 p$ y$ m6 }** Input - Frame Sync, Clock and Serializer Rx# y4 J" f; G! C2 `( H% C+ g
** Output - Serializer Tx is connected to the input of the codec 0 x. K. E- h" X) `
*/
9 q) ]# U/ c, G) Q/ R4 D4 X+ K3 {! KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 H s# x7 Y# J: D( {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' E( ]; K7 |" e/ [. N- `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( Z4 H! h* {- W: K8 i| MCASP_PIN_ACLKX! w8 e, K( h- Z6 G7 {" T$ X [
| MCASP_PIN_AHCLKX( H" f% c9 c: {. P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 L7 c2 w9 [( y6 i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . B0 E) c7 ]' U* E6 C
| MCASP_TX_CLKFAIL
8 ^9 I9 v* ^2 b! r( N| MCASP_TX_SYNCERROR
# N8 \. `6 S% L. [! z! b; g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 q4 ?* G9 C8 h* _) K& a% W
| MCASP_RX_CLKFAIL+ D8 S; T) g; l2 W" i
| MCASP_RX_SYNCERROR ( {8 U0 E; F3 ?" g9 m: ?* h4 o4 {
| MCASP_RX_OVERRUN);
' N& @* e, D' N} static void I2SDataTxRxActivate(void)" ^8 T" Z" k( c! T8 ?+ l
{
5 N9 k2 [0 I3 B3 d/* Start the clocks */
, C, V$ N9 x0 c* c, }) B; |# TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 l, Z- @3 c3 c/ ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) I [9 ? `4 c1 u$ j( E, ]4 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: X0 z/ \- u+ @EDMA3_TRIG_MODE_EVENT);! O' D" S$ ?. L/ f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( m$ A' L+ t3 Z* {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" |' A4 R- Y% w4 D5 t6 Z- wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 x: W6 I5 I" ^) A1 ~" f1 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' o# r/ j X) k' x6 U" x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 r7 a; D3 r) F5 F, eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" F. C5 W0 `6 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 V7 R5 K# w& l}
6 o u0 \/ k: S2 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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