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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 ~3 I1 y' A: s3 u
input mcasp_ahclkx,# p$ y+ Z2 \4 [1 A/ R, ^3 L
input mcasp_aclkx,
& w7 [0 @& f y1 jinput axr0,
+ ~& ]/ ^0 Y, n' d, T$ c1 p, c$ B6 o8 w: R5 |+ F' C
output mcasp_afsr,# g6 x0 V; E0 n+ n8 g
output mcasp_ahclkr,
3 F% w* l: D' a" I) ~" qoutput mcasp_aclkr,8 Y/ j/ s0 B" Q% I. [$ g2 j; o
output axr1,
9 q6 |( `0 I1 ?9 I9 s% U$ |1 j assign mcasp_afsr = mcasp_afsx;. Q) |" M: B$ f; g' `
assign mcasp_aclkr = mcasp_aclkx;( G7 [) f( ~ m7 i
assign mcasp_ahclkr = mcasp_ahclkx;% Q3 Y; q9 M* e9 _+ | }0 l0 P
assign axr1 = axr0; ; a, ~, U+ o/ o+ L. }6 w- f: h6 c& H
@; X9 y3 q# g" J" Y4 r5 G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; c* @' F! j+ Q0 R o$ lstatic void McASPI2SConfigure(void)' [$ X5 M8 G# W4 e: l+ K9 C
{8 z: `4 o9 Z# t7 S! F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 M& E/ |) v, v. H! IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. e8 Y! s z: \: Q- D" T9 N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 X8 W5 \4 _7 j& ]7 a& A$ m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 z1 z5 E6 L" D- b, m* ?+ p4 XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; W( P6 |, d5 xMCASP_RX_MODE_DMA);
3 t5 A7 G. `8 [' dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. U- c+ o. K' [% _* ?$ ?6 H9 Z' ^* vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" a8 C) |% S* _% VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & M. T. M% d( n* A ?: R/ V! ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 J1 n& o2 l+ p" v$ m1 TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! w0 r8 X# H- H# X `' v4 ~# i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 f1 H( j; I- B& R- u- YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; C/ f4 N* H' D: c3 Z% S& y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' D! r: E1 J8 X; Q: }+ L0 mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 ?2 H' x5 X8 h n& G" ?
0x00, 0xFF); /* configure the clock for transmitter */! ~2 F9 x. ]5 F7 B: v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 C* M! s3 o8 C( c* z6 ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- D- p8 R: ?7 k. }; a% {) C1 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," g# ^- x1 b: y! y& |9 C- A
0x00, 0xFF);% v! Z; a/ J8 g
* b7 V. R( z7 ?- Q; W) B
/* Enable synchronization of RX and TX sections */
4 I2 S! \- x' r( Z% v$ WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 [, e. [9 I; L P4 e- H, S3 L4 ~! y* X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( g, U) ~) C2 F2 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ x0 y0 Q, b! x( q; b
** Set the serializers, Currently only one serializer is set as; U) z) ~8 p" k" f# {, E' R
** transmitter and one serializer as receiver.
; {& n' l9 a2 s8 F: a# M/ Y/ x* e*/9 I) t& m% [& y' c0 h! U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 _5 V7 W3 y/ \. b: O- [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# h/ K+ _+ ]) ]** Configure the McASP pins R% q) o7 M" l& W; G
** Input - Frame Sync, Clock and Serializer Rx( Q4 g5 I. |& D/ d2 l
** Output - Serializer Tx is connected to the input of the codec ; R, d7 ~2 L6 o$ d/ I3 R
*/
& Y- h' Z5 R9 p$ O2 yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- I: y+ @9 c1 K z% c$ C) pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( x+ z6 a2 U$ h# JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& _" I# R2 n3 E| MCASP_PIN_ACLKX# I% v9 U! N. |, ~: \/ Z
| MCASP_PIN_AHCLKX8 N+ c! L/ U6 n6 M; E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( G, b5 e6 O" M5 c/ S3 f* ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 q1 P5 b; F& |! l9 A% C| MCASP_TX_CLKFAIL
: K+ P# N3 ~8 w) s, Q2 s| MCASP_TX_SYNCERROR
2 {& Q# F8 g- u$ w8 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( H( c) h; n) f8 P: ~% V| MCASP_RX_CLKFAIL/ @' t! C- ~( v! C8 Y9 y: W
| MCASP_RX_SYNCERROR * H4 L; s9 g; S# h
| MCASP_RX_OVERRUN);/ o% W S& H' X9 |5 O3 b
} static void I2SDataTxRxActivate(void)
4 y: v; ]: X) @# n. }; l+ q0 Y( @{
9 p1 e, ?- F$ D. k) h+ C# V5 ?/* Start the clocks */* N3 [% v: \7 q3 i5 e0 q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# M t% P! N7 `! y6 H: o8 F* K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# M$ M1 K i7 j8 y3 d9 _+ X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ I/ _3 x+ b5 y6 p" I; e* K8 H
EDMA3_TRIG_MODE_EVENT);( R. x' C6 n5 e8 A* @# P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - {- f+ ]* M# o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) A8 s* B6 H' B2 P, X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) n2 P; B' `& J* n8 y. `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, X; R0 v b; o6 P7 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ F( d. l/ Q8 _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" @% |1 x3 H) V8 O C2 WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ k: o. ~. f" d1 M+ l G} f3 v& t$ ?4 @0 Q7 `' F2 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 E u! E$ z4 o: m( F( g
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