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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 C L/ u- y( k" rinput mcasp_ahclkx,
8 X2 U( A) o: v+ Uinput mcasp_aclkx,
* o1 ?9 w# p' e/ t$ e3 F' ^" yinput axr0,) I1 n4 ^; @& M0 q9 q
/ c' Q% d0 L% _+ o& v+ c
output mcasp_afsr,! b4 M, s2 m/ v+ b1 d
output mcasp_ahclkr,
+ u. b1 _& Q! n9 N5 loutput mcasp_aclkr,
, H9 s7 r1 V7 m+ @4 uoutput axr1,
* e' Y8 o9 n( ^0 O! b# h' }: w assign mcasp_afsr = mcasp_afsx;
/ D' S9 k8 j0 z5 N" f9 r7 Gassign mcasp_aclkr = mcasp_aclkx;
" I( T0 L( C8 I6 P5 fassign mcasp_ahclkr = mcasp_ahclkx;0 H) O' T' Q& H# R
assign axr1 = axr0; 3 t4 N: J2 w# j8 C* ~' y, X
% E) H8 N) L+ ]: j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " W& U. o3 o: k5 A
static void McASPI2SConfigure(void)
$ Y$ ^/ a0 D& n8 @5 ~7 ~, |{
$ I. U% Z% |8 q+ Y& |% I" @McASPRxReset(SOC_MCASP_0_CTRL_REGS);. F( y8 s5 ~5 H+ w' E2 @- |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) Y/ ]! G8 w' \4 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; @. L! P2 s8 w. s0 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( K6 G+ ?0 X1 k" {% [/ {+ w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 |6 |/ Z5 F S0 f7 u& ^
MCASP_RX_MODE_DMA);! x0 Q6 z$ r0 t5 e% N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, h# A2 c# k+ S. H5 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. G+ j5 `, J7 S) T( ~. R6 J' @& n9 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 h% v6 V0 f4 v( F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 `" v" Q+ w5 l1 [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . V& i- L" N" \) k r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// m7 O& K7 }( O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, [3 u$ w: z" ?1 ^3 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& t8 g! v Z. ?' \1 W/ t! f. XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. B1 }8 V6 p2 Y- P% C0x00, 0xFF); /* configure the clock for transmitter */8 B$ Q& a3 Z- B4 ?6 B6 U) F E% K. C h# M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# v+ z2 T! m+ C$ XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ E0 I7 e/ Q+ i9 e5 I7 q8 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 C; D# m) x% L! ?4 b( t+ t' _- d: |
0x00, 0xFF);
$ w% I, C }* z% V: o) I! D5 j/ }- W( {: W, o ~
/* Enable synchronization of RX and TX sections */ 6 B! P8 Z; \8 K4 g+ O% [2 u) L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& T$ B% }5 K2 E+ CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 ^1 t" y1 ?; L' ~: E+ YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' E0 ~* ^; f, f& A- g) V; U8 r
** Set the serializers, Currently only one serializer is set as# k8 B! S* [- W5 t4 p }
** transmitter and one serializer as receiver.
* \( `/ M9 g( s1 H# Z3 |*/
, b0 q! J, K5 `5 qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% W: j# l' [" M8 D2 Z5 Y# r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. s" v( Q* P0 I: X0 p' ^** Configure the McASP pins 1 ]. S E) E) w4 I. o! I
** Input - Frame Sync, Clock and Serializer Rx+ v9 w" y1 H% z" ?1 G8 w
** Output - Serializer Tx is connected to the input of the codec
) i) E3 R) _" l9 {) _*/$ v. h# O% l7 h* |4 c5 ]1 P- {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ |% n2 M1 E4 I2 x2 kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& Q1 U- E! y; Q( A. y5 X9 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 P5 j) J! U) V" [$ @& `
| MCASP_PIN_ACLKX- i, q* P3 g. y5 F6 Q1 S. \' r4 B
| MCASP_PIN_AHCLKX
; m# R6 c4 I; I6 G; m9 r9 B' }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 x: c3 F/ ]( F9 L9 L+ [; {+ U2 ^; XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% Q& \8 [2 U, f1 ^9 [1 Q; `| MCASP_TX_CLKFAIL 7 y, _1 @+ h# h0 r
| MCASP_TX_SYNCERROR
. z% D, c5 }; ?, @5 g) L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 R p5 V2 G0 J" R* c [5 R
| MCASP_RX_CLKFAIL
7 n6 V3 ~* U2 a/ F| MCASP_RX_SYNCERROR
. L6 c" d! e2 ~, d* s. j| MCASP_RX_OVERRUN);
% U- I+ l( W/ y s, p. ^) N' ]} static void I2SDataTxRxActivate(void)
. L% ]) _# _. a1 V5 l{
2 Y0 h! x# V2 R W/* Start the clocks */! f4 ?+ \5 J1 w) M# @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 @( A4 c4 O4 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) k& o6 X& q; X% @- k A) F" v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( s! n: [* o9 `/ g1 o. H: a: ^
EDMA3_TRIG_MODE_EVENT);
, b5 S: L$ Q- [( N2 X- r( y wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ S/ i5 B7 w/ c4 `; Q% T! kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 r+ v$ j' A+ }% f0 G$ V8 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' [1 ^/ u" t1 o- I- {) sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& x9 f$ V8 _. o: K* P$ u0 y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" q7 Q% S3 @4 h- s" {( yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) ?0 b. u# H2 `, h J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 K# [. Q" m/ t% N0 ?' l
}
/ l4 E$ }8 K7 X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " v0 f. O; b( q/ ~* Y6 V
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