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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# s( S4 T! M5 S
input mcasp_ahclkx,
, s* E0 D, `$ I& l: e+ O. {: Ninput mcasp_aclkx,
+ V9 D" D+ e) r; ~, }3 ?5 Q1 |input axr0,
/ ^8 ^/ h+ Z, ^ |
. c0 m' W6 k" P5 routput mcasp_afsr,6 T2 X; K3 A" y
output mcasp_ahclkr,- W0 u0 p+ Z+ o4 ~. x. X: @' {
output mcasp_aclkr,
" I T5 Y, L4 b1 _; k! w& foutput axr1,
8 C+ J2 M- o4 t6 p# l" g assign mcasp_afsr = mcasp_afsx;/ j$ [- V2 q/ \" A" v* R
assign mcasp_aclkr = mcasp_aclkx;
* M) Z. c+ Y4 p8 W6 `" F0 H# P8 Yassign mcasp_ahclkr = mcasp_ahclkx;
( O0 I# ^# U8 g8 N2 V qassign axr1 = axr0; & E% [8 V0 y' I* k4 G4 o
/ H# c% I, [ m" c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! v/ V3 U4 m w( @1 Q# E; fstatic void McASPI2SConfigure(void)
0 u) T( Y! t" n4 o+ c{
% e& _% C' v! P5 S* JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 Z8 X0 u* E) n- LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ H5 t ]( i& u L9 JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# Z7 q7 G* `. G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 }2 C8 q3 y6 O- c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 m( y' n( u3 W
MCASP_RX_MODE_DMA);. t: a6 e+ \3 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; {' d' U7 m% Z: E* r" U1 n K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 X. O# m3 r2 I$ ^ P# O7 K5 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & |2 m" d3 b2 l5 w, e6 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" l+ \/ `( Q9 g& v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 F/ ]* X3 Q" g' o* S* W. V' Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 y& L: J/ U3 R* G6 w) Z1 AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 {6 g K0 K5 p" C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
@1 Y R; I+ U: E- vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 _. n& o+ \- U0x00, 0xFF); /* configure the clock for transmitter */
7 S2 D7 j) h7 p1 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 [1 A9 u& b8 R, G _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" _/ O7 Q0 z+ R8 Z5 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- J3 l$ w. |7 g: S# ~5 ~' R6 z/ v0x00, 0xFF);
4 s; U2 ]4 q9 Q6 g/ Z+ L* V
* R6 \! |) d5 n6 d( Y1 t9 M( }/ n/* Enable synchronization of RX and TX sections */
. v$ y0 y! x+ a8 {1 d' G: I2 h# vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ A4 o% m3 T! M8 y4 J% n. L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ {: I" |1 I: Y+ W4 `3 e! s9 i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 U" X2 R1 q3 n8 F. Q
** Set the serializers, Currently only one serializer is set as, q0 ]6 E) W/ n. z* w9 s
** transmitter and one serializer as receiver.
& @- N1 S* w1 }6 r*/# ?% P* C# q/ ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 K, U3 H+ G' M/ W2 c; R7 v' I( dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 l: H4 k { ]" n/ E** Configure the McASP pins
: H8 ^# L3 T. ]' e8 V** Input - Frame Sync, Clock and Serializer Rx; O) i( C' R- O/ ^ p: i2 ~/ y
** Output - Serializer Tx is connected to the input of the codec 2 y1 x% z0 A; D5 w2 V* {
*/( N$ D: C" B! R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% _1 s4 x" n( B8 R4 G7 E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* `: s4 i+ o/ e6 H3 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* b5 f j* u7 e6 u5 G- P1 D6 z
| MCASP_PIN_ACLKX
( A" K6 o5 m' }% g+ I( z; I, _; h| MCASP_PIN_AHCLKX8 N- z" Z, T$ ?9 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ J6 L& K" X# g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 M1 y8 Q9 k$ r
| MCASP_TX_CLKFAIL
+ k% J l9 L T' h. k& q3 a9 Q4 Y- x| MCASP_TX_SYNCERROR
4 r% ?; {% y0 i! D% U3 _8 |) e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - ~ t3 i' B. T$ N
| MCASP_RX_CLKFAIL/ {6 J/ g! f# ~! P" a
| MCASP_RX_SYNCERROR
/ ^& ?- s, L% P2 a, A. S| MCASP_RX_OVERRUN);
7 h! d$ |; \( O: V+ [* {* Y. F$ V} static void I2SDataTxRxActivate(void)
! \6 H0 m, G6 z4 h- t; a8 B{
- g- G i# W5 r4 O5 r/* Start the clocks */& A/ ~+ X& O- J: c* l7 h) B; k: }9 A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
K. d# ~. Q3 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 a$ k9 T+ F: N) V$ h6 e0 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% L3 o! l, Y2 z( [9 |% o
EDMA3_TRIG_MODE_EVENT);& ]8 K1 m0 g2 s. i' ]6 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' L5 @! U( i; F6 u! b7 l# u3 t* vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 F' |5 n! h& L$ U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 d/ a/ i6 J5 n8 {6 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ h# b' N: \( A! D. U* O3 U% F swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! `( w: K7 U$ QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 a* `: f5 O9 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ I3 w9 \+ l. c3 ?) |
}
; B3 `+ q) }! L: V; P% X# M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * @4 x) l. G/ q* v& @9 t' Q/ T
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