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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 O# `# X7 u' k$ {
input mcasp_ahclkx,
8 |+ w$ o' @7 e% f) u4 Qinput mcasp_aclkx,
* g$ X- L) R- e5 M! @! jinput axr0,
& \; s% n: F' K% ]- X I# g% Z3 Y2 ?
output mcasp_afsr,# m& W: `7 Y6 _9 p: p* Q+ B
output mcasp_ahclkr, R2 v: P3 E# t/ i, c2 [
output mcasp_aclkr,
; Q9 \( M- n. Z3 j& u# A9 joutput axr1,
) o5 J) m' ~9 S6 R6 J" ~: e) b assign mcasp_afsr = mcasp_afsx;
7 B; E% n \7 J' b+ j' C+ }' lassign mcasp_aclkr = mcasp_aclkx;5 v) G* W# L2 ? B, m; U7 j
assign mcasp_ahclkr = mcasp_ahclkx;
) e0 q. m+ x1 S1 i& f- }4 r4 aassign axr1 = axr0; " h2 ]6 e; T2 B6 p& E
' Y" B2 [# h% d- e$ ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! b+ Q6 ?' B3 |, J
static void McASPI2SConfigure(void)% j8 F- a! X* X, Z
{5 R7 t( M& |6 Z2 n+ D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 K) g5 z( }( r" }* R: mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 m7 @0 N1 g8 n: m6 k$ S& w- ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 ?7 G8 `/ D0 m% D$ [, n' p& _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ [( g% P$ q) J0 T2 f+ V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ C: R' s6 X$ z# n8 i* H' HMCASP_RX_MODE_DMA);- K( K" B+ K( H) Q) N, z. O4 S. B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 @* J* N+ w; B3 Y) f! q5 I$ P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; [2 ?4 l% w2 T5 U9 R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ \0 H+ o4 v( L# P! uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 ]# R. ~& r2 {5 @9 u$ {7 A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# H+ [" Y0 ]/ X4 t( S0 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# v2 k! ~; t F. V d3 |1 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; U* L Y& @( ~: g- m% m+ R8 QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! ?4 ~2 G! G+ d# g+ ~' e* JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! s0 s( ?4 K/ q
0x00, 0xFF); /* configure the clock for transmitter */0 W) O3 a4 q- A$ G P5 I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 Y. K; K4 V0 h$ J. ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 N9 o- {) P1 O! \8 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# C* R6 o9 U1 e" ]" ]* A7 e0x00, 0xFF);$ |/ f( L: I5 x9 `
/ n2 j! y. t* h) n$ u1 G& D, y/* Enable synchronization of RX and TX sections */
5 V6 }* A4 ~8 _$ V1 ?+ ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 \; M6 E+ v8 s2 h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 k4 m* |9 f" pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ x1 J1 E6 _) O* u' g. t
** Set the serializers, Currently only one serializer is set as8 O* T3 j1 N( [9 w j1 f0 _
** transmitter and one serializer as receiver., _/ ?* ^' x i/ v
*/
2 b' J2 Y* b: i# gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& v* P( c" {6 A' i2 l/ Y3 u7 O! i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- t! [4 k$ d3 W, n5 ~- ]
** Configure the McASP pins + K! W& I; f" ^7 @5 X# O
** Input - Frame Sync, Clock and Serializer Rx" u/ q* }; N: O3 V, Z
** Output - Serializer Tx is connected to the input of the codec
) \' v; B% S6 e& I# b* ?. {8 w( L*/
3 Y; ]( f" [7 R8 U4 f6 E1 |4 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 r! i2 C. \; u, g' _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 `$ ~. {) a8 O, b6 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ Y# S/ E- W6 ^4 _. K/ y; @' I% Y| MCASP_PIN_ACLKX
9 G% b8 D" c; r9 v. W! J| MCASP_PIN_AHCLKX
/ k8 K, t5 }' P% s4 ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 E: M8 G( E: B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# O" o( z: X% M# H| MCASP_TX_CLKFAIL j9 ?- q6 }1 s& w; _
| MCASP_TX_SYNCERROR
4 f* i3 A S, X. i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 ^5 E% N* `/ N5 [- P| MCASP_RX_CLKFAIL
1 J3 X: }( b9 N5 W; I| MCASP_RX_SYNCERROR
_1 x+ Q2 V% X3 I% b. J2 G! b| MCASP_RX_OVERRUN);
8 C( Y* _) ]2 Q- e} static void I2SDataTxRxActivate(void)6 C4 e/ C- n7 @4 W7 [7 C4 v
{
/ P* t0 R$ f' S. I. C/* Start the clocks */
& i( t% z3 q: d* b4 E2 ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); @. W5 f4 v' j* p& X( W- f$ U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 w3 \0 Z" Q7 A4 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' K& ]0 y" W# _4 N8 aEDMA3_TRIG_MODE_EVENT);; |0 d3 L/ V; B! E3 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% I5 B: r/ M: i) P8 d0 c, yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) [! G! r+ i- x0 v* ]2 R: SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 W2 e1 s! b9 Y( Q8 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( o8 M/ q U% a) Y7 l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' ^& E1 @" `, D6 {' ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 G" p8 F4 v) i+ [/ K! b5 d ? Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 v9 C9 A2 ]7 Z* f5 e8 {( m}
- D0 {8 D) o J) k; D' J, N! L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & g/ ]: t! ?6 i
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