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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 Y h2 v- C( V: y7 a7 p
input mcasp_ahclkx,
8 z( H/ r" M+ Y4 c: rinput mcasp_aclkx,0 x1 \: P) y2 h. b% N |! \
input axr0,
2 b/ F* X: s9 V0 S; |. }' ~* P: l/ S! H2 D. }3 Z5 G
output mcasp_afsr,; \7 a: O* ]' }8 Z' B
output mcasp_ahclkr,3 o* F) s% O2 q$ C
output mcasp_aclkr,
7 J; T: S) D3 Y; J4 @' ]* b" `output axr1,
& S7 G& X8 `* _: s assign mcasp_afsr = mcasp_afsx;
6 e- I9 n' T7 v+ ]) Passign mcasp_aclkr = mcasp_aclkx;' x+ d! h9 |2 a* w0 e' d% F! R& a! ]
assign mcasp_ahclkr = mcasp_ahclkx;" q3 [! f! X) K2 N n8 K
assign axr1 = axr0; 2 e1 L P4 F+ j% V, B- I; I
% i M0 P% i- W: l. @4 E) M" O/ G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- ^ K- Q; S8 v/ I( S& l& I" xstatic void McASPI2SConfigure(void)
1 V! R: M; J1 A- Y{, c9 `* q% K! t) ]1 y! o) h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" W3 ?. S e8 o6 Q% ]9 V8 v! {: m6 I7 T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% m. h2 @# l3 g9 rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 N E5 b7 z5 g- g$ r& G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, h% s4 `, p! r7 { p1 P4 f7 \$ e8 k! x) \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 A' `* l* B, S# g* B* F, }
MCASP_RX_MODE_DMA);
" b/ ^% s; X IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 r, f; ~" ` X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! n5 J: ^! f5 C' p0 C P9 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . n D: l# V# y/ R& t/ D; M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 y4 c; F. n2 }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( x6 C3 ^ E6 }2 w) }0 Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 P: k7 z8 N' O, ^7 jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' t2 t& G+ } j2 C6 cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - T0 d/ h0 Q" }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# _0 H3 t3 W0 f h$ @0x00, 0xFF); /* configure the clock for transmitter */9 ^8 r4 |. k4 ^5 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 _& D: H/ j* m! w# Z$ t* P, kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 ?$ K1 Z7 L- k9 I: k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! d7 Y$ _* z4 S7 W3 {1 \; x2 ^* q0x00, 0xFF);! F; P9 P+ G, J) R* K( j6 g
" ~( O0 X8 S% B* c/* Enable synchronization of RX and TX sections */
2 S5 Z9 h2 W% K1 l# Q$ h/ u8 T) UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 h4 x$ Q& C4 e% q3 c/ gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 r/ H2 b, [' p! A9 e" T; xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 t* H' t0 A* E0 A** Set the serializers, Currently only one serializer is set as
: s, [3 y% S! Y6 [. ~/ I1 ^; ^** transmitter and one serializer as receiver.
/ a# }0 e3 `+ Z- r; A+ I G" D; ^/ V*/
0 s# A( r3 m# s8 K g1 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ @' f# `2 r# l+ [! @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 |( d! `, N) ?) Z) J+ N6 [; k** Configure the McASP pins 1 w" O' z$ f# }& `. H0 C
** Input - Frame Sync, Clock and Serializer Rx/ }% ]5 E) f4 J) f- b4 r* l: J8 @
** Output - Serializer Tx is connected to the input of the codec ; U1 D: `( @3 h
*/7 |9 M" o" \( X" p+ F8 A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& }5 A% p) f: a- h5 Q; o# fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% y( Y7 U, W. s; ^6 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' Z+ F2 i6 Q' T! K1 {, k+ q: k7 j0 \| MCASP_PIN_ACLKX, g& l; M% w. Z0 X6 z
| MCASP_PIN_AHCLKX
2 O5 O8 p& N" P$ h% Q# j1 f. u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( A8 ~' F; L/ @- pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) P: [& P, P) ]; o: ] {% y| MCASP_TX_CLKFAIL
- P* V! f+ ~) ]/ \$ z# l3 L8 D| MCASP_TX_SYNCERROR8 `6 t" L" b1 d( {* U# U: D% |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' N; f3 Q8 r2 O
| MCASP_RX_CLKFAIL k) A2 x' X! @; y5 v2 @: W5 _7 R
| MCASP_RX_SYNCERROR
4 D* f+ q! P E- G7 q) `9 K2 h) s( x| MCASP_RX_OVERRUN);
* z6 E. r: r3 f7 }9 A1 F f& B} static void I2SDataTxRxActivate(void)- p# i6 e- ]( g# m
{
7 W, V1 Q h6 y+ S7 e# O% C/* Start the clocks */
, {, L( K1 i PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 O" w1 I/ J2 j. {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 ?' z; ^/ D: a- B% B$ f2 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) K$ ~; c# p1 p3 D( u( d, Q
EDMA3_TRIG_MODE_EVENT);
* {) O& x) s6 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# b5 c$ W$ p' ]8 }* N, FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 N( j# D$ P5 o6 y j, m6 P0 }, iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; T8 I. i1 R$ U& s3 q( G X0 z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# s$ t9 s( U; k" d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 p7 H9 a! M% R v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) c! R0 e/ j" D" l( T; q" d3 M+ C) X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 S; l. [ ~: o8 N}
8 _7 _. _6 O* K. ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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