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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, T% \, a% U% a' @6 R
input mcasp_ahclkx,
% T9 H/ t2 i, finput mcasp_aclkx,
2 b/ [1 `4 ^$ A- W0 iinput axr0,) x4 i. C; g+ d/ J$ m1 N
/ J, T% b6 R+ E2 ^6 r9 Aoutput mcasp_afsr,: G0 a" ~1 d8 b
output mcasp_ahclkr,2 J- U. ^: F d5 N# R* Q( g
output mcasp_aclkr,
" d, R- M9 D* G# o4 c" y0 `5 Coutput axr1,' H' E# d" q3 y, I# P6 [
assign mcasp_afsr = mcasp_afsx;
; v$ j6 V; o9 u( z3 U4 N- A& S6 ^. eassign mcasp_aclkr = mcasp_aclkx; ?9 Z, {2 [, i9 s+ S6 X Q
assign mcasp_ahclkr = mcasp_ahclkx;7 l5 Z; {1 U7 a# s$ q! b
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - k7 \, A0 K; X, W) F) H( G
static void McASPI2SConfigure(void)
! `' v i* R1 z# _$ K{* P/ {* V Y }6 v" s1 ?2 U3 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* S/ h* l5 W7 p: q0 @1 V! b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 T% A5 W4 ^- z( QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! ?# j0 R0 |! g; qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; I0 _1 h: n! I' r- ?- [; E4 aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 h1 I' F& U3 \' J1 b
MCASP_RX_MODE_DMA);# Q- [* k/ M: M4 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
h P5 s5 O9 u8 l! m( J5 ~+ vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# k* r/ `! T4 Q8 k: F9 K3 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 A6 O. T# f* o, [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 I: y6 {& \0 o4 t/ r, |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : V! m0 N8 ^1 s8 p7 E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. m# K G6 o( l1 W6 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. P2 I* b0 X) T+ y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 z3 ?8 t: z2 S- R8 J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# j2 g: y9 V; E6 h' I0x00, 0xFF); /* configure the clock for transmitter */
. X4 N. S1 L8 L$ P: |2 N' pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' A; X$ J H. {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 g5 J2 r+ |; j1 o6 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 N* Q8 \; y7 T }8 `# G& _0x00, 0xFF);1 h; ]$ _6 x: S" S# w& p' v
$ d1 X9 c& a D, P, h% h9 e9 `+ n
/* Enable synchronization of RX and TX sections */ ' l( b# U* u9 h: V& {2 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! I6 }+ C/ I7 S) PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" r% C- \: |# z; J8 |7 ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ a8 z5 F* }/ ?" _** Set the serializers, Currently only one serializer is set as; O8 f7 j. f q1 x
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. E! K0 p: x3 Q$ ]% o/ I. O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; ]) y9 [ g! E* @2 p/ V** Configure the McASP pins
0 F! {$ i( P5 x9 b9 J** Input - Frame Sync, Clock and Serializer Rx
/ N- H2 O) P& M. |) q$ O** Output - Serializer Tx is connected to the input of the codec 9 {& E) w. O! H- r
*/
- V9 Q3 s+ J4 `& B) `4 _! l0 D" ?0 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% N3 }: U5 x- BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ R9 \. e# a' v/ |) A# r3 o. OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; K& l3 | D. }# P! g
| MCASP_PIN_ACLKX: k! P% u* e4 l8 u/ T( ]" s3 I
| MCASP_PIN_AHCLKX& s+ r4 d) _5 O) \' E+ B) _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. i5 P+ ^7 C' H iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 x/ n. u5 d& B+ f2 S' E/ c# Y
| MCASP_TX_CLKFAIL
, t- r9 D$ j- V% m- _) e; p| MCASP_TX_SYNCERROR
, o! k# Y3 b2 J u, E5 E0 ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 o9 K3 ^* W8 W. T# C
| MCASP_RX_CLKFAIL% l7 N; S6 N' D& p# R
| MCASP_RX_SYNCERROR
( b* t" z$ h, X( E1 J" k| MCASP_RX_OVERRUN);
8 I( R9 \2 H' S. o" d) V} static void I2SDataTxRxActivate(void)/ S4 c6 v8 Q/ T8 _7 S8 X
{0 ]5 p& K5 f! i/ D, [9 F
/* Start the clocks */
8 k* e5 k5 c2 ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 O8 w4 y' E- a5 a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 m$ P6 y f$ h& L0 L0 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- b7 b% m! O9 G9 U* a! o, F4 u
EDMA3_TRIG_MODE_EVENT);
( ~# Q, x% F j% w9 y% @# ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; x. q. c: D; b) M2 S: c/ m4 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ _3 p: _/ B2 e* X. j! i" m: ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ m4 j/ R6 {& P3 I9 p/ N C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. {! C2 S5 h8 ~0 y3 V( Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' i+ p m( ]" X' }- H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ Y' p. M" A$ G8 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 d! J, C9 X+ S) G- [
} - J9 O0 h W1 A) h' E9 A8 g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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