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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% `6 q: W6 f9 _3 Z- \, k: Linput mcasp_ahclkx,9 m1 L: |0 W5 d$ { a
input mcasp_aclkx,! T4 s2 W- t+ m; [! U
input axr0,) z; Z, {& i1 U* F. w# n. ?
. d9 I, A6 u" x. } f6 Z+ |6 moutput mcasp_afsr,
~# K, G; D i7 _& w a4 Ooutput mcasp_ahclkr,) g% h6 C& L# }8 e; _
output mcasp_aclkr,& V/ H, q5 U5 X1 q
output axr1,
' O9 D; _* h) t% D1 h2 g assign mcasp_afsr = mcasp_afsx;
" {6 O! x! X) c, f h! x% P* ?assign mcasp_aclkr = mcasp_aclkx;
% ~) }6 H& h, I7 h2 b9 g% Aassign mcasp_ahclkr = mcasp_ahclkx;
& B( o7 I7 h! m' o% g4 E, b* @assign axr1 = axr0;
) t- ]( |! _; b, Q' V* x# ]% c# h; Y) h2 |: Q' i4 h' w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# t* b# X2 S( n istatic void McASPI2SConfigure(void)
' w" g1 H3 H" X8 Q/ X{3 f3 Q I' k5 W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ O% d, \0 W% Y. k6 G# L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// ?- E. r7 L2 [" M9 n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ [3 \$ _( r; C" Z; X) H Y2 u; U5 \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' ?% b1 J4 q! R( G: V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, x, e$ g, y2 G. m# L
MCASP_RX_MODE_DMA);
- x$ v3 n3 p" w# q( AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' X8 _9 j& L" z& n) P/ VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! I/ r5 `, C( p1 S4 R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( K! V. I" @" PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 U D |# n# n: b$ k5 ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" l' }( |1 M2 ^, Z" M& aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& s# N$ Q8 l& k2 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 l, |# E, ~5 h$ `8 e7 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- S4 |6 m1 J7 @) {/ D ?4 @6 ]; pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 h+ R* T' \0 Y2 M0x00, 0xFF); /* configure the clock for transmitter */+ r! k8 f" a( Z6 S8 W' Y4 w5 a+ W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 D8 P& F* N1 {9 A* E( ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + @7 C9 k& h$ v4 w7 F; W" M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ U% h/ C4 l# N" O0 m
0x00, 0xFF);3 e4 N) a. B3 U. Z- Z. E
! d0 n+ r. x5 E: X& o
/* Enable synchronization of RX and TX sections */
2 N4 ^2 F3 E7 o2 |, ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% N; K3 G% E8 ^$ O/ T. B) J' w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 \8 h8 N8 M# K( n8 Y( W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! L# K+ j: L% \ `. a** Set the serializers, Currently only one serializer is set as
2 ^1 \1 F" ]3 W t2 X** transmitter and one serializer as receiver.! p8 @' ?" i% T5 y: G% c
*/
! i |3 j: ]) ?9 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 N1 B1 [# h( t& H! E% O0 f7 X+ hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ d3 N% t' C% A: b0 `** Configure the McASP pins
% ^( X1 c2 L9 c5 C- t** Input - Frame Sync, Clock and Serializer Rx( |" n4 _$ h8 ^" v. _, [; i
** Output - Serializer Tx is connected to the input of the codec 1 a2 h2 s2 r0 T" Q# C
*/
# N' X7 @ b# iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) b" d! M3 z. T I5 S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: O7 E+ k }; ]. V1 c' ] O2 \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ o6 V$ n h' _2 m4 ]4 X
| MCASP_PIN_ACLKX' E6 C# u' S0 j
| MCASP_PIN_AHCLKX& Y2 ? B2 ^. x+ G" |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" C( _' r0 N7 E2 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- w8 s9 Y7 ~# f; g+ ]1 d| MCASP_TX_CLKFAIL : ?$ V% F% \6 {8 U
| MCASP_TX_SYNCERROR6 P% {& d- v; e% A q: B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 m- A2 ^/ |" }0 g. o" k. ]* l| MCASP_RX_CLKFAIL
0 X7 }& x$ U4 w( e| MCASP_RX_SYNCERROR ) F, w, @8 ~- [% `4 P' c' F" t/ G: E- v
| MCASP_RX_OVERRUN);
7 F* S9 @& b+ n} static void I2SDataTxRxActivate(void)% [ Q. C0 l! C7 y% N' p
{
9 r0 _4 J3 m- A$ D8 v' h/* Start the clocks */
) X- H7 {4 K( J! e: ~$ gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, a8 m4 c# {* A8 }' `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% D: } ^& F* d/ sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- T6 a9 }: u) b, g; G& |$ @EDMA3_TRIG_MODE_EVENT);9 }+ p0 b" m( ~& C9 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
R8 f9 H- f4 w- V1 w5 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- t! m& L& r$ w; Q$ v* _' bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* J Z! p/ C+ f ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 Z$ ]1 u. e G6 b4 v/ J' O8 L* e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* y( h1 s. P3 @0 [$ B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
a% X7 h' {1 X& q/ nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 [7 W& {! G9 N4 q% Z: H; O}
& K1 ^1 D2 Y* W$ x+ J+ X# M6 @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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