|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 K! L$ H9 \/ `0 b2 sinput mcasp_ahclkx,: j% E! K; \- s- l7 D' I* w( t
input mcasp_aclkx,
: [$ m: O5 e3 x8 ] finput axr0,1 Z! e0 ?' B9 |3 ] O
- x/ Z7 s8 e, A9 _* Y# G" z
output mcasp_afsr,% J" {& T7 F/ X5 s1 x9 f) t' P# Y% b
output mcasp_ahclkr,
( E R& C9 t; `) s; \( doutput mcasp_aclkr,$ L% {' k$ L* z. b
output axr1,
2 G/ @ h0 l5 Z5 s assign mcasp_afsr = mcasp_afsx;8 A2 C" i5 _* [( l0 t" j3 u- Y
assign mcasp_aclkr = mcasp_aclkx;9 |* b( I& A+ s5 V( u" z
assign mcasp_ahclkr = mcasp_ahclkx; H$ M" _/ Q. X* X* h
assign axr1 = axr0; 6 b1 N; R4 U: G
0 M7 {+ P Q5 `& F- k5 c0 Q$ R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; x1 O) }, Z* h( L, s, Y
static void McASPI2SConfigure(void)7 M+ t! u8 d& Y/ |, W3 H+ v
{ h$ t. V: y0 b, u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! ?( p1 t% i$ ]3 }% P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! A, }- g- }6 `' |- I1 b1 R2 t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 D/ ?* |3 C# r D. P g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" _. y- W1 F, v+ S$ c% x) DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! K! \1 W' v3 P0 U6 V, UMCASP_RX_MODE_DMA);
, @# ]5 `5 x8 d# s' l1 Y: TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
?+ ?! f' E4 ]1 _2 f. e( [- NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ L: a. z5 a: S/ M7 a5 ^9 u) ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 D l1 F; ]. G- q* ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 q7 n& o, d* s5 M% D+ pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ _0 Z! o1 u' C3 Q! NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// ]4 z4 {5 j; g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& o5 j" k0 G/ A+ t$ }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% e0 n# e9 `" p( p6 o9 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( L/ J, l0 K1 q4 W0x00, 0xFF); /* configure the clock for transmitter */
0 @9 D9 g( H+ t# M( J+ ?! C$ {$ YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, M6 B) @3 P* v) yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . e; I6 e1 k$ I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ p& p/ r: f% R, D& \( Q0x00, 0xFF);0 n% F; n B6 s
. t9 e0 b) L! O! n" F4 k
/* Enable synchronization of RX and TX sections */ , G# X" u$ a S7 L# m8 H/ e3 K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 Q2 {6 [& B3 T# s# ~. {) S: z: a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- K$ y' }* u; R. BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" ^& w, e' z1 k3 a; |& v
** Set the serializers, Currently only one serializer is set as# N. m. d7 w. \( N9 r5 w' ~+ N
** transmitter and one serializer as receiver. R" ?4 ~% |7 R6 H; h ]
*/
7 F* c F" g, [& w7 l+ G6 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, u3 N" b1 |* ]$ l# Z" e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% G- E" U" `& T4 y9 ?** Configure the McASP pins
7 W; S) }8 w- {& l( w** Input - Frame Sync, Clock and Serializer Rx
5 w8 I: v3 [% W3 I5 R( b** Output - Serializer Tx is connected to the input of the codec
T4 j% [( s& e a% x/ s*/
( O3 j- |" ~$ `4 U* y. Y2 j7 G, bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 k" a/ {9 z0 `+ N @& H- j* s2 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# G3 L( T6 ?. S8 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 d, Q) F6 t( m# A9 n5 g) L) }| MCASP_PIN_ACLKX$ W' U- D* [) V1 P2 b& S
| MCASP_PIN_AHCLKX
9 E" L' R2 m4 I c+ H ]1 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# J$ s1 M2 F( ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - x0 L/ p9 t+ w7 [2 |& T3 l
| MCASP_TX_CLKFAIL
% ~+ p$ f9 |- q| MCASP_TX_SYNCERROR
% [8 C, p2 H, F# v: h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - t( W% ` h. Y# n4 n1 c) v
| MCASP_RX_CLKFAIL
$ v% P4 j0 [* p7 x# p f6 U| MCASP_RX_SYNCERROR ) z/ B5 N5 L3 c# f0 S
| MCASP_RX_OVERRUN);
+ e3 v) U" I) x4 Z5 V5 h, V5 E} static void I2SDataTxRxActivate(void)4 G% [$ H8 B! _6 u+ Y/ d
{
( V9 @- j6 A3 ?3 m0 J/* Start the clocks */! p) E0 }% P, V' o* d5 E: ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 o& j% z- o/ [' M o3 H g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% f# b4 T9 S, a/ w2 F" o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 s1 @7 ~, K8 \- L% M& M
EDMA3_TRIG_MODE_EVENT);0 ^+ e1 `: F1 V/ b+ ~* X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 d* u$ H: _: F' M# V9 \+ H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: a) }# h _/ N3 L% r9 H5 M% k YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* K _ Z, o! Q) n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! l9 K ~: e D* t* H, ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 X2 q; S E; C% L' _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 W3 N+ b" o2 HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ K+ h, y# X [1 I/ X( I0 ^6 ?$ l}
% W9 t5 K; _3 c/ n Z& q( V$ {/ H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- m" Y6 {" ]' ~9 t9 j0 g |