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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) P8 J3 H$ \ v) c1 w
input mcasp_ahclkx,
1 ]; ?9 z+ m9 h+ i, M8 {input mcasp_aclkx,
$ e6 T5 z# j( Z4 ^- ?5 Q. e; k: rinput axr0,# f0 I1 Q7 t2 f: ^6 ?( [. z: r! H
/ N2 a6 C6 y( b* }0 V7 G* A* Routput mcasp_afsr,
' g( a, A* a6 Boutput mcasp_ahclkr,/ T. V( U2 \; s( r3 N1 ^8 i9 I
output mcasp_aclkr,8 f. X4 t& c8 ]
output axr1,% K3 H* v$ P; ^3 L6 s, W, G6 l& S
assign mcasp_afsr = mcasp_afsx;
5 y! N- @ j5 S% Z! Eassign mcasp_aclkr = mcasp_aclkx;
, R" a$ h5 Y; Y/ _& massign mcasp_ahclkr = mcasp_ahclkx;
& E8 z. U: \& ?4 e7 Aassign axr1 = axr0;
& r# L. z8 M, o+ ?$ l) F8 L# b
0 H: }0 h5 }7 N7 s) T0 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 P5 x l4 [' a% h9 ?& ~( G, nstatic void McASPI2SConfigure(void)+ f/ ^, e! {" P9 i; f& M" M6 ]
{# B5 k! |' ~( I9 Z" v+ T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: [) W. I7 }- [: F: |* {8 v! v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 x( s6 r# {( x9 `1 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 r' A4 r" V, O+ K; y2 f1 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 W8 p0 m; |) G+ hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 b) Q7 n. U$ D! K- r3 Z# C1 r
MCASP_RX_MODE_DMA);
/ J+ N! P% a# m4 X! h( _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# c) O' ^8 ?+ U5 j8 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
k+ K" Y q, {4 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # A0 C5 b0 [- w7 r0 F: X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
c; z( D0 e. t$ ?. \0 H6 {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: S5 \2 v* j( `( k4 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ \; Z( n) R7 N' e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 c/ Q' ~# h8 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, l9 x& i, l$ ?% ~& c% RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 ~ }: \' o8 [4 s* z8 y0x00, 0xFF); /* configure the clock for transmitter */# @4 T# g2 K) G: c4 j8 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 ~4 n5 h& w* F* [/ G/ f# |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . p/ F; T% Q* S) y8 G+ I, M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ O( W6 K* c) p6 O. N: B5 A
0x00, 0xFF); G1 r. M% o# I: `; o
/ y( J+ `8 p# Q8 D0 D4 L* |# J/* Enable synchronization of RX and TX sections */ - K/ Y; M' w( ]7 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 g; j+ O' p; a7 ?7 }; P& X' J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! ~9 x) Z% u- } q; h9 S: ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 n3 G; I5 m$ t6 [** Set the serializers, Currently only one serializer is set as+ H. E4 n* n9 N* _
** transmitter and one serializer as receiver.1 V& l& ^, n, u' f$ n) U. a: M
*/
, z5 f @- M0 l! W+ HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' p7 L" J- H* o; M( B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 j- J# g5 [2 z6 m+ p3 ^** Configure the McASP pins : {# Q& N+ l Y2 G( X4 I$ [
** Input - Frame Sync, Clock and Serializer Rx
K0 m- D' r( A$ Y+ i** Output - Serializer Tx is connected to the input of the codec
* L* I' \' c5 |* k" c* o. p; B8 |' ~*/+ N z3 [5 Y# `# K3 U/ k7 m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( R; V! k7 p3 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! _# ?% r% C# X7 _9 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ N" L! ?3 } N8 d' _" a' S
| MCASP_PIN_ACLKX
5 \4 l* O) h8 s| MCASP_PIN_AHCLKX
! ^$ O2 d$ L' F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ A& g% D# f( A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 B) J" X2 r$ E* D+ X W9 y| MCASP_TX_CLKFAIL 6 @/ u* N* Z; v% @
| MCASP_TX_SYNCERROR$ I) x3 E1 E# c' \. Q5 \& K* J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 W% c8 e$ W/ a- ~
| MCASP_RX_CLKFAIL
4 d" v& H+ O' X L3 i| MCASP_RX_SYNCERROR & m0 s5 y! N: a, W+ e3 I
| MCASP_RX_OVERRUN);
7 _9 t7 c& R8 }3 L$ o) B# P} static void I2SDataTxRxActivate(void)
1 p2 q) L: d0 [$ U{7 H( m( u5 F/ s0 T
/* Start the clocks */
; f; s# V& Q0 h9 \ T" J! i7 M, zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( U F# |2 ~ Y% z* O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 Q. w$ ^' l* o' F0 D4 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 i% H3 w6 e+ ^: b- x# }1 CEDMA3_TRIG_MODE_EVENT);
, W2 R! F: y- ], _* @6 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% E) C" \% `4 D) [4 F3 n, uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 |) a3 L, G; w- b& b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' W" w- C6 @$ C3 c$ c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 ~! W7 O; T$ _7 H0 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 T* i& j+ o% h6 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 }' c8 {1 |- J( R* p: I/ D+ t0 zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! r: b( R4 N. Z5 ^; N) D
}
+ i. ^- W9 i! h I# H0 p% b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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