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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) P( V2 j; F: {+ c! n; C
input mcasp_ahclkx,+ u9 l& A5 P! i
input mcasp_aclkx,3 ]7 i" ?, Z8 o
input axr0,: h+ }; { i( q3 S6 J- h0 Z
% ]! G; C2 e8 L+ ^6 \# ]output mcasp_afsr,
2 M1 w9 ^8 X: J) ?- S1 Qoutput mcasp_ahclkr,$ m6 N! t2 K/ z p8 D6 p- S* v
output mcasp_aclkr,
% f* g* h, }* Houtput axr1,
9 X2 e3 J. b$ J- f2 A) r, h assign mcasp_afsr = mcasp_afsx;) f4 n! E( H( ]: Y6 \8 j6 E* |
assign mcasp_aclkr = mcasp_aclkx;" R- c$ z2 b* S# s3 k; l' j
assign mcasp_ahclkr = mcasp_ahclkx;
$ R' R. ?0 ~9 T6 h! b1 Iassign axr1 = axr0;
/ k# l) m0 {5 R& C8 u- ^; G4 t7 F1 s5 P$ y5 ?( P: B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 Y; A5 U# |1 y- O) r; b2 R& }static void McASPI2SConfigure(void)! f7 P" h/ ~' o
{& H, _+ r6 E% ?. r" ~0 g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 v9 h, m$ i: [' t P+ b7 E1 T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ U" u( r9 z$ U+ L5 h8 Q4 h6 v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 T3 ?3 j6 W5 U, r; ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( S" L/ v, }- `/ u& q5 [9 i7 a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. H/ y2 x' s0 BMCASP_RX_MODE_DMA);
2 W U3 u, |; r3 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 t I$ E& L: i' gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 q; E G8 J* X1 s' {6 s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" S) A5 X1 N9 D2 w6 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 Z I6 e Y; t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 ?. E; K7 x: h$ o) G2 u8 b! ^4 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& O& y3 I" n" _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* v9 U9 v( |% E6 U8 ?1 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 z: Z, b5 s$ U2 \7 c8 p' N2 W: lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: x; N2 O- D) c+ T0 N$ L
0x00, 0xFF); /* configure the clock for transmitter */1 Q2 g2 {& _3 T8 v$ J8 l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 ` Y! a, |2 o/ l$ [! B3 oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# M) ~! h5 s. C! y M2 nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," z4 c+ A0 T5 z1 v- L0 c
0x00, 0xFF);& m$ i6 y5 u/ H: _* P; Y
8 \1 E4 v3 k. X8 _4 I' S/* Enable synchronization of RX and TX sections */
7 k J3 p! n L/ TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" R' ~( s/ m8 M- f8 p* m4 V7 E$ _) bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 Z1 T0 J8 c6 V2 M" R# Y9 H3 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# x6 E' q7 u; m8 @# ]' p
** Set the serializers, Currently only one serializer is set as
7 N7 S$ k; n( \! O** transmitter and one serializer as receiver.% u) A1 x3 Z# p* R$ @% p b+ K
*/
4 m1 q! }0 y7 \0 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& k% y' M' t8 BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& G0 [8 X" l3 C
** Configure the McASP pins
" G. ?2 f& H' B+ o** Input - Frame Sync, Clock and Serializer Rx5 j3 {- f& a" w: o
** Output - Serializer Tx is connected to the input of the codec ! i8 V) ^/ D7 Q4 A
*/5 Z0 ^1 {; Y# j8 D P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 f9 `( J& y" [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: a* u2 |8 s- A. H( u3 N3 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ U7 M" g! F& P4 ~6 _1 f| MCASP_PIN_ACLKX. E" A v: @8 X# z3 Y6 U& z6 S6 U: r
| MCASP_PIN_AHCLKX
p- t$ [- w2 O; V: W& ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# o' _/ C& k8 q" f" e4 y( k6 ?& Y/ B; SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & p1 I' L# ~/ A+ A( d* ^; D b
| MCASP_TX_CLKFAIL
+ E2 W: G% w" F! N| MCASP_TX_SYNCERROR
+ `7 a( i5 g6 m. z$ l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - y5 E* O( _& \ W( ^" N
| MCASP_RX_CLKFAIL
7 }( Y( A7 L5 {/ l V0 c| MCASP_RX_SYNCERROR K3 R4 h1 B* j: s$ b$ W G; }& i) Y
| MCASP_RX_OVERRUN);
4 r4 C) N& I6 G9 i# ^8 Q} static void I2SDataTxRxActivate(void)- l( y- W6 ?0 ]- h( V
{
4 A1 h' G0 W0 ] |/* Start the clocks */
* \2 D, ^ Q" ?8 `. {, KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( }* C2 ~7 h9 X( {! ?* k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 I% \3 j" U% g0 e; w" F5 x& g8 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" O Z4 I2 l8 | n0 CEDMA3_TRIG_MODE_EVENT);
9 h9 J3 e& `9 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 X" N0 [ l; @& b& G1 A" R x2 DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( ]8 t5 v8 A5 F5 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ n- n" Z2 L3 {& K- n+ ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) @1 z8 x+ U/ Y8 |8 R8 Z% kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 `- N' C4 x! z* R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 k, S" V9 ]: [+ }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) P6 t, O( h5 `" D2 {}
U! v7 ~% Z% q/ v7 y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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