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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# l: ]" y& i1 d* j& ~( Q9 _input mcasp_ahclkx,
C- J9 g, ? {+ l+ G+ ?4 Ninput mcasp_aclkx,9 H+ x P% r, X' b* b( U
input axr0,1 D( h3 S5 l" r( ^. u! H
$ z+ S ]1 K" A9 u/ |3 m6 `output mcasp_afsr,
" l8 f/ P& C: k$ G- ?output mcasp_ahclkr,
: ]! i# C- w. v) g" H( o8 Z, Houtput mcasp_aclkr,, X5 }' v0 l( J g3 L3 b" f
output axr1,
. R6 n) O7 I! m! z assign mcasp_afsr = mcasp_afsx;# T" x! A$ U) b6 {+ z
assign mcasp_aclkr = mcasp_aclkx;. E) R9 R6 [" _( U. T* c2 e
assign mcasp_ahclkr = mcasp_ahclkx;" c8 x4 f8 y) E& G/ S7 _0 i
assign axr1 = axr0; & c3 r5 x3 j3 ?( `
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) T0 F' k: O/ s( s+ h. _+ r% |2 p. sstatic void McASPI2SConfigure(void)" m! k; F7 f* B
{8 _9 @ n* U( g' C: w* y8 S3 A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- W& F* E( ^* K, @; z, k \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 K2 k! m/ W) A4 H" P0 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 M- q) T5 D3 u0 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# T- |/ g, w, W4 M! z0 EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% f) X5 B2 c. g& N4 `
MCASP_RX_MODE_DMA);
; w# Y" R3 G. X8 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ y1 l1 A8 K; t! m4 m g9 T/ a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 p% o4 |4 g9 W$ B* P/ u/ {, DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 m7 b9 K6 R5 P: R, fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 [5 [ x" p p! A9 n' g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 n* a9 F) O/ m8 o3 G8 {* C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 z: A8 A& @/ u; N' q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; r* R7 E2 P: k) F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ P0 [+ R; i( t, s5 m) F* i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, M( I) f/ J9 h3 u- Y6 l
0x00, 0xFF); /* configure the clock for transmitter */
W) S7 S9 c G) `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- v% p8 Q1 B3 {9 A) p( I& i6 C$ ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( [; K4 E" S- @2 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, p! L- g/ ~7 \
0x00, 0xFF);4 Z: W) I6 q& F" h
6 x I: Y, T& [) M8 T/* Enable synchronization of RX and TX sections */ ) M2 x0 Z1 {& ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( P" ?" \# d5 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* _9 Y, U# w: T/ o) ~: ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: E: c* b* u- w' U2 n** Set the serializers, Currently only one serializer is set as
/ N# V0 S2 M& s' A* b+ z8 j# D+ W** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
x, @4 y7 }" A9 b9 P2 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% [0 s9 j0 \7 P$ x* S9 N** Configure the McASP pins 7 l1 \ G! N3 q: \* ? j9 O
** Input - Frame Sync, Clock and Serializer Rx: ^! p' z3 _- h
** Output - Serializer Tx is connected to the input of the codec
9 Z. t R @0 i6 a*/
- D2 n$ u8 Z4 z9 AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# b( z8 c0 o; x* o+ Y( ?7 P9 j: l2 iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 g. t% ?' t- Q; {8 _0 N0 C) QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 r+ X4 \. m& ^! h| MCASP_PIN_ACLKX
! S7 C+ A% }- R/ Y9 n- u| MCASP_PIN_AHCLKX
4 u; ]( v/ M0 _) k3 m1 |8 C7 u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 ]% N+ S- B3 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; g$ y: L# q0 ]" {2 X' g
| MCASP_TX_CLKFAIL
! y& t9 I2 h+ Y) b& l7 z| MCASP_TX_SYNCERROR
5 t+ K: [/ ?2 C+ K3 H; L. F1 x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* J; M5 e6 J+ C- D. p _+ A| MCASP_RX_CLKFAIL
- `" ^* M: T D/ o| MCASP_RX_SYNCERROR , v/ } @ U+ `! f2 I$ v6 N
| MCASP_RX_OVERRUN);/ N+ w) {5 p: q. O
} static void I2SDataTxRxActivate(void)
7 j) f4 r+ @3 R5 u{
; k2 ?. A: @, m" N/* Start the clocks */
6 @/ k# }, f- g: V3 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 p' j4 k5 H- o" v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ z) U/ u* q; V8 g0 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# j2 O, o' N/ z h! }- T- r0 b
EDMA3_TRIG_MODE_EVENT);# j) F5 b( p; ~) x( Y- G9 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- G. p" K* n. G2 j# X: \/ `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& T n' g; V! l4 Q0 Z9 u/ I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; s9 e( a' O" ^# p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// E5 I6 i. V. e3 J4 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# Q9 Y% g: ]; f, m3 F+ c+ X6 z% MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 u( K. ~0 i0 c/ t! [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% @/ H6 l- _0 y/ c/ Z, G6 }}
) d q7 D/ |, a) e `: ]- b' _2 U$ ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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