|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; v: @& p. C/ @/ n$ uinput mcasp_ahclkx,# l8 l \* E2 N* o( T" f: Z# K
input mcasp_aclkx,5 N' I1 v8 O: c2 O$ l2 Z
input axr0,( E( I$ ]! w% }. z# ` C# K+ d
- |) I( t2 d0 G% |0 p) f4 }4 C. H
output mcasp_afsr,. Z5 h& r. K6 R# ~4 x6 G: H
output mcasp_ahclkr,
3 U4 A- |5 i# F* Z2 ]1 Houtput mcasp_aclkr,. E- m( I* v6 k) x4 s
output axr1,/ }4 s3 I1 B2 j3 J& w
assign mcasp_afsr = mcasp_afsx;
) a4 I( t! J. [% aassign mcasp_aclkr = mcasp_aclkx;# X6 `$ o8 p; t6 x: m, w) t# {) h
assign mcasp_ahclkr = mcasp_ahclkx;
8 \. n+ ]9 m% [assign axr1 = axr0; / O7 V3 i% v7 h* o, k
, q1 y' r8 l* z$ m2 q* _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 ?( V; k, b& Q" E5 I
static void McASPI2SConfigure(void)
( v$ ]' ^* s/ N{: R# L+ p; z6 M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" x; C. J7 w- k3 E3 f+ @% H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 P% a+ x! ^# d, `3 [: q8 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 c t7 p D2 z$ l; R' b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; [5 c% w5 K8 q7 `* ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) e" x, s% p/ k8 A/ @4 uMCASP_RX_MODE_DMA);
/ c% {. F- Y3 |; c1 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. N2 V" Q+ k) d D6 m8 n @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. D8 @* W& _9 \; u% Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * Z3 n5 i! p( {* M* l9 j8 C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, y+ v/ j! N! v8 v4 a# h, D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 t9 R* Z4 N9 v7 {" \$ X- y% IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' A" V0 |2 X4 e# b) f# Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ L% `+ w, m7 B, t6 S4 f+ l( p* q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 C* u3 R: U( s z- k4 B, eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 N5 V1 K3 l% a- Y6 W$ U0x00, 0xFF); /* configure the clock for transmitter */
8 f1 c6 I# h) uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% f: n0 d4 G8 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' Y8 ~8 U, v6 k5 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 ]9 t, \- m7 I$ \! ?6 b/ O
0x00, 0xFF);
% ?% Q$ A/ k+ i& C) Q5 s: T2 R& a! i2 ^8 Y8 I! h
/* Enable synchronization of RX and TX sections */ / r8 H8 p8 i& R, ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 w8 s9 ?' q* C" q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ J' j$ Z- @: UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 b* c" F( z9 Q3 T4 V: b** Set the serializers, Currently only one serializer is set as
& h; v/ h. b2 d# F! H2 L5 d** transmitter and one serializer as receiver.8 l8 M$ l/ Z% U' k& [
*/1 @0 q! B, A* J9 s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ L4 I* f! f7 ~& ?* L B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. m T6 Y* Q' Q; C( w; M1 `** Configure the McASP pins ' i+ k9 s/ j. n2 ]) q& Q
** Input - Frame Sync, Clock and Serializer Rx
$ _. I1 P4 c' J. L** Output - Serializer Tx is connected to the input of the codec
" s& b# U* D p$ O3 H/ d9 x1 b& t*/( h( b0 j8 t; T9 W3 g E" ?* B1 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- w. T6 ]* ]0 o2 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 y6 |9 r& \- X* {, ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- Z# I2 l/ H1 y| MCASP_PIN_ACLKX
# P$ }* y, E# w x) b| MCASP_PIN_AHCLKX: S4 {4 _ I8 ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 h" h" Q. V. k" I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 c" @/ [0 K$ c( g2 c2 {+ o| MCASP_TX_CLKFAIL
1 K3 X) ^# ], B3 j! H6 I| MCASP_TX_SYNCERROR
9 {& Q/ j8 e' W% L) e4 v3 k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & l: [: D3 f( w7 M
| MCASP_RX_CLKFAIL
' K) V) q6 t$ d| MCASP_RX_SYNCERROR + j2 @% B/ ` ^# h* j4 @0 b
| MCASP_RX_OVERRUN);% X5 i3 P, b6 h- f
} static void I2SDataTxRxActivate(void)
2 O8 \# V" y$ G& a{+ Q/ g1 j" Y7 g; e2 N& R1 Y6 A0 F% F
/* Start the clocks */9 N( y6 O' `' T q$ Z/ }# N3 E: u6 ^1 }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 k2 O- s8 T8 {/ q0 M1 \; i( MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 v& E- T0 Y4 N+ A$ p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, H4 {, w, x$ r2 \" c/ ~# s, }
EDMA3_TRIG_MODE_EVENT);. _. s- l* C# p9 x8 g9 g4 A# Z% W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 q3 v. E: }! n* N; X) b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ R3 O( P" C/ v% l! P" E7 P* ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 g. o% X6 G2 d% u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! C5 ~, m) x1 {( R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* f1 I. b# K: XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% z8 g q6 M4 s6 ^2 n% d( t& J4 r: J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 r3 {# C/ s7 ^2 Z S+ c1 O$ n}
! t; S- M5 [( Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 {, P, E: p2 \ |