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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 C/ {! N# b6 ?& f7 w. u/ B) R
input mcasp_ahclkx,- W0 ]" |) O2 ~2 Y. m
input mcasp_aclkx,
6 }8 Y9 ~- @+ g) q. ?input axr0,
1 a4 l' _, w- q: J. N/ K7 d4 d; i1 X6 a4 f' k, T) X6 \2 c% h
output mcasp_afsr,1 ?9 Q' h8 {' j3 {. @8 l. R X
output mcasp_ahclkr,
( d$ Y, }2 C* n% Poutput mcasp_aclkr," M$ B" G# n C6 P+ J& R
output axr1,
4 A* I z5 d- d X$ E/ k" ?2 S assign mcasp_afsr = mcasp_afsx;
* p: a* G ~- @( \: G, iassign mcasp_aclkr = mcasp_aclkx;
$ V! D5 {% Z; fassign mcasp_ahclkr = mcasp_ahclkx;
6 F( O' d- X6 a* @assign axr1 = axr0; , r- _' L7 O+ S! z) ~! @& J1 ?7 C
/ i1 f- R6 p3 _1 Z( z4 {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ ]4 j0 i) U5 e& C# ` ?6 R3 Q
static void McASPI2SConfigure(void)- N/ G! a) P9 H% \; b6 W) h
{
7 Y0 w" X9 R4 n% z& @ B6 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 s( F7 x) {9 O4 t8 j7 \6 a BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ _0 n# W) s0 P! L1 q# mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 H- Y6 H* K* n0 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
_ e6 _7 Q) b3 gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' A7 T5 w3 g0 S: s! }( _5 eMCASP_RX_MODE_DMA);6 d* C* ?1 g1 r/ u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 N: y7 `/ D- ^# n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: o9 m; U3 S) Y/ z7 A- PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 m; H. @( S3 F) F0 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" P7 a( X" X+ q0 D5 |% S6 ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % q3 d F+ }7 v( a+ |% m3 Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 I4 J. s0 v$ i, W, M. zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 y8 X! [/ X& s% M P/ K2 r4 u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # Z6 u* J# T" V0 v8 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 s# w2 w* I+ j6 ^! x. {0x00, 0xFF); /* configure the clock for transmitter *// |) q! y6 k* y& W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 p- X, R: g4 C% k1 e8 Q) r) W& ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # p1 w7 }% j: v, }1 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. K3 B) O! `, ~( Y" M0x00, 0xFF);
5 b' E$ F# X0 T& a$ h1 l) x( D$ l( ?" Y9 ?* v/ Y, x* K6 |/ X
/* Enable synchronization of RX and TX sections */
3 b- O3 q( X/ p9 f) }) ]0 R3 a5 UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" ^ S: _" O! n+ _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& n, n ~3 [ g7 ?0 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 @1 x& h; Q' T0 g/ X* Q v
** Set the serializers, Currently only one serializer is set as/ w9 A0 ^8 C6 G" D
** transmitter and one serializer as receiver.
/ G) X9 r6 {0 Y; c% d*/
0 J) A2 b# p# k7 Q5 o; k/ LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: t' r) ~ V* i' O; C1 {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 G! b& `# x4 ~* k2 v
** Configure the McASP pins
6 \+ X5 f; y# K3 ? f1 M5 m4 Y l** Input - Frame Sync, Clock and Serializer Rx
/ x9 s, t& E$ v0 P& y** Output - Serializer Tx is connected to the input of the codec . `, H: P4 ]3 x6 t; Y
*/
' a2 G+ m/ y9 c+ _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 ^! d% ^0 `. G) t* c3 O1 K" m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; a9 `/ ]: O' M- }" y# t! w0 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 E6 m. W; u4 L* ?/ o( e| MCASP_PIN_ACLKX
+ L3 c: z' i9 V/ T" F! X| MCASP_PIN_AHCLKX7 w9 r* D$ N$ f3 W9 @0 d* b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% U5 s; r! H4 b+ [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 U J/ [# c0 ~0 f, X. B
| MCASP_TX_CLKFAIL
+ p: F5 H' F |% E| MCASP_TX_SYNCERROR
, {6 {( I* e: a' @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 @* {: z* U# D/ _1 p4 M; Z. a
| MCASP_RX_CLKFAIL1 p! N4 p( a7 d" T9 U. y
| MCASP_RX_SYNCERROR
\3 `) s+ T" s. f) j| MCASP_RX_OVERRUN);
4 W* @1 k" Y( k} static void I2SDataTxRxActivate(void)
( [/ [, u. L, m: `) T{5 Y9 Q t$ t4 o E2 l
/* Start the clocks */0 n( [5 s% Y) @, f# `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; p; k _) h5 y3 Q8 G6 w& {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! C3 a1 y4 d. ~# E. H# h/ y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- }$ F9 _( p, ^( I6 r
EDMA3_TRIG_MODE_EVENT);
* e* H+ f, B) I. v* T$ `. FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' A% p1 A* i1 i6 i/ x: FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- K0 k6 W# w0 j+ o( b) o8 R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 e5 V/ [9 r8 v7 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) g" \( a1 `' v( |' dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ f7 k1 \; \3 z/ d+ E) ^2 zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: |8 n" v! I9 y/ V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 e4 W2 Q" T# R3 }: G}
! k9 C O' S6 u7 A0 b ~5 k6 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # Q1 U6 ^0 E1 h" M; ?
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