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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& t: T) j# g0 x! M' u1 p- ]
input mcasp_ahclkx,3 K; Q+ V1 N* Z. S7 m, I' d
input mcasp_aclkx,
0 O7 t" G$ O4 ?( v2 Tinput axr0,
f9 @7 a/ U5 D: A, B' d" n5 L- z* j( j! I+ B. J" i2 m
output mcasp_afsr,# I5 t- n" q5 \
output mcasp_ahclkr,. h0 d! p% {5 Y* g# [7 }9 {
output mcasp_aclkr,
' U# t6 R9 i: ^output axr1,) J0 P$ W f' n
assign mcasp_afsr = mcasp_afsx;7 g; v# V1 z/ R5 a8 G
assign mcasp_aclkr = mcasp_aclkx;2 m3 k3 [( n9 W% J2 A/ T" E
assign mcasp_ahclkr = mcasp_ahclkx;! W; I/ }9 a8 [0 L& e; M
assign axr1 = axr0; 2 F9 H0 ?8 Q' `- `9 k0 A
. C& u, y: K6 ?- T3 X* u' M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 b& h! r3 _7 b# n( `9 X- S
static void McASPI2SConfigure(void)
1 }! w% ?) X( I8 o! h, d{ R* ^# t+ P. f! u4 j- x/ V/ o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 f4 D A* k5 D8 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, j7 s5 L& g; L* l: M5 O0 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 U) N, H; E! E F& J* C7 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& { K L# }1 c2 A# {8 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ U& Y0 {6 k V' w% s5 WMCASP_RX_MODE_DMA);
, M: X8 T2 {/ u6 h) x7 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 `' I1 \/ C& b! ~. DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- @8 }) _1 v" Z1 H3 Q' B& F% [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 {! g, H( _# M' q& z% O; V+ `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& F9 r# \4 M( Z6 M8 A9 lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - C: E/ b8 }! J& @0 N9 @6 M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! j$ a* i; v. m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. J* R. d2 {! n, a% Q8 \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) @+ ^) t( s* o: Q; w7 n3 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, B% a. i& ^8 N7 ]! F' V
0x00, 0xFF); /* configure the clock for transmitter */
0 [! {& \) r6 s# mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& L, _0 |# s. r" ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & v3 A( Z2 u$ T4 ?; e* d! T& Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 Q" C- }$ g: y# z: n0x00, 0xFF);
" F6 z6 s0 N7 F8 g. X( g2 z5 l- S" ]: w3 q3 ~ r2 n
/* Enable synchronization of RX and TX sections */ # N8 l' x& H3 ~& ?, D/ W9 k, s6 g& {5 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ b" V* ?# I5 S" |; N7 B9 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 {6 e6 N1 `, G4 I r+ ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ k1 H5 w$ p! b' g4 o) S5 }
** Set the serializers, Currently only one serializer is set as* u! C. Q1 \. u. d
** transmitter and one serializer as receiver.* ~: g+ t: [) V2 F. j
*/% z% }9 r( |& P5 ?! X. W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! g; K9 @5 K* d. C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' A# ~; U* G" ?. _ I
** Configure the McASP pins
2 ?6 U3 ~3 k& u** Input - Frame Sync, Clock and Serializer Rx
3 i# R' u4 c s3 ]% C) O) k+ i** Output - Serializer Tx is connected to the input of the codec
- u% {+ f5 d) E& s( ?. t*/
F+ s& ]7 l4 `$ q7 h; UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% `9 Y8 q/ K- J! b- I0 _+ d! w; VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% X% u* H u+ ?% l/ z- y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' r1 @7 A, r( M6 @0 r
| MCASP_PIN_ACLKX
0 x- _; k5 }2 f5 N/ w& j* o| MCASP_PIN_AHCLKX
6 ?7 a8 }$ ~ F9 m: y. [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 ?1 [# M- ~# E5 s- l5 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- j7 j/ h+ k3 I8 _$ X9 _| MCASP_TX_CLKFAIL & s* g: t& l# A" w& ?4 w
| MCASP_TX_SYNCERROR
- P: [! r: V2 q% H; o1 n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " T) G# _' J4 _3 {* u: K
| MCASP_RX_CLKFAIL
2 w2 [" M a& v8 {| MCASP_RX_SYNCERROR
2 T% i( H2 X0 G4 F9 V| MCASP_RX_OVERRUN);
3 x: ~! b, I' F0 W( F( N0 \1 |; ?- ?2 |} static void I2SDataTxRxActivate(void)
: e2 E5 e! B2 b& J0 f8 E O{
* t, Z1 m( b, u0 _8 E/* Start the clocks */ ?6 Z- J9 Q& H& I# M5 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" \7 L$ a+ n* P* qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 t; H- ~1 [, B; X' c- B0 C4 `/ g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ q/ J6 \: U' U' E: _' x
EDMA3_TRIG_MODE_EVENT);! C$ e9 H% u/ O( ~3 g" P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; f4 z* ^/ s( e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: m3 v/ Z" I9 o) Q% G+ c+ `3 }6 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 c& q2 z# Y `6 H6 m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 ^ _, p* o- g7 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# }0 f3 L& U, F2 @+ M+ HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 a) X* ]) G; O# h. m& kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ U8 B( \2 S$ M& C& P( R} $ w; J; P/ }* a3 r' F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : ~7 {6 \4 O+ H
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