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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ F2 r# h' x" E4 |6 \input mcasp_ahclkx,$ k' B% i1 Y/ p* g6 H$ V& P& B
input mcasp_aclkx,
% t; @6 c& S" g+ o/ Uinput axr0,
3 U) w; J- _4 C. Q7 f, l% w4 G" T7 P) @+ B5 A" F% L, a, n1 c' }
output mcasp_afsr,! g- j5 B# I+ ?5 |+ c F! ~2 D* X) |* x
output mcasp_ahclkr,
# V! @! l8 F; p4 P' routput mcasp_aclkr,* T2 G# {, o0 ^# j# I0 ^
output axr1,# o+ J- H4 i, f& e$ ^9 V: ]/ U
assign mcasp_afsr = mcasp_afsx;+ @* p# B+ w# f/ i2 F
assign mcasp_aclkr = mcasp_aclkx;% p8 L4 [4 D/ z
assign mcasp_ahclkr = mcasp_ahclkx;2 F# l; \9 _1 b" o. \
assign axr1 = axr0;
$ {3 M. ^0 P: f/ V
2 O3 A5 s7 ^6 u( ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) \1 C6 b$ g5 U4 H4 V
static void McASPI2SConfigure(void)9 N& N( {: q0 Q8 q
{1 R7 I* E- w+ ~, j( S; S) a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# O& j- L* i2 e0 BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ [3 y z" ?& U& @3 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" }3 m; j; \9 x) R2 c1 j1 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ j9 R) u; _$ _5 e; b# ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ s0 X# q9 I: Q6 g% z9 F" P/ [, l Q
MCASP_RX_MODE_DMA);# c3 m+ }& ^# z# ?5 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 q3 v; C0 J1 u2 R* n" j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- ]/ E0 n9 f3 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 F/ z5 {3 \0 L5 h0 Q1 s( T9 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& m: D) Q# V/ Y- }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( }7 y+ }4 B- ?) M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
Y& _2 N& p B1 D& G |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 C9 S/ e4 q& g8 z p7 R8 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& n% l5 @5 _- B9 k# Z F- NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, @ k8 D; J1 i# o0x00, 0xFF); /* configure the clock for transmitter */
1 m' d; X4 m. C; {" ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 j3 o& G; ?& r& j( V) f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . }& m" p( a) n! ?- k8 k/ ~# y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, |) N9 w# L! D- X3 C8 M
0x00, 0xFF);& g" q1 i! j. `+ }* f' ?- \
; q+ X! S+ I8 D, V1 K8 K* n1 P
/* Enable synchronization of RX and TX sections */ ' h; b5 S6 U- g) m6 Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, }; p1 E+ B+ G" f$ N- u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 _1 j; n" r4 v1 r% C1 B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# z% j+ b% V, ]2 {9 z! P; \! {
** Set the serializers, Currently only one serializer is set as
. ~% _1 V' f* c6 q8 T** transmitter and one serializer as receiver.% L$ ^" H' p I* d; ^5 ~
*/
3 l" Y& B& X$ L% S& E( Y. dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* U4 b4 W4 M" L/ N, DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 S3 h1 }, r! G1 J( z( G$ A
** Configure the McASP pins
# T& w% e: a5 v6 T0 H** Input - Frame Sync, Clock and Serializer Rx% T3 w K$ Z# z: |& M; S% ~1 y
** Output - Serializer Tx is connected to the input of the codec / }. b9 R) E: D$ @
*/1 D+ }! G# r7 Y2 J7 @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ o1 S; ?6 x: v- r2 `# jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ A" M& |" j6 m P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 M$ X( ]" v! x| MCASP_PIN_ACLKX( Y: c: J5 B6 I1 [1 X& [
| MCASP_PIN_AHCLKX4 B1 ^% q c, P1 ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ k0 O! q8 f: H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 h! Y3 P, O4 s* V
| MCASP_TX_CLKFAIL . W) V S4 Q: |; O' d& H3 r) ]
| MCASP_TX_SYNCERROR2 P. L. w* `1 j/ ~ z. I3 ~5 \3 y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, C, n: P4 U6 R' |* Y6 I| MCASP_RX_CLKFAIL
. @- F( ~) @* h# V& K| MCASP_RX_SYNCERROR 9 J# O/ u+ p1 u/ y3 O, z
| MCASP_RX_OVERRUN);
" K+ g; a# e" z( z6 T0 D1 B' w} static void I2SDataTxRxActivate(void)
0 ~7 U0 d7 m' i3 [. B) C8 e{
. Z1 F/ a$ z$ E( ^) M/* Start the clocks */
2 r( r' P5 I t) _- [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 ]7 g. h e% p5 SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' ~) \+ E2 ]+ g" O/ O1 J' D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: \! A2 W$ P7 R1 k' U" g
EDMA3_TRIG_MODE_EVENT);
: ~* z( ?, b$ Y( j6 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( P {7 M) d4 C4 O/ OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ d: B# ^0 z+ \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 i3 V% n/ ]9 \/ b2 H. m! n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, _7 L. [" x& Y/ }* z: ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ S: H' n7 W" C; dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# i, }* _3 O% ^0 l3 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 V9 a8 \2 ^6 W6 C3 L$ K$ S
} 5 i& u8 u. Q; J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 I7 G# q% H/ Z- ~* T+ e* t8 j, k
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