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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 y2 `+ n* h, e" s4 A7 p! Sinput mcasp_ahclkx,
3 D T# R8 W0 e' Y8 J l: }input mcasp_aclkx,! n: E0 J* B- }+ X: e/ i% p, E" \
input axr0,% s( B4 D! l: g
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output mcasp_afsr,
( w+ U4 o" b' V) H" x1 houtput mcasp_ahclkr,7 K& P, F4 w& V1 [
output mcasp_aclkr,, j d) N! y& R2 I3 V# q
output axr1,6 x8 ~% [% M( `' p$ S& l
assign mcasp_afsr = mcasp_afsx;; ?2 ?% m' H/ X5 Y
assign mcasp_aclkr = mcasp_aclkx;% O1 l" g- e9 t; \& b
assign mcasp_ahclkr = mcasp_ahclkx;$ p+ T* o! V- n0 U) L
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- }- z, d3 w0 p( ]5 xstatic void McASPI2SConfigure(void)3 V% X U$ G5 E
{ m. b( z- p, n# n, h' O8 [4 Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 z2 H( T d9 ]* W9 B6 o5 ]/ ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& V( b2 \' l7 N. a0 O( T Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, M( Q0 B3 o" F" E2 U+ R) ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! R4 X& o& r4 L; q3 B+ v6 rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 T- L* v( f& M* r5 z2 M
MCASP_RX_MODE_DMA);
# a$ x8 ? ?3 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ Q* j3 I' g8 M+ G8 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* i) }, i; c) h' v9 r' `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 l8 ?0 d4 O% w2 V' z, @5 x4 AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 J2 H( s. j- p X) U" v! ~+ r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! M! [% `3 P# j4 HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% J( P. C- I* l) h7 @, h" }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, O: M' d, Y: ~% E/ m$ @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : t/ g5 [! z3 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: }) }8 `' o6 H& E8 n, g% A
0x00, 0xFF); /* configure the clock for transmitter */
( {9 N, m" C2 z! k; {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 S' l2 v" D( z3 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . ^0 N. Y/ m' w* D' D y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) A" T1 n: _0 M3 K% N" D, c* }
0x00, 0xFF);
, U( [0 A' i9 P
2 k$ h! C p- ?: G+ h/* Enable synchronization of RX and TX sections */ ; M8 U C, X! S7 m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! x; D U, ]% R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! h! b% O& d" i# H: g" w2 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ E& P% h1 S9 w5 K; _- b; |6 n
** Set the serializers, Currently only one serializer is set as
; K: D9 `+ c" M7 y1 u9 a** transmitter and one serializer as receiver.
+ R$ G; X7 j% D6 ?, X*/* e2 ^1 A% ~% _; a3 u! J4 P4 w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& r8 e) O5 T8 q4 t% o) @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* p5 l; ?3 t0 u** Configure the McASP pins
( ^+ k* z6 N" }** Input - Frame Sync, Clock and Serializer Rx
% K: I$ |5 d( s5 @; P) W! ]** Output - Serializer Tx is connected to the input of the codec ( _# w& b9 h0 q# f- {9 u. O+ A! g
*/
6 L6 E0 F! l' }' D6 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, k5 G3 D3 k. n+ q7 X; u i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 q" k& T5 [ t3 Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 j' }; F8 }! m* J% D
| MCASP_PIN_ACLKX' N1 c7 X3 F- G: ~& i; }
| MCASP_PIN_AHCLKX
( `" E$ N5 D+ N; s! H+ a. K9 b2 ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& v+ F; A7 r7 b( n0 h3 {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; f3 ]- h& n d5 l
| MCASP_TX_CLKFAIL
/ @$ r! N! ^! Z- m. y' l| MCASP_TX_SYNCERROR
7 o- p8 b% a2 o" e* x2 I4 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 Q& f9 C* ]+ y" g7 I| MCASP_RX_CLKFAIL
: W: ~0 Y7 R' A0 G1 r| MCASP_RX_SYNCERROR
& b& z) H/ ?, A& e J0 z2 `| MCASP_RX_OVERRUN);. R8 M) X; g7 a& q5 r5 L
} static void I2SDataTxRxActivate(void)% ~3 }5 b' L( @; W6 e. s
{
* n9 Z: T0 G4 x! \1 I4 [ R3 M3 h6 y& i/* Start the clocks */
1 S. M9 ]6 Z/ m3 W7 b* t1 n7 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. o0 T: O4 Q2 eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 |" j" u9 Y3 t$ v H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ C- z5 y& i& d& R4 k) ^
EDMA3_TRIG_MODE_EVENT);
3 \3 C/ J6 B0 R& K: T# |& E K" VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( u: k' F; J, y( ^) A5 \- w$ q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* r% X. J, n# |; a. s, l- NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, }$ g6 U' n4 z0 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 L p, e8 z* x# b3 l( O' c* owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, `6 x& a2 E- J* v6 jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% ^# U7 b- @( z! C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 Z: g% c* P' U1 a. x: c( `1 v
} 0 J7 T0 C l7 B+ D9 s3 N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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