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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, S! ?0 @4 d3 E2 C7 x8 }2 j
input mcasp_ahclkx,$ U$ L; U5 w# P3 `# c/ {, ?
input mcasp_aclkx,
9 p4 E8 \7 u7 y2 Z$ z' o' a- Pinput axr0,& f2 Y" Z8 k' i; Z1 c7 w
& G0 V) t4 w: U6 Xoutput mcasp_afsr,* O- t+ Q, F5 h- `# [
output mcasp_ahclkr,
+ j& V2 p0 W* _9 l+ I7 ?0 E Eoutput mcasp_aclkr,
- v$ \9 e& `' U5 [) @) Foutput axr1,' a4 i0 O+ ?# @. g' E5 {) y" ~/ f5 ], M
assign mcasp_afsr = mcasp_afsx;
% K& Y" j+ n- o- ^6 j! Cassign mcasp_aclkr = mcasp_aclkx;" l) g! o" P! A% A G! z& i l
assign mcasp_ahclkr = mcasp_ahclkx;2 @% ? Q. F9 F+ w5 f; p [: F; S5 N
assign axr1 = axr0; * v w! I* k: I+ F4 P6 L" S: { W- I
, K( c R4 ~4 H. L/ |3 M2 W7 d3 V9 p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& j/ _& V: w' Istatic void McASPI2SConfigure(void)- A# v' U( r( F* d3 f+ g
{* f9 W! b* c" A" G2 c3 S; |1 Y) m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' ~" D$ p# V. x. T V* {) aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 S; ]1 O) @, w+ B( Q! @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 ?9 U0 W/ Z# P$ ?1 W; j) p' HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% v" r& i" O# N8 H# o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ G! u( b& g" G U$ N! AMCASP_RX_MODE_DMA);
2 M- ^9 S& Q$ F2 C+ P& }: C! OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ P0 S/ h# D1 u, P" \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. o; h8 q5 {# Z! d/ w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 s+ D3 Y. l( p) I; A$ K; `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% ]& N5 z/ f% o" e7 a. Y+ \5 Q3 \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , `8 R; [( |" f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
?6 t& J, |% ^& _8 R) ?) d/ p! ]8 _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' l+ r0 g$ l" hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. Q# R1 t8 x6 e; U6 }2 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. `7 D& v$ `4 s6 V0x00, 0xFF); /* configure the clock for transmitter */2 i/ A+ U0 d1 r1 e; v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ M/ U) O5 E7 m: X9 v4 e2 cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 O" Q/ K+ d2 d; e' i# b7 Z7 K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. B; m/ m- h% M; {1 B+ E3 ~
0x00, 0xFF);
: h% J3 t& U X; |: K, m- ]
{7 l" h% `2 m/* Enable synchronization of RX and TX sections */ 3 R( Q3 i+ C, U( O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: ?: g) s! Z N/ k3 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) O! v" r6 e! |( k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. I8 S7 O! Y" I/ K% l- `# `** Set the serializers, Currently only one serializer is set as1 N% j3 ? Q/ r. ^! c4 R) g
** transmitter and one serializer as receiver.5 C3 _( X! v" F1 p
*/
2 j& K q: S/ ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- Z6 @, v" X8 [7 C, K* IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# X* K) U( e; V% Y a
** Configure the McASP pins
i% D; Z3 L/ F2 d# [ ~** Input - Frame Sync, Clock and Serializer Rx
: i2 R) c2 A3 U R \9 w** Output - Serializer Tx is connected to the input of the codec
0 S2 }. q/ K: M [9 D*/
# X* h. C1 o$ {# d4 V) DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 q- f1 K; m& m6 z- C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 \5 J4 r; e8 f ^6 T, S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, ~# O6 @7 {+ n/ Y# C1 a' x
| MCASP_PIN_ACLKX
* c8 b& x4 I. t; T! T/ p| MCASP_PIN_AHCLKX
+ |5 n2 T! N' ?$ F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( W4 p5 A+ E/ l+ [& jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & \+ R4 u0 [ g0 P+ i0 a
| MCASP_TX_CLKFAIL # o0 [( g# ]" f3 |2 e; e( `
| MCASP_TX_SYNCERROR
3 p' n, a9 U) \ ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 {; P6 i$ [: E4 O. q4 A* x+ ]4 X| MCASP_RX_CLKFAIL* I' Z4 G1 H& F& j9 f
| MCASP_RX_SYNCERROR 8 m$ W. y! q$ `4 v9 H4 f
| MCASP_RX_OVERRUN);7 n2 R( f$ L, J9 \4 O+ D9 a3 r
} static void I2SDataTxRxActivate(void)# V# W; c [! ^1 o+ C0 H+ U
{
( M4 K- L6 x" b! F& C: f1 v! j# X8 y/* Start the clocks */
( f( D' X1 ~# |: D2 g- ~7 H( vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; B+ e8 \0 M) W. c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& V9 E6 G# J, n/ f# P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 B$ r% k* F, T3 A' I! s
EDMA3_TRIG_MODE_EVENT);
9 ]0 i2 ?! X# Y5 d. q [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; e6 i$ n" u, x4 ~( q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( a! n/ [' U7 e1 E8 M! E# k# oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, d; v Y& V9 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! ?( \- }) A: w% }, Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' S( r7 H$ o a# Z, OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 y. A2 v9 f4 w1 g5 `4 q. L% S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, y% U# n0 }5 D1 N}
$ @$ F& f3 b4 b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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