|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- C, K1 w: p6 _" M+ Q+ c8 A9 ^
input mcasp_ahclkx,
; m9 k" Q' J; ]5 }& z" tinput mcasp_aclkx,
/ W+ b4 ]5 i7 yinput axr0,) Q5 U, k* z8 h
% |0 N( c/ L4 D' _$ _
output mcasp_afsr,
. W* z( T# g# s, m5 h: ?9 V% ioutput mcasp_ahclkr,
+ x4 H( J/ K7 U U9 [$ k/ `" i" Noutput mcasp_aclkr,
6 p5 x. A0 Y3 e. ?output axr1, b0 E, b/ t2 Y& Y+ t+ S0 u
assign mcasp_afsr = mcasp_afsx;# B# y. ? r& \2 }) [+ }/ Z
assign mcasp_aclkr = mcasp_aclkx;
( i. O, Z( k- z/ c$ ~assign mcasp_ahclkr = mcasp_ahclkx;
1 ]9 j& e D/ [- lassign axr1 = axr0; & D/ C5 N$ M E; B) \( p" Q: U9 q
- t- o! q! |- s6 y) `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 h. u8 s7 S2 X# y) X
static void McASPI2SConfigure(void)
: `2 L5 ^( n5 J3 L( `+ I& ~; s{1 I. m$ t$ M0 ~* H7 I I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ U) X. ?9 c/ n5 {7 z6 T' W5 R# w5 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- R) _' L8 o6 q; d! O! `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 P9 {$ B7 ^9 z# UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" e3 F2 _, D$ A0 t! E3 T% oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& u" @, p( Q1 ^1 _. E+ FMCASP_RX_MODE_DMA);
2 K2 J$ c; f- J8 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," |7 W* V3 ^2 J/ t$ O1 n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. W- `" d+ _ g) pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / _* v0 n! N+ c. s, {/ B3 T' B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 z, }0 x4 Y7 Y8 v4 a- u* |0 r) OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 h/ [3 _3 [( h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# S: h4 v- `1 E) k9 _ u$ b. uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" d$ E; ^& P: B* [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) x1 Q* l' } D3 Q$ ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 E' o/ I% e$ k' l( L0x00, 0xFF); /* configure the clock for transmitter */! m+ G% _' [& w! `* N: S0 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ Z6 m0 [8 k* s) JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! E- r+ ^# C6 A1 g* ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( q6 k `! Z" w: r/ P& f0x00, 0xFF);
1 g& C5 u6 d m3 |" x& o
# i4 o, H P" }, ?* C" U$ U& k. C/* Enable synchronization of RX and TX sections */ 9 x ]" R# c% x1 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# l. p" L, J0 B1 }( o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- Y- `! ]' A. }+ [" x5 [+ pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, _0 w. H4 b7 o- j! u; v** Set the serializers, Currently only one serializer is set as
7 G. |) d( M: v$ D! [** transmitter and one serializer as receiver.$ K" Z& P7 K8 c
*/
& |# c6 Q+ y8 F9 [* i" PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. K6 |( A3 s P" ^3 z" v( IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; s. v% G: A4 q _+ O** Configure the McASP pins
+ ~9 }/ b3 n0 e$ Z {: i9 p** Input - Frame Sync, Clock and Serializer Rx
, f" j" F0 |1 `/ Z9 m, o** Output - Serializer Tx is connected to the input of the codec ! P1 @ S, I# M5 {% t
*/
3 X" T$ a) Y7 E+ I2 {9 T( VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) @8 n- p5 V( FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 p5 X/ l" o/ N! E/ NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ X$ z. I2 g: Q. t9 v| MCASP_PIN_ACLKX' H9 n: _& ]1 {0 g
| MCASP_PIN_AHCLKX
# x' m2 g- T" `1 G+ J, O) {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. C4 m+ t0 r# X0 X% n+ k) bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% l+ M |' ?7 e6 |$ X Q| MCASP_TX_CLKFAIL
" b- E& k0 v, k0 c| MCASP_TX_SYNCERROR
4 F! h; U5 a2 i3 A8 F2 a) f$ Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: }9 k1 ~8 g4 \" C- k- Q& A0 Q% d| MCASP_RX_CLKFAIL z; ^- K2 q9 }% z' c5 l
| MCASP_RX_SYNCERROR ! X% h( b, I6 m$ o+ c. X
| MCASP_RX_OVERRUN);" u2 B5 N* @) Z F" d3 D9 T
} static void I2SDataTxRxActivate(void)& p/ Q5 A6 {3 r8 `
{
" n% B' Q! ^, x# |' s; B) |/ `: Q0 \9 ~5 Z/* Start the clocks */2 z# X0 {* _ ]7 y ?0 P) a% L/ T7 C; b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& u' y- A/ P$ h2 D+ K( Y, aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 h7 c5 w v5 m+ ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# H* I. A) w- J( w G
EDMA3_TRIG_MODE_EVENT);1 s- t4 @$ N1 s* I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + z# n6 P% m8 f; T* ?* Z% ~# Z6 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# S7 k+ L2 S0 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 W5 t5 W9 Y" C0 v5 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; Z" R, L, g5 p: f; H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! B2 w7 }# N2 {7 ]3 T* l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& z, l+ \+ C) G% ?3 A+ v; ?3 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); A8 q1 f* N" \& w, d# G. ^! o
}
+ b; d; @! d7 N) j% [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 L5 h& k- q/ \/ h9 a% B |