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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 m1 r1 v- d4 c. \
input mcasp_ahclkx,$ v7 v" L) V$ t/ Y! r
input mcasp_aclkx,$ B& k4 S" h1 r$ y- P3 p; y! m& C
input axr0,
0 c2 @3 N/ A+ ]: N8 X( \1 Q" X0 }: ~. b
output mcasp_afsr,
6 x9 o1 I7 N. A' F0 }/ o S. @" ?output mcasp_ahclkr,+ u0 j% \& a; |4 y- G
output mcasp_aclkr,
( m2 S# J3 s$ l6 V) Y( O6 C+ k1 |6 Woutput axr1, Z& P4 Z+ H/ U& g
assign mcasp_afsr = mcasp_afsx;( S' R! r' U5 T5 u$ Y2 O) H
assign mcasp_aclkr = mcasp_aclkx;
# c* i2 k, H: B* Dassign mcasp_ahclkr = mcasp_ahclkx;
" N, w6 Z6 }4 @; s4 \assign axr1 = axr0;
9 t+ i7 r3 [1 g0 U$ G
p4 {+ I7 T" [- a# L" |$ W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) s( a# I- Y0 p# O; N {) _0 ~
static void McASPI2SConfigure(void)
; U! Y1 M% s6 v8 {. z4 @& \, i{
, {1 }; W }7 S8 {McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ O5 o' ` m& i) t5 \McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, T1 }3 w$ Q$ X5 u. y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# f4 m7 b [4 n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ r; j( L3 G# B2 J3 sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# @0 E3 R5 N* s$ {" lMCASP_RX_MODE_DMA);: j) |! K6 T; y7 Q& @3 w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ y% D" C* r$ P- aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 G; B k1 C/ j- X% @/ m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 X4 G% f# [5 ~, z0 D' a( C. E1 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ r, D) [" }+ wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 `' b8 f- z- T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 k2 w: a% `, f4 G& V) W5 E. `8 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, d; w( P& `+ d) O0 R& U; i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 [ d; h5 E6 ?+ w$ tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 y- D/ ?0 [# l5 k( F; t0x00, 0xFF); /* configure the clock for transmitter */
- y: i3 g T2 V5 a+ f7 Z8 zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 f9 a$ ?7 B: F' M2 f& k4 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& g! p, J7 L7 v3 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. O* q$ ?& c' Y' }4 I0x00, 0xFF);
2 s |/ S3 {- z; s
* m+ n g9 T( l Z+ P# \; |/* Enable synchronization of RX and TX sections */ d% ^ m7 J5 j5 D. G$ H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! m w4 }9 V& b. |2 ^& C( E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 i% y9 R1 L f' d6 o; K2 fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; [- R2 P3 k6 p$ m
** Set the serializers, Currently only one serializer is set as
4 }; w5 ?; r6 {; O# I** transmitter and one serializer as receiver.
5 k0 j; W; j% @; w' k*/% Z: w% }# }0 Y n" ^2 f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( L* r7 `* T' I! p" A7 e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 {7 n a# E$ f: D; }** Configure the McASP pins 8 C5 {7 C a$ T5 s1 w
** Input - Frame Sync, Clock and Serializer Rx7 v$ {4 ?! H0 o: S
** Output - Serializer Tx is connected to the input of the codec
% i! i) H; t/ X- b2 r3 U*/+ ~+ D6 r. |) ~* D* P9 b" Q0 E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* A, V" Q G2 V, q$ u. @4 tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 K8 m8 ^' O! m% q* q' h, ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# m' x& Y( n9 Z, M
| MCASP_PIN_ACLKX
! C0 K9 F7 u9 `# a. @+ B$ ]| MCASP_PIN_AHCLKX7 l! E, F# N# Q2 a) ?% V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 E3 G% e7 R& j7 b% A, i( n: r6 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 ~- C8 d" v9 B! \ _2 ?. D5 J& n/ v
| MCASP_TX_CLKFAIL
6 P, ~9 A9 t) z0 _4 a4 N: ^$ q| MCASP_TX_SYNCERROR
' F. n6 h6 }; w l; X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : J% h5 ]4 k( t4 ~5 k) Z+ Q
| MCASP_RX_CLKFAIL
7 U1 W9 F2 f5 H2 F- O5 e+ i6 \| MCASP_RX_SYNCERROR 5 m. P1 ~* ?, T* a/ F8 @, D" H
| MCASP_RX_OVERRUN);8 [( r. ]5 v3 N. o
} static void I2SDataTxRxActivate(void)4 A, B$ ^3 P. l% B5 g- }8 u* a
{
5 H4 _5 r" K8 K; L/ q+ h' l/* Start the clocks */6 l) w. Z' X8 z3 Y3 O% l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); c9 f n# e3 b' D( S6 U% R2 I$ t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ y+ u0 P1 b+ d& b+ c! A" b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 {2 z- S2 A2 ~$ t ~EDMA3_TRIG_MODE_EVENT);* Z: n/ ?) m3 b) H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : f% ^8 b2 C" ^2 m$ h. N* O/ v3 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' B, O* u. }2 j3 u" q. k/ T4 cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" G7 K; K8 U. b K6 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: B' w1 {4 I4 P) m+ O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 P% V- v3 r) G' ]& E3 q! IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 b( L, R5 F5 |) MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ z" Y! c, H6 ^5 |& ?}
8 ^( H/ h% V. X" e8 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 {' Q, x1 i$ H! f$ |7 }
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