MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
$ @. T6 |  }4 iinput mcasp_aclkx,
# s1 T( S( l/ s6 Finput axr0,

; u9 x3 l, M0 ^5 [output mcasp_afsr,
output mcasp_ahclkr,
" L: i& l3 P7 T# G. |" Joutput mcasp_aclkr,
output axr1,
( n' [6 {1 Q# y4 H) P+ N

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

# z! M- @# ?2 \1 i9 M0 N( C. z

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
' h  k% {! o+ j8 v4 F# v. T" n{
* j( W) U1 b$ A7 E. D$ J5 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
  ?0 X* B, B/ M+ b6 aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
; l  n, L3 Y+ tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- b8 G1 B( s0 F+ j9 @MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ B7 p4 Y) W  E( U; a; ]0 nMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( X; _& e) P$ e; P  TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& v1 W! d: R2 d% nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: V8 ?5 z7 `( H0 P0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 L" T+ e5 k. O+ K) [% {% d0x00, 0xFF);
0 j, N! g$ V4 {+ @  Y. t6 ?; G
# D3 D5 ^, Y2 v4 Y6 Y2 z* ?4 F0 i/* Enable synchronization of RX and TX sections */
0 B1 f" K/ s( J! j. OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; ]+ g3 x, l0 G& P! NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
) D4 b5 b6 @8 z. M- H  f6 ~; K** Set the serializers, Currently only one serializer is set as
) S: r4 F# R, x3 M5 g9 l** transmitter and one serializer as receiver.
*/
" W+ ^0 m: L& a5 q8 SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 y- Z1 l3 `' J2 t& U3 W7 Z: [6 i- mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
: C* {- T1 K+ R& M& h** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
9 F& P$ _7 \+ |% j1 ?** Output - Serializer Tx is connected to the input of the codec
+ U7 g: J' p, L8 }" S5 y$ v% p*/
. w, }& G) s; K1 j# b3 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 T$ @  n- v& {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
' K* P2 q" J2 k  || MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
# V4 [. F# ?; e; z, x  MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
! l% N9 ?1 z# b1 J8 N  C9 o; u; S7 M| MCASP_RX_SYNCERROR
- i! Y- `) j" ?4 F| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
7 H  B8 {: L2 h! v1 O8 ^/ ^& Y{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: Q- b+ g; X% k3 M2 a% TEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# Y. h/ z9 V  j# OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- i2 M5 L6 X% \* H: r' y: ^: s) CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
9 }9 ~6 D6 ]- }' }* y6 y0 D( Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 ?" `1 V0 t7 D5 L1 [, h$ ?' fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.