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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- u: o" K t3 L8 Linput mcasp_ahclkx,' i5 D" t' {6 M4 h7 t# V) Z
input mcasp_aclkx," X- a9 S3 h7 Y0 s x
input axr0,* u8 J/ A/ f/ E- m
; w$ T- A5 m5 S! \% o* ^2 boutput mcasp_afsr,# o: L( k8 ^/ S6 y9 }
output mcasp_ahclkr,
( u9 z: I& \7 M: R( s0 \* uoutput mcasp_aclkr,
" J- D! p& i( I/ ^, `output axr1,
1 j2 U7 j% W3 V assign mcasp_afsr = mcasp_afsx;
& T7 k$ d& Z0 V4 h t0 I5 d2 y% Qassign mcasp_aclkr = mcasp_aclkx;# {/ c" }7 h8 B5 N+ y1 ?
assign mcasp_ahclkr = mcasp_ahclkx;- _! K7 S% t4 x+ \3 N$ K9 Y
assign axr1 = axr0; ( B7 p$ z1 F5 c' J0 M
! p" w3 Q& `+ H) f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ A; N X- @" h* x- |& k" Ystatic void McASPI2SConfigure(void)
' [: ]' w/ Z, L4 Y7 k) O3 T+ Z{, {! K3 f: Q0 h( A: b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; N+ l# _* G0 v R* {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 p. L1 l1 W7 h- nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. h+ o6 Q, r. S; Z4 o9 W: s, oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 S& c1 X {: J' S: b% qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 N A; u5 \( U, O$ W, `' n" O$ _MCASP_RX_MODE_DMA);
- a2 V; {+ C$ _2 f$ \7 eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; X2 I( C& U. E' V+ n# r% o: S! fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) t& |' w& g! [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 B, Z# g' G* {& _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ ^3 k. ?5 m$ U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) ]. I6 D" I8 F$ MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" t& Z$ z0 q) c4 k! z& B8 w% k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! M) Q) `- B [) `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 @; ]. F7 [7 F! M9 z" a' ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ h w3 G) G( h7 w
0x00, 0xFF); /* configure the clock for transmitter */
0 l) f P3 u" S5 Z3 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" ~7 C8 P1 s- [/ k$ f5 `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 ]& Y2 w! y/ T2 Z% ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 Z! D" U0 @% t
0x00, 0xFF);
/ x7 p0 O E2 E8 ?9 b
* E3 T* A8 i# V/* Enable synchronization of RX and TX sections */ % y9 R, S; d/ W4 R7 _, d! l7 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, p, j) Q; P, o& E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( O4 ?3 z2 {* ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" `) }" S& f8 h6 S" ^6 y" s** Set the serializers, Currently only one serializer is set as
& i- ?) y; A+ {. v; m** transmitter and one serializer as receiver.
, A' x/ o" ~" }# d+ u*/
- z6 ^; F, ~& e2 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
^$ [; {$ t. yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ G. [( m- a& P. K
** Configure the McASP pins ! j3 o, u- r( q- j2 q; {1 [
** Input - Frame Sync, Clock and Serializer Rx
" t3 T4 Y7 G; l: Q1 [& I* q& M** Output - Serializer Tx is connected to the input of the codec 7 P2 s2 O7 n. U) x) q
*/+ G4 R" a) m# S4 E$ ]5 A" ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ U& m& J% w" G$ L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; w2 P& Z/ q2 n! `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 \% {& e; j: I9 V- Q
| MCASP_PIN_ACLKX
6 q4 W8 K7 h" t8 c+ ]! Q# D8 s| MCASP_PIN_AHCLKX
* W7 l* g! l- `5 }! E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) G) {0 ?* h, R+ P- CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 c5 q5 Q; c, G3 D0 m; v; X9 B
| MCASP_TX_CLKFAIL
9 Y s4 V9 h' T| MCASP_TX_SYNCERROR
' J1 t# G, ]3 b- ^- n- y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR |- @8 b; I; H! [2 q0 I
| MCASP_RX_CLKFAIL
* \+ M; W' _: s0 t& A- d; b* s| MCASP_RX_SYNCERROR
! Z8 I( N; |. A( t1 h| MCASP_RX_OVERRUN);
$ A7 }% U4 W$ m; z% X( U4 |- d, b} static void I2SDataTxRxActivate(void)9 B# z" B$ e1 C G7 g
{/ X4 h: ~! o- [ X
/* Start the clocks */5 p' U5 g! Y4 x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! r- r2 q j# T& L/ g IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 D- K* `- X, w) r4 Z& j0 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# C6 E/ a. _, d0 Z( b; B k
EDMA3_TRIG_MODE_EVENT);) o3 r$ w# B4 S( K* E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; [9 N6 V$ l' ~+ K7 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 [+ v* G$ V, H# g' C3 @7 @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% u9 ^% s& m' g0 F& i. k( a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: G4 G" u6 l/ t9 T4 [" v: f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 g4 k( S8 \8 W6 t2 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 _+ K( ~2 T: p3 I7 t" F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 ^" I7 b, v# v' e& f6 x- e( r}
, ^, c2 r, m8 N O9 P3 O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 b5 I5 L; R; N1 H) s$ r
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