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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' }- k9 R' u; Y; S) d! R
input mcasp_ahclkx,
" `( f: H1 j* T% ^7 ]; ?input mcasp_aclkx,/ A, D" e( `/ q9 T1 }9 W7 T+ {/ ]
input axr0,; r! e1 j% Z' V5 @0 N
+ W4 H3 y+ O& ]output mcasp_afsr,4 P; f$ h7 l& U, O& K& \
output mcasp_ahclkr,
3 I- Z% a2 f8 [output mcasp_aclkr,
- `! U2 t& q8 {& Z# E+ N+ Doutput axr1,
! f. n6 W' ^6 |$ n assign mcasp_afsr = mcasp_afsx;$ @1 Y% w8 `* v: W3 J
assign mcasp_aclkr = mcasp_aclkx;2 n5 {* x# S- J5 S4 N& n( h. g
assign mcasp_ahclkr = mcasp_ahclkx;
; G) C: X# R6 P4 k. T2 r& \assign axr1 = axr0; 9 j/ C a6 |" v
) ?, J, o L, P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 `8 V6 W( C3 n* i
static void McASPI2SConfigure(void): S% w/ v0 D; ?. O
{
$ h, [- t+ S" |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 n. {! C) B. }/ ? H7 C5 |% @# ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# d: I; i, n* \1 F7 q/ R0 o/ v0 r5 @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 X/ `7 h& J: }8 S! i- A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" l! t" P$ _1 |/ O& g% q$ x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 _6 G# C' a" L5 {) I6 z% y' \. q
MCASP_RX_MODE_DMA);
* |* y- W$ |1 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 B% g1 b+ Z: I3 R# l, _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 H$ b$ R' T% D: l$ K, s) l1 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + w2 v5 I" y, d N; ~, F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ O' i& S8 d S: O3 T+ h/ gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 n& L- }6 N; K7 J% HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 t% O; \8 d7 Q5 Y4 F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 Y* s% s$ x" T2 a3 X+ ~2 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ F3 T4 U. {$ P8 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; Q3 X+ y U$ X0x00, 0xFF); /* configure the clock for transmitter */9 ]4 \$ i- A9 v- b. u8 @ M3 X! Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; q0 i& H6 e. H& MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) P- Q, U) ]$ N2 F% ~; G2 l2 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ B4 w& y" Q0 i. f* F7 k7 i3 C0x00, 0xFF);
; n0 C6 `! P" y4 e" N4 k5 Y6 O" V w5 x, y$ z% ^! c
/* Enable synchronization of RX and TX sections */
+ c' u; k; i3 w; ?# }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* f! F# g8 h% J2 l. yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. k$ T/ i( E6 d* s0 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ D2 o3 i; d7 _$ z( c** Set the serializers, Currently only one serializer is set as
! l7 x/ ]$ ~. n+ q$ X5 o** transmitter and one serializer as receiver.
' O0 r9 O$ @/ V+ u( b*/, m2 L- ? q3 R5 o$ w/ I8 c$ X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) Z9 ^) g) a1 p& p, f$ Q1 l( H3 V6 E$ z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 d9 z" w! [% _' o; b3 o5 c** Configure the McASP pins
" N; D X+ W3 @" I+ p& A" j** Input - Frame Sync, Clock and Serializer Rx/ n( N0 B' e" |4 F: p8 R
** Output - Serializer Tx is connected to the input of the codec
" [1 V! V% p7 L/ E" r2 x( u*/' {* Y( h' I% Z4 p @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 _# R4 K/ J8 d( ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" S; ]7 Y$ D3 a3 C+ {9 H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 }3 c5 s+ G c' b! J
| MCASP_PIN_ACLKX
% {0 b! n% U4 I3 f# D9 `* d| MCASP_PIN_AHCLKX; X" F6 I1 X) ~8 s+ q' k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) J x2 Z+ ^, J! fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 k c- t' Q- T6 O* s# a. i" E( ?| MCASP_TX_CLKFAIL
- G. m7 @6 `( c; Z7 x. @| MCASP_TX_SYNCERROR% t( o, S! P: o: Z/ h% h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 G+ A9 Y& M3 I# B' f! m# J! @| MCASP_RX_CLKFAIL
/ h, ~$ D7 W5 p4 K$ R| MCASP_RX_SYNCERROR
+ y5 g! {4 l* c9 e. a| MCASP_RX_OVERRUN);
& }% T) b0 W( W$ a q} static void I2SDataTxRxActivate(void), _8 {9 w$ c( b/ I+ h# o) K
{2 W6 R- v0 f {: M( W1 q+ ~
/* Start the clocks */8 d: B6 r7 s# E+ H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 }. @$ u' G: H# O5 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" d( t0 g0 q" F5 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 X3 Z) M$ d0 {' \% j
EDMA3_TRIG_MODE_EVENT);/ |. ]/ z1 p6 O) M0 r, P% O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ ]9 }. r) o6 }- ?# F% }7 r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ C. j y0 C9 W1 q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! }, F; I/ q) @" Y( O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 N+ e$ Y4 C: x7 u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 ?9 a! R0 w2 @/ g, Z+ O1 l( j/ f$ Q! F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; H, P& v1 _3 H0 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ ]7 o1 l7 ]0 [ {1 T5 Y O1 S2 y}
* J6 V) e- Q8 R$ g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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