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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 w3 T) f- [# f6 i9 n2 ~' y0 b
input mcasp_ahclkx,
. a8 G! ^. W' E1 Z' |' z& Zinput mcasp_aclkx,
4 X" W& D# O* a* J6 ?8 R) zinput axr0,
3 h, V5 T( V0 ^. H! X, f
8 N( A- O: n/ E+ Z {output mcasp_afsr,
- B9 ^# w4 V* X9 x7 Ioutput mcasp_ahclkr,
4 \ {: G. c: ?output mcasp_aclkr,
5 ]9 P! G6 u, q# B& l$ b! X& v4 {output axr1,1 G- ]0 E, O% a2 b+ `: c+ a
assign mcasp_afsr = mcasp_afsx;( c* I% K4 O, }% O7 }
assign mcasp_aclkr = mcasp_aclkx;3 @, l7 W+ _5 i7 t* P
assign mcasp_ahclkr = mcasp_ahclkx;( V* @5 z7 V+ q' y% e
assign axr1 = axr0; 8 w1 h8 \% i$ z& G2 _* K
" R2 h* O1 p: X* Q% ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * P. z' y3 z; `- @" ~9 x
static void McASPI2SConfigure(void)
" ?- a' D. [2 G{9 B1 ~/ V/ o0 T5 ? W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. U5 x8 S- m+ O5 _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 r9 S, G3 t& q Z$ W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 n2 c2 s$ n8 I7 f% rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 Z2 P% A' S- q. _+ i1 z% n& S; AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& n, ]& J* J* ], `& ?7 d
MCASP_RX_MODE_DMA);% I" q$ D- i# J' d( z% }3 d, Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 E: B4 P9 ?1 P2 `! T D( W( U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" G- e! N$ M) o4 M' M" O/ D) }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! ]5 w3 i' B' `& |7 h+ SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 }! S, G! L9 ^6 r$ C. xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & e6 G) \7 ] {, N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! u p6 X; ?! _1 ?1 q9 L4 PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 _1 t9 o( G, }4 m. }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" ?" X8 p I7 H% ^. \ }1 ~* EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- B% K% j/ {# ~0x00, 0xFF); /* configure the clock for transmitter */
: ?' q9 |" |* e/ Y+ l+ sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ f8 t. }3 V0 B, }4 NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : r+ q) R4 q- _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 V2 y! e6 W6 w3 G0 f0x00, 0xFF);
! @- j% t6 O6 k# h0 |% `* C/ t; B6 k' ~& Z, {/ Q7 ?4 Q5 J" u3 ?
/* Enable synchronization of RX and TX sections */
6 \' d6 D: q# k5 g1 n) a" l3 OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" B& v% o2 W/ W/ @0 _1 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" O3 f' n! B$ u ?2 r* N O$ ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) n/ s/ k! J; |( I5 h& R1 B. W* f** Set the serializers, Currently only one serializer is set as# Z3 m6 c# N1 Q" k
** transmitter and one serializer as receiver.% l4 S, _, `- b) N- V$ S9 N
*/
/ R+ u A. n6 ?" G6 o# ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, R% K6 y# `! O3 j, N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( H5 {, u+ X3 t& y# D* T4 x% x6 c
** Configure the McASP pins
, W) E1 z% E6 B% ~7 \: c2 Y6 }** Input - Frame Sync, Clock and Serializer Rx
! t$ F2 M0 }& [+ u** Output - Serializer Tx is connected to the input of the codec
/ d3 U; W% Z- O) C*/# T1 `( R5 ^- s. n3 Q* O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 ]' A, F0 l% K7 a! w* Z9 `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' J2 L' o, T4 l, [" Z U, KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 @ Z9 j$ ~3 V( A U
| MCASP_PIN_ACLKX( s9 O6 j, d" T( J: N$ i
| MCASP_PIN_AHCLKX
& v$ _% v8 O) o1 v6 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// D% b6 I8 `) S7 I& s, B7 R# z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / C5 a! n/ w$ k1 x2 }! e: N" r( o! z
| MCASP_TX_CLKFAIL
. n$ ^1 y- x8 G) F" b5 ?| MCASP_TX_SYNCERROR
- u1 _3 \. O$ b( p& F- W0 C- c3 f4 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 W+ X) R6 S8 j9 S! @% S, X| MCASP_RX_CLKFAIL w3 v% C+ c! H1 E5 s* o8 O
| MCASP_RX_SYNCERROR + l6 L6 A. V& I$ Q' D/ f4 _
| MCASP_RX_OVERRUN);
{: r$ U6 v9 w E9 o& q' d} static void I2SDataTxRxActivate(void)3 f8 e6 i+ F# g9 z$ q9 @. K; t
{: k, n' f$ Q+ }# L. [9 d+ Q
/* Start the clocks */& ~" w6 u3 Q8 E3 d- A# o4 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: }4 I' y9 s1 [; J8 k' n* W t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ `' @+ J! S, C8 _% {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- g. H' R' l# [2 b/ T IEDMA3_TRIG_MODE_EVENT);8 b, ^( ~( u% }4 C: O4 {, E8 U. t; q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% w5 F3 G- k7 B9 |3 ?8 W0 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 x+ J$ ]* U4 u3 b' B( S, i9 `$ I' ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% Y8 @# P2 {2 Y. C, WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ H" M1 Z+ G; s* ?0 a. x- j3 N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 D" F) y- E; ]% y( c# C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 j5 O4 q {/ O+ `7 [. h+ i- _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! l, J( W6 Y( C; [" V$ V) M}
9 W/ a3 P2 e/ u. Z1 D; x" C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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