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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) D. o" M; v8 binput mcasp_ahclkx,
1 M7 i% e/ _' |8 minput mcasp_aclkx,4 C. ?) Q. k" D8 D
input axr0,
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output mcasp_afsr,* v0 R- {9 w* E, G2 e0 h% |
output mcasp_ahclkr,' c) }# L/ W3 ?- L, A; B( n
output mcasp_aclkr,
: R; R6 E6 s/ p+ }# Qoutput axr1,6 a. M% i1 \7 @
assign mcasp_afsr = mcasp_afsx;
' L# J+ J M2 Z( e/ cassign mcasp_aclkr = mcasp_aclkx;7 M. x" r8 t P) B! b) S3 o! [
assign mcasp_ahclkr = mcasp_ahclkx;1 B% f _! A, R* N P( b( I/ _
assign axr1 = axr0;
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|. W( V: H- c" `- X; ^' K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & B6 V2 ^; ?" ^' d" ~
static void McASPI2SConfigure(void)
- i. z0 ^! [4 u! F# @% v h! f% X+ A, Z{
9 @1 I" a% t' M. U8 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 p1 N) b4 w0 c E4 l1 ?4 kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 y6 T, h' u2 x( D' Q( J3 v; W3 A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ P5 p9 [; V0 @2 H3 t. S" | r1 r aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 S, s% [, z6 z. I% Y6 o( S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 Y& h3 S5 @# O, C, e* {MCASP_RX_MODE_DMA);# W, L6 h& s& }& s+ g8 O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," e/ L4 Z- n7 t) E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 [8 d* k4 j% n X$ cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , T6 k1 G% }2 f- }% q/ \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& g5 p$ z+ A' E0 w& {$ @ U3 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 d, _$ G' w! r4 y, iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( Z! S) n5 i& u& `+ p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" G1 Z/ W; v5 w# @! ]1 k- x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 Z4 `# Z: ]9 |/ j. @2 X9 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: i$ F' P, N: N! d
0x00, 0xFF); /* configure the clock for transmitter */8 r4 J! E* B3 R# ~; O" K* U! i G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 Z" V7 ^0 A+ A$ l% BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ \ a3 z! O- y! Z: K! h2 E7 r/ r) FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# G$ T# I9 ^- \8 j% z0x00, 0xFF);) B, F) T1 k/ U( O& v! ]. I. F8 h
8 ]- ]8 O& f* G& @$ Z/ O/* Enable synchronization of RX and TX sections */ 2 h- C; M' F' Y& A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" j2 K/ g' t0 ^; m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 e1 Q& e. G" ]* X8 Q5 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 m7 @& A/ {5 J0 B# g8 c5 q5 I** Set the serializers, Currently only one serializer is set as
: i. ~! e) x# L* z$ Y5 i! D** transmitter and one serializer as receiver. `/ t8 Q- f( l" K
*/
3 g8 ^& ^! Q3 T4 Y! N) u8 I' D+ xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( g7 A( T m. i4 z4 r8 L' ]7 A" BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) v* B6 ]- \6 ]$ k) E
** Configure the McASP pins " }! S) H4 w) A2 g& Q" x
** Input - Frame Sync, Clock and Serializer Rx
& W/ d7 |7 c C$ I, P z1 C3 [** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; |7 H) H6 k& u3 |3 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ ?2 ?- o4 c g; Z1 B# C( LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 v, E; F4 X! d1 ~/ b2 S2 g1 T
| MCASP_PIN_ACLKX
: G7 C4 U# z# o2 N' {" `| MCASP_PIN_AHCLKX
/ L) X8 A" E E0 M( z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 L2 L' g9 N# r5 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; H7 g" q9 M, m| MCASP_TX_CLKFAIL ' u+ j+ O4 w& Y8 H. I2 X1 Q) v) N, a
| MCASP_TX_SYNCERROR2 ]1 u* w/ ~; H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & |& l( p* U6 n6 P9 I
| MCASP_RX_CLKFAIL
8 ?$ R. h% U4 a1 z3 m| MCASP_RX_SYNCERROR ( C$ n: |/ b4 ^: b4 e
| MCASP_RX_OVERRUN);
( G9 R. @) d/ N} static void I2SDataTxRxActivate(void)
# }, m6 G- e' n2 c/ f{
* ~; O+ j* d4 y w3 D3 L8 o: B/* Start the clocks */
7 J2 O# A6 P. cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ T- p5 U4 V Z1 V5 p1 c/ P# x& V6 O2 qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ m* c2 q! Y4 R1 b t$ ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, |0 Y) i* h2 |% y. _0 `8 NEDMA3_TRIG_MODE_EVENT);
4 s8 h9 z0 s E. `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ X9 ~2 Z( o# u kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% Y2 ]3 T) ?, rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; p7 u* \/ R) q4 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ x, f; f& v" K1 q* R6 F. Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& k' b5 h) H" J* F4 Z0 g2 q+ DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; I0 d0 [5 f- ]$ O5 \1 gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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8 G) S/ }7 B. v( f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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