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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, d! b* `$ R. ~. v6 S* f) ~ p! q, u
input mcasp_ahclkx,
5 B. T- v3 _1 x- p% n1 |- n+ K& {input mcasp_aclkx,% x+ h! R+ T# B6 ?% Y9 t
input axr0,
* J' d8 h7 d3 W$ ~* P) h$ A/ Y s& b; T/ _7 `; x! q$ a: p% K: P7 q
output mcasp_afsr,8 q- r" p ?' k: U
output mcasp_ahclkr,
& d8 [+ Y' N" p' b. Loutput mcasp_aclkr, D/ w i/ A: {' q9 W2 W
output axr1, O- Y/ |4 [/ A4 X! U1 Z
assign mcasp_afsr = mcasp_afsx;
Y6 S* A% [( Sassign mcasp_aclkr = mcasp_aclkx;
& c, i2 T4 g! @* k3 N9 X( Hassign mcasp_ahclkr = mcasp_ahclkx;) B7 g4 U6 e. \) Y$ n& G8 w
assign axr1 = axr0; 9 m' h( u s1 P7 F$ B
! T4 h. o2 E6 S7 D) L- b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! c1 R( S' i' \8 S, P" a) Bstatic void McASPI2SConfigure(void)
) A; z2 O7 e, \/ J/ K{) H, @( H. g* X+ \6 l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" D3 J8 O$ Q4 a/ dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 ^: w5 H5 X. ~, [! o# l: w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 b- {* {. \! x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* P7 x' [! D0 Q* U h6 r/ A) T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ E$ G1 C7 A7 @- F# f+ L; d
MCASP_RX_MODE_DMA);$ r# Y- S% R- C# _' A A7 H% Q% Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" [4 u! O8 l+ g. o5 q! mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# ^2 y0 A% o$ O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ R7 N" j8 {; f: EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ f& Z0 |% k; j4 L- \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 S/ y" s% F- }$ F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 B+ c+ V9 ~" t9 W8 \ \! D# o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# P8 o5 Y5 Q6 h$ K4 `7 ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ b% m( a* v$ ]' F VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, ?. o; x u- J$ ~! m0x00, 0xFF); /* configure the clock for transmitter */7 a# z: T$ B- D( o% ?( i) k0 Y6 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 m6 x( j' t' ?" v/ x& \" R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # f+ T4 @& ]1 Y9 `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 [& d+ Z& B. V$ R0x00, 0xFF);4 ]5 S- z/ t+ l# ~' ]
9 z G( M% @' V5 h5 p, G! \' L* u# ?
/* Enable synchronization of RX and TX sections */ $ e8 l, ? ?9 O" O4 Q( }4 B2 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' p& e* |& @- P9 l# v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- A; z4 j' u% [5 Z) K1 }8 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- j6 g8 H) V0 t
** Set the serializers, Currently only one serializer is set as
+ `8 m; k0 \2 j% `, A! I; j9 L** transmitter and one serializer as receiver.; o. h( b9 O3 p7 I1 G
*/, i& } Z+ C& z- v/ ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ H2 T6 q2 S6 h- s- WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ l# W: j5 L2 I, a% i** Configure the McASP pins
: i2 w1 y2 t. L% U3 ^4 A @: G$ n** Input - Frame Sync, Clock and Serializer Rx: V+ _- O! z. @) w/ _; r
** Output - Serializer Tx is connected to the input of the codec + N$ b5 W8 a3 f; u. d
*/
: L1 [. r% `* \& b' B! CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ X/ G1 c+ V6 K, gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 {, N, E3 O$ JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 M. j" Z- b- o7 }1 j
| MCASP_PIN_ACLKX* b! \* D4 ^8 Q5 m( @
| MCASP_PIN_AHCLKX+ X( H- n' p9 j& x/ ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ }+ ?; S/ x) q, z' \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& d$ Z) E4 u* Z8 T| MCASP_TX_CLKFAIL . d6 d l# X& O# M7 G! H
| MCASP_TX_SYNCERROR+ u" C1 q) \2 C4 G5 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * Q1 `, R' H9 u# P
| MCASP_RX_CLKFAIL. O& ^% D2 w! |1 f3 {
| MCASP_RX_SYNCERROR " C' | {2 K; R2 l! W7 `
| MCASP_RX_OVERRUN);
) q* u$ ~ P0 W} static void I2SDataTxRxActivate(void)) R$ d! T. L: ~. s
{; F- t6 ~* R1 I! [9 Z; t
/* Start the clocks */4 P6 R8 ~0 a0 F. X; W% I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. E d( e& l: }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 A8 [+ q$ w, Q7 E2 U8 @% E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 e+ i/ ? {& h
EDMA3_TRIG_MODE_EVENT);4 V, @$ L2 B5 d$ m. U/ {! o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . D; w/ Y" r5 [0 s ^' f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, H% ^1 f9 x: d# d. H8 Z5 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 \# b9 ^7 F/ N; E q1 N- zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' d" v: t9 M$ ?# m' X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' X3 @" `% }6 Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! ~, d; \7 }0 \0 `0 E9 J5 kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- R% \8 ~0 i6 A}
; N2 r Z9 C9 R; V, x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # W, p0 R5 F2 ~1 ?- x3 `$ D! T
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