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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 c$ Y7 l. J5 w8 N. V4 C
input mcasp_ahclkx,
\0 i* `3 v) P3 v, [, O Uinput mcasp_aclkx,$ R7 }* D3 q: g+ |; ]
input axr0,* `& n2 B/ J0 ^# {
1 |& b2 S% O- r7 Moutput mcasp_afsr,! N) m3 O6 C; ~
output mcasp_ahclkr,
* N. w& w3 z) @8 m+ i& L' I0 K% v, toutput mcasp_aclkr,1 ]% U: ]& O+ f* w
output axr1,( `) r; g# [1 }) U! W0 g& Q
assign mcasp_afsr = mcasp_afsx;5 k' U: g! Y* N+ D* l
assign mcasp_aclkr = mcasp_aclkx;
4 U. d* ~; m' @0 U7 cassign mcasp_ahclkr = mcasp_ahclkx;1 [, f& A2 C7 S$ F- E
assign axr1 = axr0; ' F3 R, f+ v8 E6 B$ D( S
1 R/ }& F {! k* A5 P# z/ c1 a: C8 Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ ]. S: z* t3 q, y
static void McASPI2SConfigure(void)
! H/ t" U" ]; k9 x2 v{
5 }7 c5 z; K& N6 F1 r* [McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 v* h' L- @. c* ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 i/ E/ _1 r$ `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- i0 y, ~0 L; A; \! Z* oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: ~1 \ X/ V2 F: E u: R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& z% t& f% b8 Z! F
MCASP_RX_MODE_DMA);
8 Q8 f# U" W) C0 GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) E1 T$ A! o9 {7 |6 C8 } r" s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 {5 } I1 q# `8 u- n( }* J9 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) ^4 d' l u7 }$ E4 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' I0 b; v& h7 ?" E b6 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , S1 b- B6 t! C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ T/ R0 P7 U" B: J( Y" x& a0 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 c" y9 a, F) T# e8 R" R6 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % `$ |- F4 F2 y: g, O# x D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' E2 b7 o, E3 u: a# {1 J" X0x00, 0xFF); /* configure the clock for transmitter */: O2 o4 x; W( Q! @, Q, K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* K) ^8 }6 h2 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. S# d. C4 c1 F' v5 yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ g9 A+ g1 a* i
0x00, 0xFF);$ V. z. J- r# ?
0 O$ J. ?" a4 E
/* Enable synchronization of RX and TX sections */
1 V9 L3 P7 I& E5 m; h1 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// ? l# q2 G; \" K6 a$ `( q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: `4 V5 Z: m2 U& bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 J& |5 ]" }( L. n0 G** Set the serializers, Currently only one serializer is set as
/ ?6 o$ L; @& L7 ]** transmitter and one serializer as receiver.! t7 z8 V( Z7 a7 h1 A t9 N* F
*/
8 G1 p; P* i7 I! }4 w0 HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 k8 L! t; k! W3 K+ x& C3 m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- d7 C9 F+ Z' p5 j3 W* C** Configure the McASP pins - s0 N) D- {+ p1 d, ^/ Y% b( o: g
** Input - Frame Sync, Clock and Serializer Rx
+ b6 C3 h% O8 O4 n& @** Output - Serializer Tx is connected to the input of the codec 7 G9 e Q& B% K2 L: h2 }
*/6 L+ U/ |8 f% H" ?6 e5 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) j. a7 W! _" P1 w- b% Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 P- q3 T- c# @6 d, Z0 S7 v. x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# Q- ?2 i- e9 S. n+ _- z| MCASP_PIN_ACLKX3 X+ f1 g' H$ x7 \: |# f
| MCASP_PIN_AHCLKX
8 N" P7 B" {% [. D$ T7 q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! N$ F0 ~% s- U( a! Y1 ]+ Q0 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 ^# z% z# t) G. `# O| MCASP_TX_CLKFAIL / `5 i4 Z1 s, y7 X! _: V
| MCASP_TX_SYNCERROR
" K3 E% c# q [( N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 A$ M2 S7 a0 G8 S, J1 s' j. k: j
| MCASP_RX_CLKFAIL$ }: h( F0 T A& f, I; h1 D8 I& A
| MCASP_RX_SYNCERROR
, K8 c' p3 R6 F$ o% j2 l/ w! T| MCASP_RX_OVERRUN);
3 | p5 Y" w( h3 g} static void I2SDataTxRxActivate(void)+ W: g. {9 Z3 b0 [4 g
{) L" k1 |. m) r* j
/* Start the clocks */
, X; L/ u3 t6 s: y" ?. SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 ^2 W) E3 K: U3 l2 x' k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' N; A7 G l9 u* v! y4 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. u, V$ A7 i% \6 b* ~
EDMA3_TRIG_MODE_EVENT);- R3 I5 C, ]$ d5 e4 j$ _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- F4 f/ @" Z- a7 P8 X; pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 Q; a: \' x4 N% iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& {& \7 r" X: n8 H! _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 A& y! r8 z! ^) lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* k+ Z+ K! i: I" g! kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
q$ N; k6 D3 Z6 z) mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" R& v3 G# `+ b* }' v}
9 X9 s4 e0 _3 L% F L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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