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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 v2 \" I8 G. ?# finput mcasp_ahclkx,
6 K% H h! q/ c# N+ Jinput mcasp_aclkx,4 y9 y# [# X3 Z2 h
input axr0,
- F; t) W" P+ `
. J" K% ~& y) [5 w9 E! Uoutput mcasp_afsr,* P! t3 e1 ?8 X( j4 V" @
output mcasp_ahclkr,
" t4 B2 U2 c/ C- A( r. Y, eoutput mcasp_aclkr,
/ g/ Q# Z' |8 A8 ]4 u1 woutput axr1,
7 h# i" N" Y( w) H% C" { assign mcasp_afsr = mcasp_afsx;
: p2 U. v) k' ?8 n% a2 d1 E2 r; ]assign mcasp_aclkr = mcasp_aclkx;
& X9 ]$ b( { n; ]assign mcasp_ahclkr = mcasp_ahclkx;5 m u, x9 F' ?2 L5 N5 d3 }7 a+ c
assign axr1 = axr0; : O+ W7 ]$ j6 d7 b" q
' J% H6 z( f5 W$ p: c4 Q: i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / c# z0 n: O/ j5 R/ M' \, d
static void McASPI2SConfigure(void)) F: N! q4 m5 E$ C
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- v: u5 A. s( CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: p( \+ V u3 v4 a& j5 F; I' KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, }! b4 u3 x, b; f8 V" M! g, p3 H- z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' Y6 g" L4 W7 S2 _* E" h3 L: ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, ~- Y( a6 D+ E# L
MCASP_RX_MODE_DMA);, }+ u' E9 `: }1 T% @- D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 I) d ?/ e3 _2 g9 g2 B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) m% K; B" ~5 r5 d$ {* P( h. b8 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, j5 ?4 F1 _# f% j @+ g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- ~ }2 k" P- Y0 ~5 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
t2 J0 I$ h3 B; g" W& VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 w6 s! Y; a, s! W/ l: L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- I+ ?$ z, P8 ~; c. D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' \' f7 u r, |$ J/ H- L# |8 q' k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* a. w0 T9 k& c* ?3 a; b
0x00, 0xFF); /* configure the clock for transmitter */
% C+ J/ E/ s/ W3 f1 D, XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 n, o' y* k7 W1 r8 ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, I& i' o. b! Q. C: @- _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' v0 e6 D7 L& J I0x00, 0xFF);
2 m3 {, x! W" l) v$ V! O8 P( ?2 z, N. a0 W3 X+ g& V4 G1 |
/* Enable synchronization of RX and TX sections */ * D, a: w# l3 N- L1 b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: [" @4 g) ^+ p0 Y/ sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ `/ I# G j& p0 H8 \& b qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 a& T& d0 p; z" _/ _** Set the serializers, Currently only one serializer is set as2 c* u _* i* K4 m2 d
** transmitter and one serializer as receiver.. H: {) n* }) |+ }* G
*/
; }! j0 L* U& o3 M# n% |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ ~ y2 s& E0 ?; F3 QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 E) R' }5 ] `- m) \; c/ m** Configure the McASP pins . _' ?: l; b0 V* l: F3 \
** Input - Frame Sync, Clock and Serializer Rx
7 |/ C5 b- v3 }6 k** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) A! E; u; a# J( M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ K) w) F1 \2 u- v! K0 ?, q b! y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, O' `/ y1 w$ e2 w4 \( a
| MCASP_PIN_ACLKX
/ |4 }' z; a! m) ^2 N| MCASP_PIN_AHCLKX W" e, j: G4 p) e4 D' X9 J- r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' `5 b0 C$ F5 V' Q3 f. ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 M: n2 l3 p x5 G4 G5 X3 E| MCASP_TX_CLKFAIL 1 v, @ d( u5 ^0 O7 F
| MCASP_TX_SYNCERROR* c& [7 R* \7 X/ I" s# P) y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 x# h, q# m8 Y! F; f( m8 I" E* b
| MCASP_RX_CLKFAIL; i; n* w. b+ n* S7 |5 I
| MCASP_RX_SYNCERROR
1 t( k! k+ Y! l) ^. ~| MCASP_RX_OVERRUN);
) [9 C s9 X" q& H( Q} static void I2SDataTxRxActivate(void)$ e/ |+ s: Y3 R7 D; ^, X5 Q! ^% l
{
+ q f! c+ F2 A [) _+ M: T" N3 \' w( |/* Start the clocks */
% C& m, u! P( ~( a1 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% J; A* n5 b% x9 M- O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" x" W B3 R x4 X z7 @2 x. J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( U0 I* D# v6 u Z$ U* KEDMA3_TRIG_MODE_EVENT);0 {0 {0 p1 [3 o- E8 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" @: S1 S* p( k* q+ i" OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" T0 X v( ?; F% L- P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- }& P( v1 Z3 U, Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) n; M. Q; X" ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: Y0 z8 Q9 Z- y: E2 `8 T* ?3 I( l% @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 J9 J0 V, a! ?& NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& w& v- O3 i1 G: B2 y3 H* L8 [
} : X+ L& K6 d; t7 Q( A! m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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