|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" u/ b- T4 H3 i5 binput mcasp_ahclkx,
1 N# R4 c$ G, h8 R5 f, Ninput mcasp_aclkx,
% W& b+ J% F d& l/ i- o! h) Ninput axr0,
4 k) w" t8 Q. G/ O, ^( j0 }: ]7 t4 t
4 X, o" F, n+ j' j" @4 R. J! toutput mcasp_afsr,
- e" ?. F" G5 i! l) N+ p* _output mcasp_ahclkr,
( q! d! W8 k4 B/ U. E$ B3 @output mcasp_aclkr,
( H( d8 z. n$ S f6 ?! U# X* Voutput axr1,/ B0 h- p: K) |4 P1 f2 d
assign mcasp_afsr = mcasp_afsx;
8 u* s1 o+ x$ l: X* Cassign mcasp_aclkr = mcasp_aclkx;
, A; a: q( q( Qassign mcasp_ahclkr = mcasp_ahclkx;6 a) F+ i7 t' p5 U
assign axr1 = axr0;
2 Z" F) w* M7 w, _4 U q1 B5 a, V( }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / \2 \# `% N6 G
static void McASPI2SConfigure(void)
/ g' `- v7 b+ o0 y/ B* G' H{
, R7 Z a" O2 C/ x2 q; ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);- q( v4 H0 X! x1 [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; k- l( V h3 H7 u* m" c: V6 B' M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ o: }2 A" w8 ]" O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- m( N( W/ n. }2 t. U% M( I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 t1 w! E8 ^: E$ l$ @2 @/ TMCASP_RX_MODE_DMA);3 D2 ?( M) a* W8 h' ~) x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, ~5 \; Z, F1 F6 q. Z" W9 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- ~: z6 f( Y/ L6 sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & k" d! T+ b# A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% P7 `+ d+ I$ J4 B- AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 r) \) r" T1 v. y0 o% x% F! W) T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 E+ ]' l% m# B6 F0 d6 {2 l) i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' y4 w6 m* t, @, y8 ^4 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 l p# B( k9 V4 v% p" @+ B7 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 p6 Z; Z6 ]2 t' h) B0 O. e( T: u0x00, 0xFF); /* configure the clock for transmitter */
. k% k' O' S# |* _0 sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 Z/ f+ U5 z# ~, [- \1 F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; N g# _+ [5 b* g( _4 Y1 Y0 x. MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& c1 e: |4 p8 D7 F; y2 S' h% S0x00, 0xFF);
2 ^& A; @" U; ?+ _, d6 j. C( Y8 T B5 M' e. z" m' V! C' A
/* Enable synchronization of RX and TX sections */ & W# l2 z; E. k! ?) K( {" G4 l- }- i, p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 s6 p: |3 {# |$ r$ X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' K5 f1 t& [ M0 o# ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ [! I: R4 J" v! O: G y, l: z) B** Set the serializers, Currently only one serializer is set as8 A# b; K) S3 Q' m
** transmitter and one serializer as receiver.# k* N- ?( Z3 B/ N% Q
*/
8 C( e8 v1 H1 c, r( \7 q4 SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 r# }' N9 {8 `+ c: U' X. U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& _7 g/ a6 e' F9 D( |1 B# W
** Configure the McASP pins W% B. Y2 R1 D9 o
** Input - Frame Sync, Clock and Serializer Rx! `0 p- i4 X3 O& e1 Y& D" d
** Output - Serializer Tx is connected to the input of the codec " }1 p0 h8 G/ O( \/ }8 m$ W3 r+ n
*/$ [/ }4 K, }5 @. H! y0 W' B; u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. \7 w( Y' y( cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 j0 ], U# a8 ?8 |0 v" T( ^- zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 e3 k* [4 O$ x| MCASP_PIN_ACLKX
. y, B2 B; _3 o: v2 e' o| MCASP_PIN_AHCLKX
# ?6 l& \/ g6 F+ O- n* {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ O7 X1 A5 j7 }% c1 z. t3 w* u7 L% k; B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) C0 [4 ]! h4 S$ u8 v
| MCASP_TX_CLKFAIL * i2 ~6 w$ ~2 y+ w, O+ _
| MCASP_TX_SYNCERROR
0 [) R* o' a; e' b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 Z) b: }/ V# g% _ z
| MCASP_RX_CLKFAIL
: {: v, Q) q3 T% {+ y7 {) q| MCASP_RX_SYNCERROR
7 ~# M) [+ W6 r+ h- E( y| MCASP_RX_OVERRUN);
; @; W6 o ]6 r x3 a S" k} static void I2SDataTxRxActivate(void)
4 d$ y. `& w9 q; T& T, q{
f' ~4 Q) B/ M# w/* Start the clocks */
9 E% T3 k2 p. C1 [* ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# u) @% B: g$ H4 K1 WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 S) j7 H9 v2 m) ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 [2 L4 ]& q7 }2 N% R0 o
EDMA3_TRIG_MODE_EVENT);9 _, k2 N+ I% l* y( H$ v: K# J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ |& W( ?2 X; |: mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ E$ U$ O+ ]" u- o! b* P$ t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, l6 L/ b/ O5 M5 z: `; P' M$ V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 S# a8 M" z0 g4 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! \7 M+ Z; Q4 ^4 D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& T6 l4 r7 Q& N- u; }- J) bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ N6 Z" o( j ], C$ }! x4 {$ `} 0 Z2 ^. ^7 } V; M+ `& M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 a. i5 |* D. m. q- q1 F$ r |