|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
t% n' N5 A# ~input mcasp_ahclkx,
4 Q4 c4 g' P$ O$ p% j5 iinput mcasp_aclkx,
# U+ w: v! H, oinput axr0,. y. C) W \8 t" e$ R% D6 O
( j( J. G7 Q/ \3 q, e& h7 Goutput mcasp_afsr,1 A; y R/ t1 k* e
output mcasp_ahclkr,- {. d- S7 s9 u9 A3 d# W. K# s
output mcasp_aclkr,$ x/ P" ^8 G. X1 k7 \
output axr1,) }& u4 }8 u6 ~4 J
assign mcasp_afsr = mcasp_afsx;
1 S: k6 E, R! K0 x0 L5 g: Jassign mcasp_aclkr = mcasp_aclkx;
# s0 d- w* P9 `8 ^ v) k7 R2 fassign mcasp_ahclkr = mcasp_ahclkx;
, D. J. K$ ^- ]6 N) \" X% V& passign axr1 = axr0; 8 a) H" H& D7 B v4 k) u5 |0 V! l" d
y: t. u, e7 q( q! A* `4 r+ \( U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( ~$ }5 |. U6 Q8 W2 Y& fstatic void McASPI2SConfigure(void)3 P6 h! M: G7 G4 b
{
% H, @- n* n* t' q! K) nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
T( [' y9 S) p$ u/ I% HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 |; {6 A) ?2 z& b6 Q# fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# W% j+ h4 i) r* {/ [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
@8 _' g! ~' A4 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ v! w8 J( u, }* M: U% U$ @) L, J
MCASP_RX_MODE_DMA);
( @: X A" v! M3 P; }) _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" L: S3 s& c6 j5 S$ hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ }" v4 |5 }8 N& z" D2 b! lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) r" b' | ~1 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 F& w! o% |0 J i- l* kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 q ^5 E( \# A- A1 h, y7 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ a3 z# N! p7 P* x$ h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( S$ b; y6 a. _ I, q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( U) G/ h5 A, ?, N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, X4 A' }' d9 O+ e. [0 V2 {& ^0x00, 0xFF); /* configure the clock for transmitter */
9 u) o5 g4 [' jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' F# N0 h& b- ]6 U3 iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 H% m4 v7 M$ Z* z! ~$ I2 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* J% M( T/ k0 e5 O0x00, 0xFF);. Z: y4 ?, M" \% `) R" u
* v* s2 j4 X" e# ]# u% A! {/* Enable synchronization of RX and TX sections */ " {! L1 R$ h4 i: {6 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* ` |0 u. L1 B9 r4 X) ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 {6 C' D- i3 i2 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 w9 @# T% z1 r
** Set the serializers, Currently only one serializer is set as
1 l' T2 Q4 c3 d) Y) m** transmitter and one serializer as receiver.2 a' a6 y9 C+ k% d( y4 M
*/1 k9 F1 n/ P* F% y- ^9 S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 @# x5 P. |4 a8 h3 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 B: s' V' [* O5 `* _
** Configure the McASP pins
; e* M% T% E q8 v** Input - Frame Sync, Clock and Serializer Rx
2 X1 E* w9 N4 Z** Output - Serializer Tx is connected to the input of the codec
- s5 d7 }: y7 j1 F5 `# ^*/
. E& o7 V& |! @) j% G7 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 k* e' a3 f9 l2 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 c5 H9 w. T6 f& DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 Q0 ~: F# L+ i6 ?. b
| MCASP_PIN_ACLKX7 C$ t# \ J$ g1 U% t0 P0 C% q* G
| MCASP_PIN_AHCLKX
) T$ r1 H9 Y) a( b. n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 q5 a+ C: I& O# t5 A2 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % S7 h3 U# b0 K& [9 k
| MCASP_TX_CLKFAIL 6 O: b4 @7 b0 x
| MCASP_TX_SYNCERROR
: j) r/ U8 f, I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; w7 F6 l+ ? S t. t) C
| MCASP_RX_CLKFAIL
, x! ^* E0 \8 {# S* |3 s! V6 K3 R| MCASP_RX_SYNCERROR ; q9 G& x5 b8 `( ^/ E: d. }
| MCASP_RX_OVERRUN);2 T; \1 N, V: @, `1 Q/ h n
} static void I2SDataTxRxActivate(void)7 J7 v6 T3 K) W6 J4 C I' K
{7 m4 c4 N$ B! S
/* Start the clocks */& o# C% |4 y. l* ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) g+ V% U* g1 Y6 R( ]" GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 v% H6 ^8 q a$ X: ^' ~0 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% w/ O" P' ^ j" f
EDMA3_TRIG_MODE_EVENT);
- S1 Z) V/ M9 @( c3 n1 J8 |- @# |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! B! w( ?) |" ] {5 L8 Q* N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: K; A" n D8 A8 Q! d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 t2 l4 ]% }. V) g' v4 M5 ?5 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! Q. q8 W4 D3 ]( w) n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" Q. }9 n5 H6 h! s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; H0 _! w! Q* V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 U! f. ^8 \7 A$ ]" {9 n}
: d0 d I w, w: \- C' G2 J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
5 z4 I4 B$ `2 y0 b9 Z: s7 g2 S/ U |