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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, s+ e' }0 H3 t( ?
input mcasp_ahclkx,$ H3 M) D" h% K( C2 p9 e" ]
input mcasp_aclkx,
0 u4 V5 w4 h+ L2 D% o$ K0 v$ Ainput axr0,0 S G+ B" j3 W) |, k1 ]) U: V
: w2 t# C5 m) i# s; j( @
output mcasp_afsr,
% E' o3 R; W* I+ {output mcasp_ahclkr,
& I( _1 [0 B" ^5 koutput mcasp_aclkr,5 ]% ~& C4 d& g
output axr1,
! w# O6 Z5 P* I5 }* _/ h, t assign mcasp_afsr = mcasp_afsx;
9 Q7 n* ^9 X$ T! _8 f: d! c9 X& Zassign mcasp_aclkr = mcasp_aclkx;
6 ^: V) P& Z' E1 \: N9 p9 O; X4 ~assign mcasp_ahclkr = mcasp_ahclkx;
; {& f( @, l' c' aassign axr1 = axr0; " z4 F' c9 o3 R+ s* u
& ^. K! x, b* }( o" n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . M# P3 w/ q* O9 ^2 Z2 A
static void McASPI2SConfigure(void)6 j( p( E- i3 {% U
{
2 b$ s X+ Q# H: P/ ~8 W! n( X+ C; TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' C% O7 S Z* Z/ U' @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ p! r c8 X) Z; JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) ^1 @& T+ k2 S8 T; }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* }: t+ Z: g. D DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- J c! ]% y" p6 Q- R5 sMCASP_RX_MODE_DMA);; P. t2 s+ v i5 M! P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 V$ d8 y4 e8 e3 v& I% V2 ^$ P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: m, Z) l, T0 c) l- |9 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 {9 Z; s/ A# S- |6 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! U3 i' [0 W! e" Y1 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( N7 n X5 }/ T3 z) Q+ E9 g. K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 N( ?5 p; V# }& YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* @0 |* e( F+ g5 G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ z5 B; T. ~. K5 ` xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 |' t: m/ O+ f% H5 R+ I0x00, 0xFF); /* configure the clock for transmitter */
: D O0 q* j* {1 \7 lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 {- F2 K$ q; ] C4 r! ^1 L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 ?5 U- F/ ~1 |& R4 d; d1 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ P, @% @% r) g8 g
0x00, 0xFF);
$ U# r) z7 e$ S3 \, b% a: l! s6 |2 P
/* Enable synchronization of RX and TX sections */
) O; d4 W. m9 C9 oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 P( ? H/ c. c4 L% ~. t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 ~! g& ~4 m5 d2 `- f: ^( CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! [8 ?$ b! R2 V) }* Y7 X7 u
** Set the serializers, Currently only one serializer is set as; [3 G+ l- C/ s' V' u$ Y8 ^; ?( U4 X
** transmitter and one serializer as receiver.
c: Q3 `, E- s, a* w* u. n/ t*/
" E; ^& x6 z! ?7 ]$ u$ SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. N9 M6 V1 I4 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. B; ]- D) ?1 B3 p2 l3 z
** Configure the McASP pins
9 q, Q6 `& P* R8 w' {& `9 |** Input - Frame Sync, Clock and Serializer Rx' @! d$ m# l; Y O
** Output - Serializer Tx is connected to the input of the codec ; Z' ]7 K% a$ y J
*/ M9 i6 h/ q* V a! @; D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, S! {0 ]1 V+ H$ o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 H1 i, n7 }+ d' N0 y8 }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: G& P+ ^/ O6 Y3 C1 j
| MCASP_PIN_ACLKX0 S0 R' j- ?' m! q2 z
| MCASP_PIN_AHCLKX" W; @- p U% U* Z4 H2 a9 C) `/ B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* l2 _9 {' n' w" I% L: P# M6 `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 y4 j, G% R8 J6 N! ?& P$ ^+ N0 D% u. I| MCASP_TX_CLKFAIL
9 \) c, k* L' T5 g* i| MCASP_TX_SYNCERROR/ x/ W6 v3 Z/ q* y! n1 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( c& W7 Q; E1 h: M
| MCASP_RX_CLKFAIL
# o, b( P. T2 X0 A& A| MCASP_RX_SYNCERROR # ?! ] p# N. r- T5 Q5 R4 t/ ]
| MCASP_RX_OVERRUN);! n2 M: |3 {: J& p$ A
} static void I2SDataTxRxActivate(void)& h8 K5 C5 p) ] F8 U l
{
+ C% Y1 Q: J# I, v; a8 M/* Start the clocks */5 ~ Q1 i8 \" L% N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 ~0 }6 U6 I! ^: U- i- D6 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ f3 M1 M+ L$ f* IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- f* J# C! E3 A+ s% L) V9 O
EDMA3_TRIG_MODE_EVENT);
% Q/ a* b( w8 h3 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- G( I: _2 P9 G9 [) S! l1 CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 k# m/ j8 q* T: K. eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. v5 E8 h, D: ]6 z1 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 }4 |2 {) V# B5 q4 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; u Y, A$ S$ i; D0 V6 m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 w+ N3 L) } _# ]6 b; Y3 E# k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( w0 e. O; ~( |- v/ [}
; d3 b# o, ~4 P8 v4 e. D* F& l# p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + N2 ^ f5 V7 S& X) T. g2 H
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