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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ J3 X- b2 |. Q* C' |
input mcasp_ahclkx,
4 Y4 i1 Z+ P+ q2 [/ r# X. D9 z* Kinput mcasp_aclkx,
$ P W. b* @/ Xinput axr0,2 q1 C$ q$ o: r2 N" d& S$ M
+ N1 T2 @: d+ y( {, noutput mcasp_afsr,8 g- l9 A; H& y* p
output mcasp_ahclkr,
; o* b% B0 C. Y: p9 qoutput mcasp_aclkr,
# H# Y! T! w; k! Aoutput axr1,
( ?) N3 x2 z1 w/ j! C assign mcasp_afsr = mcasp_afsx;7 ^3 |2 Q3 [/ l2 B( |: M: c
assign mcasp_aclkr = mcasp_aclkx;$ @ D7 g: P2 D. G' M! M+ {, I
assign mcasp_ahclkr = mcasp_ahclkx;
) _+ h, c7 j+ i0 k- M! Xassign axr1 = axr0; ! j' J0 n; ? q2 L- J o; h
d5 {) \, h0 @& [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* c5 e K( k- ^6 M4 Cstatic void McASPI2SConfigure(void)
[8 U+ t" m; u{
* k* `# o- L& \/ ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 M, U f5 t+ J4 H2 s- P, W" zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 L$ I9 X; w' D* m5 ~# yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 B, v7 D0 i. E( Q: O8 P. D/ X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) k9 s! X7 { x9 r b& j' \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( w- W3 l8 L1 @# h5 C5 V
MCASP_RX_MODE_DMA);( S1 ?1 D$ i) o) g5 O8 y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 p! p0 ^: F% j& s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( S( F8 r# j- e. D( bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 D, ~3 Z+ A9 HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 Z- Q/ c9 ?0 a# s% X+ yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 W$ p) z& E; s5 Y, E/ z. r1 ?/ eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, T* r/ t% l' Q* o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 d+ K" C# t) w. p5 u6 zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! i5 z0 J, H% V7 K" I* j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; ?; q4 z1 |( y5 x0x00, 0xFF); /* configure the clock for transmitter */% p; T* K' S' K- R# g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& E) a+ \3 o, e' pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 Y; b- q7 {# k+ [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' }* y4 D8 c/ }- V9 p7 S
0x00, 0xFF);# M* D& b8 E: A
9 _1 |; u+ G6 i0 U1 n$ \' E/* Enable synchronization of RX and TX sections */
- ~8 n/ X7 I& M4 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 J5 a" u6 N3 z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 S$ r' V# m8 H: R' O+ WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 m1 [- W) ~; C @3 i2 [
** Set the serializers, Currently only one serializer is set as
5 u1 a S( i* [; d" H) N** transmitter and one serializer as receiver.5 g+ z& F; B( z9 \" r- H
*/* N3 e2 B) S4 o! O" `2 ?. @3 ~; C. j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ \* m3 C/ W$ x9 u- r1 v! SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 O2 n4 M, k, m! e** Configure the McASP pins
5 w" a& M ]" I' s** Input - Frame Sync, Clock and Serializer Rx
w0 q9 v1 U$ k, t m- d** Output - Serializer Tx is connected to the input of the codec
; R& {2 P+ _4 g, Y8 w$ n*/
+ l' \4 {, G. e4 H3 w: MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* g- {% r+ ~! o1 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' T+ E* e1 U6 D" P. @$ dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 t: P. L" h& i1 M* V k
| MCASP_PIN_ACLKX
+ p: Y2 m0 H) v/ x| MCASP_PIN_AHCLKX
& d" P3 S* t1 n" c$ A0 {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ R, e4 D0 q" B4 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 D' s r2 g# H0 J; A# X- K3 D# f7 K- z| MCASP_TX_CLKFAIL
5 h) D* _$ n; S/ P" ]| MCASP_TX_SYNCERROR' A0 \5 R6 G- I# Q( [! X. k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! F$ T0 X0 i1 S/ `5 W9 {& t' C/ {| MCASP_RX_CLKFAIL* l" ~1 q3 G3 J# \; \# d
| MCASP_RX_SYNCERROR
2 T. l U7 E, m. k* z7 \& I; R| MCASP_RX_OVERRUN);4 }+ A' ] ~* M1 B
} static void I2SDataTxRxActivate(void), b8 \$ ]! |" [$ y+ w
{" w; O/ v4 y" b! m! j
/* Start the clocks */
, i- Q$ E: K0 N- VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ @9 x7 T. v: K! b" u# ?8 o2 EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 g( j' z5 U/ \9 r8 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 ]" |6 e5 y$ E1 V2 `" fEDMA3_TRIG_MODE_EVENT);2 q- [/ D' M; \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ R! V6 f+ J8 d' [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 I0 o ]9 V5 y- t7 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 p; q% I7 e6 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! ?1 h! f. J) q+ J9 y. O. pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 R6 U( h( K8 j! u/ @" WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 [, |, D, f# D( i, c; W$ N" \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 x% g @ z# |* z
}
# ^2 ?- E8 I3 b6 w+ n+ i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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