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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, u+ ]6 a& r, C7 | l0 X" W5 U
input mcasp_ahclkx,
4 s9 L% }: \- ginput mcasp_aclkx, Q l7 A/ P/ M9 z8 T" S% G; t0 ~
input axr0,6 @! W: J$ N/ H+ m. d; W @8 i
5 s- d' i& M* Voutput mcasp_afsr,, x, o% _; r9 ]$ P x
output mcasp_ahclkr,* C0 l6 H% L' n9 Y( _6 D6 K
output mcasp_aclkr,
: ?# h# o/ {. G* Q6 ?) aoutput axr1,
! R0 z Z1 e j/ C% w8 ? assign mcasp_afsr = mcasp_afsx;+ L$ A8 q* \& u- F
assign mcasp_aclkr = mcasp_aclkx;( i1 H* t, L5 U" O7 \, o1 U4 o) {
assign mcasp_ahclkr = mcasp_ahclkx;
4 q& m# l: f' gassign axr1 = axr0;
6 d" ^( q5 m0 X8 L
! P7 D7 T8 D) N$ a5 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 G1 q+ d4 E k/ B: T+ }2 \static void McASPI2SConfigure(void)
( E. p. p! f3 R! N. W( K+ I8 }{
- ^% C1 Z# I+ k, q' x, n6 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS); E% [# @0 X- R) y5 {' r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- K0 d+ X+ ]7 g- `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 i$ J( K, |- a9 G4 z2 ^0 H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. d' t K$ k' p* I } d# ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 C- G: q; m) n
MCASP_RX_MODE_DMA);
- p! K3 \4 q8 i9 W0 eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 y' r6 O# g0 I* _3 A% YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 o" k8 d1 o& [6 o# R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' _# P0 y: F$ \# `! N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 X! _+ J3 e% j/ A2 QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 Q% a u9 x4 q jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, _) y7 k5 C; b2 \' ^! Z7 Y: b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- T# w9 ^8 \& f8 R& u$ n1 }: t8 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " y p) J1 N2 l0 t' O; J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' W, I9 {+ {5 h) u8 E' m0x00, 0xFF); /* configure the clock for transmitter */' I7 C+ N1 ~7 R! I: c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 u( c: W% J l8 ` w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' T1 A, b3 ~ }) GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 j6 H% j% x7 y( {3 s6 B0x00, 0xFF);) ?2 b) ?8 K8 N! `
& d+ r* d* A, u4 K$ s# {
/* Enable synchronization of RX and TX sections */ 8 I& H% F5 `; `6 G j' X+ D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. J* {2 D2 [% \5 f7 a7 t, ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. x/ |* W* T6 u8 O8 @; `1 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 z/ e4 X6 i1 T( G** Set the serializers, Currently only one serializer is set as' @5 r. l' \) Q' E4 @9 J& T- P
** transmitter and one serializer as receiver.
C5 Q: X; P. r" A! e*/
# ^6 I; {" b1 r* d' IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 Y! j/ k' X$ e7 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# p+ W% H B! F) U* v, @& Z* J** Configure the McASP pins
2 H1 P8 _/ t$ n6 J6 E1 Z1 _' \6 P** Input - Frame Sync, Clock and Serializer Rx
$ c- G. a5 C1 r; Y** Output - Serializer Tx is connected to the input of the codec
+ \+ H3 D0 |) e( X- A+ r*/
% {# Z3 G. m9 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 o5 y" t- H M! B( O6 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ G" {- e" c! \7 s# h [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 O3 t% b9 U! u9 P& _4 G| MCASP_PIN_ACLKX
) P) ~- _7 @/ y- N| MCASP_PIN_AHCLKX8 D, _# n* \9 ?4 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' n% h% M; h! O& n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 {5 \- V3 K) h. E; b3 z| MCASP_TX_CLKFAIL
" E" I$ Q$ T- d, m5 k) y/ M| MCASP_TX_SYNCERROR
; q5 ?; r: j& G7 a* U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 F! U8 n! P! \' w6 e| MCASP_RX_CLKFAIL* `% j8 A! U ?/ c$ v" g
| MCASP_RX_SYNCERROR # \1 V! a$ @. f u. A2 S5 Y! m+ S5 T
| MCASP_RX_OVERRUN);
2 ^) c1 g% w2 v8 t4 i/ h7 ]} static void I2SDataTxRxActivate(void)
) a5 I5 ?$ W+ C+ Q i5 ]{: } M6 h6 ` P: F' {
/* Start the clocks */
- ~$ i- n! p3 Q, OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ w+ @7 S0 U0 q$ F- M5 z3 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 v# a) |2 a1 z4 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' B3 N" e9 v+ I. M4 Y& G- eEDMA3_TRIG_MODE_EVENT);
; g5 _- Y, x+ ~4 E$ |! REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 s$ K5 q# i, C3 V7 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 s% w) ^- w+ i2 M0 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 I; f6 K1 S; T |+ r' R; `7 |) e. y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 z% }2 p8 p4 }9 o) M3 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) C" [" S9 `8 W0 I3 r! X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ j+ L+ _: g0 [: x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ I! I% H9 R$ Z" b
}
+ z5 j* }# V6 K8 Q8 p" F. a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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