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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 l% D" W+ R- Z( jinput mcasp_ahclkx,
; |) D- f2 j) C1 p9 r; V% einput mcasp_aclkx,. v3 q# X8 O7 v* ]
input axr0,9 a+ t4 Y' u# Z: S
0 [; Z. C; r9 i' k: B
output mcasp_afsr,
7 M, b; q& C$ poutput mcasp_ahclkr,3 X9 `0 z: `$ [
output mcasp_aclkr,
. X0 F3 y# p" P: X/ a0 b( h" ^output axr1,
& W5 ^. |1 d2 G assign mcasp_afsr = mcasp_afsx;
$ i0 g2 F* H* kassign mcasp_aclkr = mcasp_aclkx;
7 ?2 j4 o9 v7 I. q) {1 ?0 r% Gassign mcasp_ahclkr = mcasp_ahclkx;
: @0 Y, @8 ]! G+ ]+ ~# vassign axr1 = axr0; # [3 e" A" F. I& p3 U( B
9 T% z' Q% r: t. L+ I$ o% e7 U5 L5 l: T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * A) k; L2 G4 h" T6 W! c1 s
static void McASPI2SConfigure(void)
' m( q/ n% J: z, d n2 L, A{7 T A4 Y) n: O' `/ W; [# I2 Q% B% A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 q0 T; T0 G4 Y( t; mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% [; g: ?: p9 x9 z/ G; T, Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 i6 g7 w# c# J! F; {, v7 @- uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% r) m# e) H. R) L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ ^) U) Y; f8 E$ c0 U
MCASP_RX_MODE_DMA);# D" a4 f4 a1 A+ a! \4 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- _) v' P, o! n2 M1 i6 x( fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ p8 Y' y* D8 d+ u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
`5 q$ g4 ]9 P; cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 ~3 i' t1 m5 d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: \* J5 C! A: VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ c; h/ v% R a3 E6 eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 d' e" R0 T- S+ p4 sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: W X- M; _: i0 a0 l( E/ }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! n- b7 k# ^0 g$ x m' q8 l- P6 M
0x00, 0xFF); /* configure the clock for transmitter */4 g9 b, b) v$ M2 V; _6 l) M1 L1 t4 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 m& {" v( x0 _+ q. K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ]/ v% E7 o! I& Y( C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 d$ i$ G. E* u5 n2 |. I1 M
0x00, 0xFF);
" Z0 B% t, O; E1 ~7 ]3 [! J
- u/ ~' { g! H0 @/* Enable synchronization of RX and TX sections */
- R9 _4 M( H+ R1 ~8 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 ?: c5 L) I" M3 K" c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ [6 N% c8 P; Z9 s/ K$ h# u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* {* x5 B- B* T% g7 l" u8 Z- [
** Set the serializers, Currently only one serializer is set as
. w: `; @' i# L- d- t** transmitter and one serializer as receiver.5 e5 G% U& v! f8 d9 @8 t& o" O
*/3 i" B e" \8 v, |) b6 `2 D7 V+ S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 @4 }- a8 }: d% lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 w* O B; O' h' s v' u0 r2 G( p
** Configure the McASP pins + \$ j4 C0 `! l* R; T
** Input - Frame Sync, Clock and Serializer Rx- X" k! S5 o) ? _% |" v
** Output - Serializer Tx is connected to the input of the codec
' @% c- j: R0 w( p*/
$ j) s- J V3 L4 K* ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 P; Z6 d& l3 N7 ^1 Z0 WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 W2 q+ `5 P& S& ?9 H- D9 z) {- `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& w" k$ c# ^& J' ]) _, X- ]! Q2 Z& Z| MCASP_PIN_ACLKX5 C5 J% P( ^- [4 p9 ?
| MCASP_PIN_AHCLKX$ m* e9 n( |( v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& Z# `0 U" C7 V- `1 Q6 s- X; B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 i% h$ S5 M+ B$ S* e
| MCASP_TX_CLKFAIL ( Z8 e3 b# {+ q2 O6 M! t7 D
| MCASP_TX_SYNCERROR
. A: l5 O5 d/ ], s+ o. g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * o1 Q1 T( k L8 n8 _* c
| MCASP_RX_CLKFAIL
3 t$ Z# T/ Z, v& B; j+ y y5 X| MCASP_RX_SYNCERROR 9 D5 }* K$ P b( e
| MCASP_RX_OVERRUN);
# b# C3 w+ x$ ?5 P. v} static void I2SDataTxRxActivate(void)3 f1 ?: @( t+ ?- ~0 D6 ~& ]
{
3 ^7 U) O9 z5 [) J. W2 X/ S/* Start the clocks */
' e$ k4 b. b8 ^" X. j( {. xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& V& p) O% n7 P, J6 E3 q9 U# {& m. u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ u7 i; L3 s7 U4 b9 j) I* ], d$ NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 I& I* O* i1 _ d9 B6 Y6 w/ g
EDMA3_TRIG_MODE_EVENT);
! O/ ?, k+ m# L- ^3 F+ R% G- yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - ~( I* m# d$ N/ A% X4 _9 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 K6 ^' h. ?9 w5 PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 A% H8 P! m+ {$ W. J# J, bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 k5 j* f! d5 e; j# i! \. Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 D; M3 A6 t4 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); R. m% Z# N$ D: c9 {% ?1 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 C7 m9 [0 e J* f
} 6 x2 `8 Q D, u% n8 A) m l, I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & d2 t1 o( B- M8 g3 N$ X) C7 t
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