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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* w( r4 p5 m9 q5 x1 S) Xinput mcasp_ahclkx,
& ~& f3 x: m" g0 finput mcasp_aclkx,. f! I: S3 O! `, V+ L( N
input axr0,
$ y s$ K, a7 E% E. j t6 ? ~" ^, L" Z6 T' [% b
output mcasp_afsr,
8 E {& S' D6 Eoutput mcasp_ahclkr,
8 F n4 Y5 a1 h8 b m" doutput mcasp_aclkr,8 Z$ n0 z1 W8 G. T r8 q( b9 m" ?
output axr1,
4 _) a2 ^4 o& t3 B assign mcasp_afsr = mcasp_afsx;
$ z' z0 N9 z6 j7 Passign mcasp_aclkr = mcasp_aclkx;+ W: y; @& m1 o1 Y, C r$ A
assign mcasp_ahclkr = mcasp_ahclkx;* b: e. ~6 X2 C! Q4 Y& M( A
assign axr1 = axr0;
" B5 m8 p+ c0 m- M8 a) K) F8 O6 i/ V0 o0 d |: g3 l4 d; y6 ?1 I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 C1 w0 J. F- n/ {$ |static void McASPI2SConfigure(void)
6 o' |! S9 C+ I e$ ^- t- Q8 ?5 ]6 M; o0 S{9 `) h' u) r) o* `$ x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 @4 \9 W6 ^ e: }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. z2 R; M$ k" Z' d' L! j4 rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 U! R/ |, {: [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& }' |! x4 `: M1 S+ B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 t9 C) m2 A& o* U o+ V* G7 V3 X. [2 j
MCASP_RX_MODE_DMA);
( }- W" G6 g0 E& t- c( SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% w$ Y B# O! G. G' }) X$ WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 d0 i. M9 S" h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 b6 _- N9 @( I! C0 H HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) p. n( ~- l6 ]; d* x% C: l% W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , l5 g" G* k* V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& z& e) j1 ^' h' z* `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, u4 Q: w, J: k6 C: G) \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 ]1 ?! a! m; v8 e- ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 s4 h$ J. Y3 o% M; ?8 u, n: N
0x00, 0xFF); /* configure the clock for transmitter */6 l" P4 Z& L) R( K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
v) W. w0 J. eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 l( t' T. a! E$ GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- O- ?: ^% ~8 B; _' [6 _9 Y
0x00, 0xFF);
* }" s F! P3 |) t. Y; q* ~4 e4 J7 A# q
/* Enable synchronization of RX and TX sections */ - A* L8 o+ b, x! [$ Z* V8 g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- e* G2 G4 e4 B7 ]! A. ?4 D( d- N/ C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 t2 o' R) M& [0 O5 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 [6 H, X9 b. t3 n4 }$ r- R: X** Set the serializers, Currently only one serializer is set as
+ D& I$ ~5 }7 d3 Z( [' D** transmitter and one serializer as receiver.
$ m4 h2 T4 K' `7 u! r% @' ]*/$ {# `; Y* m7 q% @5 s, ~& ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% B! X, l# G4 i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( i. G* m8 O* P2 k8 I1 ^
** Configure the McASP pins
& z( H* f4 g4 b/ n P** Input - Frame Sync, Clock and Serializer Rx
. N: H1 M' x+ Z9 x. U** Output - Serializer Tx is connected to the input of the codec
6 E7 ?. i! T c- B L3 a! o3 a*/! ^" o& d |* S5 j7 c, G4 @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 h9 w- \" s* Z" `% GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 ^+ m( U' B6 `2 Z2 j2 m$ H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) q3 K6 V; s: p6 d
| MCASP_PIN_ACLKX
! U; F) i0 I7 d. f8 I7 ~( G| MCASP_PIN_AHCLKX
4 W: S0 d/ ?8 t2 b7 U' `( G* Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- N. X! ^1 [. h. E; z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 y }* y. N+ Y
| MCASP_TX_CLKFAIL $ D' f! O7 N; @
| MCASP_TX_SYNCERROR
! G6 T: S1 l% o) ?& d- ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# R( J( H3 Y3 r& L! F| MCASP_RX_CLKFAIL4 |/ I7 N. E0 A! u# u
| MCASP_RX_SYNCERROR
/ }, h5 W" q1 h( T| MCASP_RX_OVERRUN);( S: @8 @- \$ x; R2 a. l6 v( A
} static void I2SDataTxRxActivate(void)
! h) b4 n& W2 X# ^) u$ e{
& z8 u: S* Q( n* J/* Start the clocks */
# E# O- \, D' B4 X" Y" t+ cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' }, S$ C; x; Y( ?, M. e; z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 s$ G. A# P. B& _4 U$ {( EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ o2 C" ], A6 P( H1 [EDMA3_TRIG_MODE_EVENT);
5 N; {2 ` C" j* ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, }6 r4 F5 ^# q* z: j9 B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 r* T. O: p3 L BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 _- J$ h) ^ |" ?. c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 |$ A$ k/ \8 ?. P' u+ R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 L$ ^( n0 `: [- F) \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: [7 J/ ?1 q) T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; |5 \7 ^# v1 `! r* _+ i
} ( ^' `# c' T4 R- r4 h0 n4 L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! P" }- S3 o2 Q: y4 v3 M( m
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