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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! t4 T6 w+ e& d, f/ y4 ^input mcasp_ahclkx,, e; L( b( |$ Z4 Z- O
input mcasp_aclkx,% M8 C u4 C) F3 ~/ \$ r
input axr0,
: F, [8 P3 N4 _& P9 x, J' Y5 j) S8 ?! n j1 s
output mcasp_afsr,$ F: \7 F' g2 `$ z" g3 c) Z
output mcasp_ahclkr,( w' G9 s) C. W% g
output mcasp_aclkr,
; h8 e) } b9 K+ P3 y4 e( i Woutput axr1,
8 p7 z. R9 X% C3 @' ?) n0 H( b assign mcasp_afsr = mcasp_afsx;& _4 h3 F6 s" ~: ?
assign mcasp_aclkr = mcasp_aclkx;
& l# q+ `, P& i: _0 ?assign mcasp_ahclkr = mcasp_ahclkx;
/ G; a* x* _: p9 ]$ S+ W2 hassign axr1 = axr0;
9 r- E8 Y) v. ?" l5 {! C x; T( K( N. \' b9 [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 R0 H; ^( ? a0 E1 A7 V) F
static void McASPI2SConfigure(void)
! M8 ^ \( K& L2 n{1 _7 D7 J, Z8 `* g. e H8 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( O- C, j8 @- Q9 X% A1 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. V- ~6 P1 ^) X% c: WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) a+ j- S5 G, h) ]+ J; GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. ~) Z' Z" C2 R* t: i$ s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, z0 h$ t6 s2 T( C
MCASP_RX_MODE_DMA);" k% L3 Z2 V! U, C2 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* d5 `+ F3 o' \" K% A* k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ z7 d" I# r; O" e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( @! j% b" ~& S9 {9 v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 b/ v. }+ @' @, y, oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; H$ m3 t! @/ H- |" [3 e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 O' A9 w ~& Z# t; P5 D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 s! T0 p* \* K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* u$ f- t+ L* N! ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ b, c: o& w6 |+ f) H
0x00, 0xFF); /* configure the clock for transmitter */2 H V8 u" t |6 o; B0 @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ O* `: H1 h" |' t) hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 t# M; B+ q# d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# Y" r7 H) ?; i2 _4 V) M
0x00, 0xFF);; I: o I6 j8 q) J8 `) X2 S
5 B. L" ~6 D: i1 j/* Enable synchronization of RX and TX sections */
# F% c0 Z9 I O7 l: MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 Q! h/ u6 H9 C3 X T# E2 ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 w6 ]; r4 {3 ]* Y7 F9 n5 d) f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) P( l/ @$ w- B+ i** Set the serializers, Currently only one serializer is set as
, o9 Y$ a5 s6 [( m+ y2 Z3 s1 R** transmitter and one serializer as receiver.
' n$ z. v8 a, _8 v' s1 l* p*/+ N) \. a `, U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" G$ ]" S% Q" t, M! a$ e% Y- c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 ~% ?# V( N! @: ~; @# X
** Configure the McASP pins
% p3 _- A Q: n** Input - Frame Sync, Clock and Serializer Rx+ b0 k8 n+ y u1 s+ b
** Output - Serializer Tx is connected to the input of the codec
( b7 u' P3 k* _*/7 l7 _" P7 F5 V6 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; n4 B" k+ u% e+ q; D u# |% [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 r. a; Z1 o6 d+ M' X& u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. ^3 c. K7 I) ~$ ~+ h" T9 I| MCASP_PIN_ACLKX
$ v5 ~ s$ }) F, U| MCASP_PIN_AHCLKX3 c4 Z: S& `0 N+ \% V6 I) k6 j3 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, t# [6 J. C. o$ A3 }# h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , M0 y' V" ?, J1 Z7 y; K# m
| MCASP_TX_CLKFAIL 6 p( _! U* f o s, i* g
| MCASP_TX_SYNCERROR
! `/ }9 L; l y2 i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 ]" u' O. z6 F( E- g| MCASP_RX_CLKFAIL
! U4 ?3 ~0 U. ]; ?& I| MCASP_RX_SYNCERROR
/ D0 ]" y' `! c9 z( J| MCASP_RX_OVERRUN);
! Y) L4 l3 j6 S. X0 r} static void I2SDataTxRxActivate(void)
% [, Z' s" _, ^% q2 D{1 y, ^8 z2 m( K7 R) k
/* Start the clocks */! c- n$ @4 ^+ z9 h$ O3 T1 v* }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! y9 Q+ E0 x4 z& p: I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 r! ]9 D! D; \' _0 K% ]9 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* V& j5 u$ R5 c; W, ?. d' ~
EDMA3_TRIG_MODE_EVENT);
# q4 s5 ]) _' n2 b) r/ KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , L+ s4 O5 D5 n9 [' u5 r3 T/ p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 n3 Y4 E# h, I9 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
^- i9 D+ z4 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 E" r( ?! @/ R& J- F( Z/ _$ k: Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// k7 ]9 j+ |( a! h l, @9 Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" N: W% p8 z4 Q' I, H$ U$ J t% H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 k6 z) {/ j6 y- [
}
& q: Y8 j; o. O9 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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