MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
3 B4 B  G0 f6 Yinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

  _" }  z$ e( C' n0 X& v) }$ J7 Foutput mcasp_afsr,
output mcasp_ahclkr,
  E& I* Q9 L; x" qoutput mcasp_aclkr,
output axr1,
1 X: o5 d, D; m3 a$ F" s

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
2 q& R  T7 R4 I2 N- n9 Passign mcasp_ahclkr = mcasp_ahclkx;
  p+ ^; R: W2 B) U0 X0 c. B5 e% Qassign axr1 = axr0;

5 X) ~# V2 V! t. {

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

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static void McASPI2SConfigure(void)
{
3 R6 A5 I0 N; c) z  R4 }* m6 |( m, rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 `. M' V2 @5 hMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( }/ V+ Z2 M; [2 ?8 DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* N; v! L& q, X, {0 m" ?MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 w, c, r" s# {. s8 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 o2 G: E+ ]9 @0 q" B. F7 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. ~( I9 A& ~1 R$ lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
; F; V7 ]! W! \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 \. ?  ^5 w1 m1 M0x00, 0xFF);

/* configure the clock for transmitter */
' L- k7 D! V( o8 s4 l6 o6 ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. [, V8 P# G; t1 l* EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 k6 l- l' a" P" I0 B. uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( b7 b* j# C8 J( ~( {0x00, 0xFF);
( l, R) k' N# A$ z# I/ y: z
7 v: a) i  ?; f- P( X/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
. @- i- |" f; f- p7 J4 }1 ~' AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 ?9 x6 b  E( G" b$ _, P, \- VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
2 D, h6 j8 G8 ^3 v8 H2 [- K# K*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
- t# t+ f+ G- M! @1 g** Input - Frame Sync, Clock and Serializer Rx
- ^3 w$ T) |( W  P' }% M** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" K0 m; a+ I- H9 [6 EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 E' R3 A& C; M; C9 V+ \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' F% m7 E" g" n) X| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
) i2 H3 j, Z, Z# ^| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
: u: f5 B  {) w9 x7 u1 M4 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* y  y* E. k5 l" i| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
; M2 M$ F: y4 S0 S| MCASP_RX_SYNCERROR
( C( s. V2 S/ n4 O! |; G| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 a, L" f* x( F# L  P; X; Z0 ^0 MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
  W1 q) {6 R4 v! p! D$ D/ xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) ?) B9 P3 C2 }, j+ aEDMA3_TRIG_MODE_EVENT);
- d: u" {; V9 y- CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# V$ `3 u# g: }4 y6 E8 s" k6 |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
1 J3 ~8 }  v" I  J4 M- |& CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ @7 q9 i$ ~, s" \* jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
% F" d; I$ X) A$ {0 cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
% c2 [; n8 o; S6 v# NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

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请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.