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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" c! ^/ N l. X8 F" v, @: V/ @8 ?input mcasp_ahclkx,
& w' ~4 S6 |5 d; O8 vinput mcasp_aclkx,0 E. s F% Z. F; u% [; V
input axr0,1 b; p8 f5 O6 }; X9 x7 G
8 P) C# k2 R& E7 Woutput mcasp_afsr,- K' b* r# c" y0 I, \) F+ U" R7 a4 Z3 g
output mcasp_ahclkr,
! o1 \7 {* r* p& ^! Z) w& Ooutput mcasp_aclkr,
5 F. `) j9 g0 }3 loutput axr1,
% t7 {# V4 h) u2 w# e4 z assign mcasp_afsr = mcasp_afsx;
4 u ~* ~' j: u7 }$ P! }assign mcasp_aclkr = mcasp_aclkx;
1 o: _1 H2 l. }) P. Tassign mcasp_ahclkr = mcasp_ahclkx;
5 M2 c7 n' f& O* R$ }assign axr1 = axr0; ( F4 W% N' L- y* G# l- }8 i
0 {" V0 V' U* o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 o, j2 c8 G8 |2 K$ g4 ]
static void McASPI2SConfigure(void)$ ^4 D4 j* ^9 C3 w p0 i
{
% f+ m7 A/ a$ h' m, l LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- I2 [" ^5 B" R" ]( n( ?+ j, K* sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' A w9 F* c, ?! k6 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 @$ {* z8 M7 x1 V9 g' SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 B; Y% }) A! L. t* j( AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 d8 a3 ?1 J8 g) }% H( U7 iMCASP_RX_MODE_DMA);9 p0 s& I4 h7 D) d" G- y8 T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," v3 Z# a5 q( f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 v% u5 O3 `" l) Q, o. j U7 T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& _) s! Q8 [/ f0 \& t5 iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 X5 s0 ?* b7 B: [6 H+ w# d hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, ^! ]3 m! c; H8 l, e* e5 ^7 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! y6 O& k5 A8 h5 D0 q0 r5 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 @+ _3 L; C9 U% ^/ dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 J& Y6 d3 U5 _7 V9 r( _/ F0 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 t- ?6 Z. q, t+ f+ n: k i i3 f
0x00, 0xFF); /* configure the clock for transmitter */
/ X% N; X/ L1 w; \( y e2 LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. _3 a _9 i7 |" |; l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ x" m2 w2 ^6 R+ f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 v" J9 F4 ?1 L1 p; T- d# G
0x00, 0xFF);
' m0 [# i' f$ S+ ^3 f, G0 e' N: Y8 G" S6 O5 u) y
/* Enable synchronization of RX and TX sections */ & v& i9 t1 S6 d7 V' W* e* s8 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 M/ s- B9 \- d' b* q0 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 r7 q5 s9 H2 J& GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 p) a3 K9 i, ^0 ?5 R/ J( O% h** Set the serializers, Currently only one serializer is set as
5 j$ Q( h; h- P5 O' D( d** transmitter and one serializer as receiver.9 w( X8 {' v6 K& T
*/
: N! c6 K9 y, a, u9 x9 @1 `( |. h: PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- n$ Q; d1 Q. N6 [6 m/ M) O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) k$ v$ P S# d! A. I ]( V R** Configure the McASP pins ! m1 R8 `* E& B$ M! n
** Input - Frame Sync, Clock and Serializer Rx9 f% M6 p. l. x2 \
** Output - Serializer Tx is connected to the input of the codec 0 ]2 v6 J- u/ ?* r/ G" ], O( t1 j5 `& V
*/* U' B: L( S* T$ Z& I4 M8 u# m1 u9 \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ t: k5 f/ |6 w" o4 b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ C: b8 s, n Z+ f1 aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" W R$ L5 x: e1 d3 [1 f% Q
| MCASP_PIN_ACLKX
5 V* D1 }! `; J) \0 g5 @- x| MCASP_PIN_AHCLKX
( t2 t2 ^2 e; A% U( [, e6 n' a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- C" j$ p( \6 J5 ]9 G- {7 u: |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR a8 U5 `7 ^4 z9 D5 P* `4 D
| MCASP_TX_CLKFAIL
8 y% Q8 Z V9 {| MCASP_TX_SYNCERROR
$ ?9 L1 H6 V5 ?) a8 d7 ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( h/ A: J* U, Z9 r% N# G
| MCASP_RX_CLKFAIL+ z, ]+ ]+ z+ n+ k/ x- R4 o
| MCASP_RX_SYNCERROR
6 f( @% x) u# m, H* m| MCASP_RX_OVERRUN);
9 R: m" H s* S3 l( u} static void I2SDataTxRxActivate(void)
$ S2 n2 W/ X+ W6 B{& h7 o# j0 v9 O
/* Start the clocks */: W% m( s/ G- d/ B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: i6 N- J0 b/ X, l4 K, ~6 U: s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' O# m& N/ S/ u4 A$ e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* o0 R* _' l7 v8 |* T1 wEDMA3_TRIG_MODE_EVENT);
4 S/ b$ d t8 d: {9 c7 j! X3 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 G7 ?4 T' y: P3 J. ?/ r* ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 X. V4 g) m4 R8 dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 {6 j! L8 ]6 n- l! }4 l/ ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, X) W& t' q+ I: K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 M2 M) p$ M; A. U7 W2 T7 @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' m" }6 s* R0 e6 Y9 i4 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ O6 Q: [2 g$ X* Y
}
4 q5 E- c9 X+ K. `7 z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 y5 ^3 L1 `: t1 e+ M+ g# w
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