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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% N, M1 C0 e1 M8 {0 M$ {- Rinput mcasp_ahclkx,
# _ q9 n/ S; g0 g( ^" D7 P1 e, Oinput mcasp_aclkx,8 V) y1 u6 Q E! ]( A% h, U
input axr0,
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+ A# y8 }5 r9 p$ O3 F. ioutput mcasp_afsr,
$ a( K& @0 Q, `output mcasp_ahclkr,
' J. z9 a F6 g% _" K' O" houtput mcasp_aclkr,
) g( l" s8 U% l1 P* q" u) d8 Poutput axr1,
% W" V- l3 |4 `, C0 _ assign mcasp_afsr = mcasp_afsx;
" S5 {' n2 J/ w7 C7 A" o' l* L/ eassign mcasp_aclkr = mcasp_aclkx;& J7 I/ V; g+ B" K+ [8 }3 l: l6 t* \. @
assign mcasp_ahclkr = mcasp_ahclkx;
+ h' o# f* E1 ]( Y/ [# E, L0 c% qassign axr1 = axr0; * q# H+ b' |) E
! O9 Q9 _- s. l: y/ `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) _2 _& Z+ V7 o; N# H! |8 k- A+ \% Q5 t5 T
static void McASPI2SConfigure(void)7 e0 q+ W2 @- G! l; J8 C1 M) ^
{
2 q' G) ]6 m% M' F( ^$ MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 r9 v4 j! G# T, f0 F5 W% G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% j6 ]7 ^0 p5 k/ n, r4 d, o$ N; |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# y' n4 @# ]% D+ B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 i$ A% s1 u& U1 kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. t: [- Z* k/ _1 ]+ q# B9 P# wMCASP_RX_MODE_DMA);! @1 V% \3 ~6 G) U- S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 a9 ^, Q# P- X' E8 K/ ]* cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ W( ?+ N2 e5 H, Z$ Z7 ?0 d4 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 }9 w6 M6 B, v: R6 s9 L$ zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: s: P Y3 f2 X8 {5 r' LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 v* R( w% Y3 c5 g1 j6 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- A1 N/ W% i. w- _& c: dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! Y) K$ D+ @/ s1 A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 m' G9 @; v$ {% W7 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, h) N) V- C4 E! {' V
0x00, 0xFF); /* configure the clock for transmitter */: ^1 E0 \8 V3 e+ j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ ?: O* \+ @! R# e$ u4 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); k) ]. c/ a" q9 F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 X8 r' t+ i; N$ G' d
0x00, 0xFF);
7 A$ k3 X9 K- U# h* m ~% y
) \' l- [, \# P4 |) H/* Enable synchronization of RX and TX sections */
! a; F" X& L+ F. I2 K; k. SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 S. q7 S3 I1 @ w+ O! qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 }: |) k V8 V0 [$ ^1 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( Q) b3 K% U* X, S% ~
** Set the serializers, Currently only one serializer is set as& e1 j' O5 y/ w# t
** transmitter and one serializer as receiver.2 |3 A: v1 @: S; i( ?( d- W2 J
*/
& m% T( j" p, _/ P8 j1 M* ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
N, h) s; P, d4 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 [; B: U: M6 v' S0 a: U** Configure the McASP pins
4 j: g- `& ?/ x1 v, T- @( f" z** Input - Frame Sync, Clock and Serializer Rx
i* `* u5 s6 N# U2 H0 D** Output - Serializer Tx is connected to the input of the codec
1 Q7 ?* @ v. @8 f+ T0 W- t*/
: i! Y& n7 z* B3 p( l& @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ ]9 I* o1 b- I- u3 s7 }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
d. |0 V8 x8 M9 O( w! C4 ^% ]( s- hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 B {# G+ J8 \. n* t| MCASP_PIN_ACLKX/ t8 F6 u7 O" I% j- T4 c8 A
| MCASP_PIN_AHCLKX
8 M$ L$ w5 c- A' c6 v7 d: r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 k) V, P: O/ B: {( O. h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, j/ X5 r6 i9 A; V| MCASP_TX_CLKFAIL
0 s, c6 K, O" p: H1 h% S8 x! V0 x| MCASP_TX_SYNCERROR
. e8 t' n* {9 w8 Y7 ]# b2 S! B1 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ C' {! @* v" x* F
| MCASP_RX_CLKFAIL3 Z7 [0 [. w1 ^+ n- g* M' z) T
| MCASP_RX_SYNCERROR
0 B) ]6 w2 j, r! k1 R9 a" A9 ^| MCASP_RX_OVERRUN);* ?- Y% Y& e( x" w
} static void I2SDataTxRxActivate(void)
+ P C3 v+ J# X. Z/ Q Y% y{
- ]2 K4 v) X+ z/* Start the clocks */" z4 F8 u! F& n' q$ [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: e9 W9 z( n$ I) y K- M. I1 L! `4 v- P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ a/ R( [, H/ C5 T6 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 p8 F! _6 c- R! r
EDMA3_TRIG_MODE_EVENT);, [. B, f4 t4 @+ P+ E* o9 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 \; B7 {. l$ }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' c/ v* P$ [1 K4 O0 ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 d+ V/ t2 e8 o& ]/ H. ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# w# M2 v. Y% Q0 u( S! j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 [% a0 J1 w1 P( J: d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- h/ b, G$ y. s1 m/ V. ^, @2 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, D. s: L5 C A1 W. ~$ U7 s
} . ]1 n: ?$ U7 A( X5 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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