|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 W3 e- E( i4 f! Linput mcasp_ahclkx,
4 `3 L" m; _% c! e% Jinput mcasp_aclkx,
" e. f8 \+ l$ ^- v. x2 T0 Uinput axr0,6 C7 ~0 a3 |0 R* g1 J% Z' }: E
6 q2 n6 E8 i' g7 Q6 t/ f
output mcasp_afsr,
; q$ i2 @* e; K" J! K( t) x6 ]output mcasp_ahclkr,6 i5 H2 {) h7 s: _$ _
output mcasp_aclkr,
" J7 z+ {1 K L0 I: ?: Loutput axr1,4 {0 y. i- {+ D
assign mcasp_afsr = mcasp_afsx; i$ a! N0 r: v$ g; d+ z& C
assign mcasp_aclkr = mcasp_aclkx;
* O% |# d6 @% E( D6 L" `assign mcasp_ahclkr = mcasp_ahclkx;
4 `1 j% B% ^ Massign axr1 = axr0; ) V! C' \5 W6 i/ z `
: o9 w0 j; F4 i+ {( A: {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ e2 F' M# ?/ W7 Q# q8 p. _static void McASPI2SConfigure(void)
/ @; |4 z! ~2 x1 J2 w{
+ D5 ]4 R z }: ~3 g5 m, UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- x% h8 d S1 U6 P- ], dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 u T" e Y( s5 c9 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 ]; E# K; G) M$ m$ S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" E5 n! c2 \& c" t" @/ X7 x/ m- }' r/ F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 E- {. ~) E! \1 _/ }MCASP_RX_MODE_DMA);
2 Y+ c0 J3 T' I0 Y. D0 O; pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 D; U% _$ | c1 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 G) j0 R5 u$ B% F! M2 f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : T! d6 w, n/ Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& h% v, m9 c' v2 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 Y( j+ }+ Q2 G+ U# N2 ~, bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 E2 P4 l& C8 C8 A* _2 a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- }8 n% A: G# S- S5 \* H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ S# `( L0 W" @0 ~3 D, c$ a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( }8 b- S$ ~% Z) y
0x00, 0xFF); /* configure the clock for transmitter */
: t; R& u% D; y+ L' ^6 n4 A$ VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ _+ G [* m5 C6 U8 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; w8 @9 R+ S6 a* n' sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 I ^# A2 @) z" m0x00, 0xFF);
7 f0 n _& Y+ e0 K; ^, p. M, U) o+ b) d: Z! M2 {
/* Enable synchronization of RX and TX sections */
% D$ \" m6 t4 f. w! tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 J7 k! L* R& V8 b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% r. @/ i! K* }6 Q; P0 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* w5 U. w3 M6 |2 B- h( C( i** Set the serializers, Currently only one serializer is set as. p3 k5 H' H7 u
** transmitter and one serializer as receiver.
, J+ l3 y7 W/ ]*/0 z9 S. t* @9 j3 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ @' \- B# v" }: k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 h, X- a8 c5 }& U# |: K- w
** Configure the McASP pins ! G9 O( }! y8 l
** Input - Frame Sync, Clock and Serializer Rx
7 i7 E4 t# L9 _( H** Output - Serializer Tx is connected to the input of the codec
! D" `, k; X6 o, H*/
! E* k+ ~4 s( Y8 U6 ]6 k% pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; d. l+ ^: t4 ?. F& g) OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ R% k1 F6 V8 Q' M1 @( [: d6 [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 U2 b5 _6 _! r7 j
| MCASP_PIN_ACLKX! K5 ~6 q' B; K; d( H ]) e
| MCASP_PIN_AHCLKX
. z$ t1 Z6 Y, D V, g4 s9 v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* ^# v$ w) h* ~) f8 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 O$ v( M8 I4 c5 G% X
| MCASP_TX_CLKFAIL
- u# a3 I. u" t& s| MCASP_TX_SYNCERROR5 B4 y( M! @. t* l9 v1 C# V" }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 Q4 ^& U* f8 w$ L3 G1 \% G q1 F| MCASP_RX_CLKFAIL
" K3 \' ~2 [) j| MCASP_RX_SYNCERROR ; H: u9 v. _* M. ~
| MCASP_RX_OVERRUN);
+ Y' c; `# z! G0 S' C' X8 j+ J- n} static void I2SDataTxRxActivate(void)
1 L$ V) F7 q( Q2 P& S{
5 P+ s! q: i' C3 q* k/* Start the clocks */& l1 ~. z; t+ _! w: x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 {. Y( Z* ^. Y/ i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- X5 T( i. R s! t) Z3 M& [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 a |; W2 Y" z+ V
EDMA3_TRIG_MODE_EVENT);+ C6 ]% y7 v F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : t9 G8 |1 ~) s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( Z. d* a9 {7 e# C8 F$ C0 K: NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- ~3 g1 i4 W2 L3 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) @1 Q8 M# j+ Z( P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 I1 b3 F1 g. X! n0 a$ Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! l) a6 k. y2 ^2 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# o6 P3 X7 c8 W2 {' i$ G} + u( X- h! O# C" K. e2 x/ n' d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
/ l8 F' A) G3 I+ Y e |