MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
4 E1 F8 Y& j3 linput mcasp_aclkx,
" d" ]# Y$ g0 Y& j0 w, B2 Cinput axr0,

output mcasp_afsr,
output mcasp_ahclkr,
0 R$ h1 L0 r6 k2 g' A, uoutput mcasp_aclkr,
8 \8 e: d& x5 a; `0 Y' Foutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

. g+ U3 r; ]$ @1 y

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
% O" u, D  q& o! m( @# U5 o{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 L% K, k5 c7 I% u+ q. KMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" u$ J' i' c. ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
' q5 J$ y; _- F/ Y. a+ \$ YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
) h8 d1 A; q6 g, hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 u% H% V1 C0 z' d% oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ H- k) ?3 p2 z; UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
  `+ ]1 s) z; ?5 N. SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
. h/ S: C' Q5 ]# S4 F' d8 U# jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" I) o+ I, @& v# kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
* l* N1 G7 T/ Q: k# `; fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 v9 m; O$ U2 z* G, tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
. [0 |9 w$ w5 [+ k: W6 s
# K- K' o( T* V1 I4 I8 B3 o/* Enable synchronization of RX and TX sections */
# }$ a# l: v" j& O: LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
$ m: x# V9 ]2 ?- E** Set the serializers, Currently only one serializer is set as
! A6 d. R0 a0 n6 W** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' u% P/ R8 z; L: |. v0 U- y! t4 rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
/ n% w9 v6 g; a; q4 _' \+ p** Configure the McASP pins
' z8 @* D' p6 `6 ?3 B1 ^/ J** Input - Frame Sync, Clock and Serializer Rx
5 `: b8 L9 E7 k** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 T8 B! R& A, x- [! T  sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( x2 d2 H( z, V! v1 m: H  Y- D& NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
2 J0 r# j' T: s$ R% ~| MCASP_PIN_AHCLKX
- k9 J2 g! l# ~8 C| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) F! l) G# Y. ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 t3 C; {# s+ ]: e3 r| MCASP_TX_CLKFAIL
8 L5 ~1 k% m) p, V8 Z% H| MCASP_TX_SYNCERROR
' M5 I0 N1 \3 `2 T  A7 B| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 G/ P! ?% K6 e# `# p9 T/ h| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
5 P3 T8 o2 [$ L+ C| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
4 \3 Y, ?9 ]3 f& y* ]3 o/ X9 D7 F{
1 A. e2 I7 `* b" `" u/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 C; _9 |5 m* R* z6 R6 b7 X9 i  aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
' ~3 ^( X: m) ?6 @/ j/ w# ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ K5 J; ^+ y7 M2 XEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
0 v2 a8 P  e) n% m! i5 P) MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
1 f. G$ n: g1 j4 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
! t. g* [+ b8 c6 AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( j  X" s/ D* ]$ o0 r9 M" F}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

# ?# H& {7 A+ b; a$ r