|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 K+ |: j \7 M7 Q/ y1 }" `input mcasp_ahclkx, a5 H# i8 y& P
input mcasp_aclkx,5 o+ ~/ N+ D$ b
input axr0,
, N& O1 V7 o( c) ^: y" ?( X
. X6 U+ c( T2 a3 l9 doutput mcasp_afsr,; I- K+ g' x; D9 F
output mcasp_ahclkr,
8 f Y4 p4 ^! i7 [output mcasp_aclkr,4 W$ R+ {7 G; w
output axr1,
r! _5 F7 ?) p% |5 C b- Z, e assign mcasp_afsr = mcasp_afsx;
- ~1 D. M2 S$ P) r6 Y: y; N3 xassign mcasp_aclkr = mcasp_aclkx;: J4 ]# A1 L8 o0 r2 A' n5 i* i
assign mcasp_ahclkr = mcasp_ahclkx;( C! j; h: t7 }: e6 z- {, e* O
assign axr1 = axr0;
+ D" |+ h6 w5 p( _9 u0 v* |" ^
8 C. W* z. u. x7 v4 o8 `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' _9 V. p# [& o6 S, E3 p+ x# s
static void McASPI2SConfigure(void)/ _- H! M6 A+ U* M1 F
{8 L6 D% {! D# z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 _. V" X9 Z: Y; Z8 ~! BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, o) K' g/ j6 u* ~# a2 x y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ V. ]. v% Z5 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- @4 g$ O" y3 s1 ~$ A% Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 V1 l3 i: {% D, ?- i- P* |MCASP_RX_MODE_DMA);
# b h& i( t2 i. M/ _' vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. p0 u, u8 c |5 a4 xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 I# m& l7 m1 F' K9 x {% i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: G- m+ n. u ^/ L- ]$ R! kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% J" k. v- }! B2 K( v% s% A" u& FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" K% `+ P' a" CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 n3 T$ }& W" L' n2 S f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 c, d1 l" `* i4 G4 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: V6 t! x3 j6 }# w5 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, J3 }& H! {! @3 ~
0x00, 0xFF); /* configure the clock for transmitter */3 v& V6 ^1 X y2 v3 F$ _; b, i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; J* o5 L9 Z6 `7 A1 {% `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 ^( D5 b* s, ]3 p8 j1 L' Q& h2 OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& v$ ?5 R: K6 e6 u0 I0x00, 0xFF);, `& Z; p) [/ j+ W
" {& @: h+ F9 M1 D$ z; V9 U
/* Enable synchronization of RX and TX sections */ ' J8 \5 z$ h5 X' @, j q9 i. x, C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 M/ o( Z0 w# A+ x/ Z7 i) M- T8 X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' d, e% S5 r0 n6 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 p9 z7 \1 W2 X' s
** Set the serializers, Currently only one serializer is set as
$ P, f( Z8 ?/ D' M `: x** transmitter and one serializer as receiver.
0 G' a, F+ C1 E) t& [% z$ D*/
% r/ {! G( s+ Q5 `$ G& GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 Z3 g( Y+ @& S7 ?/ q/ Y9 K; m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 S; L8 `; r$ [
** Configure the McASP pins 9 Q2 ^# x. Z$ r+ u
** Input - Frame Sync, Clock and Serializer Rx7 N. S; ?: @, \& j
** Output - Serializer Tx is connected to the input of the codec ( p& E3 d( R* z7 b/ m
*/" G+ A! T+ U; h! R& E' @! ] M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- y p& V4 n0 w3 W) s1 n* j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: p+ ]2 { W V4 f0 G. Q1 ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 W# ^9 p- D* w5 T
| MCASP_PIN_ACLKX
2 s& @0 k, Y1 T! d* L" f# X5 z| MCASP_PIN_AHCLKX4 d. c$ ` A7 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 y1 [) c7 F* X* e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; U' Q6 U. M$ _7 J w/ O| MCASP_TX_CLKFAIL ! O& R3 W) r/ W$ C: g% x
| MCASP_TX_SYNCERROR+ N& C( C/ p/ I. m, l5 H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 k% M" ^0 o. h9 X; ]| MCASP_RX_CLKFAIL
$ d- W/ t8 _8 E5 P| MCASP_RX_SYNCERROR
% g( K% f" r* b2 u* h3 G; P( @| MCASP_RX_OVERRUN);# F# _" r% Z# u9 U
} static void I2SDataTxRxActivate(void)
: U* M9 y) X: i- ^6 f: N{
" }1 y! ?4 h' W/* Start the clocks */- j: [" }& F6 m0 y8 ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 D" c" B3 c9 R: O# ]5 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* N$ H9 _, l* z0 j3 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 K* n$ |' T, n
EDMA3_TRIG_MODE_EVENT);) N7 `0 U9 b5 w% o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 c$ J9 G$ h+ \7 t8 t7 P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. h e ~" C6 \- T+ UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ X+ h. e9 t3 z3 \2 M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ h1 T) N h+ [5 E4 W& f( fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& v; o/ N. N$ T- j( i7 `$ aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: Q5 B( {8 q: j( j- A$ ^ ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* U) y% J9 ^" K* O2 K* ]
} 8 {2 d. O* U9 d6 q9 g- Z4 _4 i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 k) ^. `1 H: o3 I9 ^3 g, f |