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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 i% m4 k% y" Q4 N' k
input mcasp_ahclkx,
2 L+ N3 _; l0 kinput mcasp_aclkx,
& K, W, i2 I+ ]2 } Y' z7 `' Dinput axr0,6 t8 J, `: ~2 n m/ G! a3 J& \
2 [1 g, E5 v4 ?" Poutput mcasp_afsr,, S: s k( H0 N- R
output mcasp_ahclkr,1 ~ N7 ^7 a P$ v/ M
output mcasp_aclkr,- z# K% l' Y% ^
output axr1,& k. v* E! C0 @- g. a5 }- z
assign mcasp_afsr = mcasp_afsx;1 l2 `" C- }0 [8 u: x8 V$ e
assign mcasp_aclkr = mcasp_aclkx;1 j9 c. o$ G" }" C
assign mcasp_ahclkr = mcasp_ahclkx;0 r# u1 k, _4 _
assign axr1 = axr0;
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: s' u/ @+ [4 P& ?- Y* D5 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. K: _, j6 @% Mstatic void McASPI2SConfigure(void)) F* e6 W* w3 f9 G
{$ R* H; u4 N. t0 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ n* f' o- D' a, v+ Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* K" ?* R K( [. ~/ A( U3 J9 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 F" l2 T6 J5 q% I5 H8 r; l. _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 {' o- z- t& ^1 R3 g3 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 |" t3 s) s6 J
MCASP_RX_MODE_DMA);
. E: k, R4 P' R8 y+ _0 _- R' E/ yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; u P' x) V7 o8 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 y# |! n# J5 @- N6 u2 R% f1 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # g r8 B2 i: I( e5 O6 }: J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 h# M) K( d7 ~& P% ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 K9 P4 e5 p9 {9 jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! j3 p- I& a1 l) |$ ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: @; M, L" n% t& k* tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + N9 |% ?* n K) j! E' e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 ^1 Z6 q' S7 i% S+ C+ c6 Y0x00, 0xFF); /* configure the clock for transmitter */
9 U5 s, ~; B& YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 c* m2 T- c- G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% n) A) }: `% k) J. C8 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' v. i2 z5 t! f! d e4 d
0x00, 0xFF);+ r* Q F4 \( ?( c8 a
4 q$ |7 r3 Z/ M; z& |7 E, _/ x; p
/* Enable synchronization of RX and TX sections */ : U. p" J. M* ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 A! i) g) @5 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 G9 y( J$ c0 B5 [, ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& ]6 [" f% N: U* N** Set the serializers, Currently only one serializer is set as
! w7 J- W2 [8 [** transmitter and one serializer as receiver.6 v5 G! s+ ~; m( I e5 I
*/
; \! o6 f1 ]* x/ y; k/ Z( z9 FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% t- e% i2 d; a6 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 D7 F7 L' H8 I2 Y8 {
** Configure the McASP pins
0 x1 f0 J7 {8 M** Input - Frame Sync, Clock and Serializer Rx5 }( Q0 x' U9 ]$ U
** Output - Serializer Tx is connected to the input of the codec ( t4 r& G' G7 ]' r! \# k; D
*/
% I) B3 q e1 a6 t& Y/ U0 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: p/ [/ c: C5 H; Q3 w! jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 o+ _5 d0 `. P. P) Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ m' N# m$ h) j; l, y, Y
| MCASP_PIN_ACLKX" b8 ^ K0 Z5 O! k0 n
| MCASP_PIN_AHCLKX! L6 f, h) ^" d( `; \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- G& U* r6 \7 H& [' {( L% {) g) J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 \, e0 E: _# j5 W( c| MCASP_TX_CLKFAIL
/ t% |% |7 b5 p: ?# u: y| MCASP_TX_SYNCERROR
1 Q4 V; L- h4 X/ _5 Q, E/ F- A2 G: g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( K' n+ {; a: |, k3 L! w! x| MCASP_RX_CLKFAIL
4 @7 @ H2 Q% ]9 ~8 ?2 ^| MCASP_RX_SYNCERROR
3 F: B4 T. Z }, A$ C( t6 F| MCASP_RX_OVERRUN);. w. n8 C& a, I) }! z
} static void I2SDataTxRxActivate(void)
" f1 a# d2 J5 n7 i{, \4 \5 [3 R* i# p
/* Start the clocks */* ?/ @1 j! B2 W) J8 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 h2 ]+ k* |! a1 Q* f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& e9 b5 A7 _5 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' O- E; j1 ^; }+ ~: n$ J
EDMA3_TRIG_MODE_EVENT);
' y7 T8 R' i- t8 W gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # e' } z0 g+ U$ o/ \( v# U5 q$ F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 p# d6 P6 d: v7 K4 B9 h( B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 }' d! ]+ l7 v u4 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) E" y( r2 B$ ^$ n7 d+ }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( v% i: U# i+ n2 u! z' N6 dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
~8 A4 \( H$ S% pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 X$ O+ R+ Z1 ?+ c8 V3 }5 T} 3 u1 ^+ d) o9 ^/ n- A# Z# k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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