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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% n) ~: U( ^- N
input mcasp_ahclkx,
2 e E% F- |4 Hinput mcasp_aclkx,
: X3 M5 a0 e$ J9 I( X. q1 q: ]input axr0,
; R# [3 l/ Y4 K7 a r0 R, ?, f: z
output mcasp_afsr,
2 ], [, X$ R8 F% U& z Foutput mcasp_ahclkr,
5 A8 Y0 n) { x% K; Youtput mcasp_aclkr,
) A V+ O# p+ Q& H: S6 @output axr1,
8 C; r& u: [; Z6 w' T assign mcasp_afsr = mcasp_afsx;
3 R& b! b2 A. D7 gassign mcasp_aclkr = mcasp_aclkx;8 s0 P t0 f7 {% H3 y
assign mcasp_ahclkr = mcasp_ahclkx;3 t# T# d2 f7 w r( {
assign axr1 = axr0;
: c" J9 U L! m1 j
& L( c" U; l- a6 x: v* y. B3 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) J0 h! V1 }& D3 p# |' J4 y
static void McASPI2SConfigure(void)
; t& t& B8 @7 |* C( T' A{
3 ?1 s# G. w3 L3 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 o9 X, P; a8 z. K0 a5 ]4 ^9 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) I H! q5 [" I2 {% ~5 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; I: g! O0 v; m; e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 B/ Z' U, U" I6 i3 wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( e& ~% }$ Y' m$ S( |/ o) ~" P9 Y! _MCASP_RX_MODE_DMA);
/ l1 Q4 d4 ~6 }: m6 H1 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, X4 ^& I: }/ Q4 `3 N- Q9 w; T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 P- `8 w" k7 ^. P+ VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 m' w7 C! B, n# G- Q2 e/ ^! U2 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( B5 x+ o D8 Q. v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# O- L( x6 n* z7 O* s8 n A9 dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' J7 Q' ?; [- v9 r7 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% O! G0 F& w3 W( t7 f" L! z" p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) Q7 W; u" C5 v8 V, q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# y9 G6 U2 s0 N6 P) K0x00, 0xFF); /* configure the clock for transmitter */, N$ y" O0 N/ Z9 o9 @/ W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& N1 g! ]8 a5 o( e4 p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 w# c$ @' F( a+ w9 q( u- l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% r0 A7 Q" ?2 K3 F! F1 u
0x00, 0xFF);
. e8 l2 j' j7 N c( o+ v4 q m. ]' P9 l- m, W1 ~3 R) a! H
/* Enable synchronization of RX and TX sections */ ! r" B) C! a+ K0 Y" w9 B% ?4 u+ k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* x& }6 f0 H* \) K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! z G# D+ b0 n. d% R0 s! F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 t2 u0 H) X9 ?) z9 _** Set the serializers, Currently only one serializer is set as
+ c- W p7 t; g/ \' A: X; j** transmitter and one serializer as receiver.8 J; h- _( P0 I& R( E& b/ r7 p0 W1 F; X2 L
*/. J/ O2 _5 u ?! i. R$ P" Q, j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' \3 s) f. f, uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& w. a6 c9 R* `
** Configure the McASP pins . H& p- S0 ^% M% w4 b
** Input - Frame Sync, Clock and Serializer Rx
9 N9 v9 r+ e; u ?6 e** Output - Serializer Tx is connected to the input of the codec
5 ~; X8 m2 Q7 d. U% i8 E+ E*/! v& s. f' l: s4 }% y: _5 Z* z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 e# t0 A# B& _' VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# |5 q1 H5 }2 a" Y( g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* I3 B$ X+ M* W" l( S; \
| MCASP_PIN_ACLKX
: u+ |8 Q! x2 D2 B$ j| MCASP_PIN_AHCLKX
0 H9 Y8 I- Q) V$ ?6 |+ V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 h1 h8 ~1 c* ~/ ~) P- Z; z3 p2 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 U5 z( l4 Y& K| MCASP_TX_CLKFAIL
- X. Q0 O! b( w% m: G| MCASP_TX_SYNCERROR
! R5 o0 z7 `# g: R" R! E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. G+ k8 K2 F' c. |3 T% c0 `) a| MCASP_RX_CLKFAIL# m1 N8 M" S, o
| MCASP_RX_SYNCERROR 9 R7 k. F0 U% P) u/ s* ?
| MCASP_RX_OVERRUN);
) T9 t" }. s3 L2 B7 _: A} static void I2SDataTxRxActivate(void)
+ P5 I- L0 q$ _! a. k{
8 C' A7 b' a8 N% |! M# g/* Start the clocks */# h, u) d. T1 t" I8 d7 d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 M1 s) Q& `& k. W2 c9 `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" g d2 ~8 r4 F' {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ y/ O* O. f( Z& N, {EDMA3_TRIG_MODE_EVENT);6 b/ m( I* B6 M" Z" R" ^ D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 y% @7 i9 X0 X0 Y3 z& h6 c- O2 F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# l; ~5 t+ p: m/ w o! ^( cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' a7 Z/ m0 x: D, l+ gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// O% s" Q) _! b" f' F- G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, ?' Q+ T& [6 S! Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# S8 e6 d' F2 _2 e. z0 g2 {& d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* f; s& d2 h, i, p
} 5 I- G( C1 F5 A0 m! m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ x) K; N8 t* B0 ?+ q" s
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