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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ {7 L( \4 {: t& C& s" m
input mcasp_ahclkx,/ e8 H! Q0 w3 @/ @6 r+ V7 X
input mcasp_aclkx,
8 {5 r7 S- J- W/ E0 \$ {input axr0,
" t) }. Z9 U U) I* C2 R- Q: t
- @8 u. q! o5 ]output mcasp_afsr,/ r) u) x, Z" O
output mcasp_ahclkr,
2 R: U0 Y) f2 l) Xoutput mcasp_aclkr,. h! F' ?" A( H
output axr1,
9 G/ E/ M1 G& |, s& X, r( X assign mcasp_afsr = mcasp_afsx;
" q& ^4 F2 E- ? E' N6 F# Q7 g9 Yassign mcasp_aclkr = mcasp_aclkx;
+ ?5 V, p5 s; C# uassign mcasp_ahclkr = mcasp_ahclkx; r* i! A: R( i8 [8 K3 ^: V
assign axr1 = axr0; 9 a g. s" D& r6 a: x8 z9 }$ _
* j' J; K7 Z7 N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 f' D* d: D' _5 M8 n
static void McASPI2SConfigure(void)
6 R0 `5 ?" g. U{7 y$ `0 H/ e1 g0 x0 k9 l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; \ ?2 d, Z- B; h% o* Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
m' ~, b" G9 s7 G7 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ F. ^ x$ ~# c& H8 ?' e* C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- H, E F) Z* t; h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# w8 U5 E t9 X( }( cMCASP_RX_MODE_DMA);' B/ e, {4 Z1 z/ o8 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 M( g" Q% E# g- B# |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. @4 V9 Q! ]2 V* W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# D0 j1 z: g& Y# Z" A ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 n0 o. k" q1 X2 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # K* t9 m" {% h! m0 `5 Q$ v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 z" c3 }7 v/ l2 \7 I) rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% e1 Q( _- z4 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * L0 y6 w+ J7 M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% w. }/ @! v- y5 j6 o$ i- h9 {
0x00, 0xFF); /* configure the clock for transmitter */
& M7 m5 b5 [& F* m8 W7 `7 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 I$ J5 t7 g7 P( J2 ^' Q9 }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 y% k) o1 b" c$ J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ [; E( |3 ^; u7 E) s) p* I4 \0x00, 0xFF);
$ A7 M( J; L. Z" h5 [0 O* P1 C
% e- r8 N1 k1 l2 s8 \/* Enable synchronization of RX and TX sections */
* |7 r. Q# W" k$ V$ C0 i: l% FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- d: N9 u) R; z5 ]9 d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. K' e' T6 {- U2 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" I. E" \. {; \9 M' S4 V** Set the serializers, Currently only one serializer is set as
* {. K, n& @8 E; W6 s** transmitter and one serializer as receiver.
& D) w, k- X% S8 W' r# j*/! s+ {9 A5 s- m" c+ L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* r1 h f* {. U4 QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 F0 r2 q) {3 R$ C** Configure the McASP pins 3 n7 k* L ~8 ~" j
** Input - Frame Sync, Clock and Serializer Rx
) q. c# i: ^0 x( T Q, c** Output - Serializer Tx is connected to the input of the codec " `2 k4 P% [* I. x8 t- `( J
*/2 L* Z' |. Q! H) C' ~+ c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% b( Z, q: v3 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ V8 k. b; Q1 @' ^ B$ u# f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' f# I% H! ~& t( i9 s( B$ a
| MCASP_PIN_ACLKX
, l9 y; ~, r2 T) F' `' V0 ~( C- y| MCASP_PIN_AHCLKX
; }: O6 b5 R3 _- j" \- ?7 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ A& H. l- {9 R8 o: FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 q# n8 @, V: l z9 C
| MCASP_TX_CLKFAIL - F) O, a% U: \6 L
| MCASP_TX_SYNCERROR
J$ ?3 Y6 z+ G1 i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : |! g8 y# z+ X
| MCASP_RX_CLKFAIL
* B ~, H' j- g1 e4 H- I" z| MCASP_RX_SYNCERROR
0 C0 {, z" Q/ a; z2 t- ~| MCASP_RX_OVERRUN);0 z# j) c3 f1 s% e: I# i
} static void I2SDataTxRxActivate(void)
5 t# I3 m: A4 [{1 ~1 }6 J i& u* y$ ~
/* Start the clocks */
# n# l; ]3 F$ L* \& L$ k# NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. P7 X' ^. w- _+ ?, s% T. |7 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 C+ W, ^, s ^- nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: L8 V2 ^8 R: ` O) fEDMA3_TRIG_MODE_EVENT);8 H- {9 h9 }. X/ Z- @1 s3 y0 I0 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! J$ b1 N$ e- d+ C4 c! W+ | V& sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" U% t: ^# v. d6 Z x0 _, b% o# _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( B# T! ~( }2 A" `3 L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ V2 P/ t4 H& t/ {# e5 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- z0 g+ t+ B" B! fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 k% x4 n( j- b5 N; c1 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 H( P, M! p% i1 K J; O/ k
}
7 M E% n _. E( F3 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 J; y( C0 Q4 m9 [2 D# Z+ Z
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