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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) h! V+ u; R, q
input mcasp_ahclkx,
# J: z0 T% l* F' {input mcasp_aclkx,
9 O2 H/ {, i3 E+ ?* ~input axr0,
, r8 n# `/ `; J! @4 z2 H* ~( i$ x' u9 v- I3 x
output mcasp_afsr,. J9 Q! U' h3 K- n8 u" G+ R% P
output mcasp_ahclkr,% O! W7 a& R! U) B7 F8 l
output mcasp_aclkr,* }1 C0 B( o! u% X
output axr1,: x, u J2 o$ G* c) o& r
assign mcasp_afsr = mcasp_afsx;/ G6 N( w0 ?4 x/ U/ S8 }: n
assign mcasp_aclkr = mcasp_aclkx;- A4 e) }% W. a
assign mcasp_ahclkr = mcasp_ahclkx;8 d' |7 ?, f' u+ T; L7 X* o
assign axr1 = axr0; $ z1 w- v* y s: ?" c; f! A8 c
) B7 @0 B( {" k- C- P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 q. a1 @: O5 Y1 Y5 a
static void McASPI2SConfigure(void)
: h l9 F$ {4 v! p4 R+ s/ J) u{
" O) p0 ?9 ?# l; f7 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 L1 ]& g5 |9 c" WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: }2 D6 m: I9 I- S/ j# t/ `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) p9 A+ C2 E7 ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 z6 ]" C& v' n3 f9 L% x- v I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
J$ W7 h: y$ Q$ S( m9 }2 i8 }MCASP_RX_MODE_DMA);5 L' x5 W" \" V# K7 K0 v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 K" q; y) J0 S" V; M% q- P6 h( }- JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 R) }0 D( ~6 F0 d0 ^8 h- qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 j7 L. _2 E, M: `$ n; ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: ?' ]: r0 G: }0 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 Z, e) P" o& P/ E/ QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 y- B& p0 h& P5 }- CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, ^& \, n0 U3 e5 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. l! t6 t$ l3 i" Q* d9 w8 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 U Q/ b0 x u
0x00, 0xFF); /* configure the clock for transmitter */' U* k9 d8 _( P6 s5 H! j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 s8 |- n9 G5 t1 Y. u. H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * A( M1 e2 l5 `2 G. M9 d9 V. w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" ^! p0 I4 }2 d9 z) r5 m9 @0x00, 0xFF);- B6 z9 Q# s7 T& N8 j4 v. }
7 _# s6 s- B$ B) V3 P6 ?5 h/* Enable synchronization of RX and TX sections */
g0 M3 C; n9 n0 t4 s0 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! o5 o R( w4 n' e# Q' r% F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; _8 k% [* ?! g1 }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& H. k0 u8 k% @: {! ~** Set the serializers, Currently only one serializer is set as! r" G7 i0 I% O
** transmitter and one serializer as receiver.7 O. m+ O, U. A. J0 p* [. Y1 |
*/
, G6 J( P, y3 S. v! |! LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 {+ \* d" W$ S( iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( a6 L+ K, V6 B R7 G, l6 L** Configure the McASP pins
4 n& X* }6 o; ~# |. r# I** Input - Frame Sync, Clock and Serializer Rx
. @" ^. u' w& l3 o |** Output - Serializer Tx is connected to the input of the codec
8 i9 P6 `4 F; H$ \! t9 u. R4 i8 F*/
; I+ V, G8 \0 u4 a4 i4 n( r7 s% V" k9 oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ x: q+ j9 o( O5 t; T* R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! \+ O4 r! k/ Z5 v) t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& z, G2 q5 `0 w* Q. l7 g4 ~| MCASP_PIN_ACLKX
& p7 k5 k. n# W% ]* T' k3 ]| MCASP_PIN_AHCLKX
' N- z1 G* E6 o. c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, u3 w+ h g3 i" @( f, HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: e7 T# \) O2 B4 S2 || MCASP_TX_CLKFAIL , {5 `' X q0 x& J: Z: h
| MCASP_TX_SYNCERROR
9 T( @7 y$ ]( l+ f0 L- X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 d% H& _! P+ d5 A) F( A| MCASP_RX_CLKFAIL
) M4 i9 }! f; E! o| MCASP_RX_SYNCERROR
( o; D" v6 E2 m( L# A$ y2 k- N6 _| MCASP_RX_OVERRUN);
& E! N/ q% @* D} static void I2SDataTxRxActivate(void), I# ~" p7 E1 N# t5 x/ Y
{2 F1 o0 F- |' N3 U# l" I
/* Start the clocks */ Y7 X" z3 c" X. q8 g- |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 r4 R% E3 r/ l4 O6 p: x3 ?# i5 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- J. J7 H' j# p% Y, J: lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 N# {9 Q! ^7 a% ~
EDMA3_TRIG_MODE_EVENT);: Y% G- w! }0 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 ^% s* N% a5 V1 M# C" d! X. bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& m6 q; |. l5 L3 o) G# JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ e4 S1 U, H+ Q2 r; T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 x( E. p& t4 A% E7 f( [& \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 u; d2 j( w' O# @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ D% w) d, u. h2 q7 f: \2 ~: m+ qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( l$ `: x U6 _) k7 J" _6 Q8 k}
$ F- ]0 F* b& d$ q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 N ~. |, R) p& ~' t4 ]1 r
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