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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# S9 D. t0 n/ @& x+ kinput mcasp_ahclkx,- B) b9 c$ |4 R; G6 |* s, r7 s
input mcasp_aclkx,
# R! y8 C0 u5 G- z- X) Kinput axr0,
( g; C: k( x X: g$ T9 O: {; d7 P# O I u
output mcasp_afsr,
- k9 ?: i5 a9 {# Doutput mcasp_ahclkr,
7 Z) K6 ~" \5 l0 j# H9 h; N# zoutput mcasp_aclkr,3 e8 n% k9 T& W2 g* y! A
output axr1,
) D- r; k7 ?2 n$ B, i- v assign mcasp_afsr = mcasp_afsx;
3 a6 o# ?. @1 \" l! y% S# sassign mcasp_aclkr = mcasp_aclkx;, G8 l# b- n, k" R9 ^* C8 _3 }
assign mcasp_ahclkr = mcasp_ahclkx;/ B2 R9 C. F# u5 ]* u% U2 w
assign axr1 = axr0;
3 R6 p: D0 q2 ~) h' t9 m0 j6 r: k3 e' p# p0 u! Q9 F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 H5 |7 K: b( x
static void McASPI2SConfigure(void)' ~9 M* c, H/ r9 y, K# T, d% h8 ]. o
{1 X- J |0 x% @9 R% ~- n+ k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, d$ q2 I1 M4 S i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 v* n8 S. \! M9 G7 d8 M& i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 B/ t7 ~) Y7 ?! c5 \3 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! j% p9 t F" v, y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' L: P: G# U3 c% `: M
MCASP_RX_MODE_DMA);. s: ?+ ~! b3 R& l/ Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) V( c7 Y9 ~( p8 lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: X$ @4 c. ]" L1 k8 b9 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% [8 z) M# B( Y& JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ l; x+ C3 \' D, Q4 \6 e1 V& kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# c' L% G0 n7 B. V& S. j4 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. B8 v/ a) l* \1 f$ R1 PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% l8 t0 H/ N* `5 cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* t0 `+ C8 v$ e$ DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& s6 d5 R8 }; G3 R# ]
0x00, 0xFF); /* configure the clock for transmitter */# f3 b4 }/ p3 F0 C: _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' R2 n: |# W# r0 ?) ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); c7 Z6 r* K6 m& W' r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: R+ P. o8 H( R4 O0 O- S. j0x00, 0xFF);; a" x* ~& y+ F. c8 Z+ J6 y
( Z0 |+ A% b) S2 W; S& ~
/* Enable synchronization of RX and TX sections */ / v3 e% x6 f1 {! d$ m. l1 `9 l$ b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 b. m E1 a# D% {5 D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 h7 F4 I0 W" N/ x! iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 s& t2 c1 ?3 b/ {; B
** Set the serializers, Currently only one serializer is set as1 j: O- J/ J6 q- J' Y4 m# Z: P
** transmitter and one serializer as receiver.
& ?/ A1 x4 y" X8 x" V0 G8 _: {*/
7 n; d+ K$ v' w) f; f. PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 g3 b1 a" b- c) k H# a) @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) y; K6 ?+ x# l7 c9 x% _
** Configure the McASP pins # W, M$ X# P$ B0 `
** Input - Frame Sync, Clock and Serializer Rx
: B: C k S0 P** Output - Serializer Tx is connected to the input of the codec ' V8 \) |# {0 v3 i D. R2 H
*/
! ?8 u/ A! m- w( m+ F! tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
i2 Z6 m s/ H5 k8 L$ _3 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' e5 t1 ?3 \& h6 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX z: I* K) Z' S5 J: W, t( z
| MCASP_PIN_ACLKX
$ p# j I$ \4 \6 v( n- r0 W| MCASP_PIN_AHCLKX! a9 Z$ L' c- \* F2 ?5 E& n+ R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! z/ F: m7 {. n7 r- @3 KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ ?7 ?9 E: C3 ~$ `4 O| MCASP_TX_CLKFAIL
5 f* C& U% S" @2 `| MCASP_TX_SYNCERROR$ x. I# ^( i8 ] |% ~& z. y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / E5 N- O. r1 K3 ?9 c
| MCASP_RX_CLKFAIL
; B7 ]/ F5 |6 a- W% j' B2 N( A| MCASP_RX_SYNCERROR 3 x$ T- h: [" o
| MCASP_RX_OVERRUN);1 s) `/ f: \4 N; v. ~
} static void I2SDataTxRxActivate(void)
* t K4 ]% k* E{
4 Q, E7 A1 I- ~6 Q/* Start the clocks */- U3 `2 \6 @% ]7 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" m8 M& c2 I4 K2 EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 k6 \. t2 Q; Z3 J$ L( Q* \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, L$ m: e; L- \$ {+ F
EDMA3_TRIG_MODE_EVENT);% `0 B0 Y2 H4 b) c* x8 B* P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 {( B* e" x' u/ c# D+ U6 P, m6 T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- H+ A$ R( l4 Q' D. M% G# Q. _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' B+ i$ Z; _" m1 iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 g2 O& A7 v( {6 M3 _ Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( \2 k/ {$ Q! K% ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 o4 v) g. M+ j/ @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
u; p) M! g G B/ d- p} , B& B$ q! K8 R) ^4 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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