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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- F3 z9 g9 F* v5 y0 H
input mcasp_ahclkx,
y: Z; u+ Z! T- O) X0 kinput mcasp_aclkx,
) L% W4 h( A, l; s2 Y, {input axr0,
e1 h: S! c c' j: w5 E
# f: x- ]2 K7 O# W; u0 w6 {* Koutput mcasp_afsr,
: E6 C) ?' n8 k8 poutput mcasp_ahclkr,
: H; S! p7 o) N d5 k- z o0 o7 Loutput mcasp_aclkr,/ |9 B# `, j! ^" s
output axr1,
! ~& U! ]: y9 c. s1 p8 I& C: E$ G0 B assign mcasp_afsr = mcasp_afsx;/ A0 H$ Z4 d+ Z' _& _$ v) m# J
assign mcasp_aclkr = mcasp_aclkx;
2 \, x$ t- N2 j, s7 passign mcasp_ahclkr = mcasp_ahclkx;
% c+ q* a+ a9 f/ `assign axr1 = axr0; 9 K/ }3 n0 u% _+ _6 V
5 x0 O9 t5 P& ~! O( g) Q V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 w- j5 g0 u& f: }' v( |1 j- X
static void McASPI2SConfigure(void)8 s- f0 R9 ^* S9 |9 ]3 \, Q7 p
{
) P8 R# ^4 o/ E3 ]7 r/ e# M7 g t7 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- Q3 f8 |( Q- ]- G5 C- S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
V9 [2 `# }) b+ vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 L C+ o: q* I- i% T$ sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( Y% S: C- P! }6 o+ vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) U( F _; m; M2 U+ r4 |% l' FMCASP_RX_MODE_DMA);, {- ?6 y2 ]: M3 v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 P$ O' y9 X6 B0 [2 B+ U# d5 b9 n$ hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 Z) O& x6 I& m: I3 U8 c1 L$ h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, M7 E# A- S4 }( k1 I! @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 B; Z' x6 }. [# l0 }. y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! A( T" N' u3 l% B7 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' D- _( F" Y* E2 j' i& w" ~5 qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 s) {2 z8 ~) {4 t# j+ cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; w( s8 f% G! i) b# A2 O5 [9 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 A( J* h+ x: A: ?0x00, 0xFF); /* configure the clock for transmitter */
! v" W$ ]& ^# G: R5 L* M6 I1 `0 T2 N( oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
A' p% A: ]2 _% M8 I) a' f3 [9 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : p( e. E+ u5 ?) u5 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 v. G# i/ `' _; {
0x00, 0xFF);
9 ? @4 L" d- ?) \# t% j" _5 l: M" m9 R" ]# y: u1 s+ J& Q$ x) `
/* Enable synchronization of RX and TX sections */
3 h1 U, S4 y& yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 o5 S! x. I& m2 {: g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# ? p6 M% z0 o: \* H. q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) r/ l' }/ d$ F4 x** Set the serializers, Currently only one serializer is set as- |6 \% O* n0 ~7 f" V/ v1 D
** transmitter and one serializer as receiver.! g; @# s2 I* B6 W0 A9 {4 v+ \
*/
. G' C: F: A7 B7 }& D2 h! J' ?, hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- [2 X5 g; I. b' a4 q; ?, o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ R! G S" @* S% q6 N6 G B** Configure the McASP pins
9 _7 p' j7 y8 @5 F9 s" V' G** Input - Frame Sync, Clock and Serializer Rx
) n' P( C4 ~8 Q2 C# E. j** Output - Serializer Tx is connected to the input of the codec / K4 r% Z" o7 y! |; [! F
*/
& y0 G5 c" G* j' _3 j8 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 A q. R; } e; p3 x0 b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 r8 U ]7 O/ @* X3 o% A2 D0 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 i! g2 E: F V2 q, m| MCASP_PIN_ACLKX+ k! x: C7 L2 l0 T2 U7 H) d
| MCASP_PIN_AHCLKX5 h. I* M) U+ f6 y% k9 u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ r; h3 o& b4 T. O$ u& ?) A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, n$ ~8 ~- u7 a| MCASP_TX_CLKFAIL 3 F' B& `$ ^( l) b: V
| MCASP_TX_SYNCERROR
3 t! ]) |# f2 h+ P6 z& H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & `4 h8 O: r; w% r+ i# M
| MCASP_RX_CLKFAIL' d) Z: S: }% u
| MCASP_RX_SYNCERROR
' g0 }& d+ [( V; y8 h- f| MCASP_RX_OVERRUN);" U. S/ J+ Q. S8 m c7 G: j
} static void I2SDataTxRxActivate(void)
* P; I; Q4 K9 k I1 W% S{
8 Q0 O+ O# w# x* @/* Start the clocks */+ u" ^" U5 V( K" X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% U) _' a0 r0 }- ?( @/ E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 M V- e& b2 r$ wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# s! A6 v7 y3 ^EDMA3_TRIG_MODE_EVENT);: B# X% }4 W' w) A& C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 x/ h0 i/ ~2 p" b6 F/ W# eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 w, F- O- Z+ S1 f9 l' p6 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: u9 N* u( @% \& b" t2 E7 Y" H* P* IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' D2 b& {8 X* Z/ k5 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// @% U0 r6 c7 [/ W% t1 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 y( p3 b. T5 Q, A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% s& }: g; l# r}
2 ]- }6 Z& `% y; \' x; h2 G* E( S1 P' p. u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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