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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' s/ [4 A. V, p- s
input mcasp_ahclkx,
# U3 Q! }# ~6 r. Ginput mcasp_aclkx,
" I" R' O: o. S9 f' Oinput axr0,2 X3 ~, l2 ~! H, s8 v! O& K
) C$ D, c, r' N3 `) a; {) a5 Joutput mcasp_afsr,
! b) O7 Z+ d! M$ x2 p6 }" Uoutput mcasp_ahclkr,
$ N: D8 M& t- S/ A' q) w" houtput mcasp_aclkr,
$ w- W4 \0 X! C. X; D. I- L4 |& }4 Zoutput axr1,
: w, @. c& T) \9 [" k assign mcasp_afsr = mcasp_afsx;, M+ V2 }% d9 s) k/ D
assign mcasp_aclkr = mcasp_aclkx;
8 b3 t! j3 I( M7 ?# i& Q9 U. \assign mcasp_ahclkr = mcasp_ahclkx;* A& x3 B! M! W l% s2 t4 L7 o# N
assign axr1 = axr0; / A! M8 n2 u! S+ H/ \5 R
0 q% W. R4 F i# q2 L8 b$ ^: T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * g( ]7 v1 U0 u
static void McASPI2SConfigure(void)
, v: ]) N6 N) ], E% u{# p/ q1 Z: {; E/ o. {
McASPRxReset(SOC_MCASP_0_CTRL_REGS); M. p9 A4 ]3 C8 F5 \9 Y, [5 Y+ N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 t5 r/ P$ x) h6 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ k/ O( R. Q ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 C( C1 V6 g) z H6 h) B8 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ F- B; A9 U) _* V; X: ]0 m' wMCASP_RX_MODE_DMA); t3 Z) ~- z) U& B1 E' ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: s8 _$ ^6 a$ \) H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& m+ u$ O& j V3 T, I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
G9 e0 ~! l/ i& i/ E4 PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 _# P( K4 Y+ v5 ]% v4 m r+ UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 F( M! W. O$ [- d. v2 ]* k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// ^& H. n4 H! b* v5 U; ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ |% K% L8 E+ v4 G, j; s8 t8 o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; e+ l: _2 z0 ]. D7 f7 R# sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: J8 }( n9 n0 ] n' c5 |
0x00, 0xFF); /* configure the clock for transmitter */6 T: W& b2 l) p8 a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ X* Y% L9 G# X2 f1 KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # h3 c( G1 \; f3 z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 s+ u, i- [9 z9 ]" Y1 Z$ a
0x00, 0xFF);; ]# E2 Z) `$ r* M J! p
3 M% @! H0 G6 w! R! x/* Enable synchronization of RX and TX sections */ " e/ I ?! G' a9 l; ]5 c+ Q. _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 e$ b; C# K# y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* L U& J: Q4 K1 t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* v' h z% g: d( i# L5 y** Set the serializers, Currently only one serializer is set as
$ a6 Y0 H1 D$ |1 p( ?1 V/ T** transmitter and one serializer as receiver.. G) i, C+ A& E& o& y1 s1 ]
*/
8 Y! _9 U" q6 {- f. qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' P& F9 ?: W8 R5 u' r9 WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ e1 K0 v0 R8 f- v+ Z h** Configure the McASP pins # {' g/ |, K; W7 Y
** Input - Frame Sync, Clock and Serializer Rx
2 N8 O! M5 i+ Y7 } b+ N/ g- J** Output - Serializer Tx is connected to the input of the codec
G3 r( y8 ~3 k( L*/7 z% g P/ L) U$ u( B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 [8 j- U& n/ l: qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* M' W0 u' q/ y/ Y8 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& |5 ^/ L G( U4 }* S M| MCASP_PIN_ACLKX: p# c0 B/ Z- Z1 q) K) d/ W
| MCASP_PIN_AHCLKX* l7 q: b# m+ P, a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 ^/ D+ V" o: i, C8 D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; k, \$ {' H/ o& f' A! M| MCASP_TX_CLKFAIL * h) ]8 Z$ ~# W8 B2 s1 D& d
| MCASP_TX_SYNCERROR
g: Z9 A* u5 u1 M% P4 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( K6 T: O# ^% l# ]+ ^) q. h| MCASP_RX_CLKFAIL# E& P, _5 f3 e* T9 P
| MCASP_RX_SYNCERROR ) D. f& s0 i- b: o# `) v
| MCASP_RX_OVERRUN);3 d5 X& \; x+ B$ f' R' v
} static void I2SDataTxRxActivate(void)
, C& N0 H( f- A# J{
7 U1 I% h# G/ }, {3 T% r8 @/* Start the clocks */
# o E4 J' c! \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. t" ~9 q; L8 G9 J& `3 S8 c( bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& y, @2 }9 S) @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 ]% ~9 ?+ n0 y2 G3 N+ x2 ]0 a5 m
EDMA3_TRIG_MODE_EVENT);
/ L* t c: P' ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ p) P. j3 A1 N( }$ N1 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 ?7 j) x) Y8 jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: j8 k& s# E( D! ~+ @* ~) n4 L. ?' t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 X; E) r5 S3 y6 x, G) u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( k& f2 ]& i( r3 Q, b( c0 b$ UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! q) x5 V! i; }$ P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ q% I5 q$ a2 C, r
}
4 Q0 C z" N' i4 E$ `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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