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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 L5 [2 V$ f: S% C$ Z7 L4 d9 r% t" Ginput mcasp_ahclkx,0 S2 o7 l q- H
input mcasp_aclkx,
/ T5 l$ D# T2 ]3 C$ Hinput axr0,* B: E$ d0 t+ i' V
6 y2 {& M$ |0 Z, ? soutput mcasp_afsr,0 u7 y, L$ Q7 T* u
output mcasp_ahclkr,
- B# w5 g, ^' T% Q8 [' G! aoutput mcasp_aclkr,
9 [4 C1 j& {' Voutput axr1,
7 c2 j' b/ o! T: B+ Y( z assign mcasp_afsr = mcasp_afsx;
, q. [- y6 X5 a5 k. i% Rassign mcasp_aclkr = mcasp_aclkx;
- `& e+ u6 r! X. s5 {assign mcasp_ahclkr = mcasp_ahclkx;
+ @" m- }. F+ C8 a C$ passign axr1 = axr0;
6 r. M- m' c, Q$ V8 L
: s. E: ?3 ]! H7 z" q' g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 L. [& p2 |* j7 hstatic void McASPI2SConfigure(void)
0 J) E& ?* |# C0 R0 Q# Q1 x{
& W0 X1 e9 t+ h. Y) [ m3 ^0 {McASPRxReset(SOC_MCASP_0_CTRL_REGS);' f% O8 v# O4 I/ v* |" v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 ~* }/ G! ~ P, j- _+ \! v+ kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 D" ^2 _) T2 \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, P% D2 P4 l! a6 g8 l5 ]. N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, M$ u6 h2 q# ?: f$ l8 m3 HMCASP_RX_MODE_DMA);/ ]6 j; F5 w7 U( V* z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 q. y# h5 t) T- \1 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 q: E5 b: z9 p, b- |4 b) hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 k2 Z, ] j4 d. {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 \" W1 I8 f$ U, K, ^, i' C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! d2 Y& L9 I1 o8 M5 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 G6 h* c) E4 i4 _3 kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( r1 m, w8 S" ]; f, g/ qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & [5 b% U5 T* {! j" {% z" F' m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- y" i. P' X" o
0x00, 0xFF); /* configure the clock for transmitter */* n& R: i' |7 X1 N) f( c3 J7 M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; l. f3 r& O# L3 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" i4 u5 N" R0 O& W" QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! Y, c. s9 D# Y$ M" I O3 ?- h
0x00, 0xFF);, @8 Q) o, C( J0 e0 y/ U
" G% m. f+ o' y" r- F; k& n/* Enable synchronization of RX and TX sections */
% e' b, E4 p) G+ f" wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 c8 p, r2 v1 }, YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 d9 l4 L1 y; x) g& X# gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& F7 o* j) \1 q9 B2 s
** Set the serializers, Currently only one serializer is set as
% ^0 H2 W6 ^0 T/ F** transmitter and one serializer as receiver.' x8 b/ I/ E$ @- S4 x' E
*// {; P( X8 }; ?3 z3 A! k. y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; G5 P) k ?- D4 B3 W3 H5 e0 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; b9 c7 [' A* \* [2 U$ [9 }, H
** Configure the McASP pins
: Q- Q" L' I( A( ]** Input - Frame Sync, Clock and Serializer Rx1 ]( Z8 ^, C# A6 r: R. [/ X
** Output - Serializer Tx is connected to the input of the codec & [8 x; A/ p, P+ W
*/7 z$ X5 G. j' F7 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: ?6 U- }( x _$ Z+ K! b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# g$ ? ?9 E' Y) [ rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 }% h) d" d& d7 a4 t+ j, o$ a
| MCASP_PIN_ACLKX: q6 ^$ b5 ]0 i' }3 v. l. W
| MCASP_PIN_AHCLKX
6 {- M/ z* z! A, `2 y: H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ f% a) g( D5 l, B7 W% v8 u, B2 T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 N V4 N7 `5 O| MCASP_TX_CLKFAIL ' F$ p; t+ _& l8 N6 M7 D. h B g; `
| MCASP_TX_SYNCERROR. y8 r! M5 o( i- C# ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; T* r2 t9 F6 q# i& L& p: y( e5 r| MCASP_RX_CLKFAIL
& K: x9 A- ?% q| MCASP_RX_SYNCERROR
' n$ ~) c# B4 M9 B| MCASP_RX_OVERRUN);! B! k+ C! `+ b, p9 p* W; Q
} static void I2SDataTxRxActivate(void)
3 i1 t, ~2 K* g$ K7 _8 F{
3 r |% B, x* o3 n# j8 E" |/* Start the clocks */. }7 O' _9 @! y" l9 J+ D. b7 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ a" {' A0 V" _2 p3 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* Q/ s, l6 {2 J. h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ G" B/ r% M; P* L
EDMA3_TRIG_MODE_EVENT);
9 y8 w. t" U+ S* i6 a, v7 |* y9 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 a1 r. Z" l9 G: rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% H% ?7 S- R( v& Y2 ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* j1 `& P( x0 H7 t* bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ }7 b# Q9 v- `2 ?+ Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 j9 g* J& j3 @( R; m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ [$ g& u0 b5 X7 P2 B! U( K A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. @5 \/ ^0 \* j) X" u: ^}
1 S$ J, @1 \5 m# @& ~5 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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