|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 U' C( p9 w, ^( r0 t& P
input mcasp_ahclkx,6 t7 l" I) u% C2 c% E- z6 {
input mcasp_aclkx,5 ~+ Y3 H( @; a5 }4 U1 n; \1 G- o, P
input axr0,. `) B. c: { P
1 s' Z) {- s# o3 v; soutput mcasp_afsr,6 ^* ~* m1 r0 x
output mcasp_ahclkr,6 [. f. e1 [ }, C7 _/ M) G2 }
output mcasp_aclkr,. f9 e: R1 a! G! Q3 G7 c3 U. a& S
output axr1,
3 @9 j/ Z! q; h: G assign mcasp_afsr = mcasp_afsx;
: m9 V9 }/ m' Z% J9 _assign mcasp_aclkr = mcasp_aclkx;% s# E5 O# F- x! O& s$ Y% Y: M# f
assign mcasp_ahclkr = mcasp_ahclkx;" ^8 ^5 }+ O! A7 l0 X7 P/ \- ?
assign axr1 = axr0; : G* |/ G9 O- k5 h1 h6 D- ]
1 l/ h$ a- X% W% K7 c b3 Y6 y. V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " L) }0 a T; h
static void McASPI2SConfigure(void)
& F" Q2 S+ h8 M4 x0 h; K{- p1 z2 _) s9 R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% ^/ w$ e: R5 N6 q' XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ T- a/ b) {0 e% H, b8 E4 w5 T8 ?: [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* K' J+ }$ F; M. UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; h& g( @) ?& I" LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. \. B, O1 v! e4 u3 y G6 vMCASP_RX_MODE_DMA);
# t+ `0 T1 p6 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: D9 T. E2 J, r0 a% t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; U4 v3 B2 h# R0 [7 k; n3 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 ?! f, l3 O9 Q- h6 n" k2 L( m6 C r! xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ f- a7 e' T1 I/ r1 |8 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / ~+ Y9 L! P y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! L/ i5 B% t4 L+ ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ ^+ d7 ^6 i% v# N" K( ]6 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! [+ m- m9 x+ o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ t M* D$ j6 {8 x% P4 K& {# t0x00, 0xFF); /* configure the clock for transmitter */
) d, j. u% d1 ^" } q: u; X. QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); P6 P, D5 N& A! n" x {- F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , |6 t7 S' A4 I6 B- F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
@1 G) _0 ~. k; \4 v1 Q p% @3 p0x00, 0xFF);
4 ~" [* M, g/ K9 w' n6 j- U# Q5 L) P* C/ R! v4 l4 P: x0 s
/* Enable synchronization of RX and TX sections */ 1 i6 ?1 f% c7 w8 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* i0 Y4 e. U6 E! N3 A7 T! P# r1 V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 }( k9 O4 W2 P8 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; C: z0 u2 f" f* L9 U( t
** Set the serializers, Currently only one serializer is set as
; X+ v ^( ~$ F9 O9 k3 D** transmitter and one serializer as receiver., X9 S0 w, r) a' m/ S% [
*/1 S' {% R, h% [3 Y1 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ [: M G- M6 M3 b' N& B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( q2 M6 @6 X9 J) u7 T C0 s \$ ]** Configure the McASP pins
6 S. o& o$ y2 @+ j# _$ d** Input - Frame Sync, Clock and Serializer Rx4 j/ k' L/ ^8 W6 N& b) k; Z
** Output - Serializer Tx is connected to the input of the codec * o& k- g, I( z! i# j7 V: E) a# R
*/* B' M8 J \* Z) `7 M" F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' v5 ?- L- O+ r9 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' d5 u, W. q4 F4 z, O5 J. A/ XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% L, v$ K7 @- P
| MCASP_PIN_ACLKX+ c* O; B, O' e1 I. T
| MCASP_PIN_AHCLKX
& d4 m4 l5 K; M' |7 F5 A4 H6 E* {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 m- `/ b1 E$ ]% G, u- {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 y! t& f2 o7 t' e) E| MCASP_TX_CLKFAIL
# [. i/ G# u1 a| MCASP_TX_SYNCERROR9 `7 m0 O4 S8 f" m- B! ?9 w a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 ~8 e1 s5 D3 G6 `1 D+ k| MCASP_RX_CLKFAIL: e+ t" O3 _9 v2 z- U t5 ]( h8 O
| MCASP_RX_SYNCERROR
" y- [+ \7 C- a" j- L* E| MCASP_RX_OVERRUN);
) b0 X% {& H, i$ S' C} static void I2SDataTxRxActivate(void)
8 @9 o1 i6 z, x2 o{
. U2 d0 m2 v8 P4 Z6 C0 b* z/* Start the clocks */
9 X5 E( s6 X) jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 b! r: f2 @/ z; L* LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% I# b) Y( h7 ]' ?7 p; J) OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, w. x l, e$ C/ G1 ~
EDMA3_TRIG_MODE_EVENT);/ k# ?7 a5 k( [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! M' M% ?4 j. N4 t bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: r x: T5 {/ j. t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, j" Z, V) d6 F7 J: Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& z2 b, X, U6 V4 Z* b) f; Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! i( W/ Y9 X# p) F- |) kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( m+ b" L6 k% [+ [0 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! {% J$ |: v5 H1 A" \! `/ r}
( I% m% e( g3 p# @/ p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 f7 C' I6 k8 Y' P |