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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; J! G ]6 a7 Z! u$ Iinput mcasp_ahclkx,
1 M: J8 M: n* N. W' Z7 h" E1 ? y& j0 minput mcasp_aclkx,' u! c7 \; I) ?
input axr0,' e5 G, W/ p$ c
/ i( W' x: L1 g' c$ z+ ~. o
output mcasp_afsr,
0 z6 M2 m/ \% m2 |5 s6 Boutput mcasp_ahclkr,
4 ? y- u7 N; ~& K* `# ]7 uoutput mcasp_aclkr,. Z/ Y$ \. z/ B% g! F8 J
output axr1,. c9 J, O& v" }+ |- k( Q' j
assign mcasp_afsr = mcasp_afsx;
& l; a9 } _0 ]2 Sassign mcasp_aclkr = mcasp_aclkx;
' l+ k! V* [9 e4 u0 Z8 Massign mcasp_ahclkr = mcasp_ahclkx;0 ~& y0 ?$ E% n2 C
assign axr1 = axr0;
' ?, R& j6 J) B; n8 E4 D& `4 K3 L6 ~* A2 s! K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 k" j! U$ |( B1 W8 Q1 u6 S
static void McASPI2SConfigure(void)" E& ~# t) |( V, ^1 b+ t) f
{) z0 d- z, K6 Y- c9 A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) S" \- ~7 h4 _ u7 z" EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
A0 x) j3 O4 `& G1 a% PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- N* ?$ B7 \: y/ w, y: r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 T. v* \& Q0 F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. p) F2 h) o6 [% EMCASP_RX_MODE_DMA);. ?+ ]" k( t3 n+ M( ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% Z( S9 T9 M' c, hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 v4 [6 y: H: Y/ s0 |( H, A; K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, w2 A6 T/ X& V* J. U% p9 c- pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. e7 A" a' c6 P) X$ p3 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
V. a8 x, n0 }' q! D6 z# OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 O( y3 V- y# f' qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 `9 G6 m5 _- o6 g) X0 ~- C) UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# ]. u2 H9 y3 K& N" s: qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 S O" |/ t/ C* P; p- I1 b0x00, 0xFF); /* configure the clock for transmitter */
f5 @9 Z: @% y0 {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! ?/ O- o0 \/ `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" E) ^8 T0 q$ A) I" @( iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 `1 ~5 R- P3 H: K0 f
0x00, 0xFF);# @" l! }! L. o% g2 a' o% S
# r/ V, }1 K: w( M ^1 D+ \6 K
/* Enable synchronization of RX and TX sections */ " e, {* L2 n. M. d# W: ?4 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 i! \$ _4 n1 O3 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) f: V0 i+ U. ?& s! ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 p* R% n0 `& O" V" S* C** Set the serializers, Currently only one serializer is set as/ z. J' d: X+ B7 `$ f' V% f! v
** transmitter and one serializer as receiver.% L9 b* ]' U* I8 [) t# _* y
*/
, y1 D* v2 r9 {! N1 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 i2 C+ c: F" R- V! D C; Q' @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! h) p. s8 o V& Q) ^0 m" _' s6 q** Configure the McASP pins 1 @% }2 T# D0 E# S7 ?
** Input - Frame Sync, Clock and Serializer Rx9 |4 q4 X! c6 g7 c+ z
** Output - Serializer Tx is connected to the input of the codec
* f$ @1 M% S* r- h3 I/ s3 L*/
8 z% y% {: O& [3 S6 z1 u1 j [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 T: G, E1 T `: `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# @7 I1 z, u# s& G; f0 @3 d; F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 i# k2 y' A6 g6 q+ q| MCASP_PIN_ACLKX
0 x- |* p) J$ ?0 s: u0 F/ v| MCASP_PIN_AHCLKX, W3 H4 l" G$ F2 y, }1 j" d) K4 \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 ?, A" ?4 D9 Y1 j) T: fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 i" S$ {7 y7 k7 u' R; A
| MCASP_TX_CLKFAIL
1 A% Z( V1 w# l' ~/ U+ O| MCASP_TX_SYNCERROR; ~+ q3 c5 b2 l, X" t# \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ p0 W9 p4 ?$ b3 x t# I| MCASP_RX_CLKFAIL
( B) H. [3 e7 q4 I% U; `; |5 c| MCASP_RX_SYNCERROR , H5 X& F( C1 r# K) O3 p! c9 }
| MCASP_RX_OVERRUN);
% o* b# u+ V) c ~1 `6 b} static void I2SDataTxRxActivate(void); C$ N. r, C# V2 m
{
2 {( y& K& ^- D4 w* o+ c5 R. U/* Start the clocks */
% M0 G5 c) b2 _" VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* U; C1 U: Z! u1 l' K. ` f& j0 n0 f5 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( E' p/ u9 |( U: s0 c( Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ L$ t7 Z2 p/ CEDMA3_TRIG_MODE_EVENT);5 l- n0 C- B. w' h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . h7 O9 a' m& l! W& }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) [) v9 s) z ~$ v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: b; ~ d0 X! U/ T0 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( N4 w5 m. ]+ u ?( Z" T1 \+ Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# _- R- N. F; u1 s+ C* VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 O e5 O+ P& f' n, P/ `: kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 ~; _6 y3 b9 n5 V7 y
}
" M$ o8 F/ [; F* Q% s0 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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