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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 q# J0 P: q; c9 cinput mcasp_ahclkx,
4 S. }# {9 @" N! f! K/ Q" oinput mcasp_aclkx,
/ ~) H5 w: K" g9 ^input axr0,5 j. i& U1 v7 l1 [ P" |; N* {2 ^
. g! n' N& x; u/ Z3 }9 Y/ v2 woutput mcasp_afsr,
! o4 @8 E: B* M1 M, G% h5 Y, loutput mcasp_ahclkr,3 ]( d7 y# a' T! t
output mcasp_aclkr,
, S5 h( X* t _, soutput axr1,3 ^ c" P1 g! L; M0 y1 e# R
assign mcasp_afsr = mcasp_afsx;4 G- Q5 D" S1 x0 g
assign mcasp_aclkr = mcasp_aclkx;* T' a3 s, F/ ^, t5 W8 [0 v
assign mcasp_ahclkr = mcasp_ahclkx;9 f0 S8 ]1 u) c' ?1 w
assign axr1 = axr0; 4 C% @2 m* D, k. |' ^/ H
' W. s! Q. g1 i9 V" M# } ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . m0 T3 V. h2 I1 v! S) T# b
static void McASPI2SConfigure(void)
7 W5 t: j; n4 |# v5 M5 V{! g, G! I9 v# N6 ?# g6 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 K" @. C! L8 [( S3 ~9 N9 W% f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: L6 C+ M6 K$ Y5 a# z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: l5 p9 C/ G, F3 ]4 n+ ?% T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ f/ [: G# E# E( IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 d6 ~5 G9 w' E4 F% ZMCASP_RX_MODE_DMA);4 j# D P ]) `* a* d; F7 C" }0 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& @% p- U6 y- T5 W. D5 B! x* q/ xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- P9 y" H( D, ]: q' Y6 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' ?. q' U& o8 ]& u, q( W- ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- _% O! q; `- Y5 i2 I8 [# n# mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : B* k: g O% g$ a7 c& `, I C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' Y w+ S) }9 z! U( W& n4 X( L4 s% NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 D* P; Q0 u9 e- O! e6 d4 w, K* R1 ?7 q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ P' k$ l4 m! A1 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 g1 W$ S# m, g' f0x00, 0xFF); /* configure the clock for transmitter */& O! [$ U7 k* ]. ] @8 M" Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 r4 y8 W8 v4 w! g2 _9 Y9 I$ SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' Z) t7 [: L, ^6 B2 l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 B7 G# Z5 f, Q v
0x00, 0xFF);3 M4 z/ W+ v9 I1 ^ z
/ f. w/ e/ v' v s, a: d o
/* Enable synchronization of RX and TX sections */
5 h+ V' P' a; S7 g" B2 l) o9 WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: O; A4 F {3 V+ R( q; ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! a7 j0 ^, X$ SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 |4 o8 L( e8 P% P. i
** Set the serializers, Currently only one serializer is set as$ Q. [% c& w! h
** transmitter and one serializer as receiver.( U6 E ]* b3 R% F. M5 _
*/
' C l8 a, P4 z Q/ f1 l, kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% S& M, L# G+ [# Q# M; X4 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# `/ d8 `0 Z% k) w** Configure the McASP pins : o; N4 g5 G; Y
** Input - Frame Sync, Clock and Serializer Rx9 J6 H; H5 g. M2 Z) x
** Output - Serializer Tx is connected to the input of the codec " ^ w# q4 X, B6 j
*/
) F( V- a) t& \% ^) R- hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 \5 w7 f; t: eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); G2 m: r+ S9 @- A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; l1 g e& x+ H/ x; h& P) [4 M7 A) s
| MCASP_PIN_ACLKX. J# n' z/ K7 ?& @; j0 ?3 v, u
| MCASP_PIN_AHCLKX* o7 F! y# i, ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) \" ^8 d$ h @+ f! tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 G0 A. r) @+ L8 {3 S
| MCASP_TX_CLKFAIL
i2 E! q; T2 p. W) J6 A| MCASP_TX_SYNCERROR# a2 O2 l1 X* ?: |6 `7 [; k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! @9 W5 `+ Z& `' d, y6 |2 d0 V| MCASP_RX_CLKFAIL
* R# ^/ h$ v& e- l& ?, \3 A| MCASP_RX_SYNCERROR
( c! c3 R% j1 [| MCASP_RX_OVERRUN);0 S7 Q+ _- m+ z& T. }5 ^) H7 F: t0 J0 ^
} static void I2SDataTxRxActivate(void)
3 d! Z8 G7 b7 M& j, M, t# r7 Q{$ j% z; |! s6 g9 g) h9 G# ~$ F C5 r9 v
/* Start the clocks */' _+ n6 @ ?, z3 l( [" T) n2 B& E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; j2 }; q; f% h' NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 D6 ]- S/ _: E& r& XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ c/ Q% z+ G& b: _5 K0 B& o9 @) P+ LEDMA3_TRIG_MODE_EVENT);! H2 d2 T/ g1 P8 O3 F% i5 b# A% y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ v/ q' T3 d% n. y: X; bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. ^& T% c5 P3 N9 N8 u7 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 \# Z/ G% h9 J5 J' TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* L" t3 U7 T0 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 n+ i, B. Z; s# BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 m& v* V; }8 {. }$ t5 x- e6 ^# cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 \7 q4 }2 ^$ }
} 0 S7 e& a1 m+ @& s0 u. M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 X+ B) y( F+ E$ s' E) s
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