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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 D6 w H8 F. {
input mcasp_ahclkx,
* c0 H# \) E& j" l( g+ i% |: Dinput mcasp_aclkx,( X$ d- ^8 _! N% @
input axr0,
3 K# O; H& b1 c4 y6 T4 C, Y* d
& N+ w6 l; [- s% g7 z1 Eoutput mcasp_afsr,
9 N- B: F) D3 S! O9 A8 [' I9 {/ Xoutput mcasp_ahclkr,
0 X* z2 M1 @/ k ]" ~1 U# S9 Soutput mcasp_aclkr,
8 {) w& r. j3 q7 T0 I4 O Eoutput axr1,2 @4 ~! f% r" s' }) v
assign mcasp_afsr = mcasp_afsx;+ P- C0 Q' S" \1 c# V/ k P7 z1 L
assign mcasp_aclkr = mcasp_aclkx;( E: Z% \- l% G. i, g4 D
assign mcasp_ahclkr = mcasp_ahclkx;
$ Y$ p$ o N* j8 ~. kassign axr1 = axr0;
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4 Z- Z. u* |$ N) p. C0 K- I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- d8 A4 u0 G2 b1 H+ x" t$ \static void McASPI2SConfigure(void)
* ~0 U! n) k+ p G9 h: ?{
, |, m1 A. d& w5 b/ l- FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' q1 R6 ]: H) W) [0 _3 kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, g- P q; K- Z, |$ G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ h* t2 n9 E! n) w/ @4 {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" ]/ ~& `+ T3 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* s; T: Y( p |; J- M$ K2 R$ W4 c. m
MCASP_RX_MODE_DMA);
% L- k" }1 z3 j7 h) `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- I$ g) \9 i4 y' o, PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 S* A9 I# O f7 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; q3 l1 t. ?. q: Y; @6 v* Q( ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 }- g L/ R/ x& i% m# x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 u* p* Q4 o* `* @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 [! `# G! b# H( Q9 ]1 |$ ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( R3 d! X) S. A; }$ [/ hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, q" v2 h6 M% Y9 N3 u9 A2 q+ ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 R. k) z0 L/ Q. D0x00, 0xFF); /* configure the clock for transmitter */
$ P- k% ?" _. w' n4 LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ [ j0 a, J* g4 }. ]/ [; Y) bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 j. U5 n- H4 cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; C6 g/ o" Y4 H. K4 |. {! i
0x00, 0xFF);
/ M: B1 J+ y: @% U) ?5 V
+ W8 V9 s% W8 z. I5 D C/* Enable synchronization of RX and TX sections */
. l7 @6 @4 Z$ {6 W# j4 P! W$ sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 x7 P1 @% H2 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) F. q1 n- f- o7 Q- S% ~# h& h) h9 CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ i' L# B& Z/ p
** Set the serializers, Currently only one serializer is set as" v4 G; w/ n8 A/ W
** transmitter and one serializer as receiver.
1 l6 ~5 _+ C, _' P4 {& u1 A5 R*/- {- F' d$ o4 n5 }: w1 |4 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( Y) o, ?$ e, Y# O. C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( P! M; b' q8 \4 y% N( v
** Configure the McASP pins ' Q7 w+ r8 i, K4 Q. |, ?
** Input - Frame Sync, Clock and Serializer Rx" r/ {! N9 W. b: Z; p6 G3 i) A
** Output - Serializer Tx is connected to the input of the codec % M8 d. r6 H. |+ j! j
*/: {# D7 Q4 S" P+ i/ l! j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- F5 b( f: W' T: @% ]4 g/ l; AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* B! g: H1 E fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 V0 d8 M9 x0 B! i$ Q! F& p| MCASP_PIN_ACLKX
, W( x+ k' T9 [/ b3 I| MCASP_PIN_AHCLKX
0 z, \. c6 N" Q8 K+ P/ G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 [/ G3 P Y0 r7 z* @: X: M4 }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' X" _5 h! v; I- v
| MCASP_TX_CLKFAIL * s. Q4 j. |- b$ e9 }( |, d
| MCASP_TX_SYNCERROR
. a) I: p1 M+ t/ {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 P" `* R, D# I5 S9 i
| MCASP_RX_CLKFAIL2 ]" Z" i- s1 _% @8 K& A
| MCASP_RX_SYNCERROR + F% I% H( C2 p/ O
| MCASP_RX_OVERRUN);
; g# Y3 B# x5 K9 a/ L- k" _1 m% M2 m} static void I2SDataTxRxActivate(void)1 g/ M) q) ]7 X7 Y, J
{
3 g- W1 i) o9 c( o/* Start the clocks */
$ h! f* H% w7 u/ Z; B/ UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% G3 D: s+ n2 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! H5 b: u ^- U) f, n3 w1 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# d1 t8 M4 w2 ~2 o# o' _; k
EDMA3_TRIG_MODE_EVENT);2 K; y0 ^! x+ m4 _) R9 y5 t* ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 r* Z! _7 A5 y0 s* a" x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: u% k, Z" X8 N, X5 u8 \) CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 D6 O1 a" {5 A! UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, z/ w1 ^* W0 F+ F y' s {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- j$ a/ I& i- W$ MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 B v' C+ ^6 w$ f' P" U0 S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, F, a+ V& v- V7 d& ]) _
} 5 Z) G4 t6 r+ n( Q3 _& J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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