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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 F) _4 |% `( [$ h+ V& G K, }
input mcasp_ahclkx,
4 O( O! D9 R) F7 _7 b/ C# R( {: ]input mcasp_aclkx,' k1 k% ]0 L7 J4 a- u3 ^( A2 X
input axr0,
8 U" H. \. |. P$ f- ]- F, [5 R
& V% h8 f( C5 g$ P/ Voutput mcasp_afsr,
3 Y% A+ Q3 j. t7 Z2 a# zoutput mcasp_ahclkr,' o/ A N9 m7 ]/ {2 {+ r- `
output mcasp_aclkr,
6 F1 ~) K' n) d1 ?6 p; voutput axr1,
+ E! O- m+ D* `7 h: [ assign mcasp_afsr = mcasp_afsx;) a2 C) X+ f4 L
assign mcasp_aclkr = mcasp_aclkx;. }. m0 x! g5 O. E- C
assign mcasp_ahclkr = mcasp_ahclkx;# Q9 d0 \2 s7 S6 w! d' \
assign axr1 = axr0;
: ~8 a, g: J/ c0 ~) o! Z
# }& X& {' b; Y" k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' g2 _! G5 ~/ o
static void McASPI2SConfigure(void)1 F. C% y! O- \) @* H; `
{
2 U; L8 }( ^+ f" _( z' W1 F) HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 \ y3 Z8 {; S* h* b/ j+ ]* t! ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 V2 e2 c0 K: g- r5 {1 L+ ^6 G, vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 r: T: U: v% H: g WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// O% Z. B* m2 v$ m1 `; \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( ] O: L2 Q: _: u% c, T0 SMCASP_RX_MODE_DMA);
, s* p8 { w4 {8 f. @2 a0 ~* nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ]9 m2 ^ Z' r! I* N+ E. j$ W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! n9 j: j$ H" Z/ OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
F& y' b: }+ h0 B0 c2 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 u6 W7 v5 K. u: b! G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 o& K' X+ w& Q% H* o+ M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) H4 G# P* O2 g! _" a$ s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" [3 k4 T v2 r g. BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ R$ q* R* R4 l9 y4 E6 O. ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 o+ `5 s! W; {" r
0x00, 0xFF); /* configure the clock for transmitter */
# F& D% W9 Z6 Q: ~. c- Z& r+ D! j; k! zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# g# D( ~7 v, R: j& i& z2 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( ^3 i# D! ?4 l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ B) i9 t$ S; V; A) A7 I2 ^" {. g0x00, 0xFF);8 \$ L9 X" T: V @$ O4 z; M [
9 P1 T0 K3 j. K
/* Enable synchronization of RX and TX sections */ % a* p% x7 r1 E& G o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( v; ?# u9 t. b+ z" X1 D6 q1 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, p' T7 }' N" uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 g# ^4 G2 W* Z** Set the serializers, Currently only one serializer is set as
! g/ [/ l& ^5 c( }. e) }** transmitter and one serializer as receiver.) o; `* i* F$ i4 F4 O. U6 Q: V/ h
*/ Q- g d- Y, M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; N, s* X7 x/ M+ \. K$ d5 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 T. i B3 P- H& [% o; w1 o% z+ g
** Configure the McASP pins
2 y5 j8 _+ {+ Y/ k2 u% B8 \** Input - Frame Sync, Clock and Serializer Rx
% E( X0 N& S( k** Output - Serializer Tx is connected to the input of the codec W9 ]9 j1 C8 A: R
*/
) w9 o6 U4 S6 n+ O. yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" m- f, t; K/ J/ ~6 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' r0 R3 Q1 v" R* P- K' f0 H7 O+ ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, e2 n4 L. N3 z% o7 s7 N
| MCASP_PIN_ACLKX% a& d6 k# D# f$ v6 U9 b
| MCASP_PIN_AHCLKX
- m+ z1 [ |( P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 }$ J7 s3 I, E, U3 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " Y1 J! H/ @- |# Q: c! C
| MCASP_TX_CLKFAIL
( p# v$ r( L, r% M, T" J6 i0 K| MCASP_TX_SYNCERROR' j* D0 P8 @2 Z3 G; }( |- W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 z+ l$ E1 ` D4 v% ~| MCASP_RX_CLKFAIL
1 r3 U* J& `/ ?+ s0 E" D| MCASP_RX_SYNCERROR
$ L' H' [5 E5 {" p0 [| MCASP_RX_OVERRUN);
) p8 j) }# C3 P0 M} static void I2SDataTxRxActivate(void)7 R$ o* C# B3 w" e
{
* v8 m ~ }% w& Y' u/* Start the clocks */7 D5 A: x H! G3 y, L/ [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, ^5 X* w+ b0 T. q; `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( P( R w4 ^) x% oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, n1 W D: C1 D0 I/ I6 H" N, o" p
EDMA3_TRIG_MODE_EVENT);% _( F; g3 ~0 u! p" n. Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 [' R/ {& M; c @1 R5 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ _& O+ N, _" Z5 c( p( z6 w$ g0 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, m2 j+ F! P4 P1 J, D! dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: j H4 s/ h1 {0 W2 e. k+ `: s3 m& u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! X; X% @' j; H, w$ Q0 n& OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" t- { M$ H- B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. g/ b2 u& D+ V9 w! Z8 D1 u) r
}
$ e/ e5 U* G# E* U2 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 [4 g" @3 G+ A, K- o/ j* Z$ E7 K. c
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