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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! o9 Q! E4 I# z* x
input mcasp_ahclkx,& e. G1 P" u& G P. B3 d
input mcasp_aclkx,
9 }6 `, Y* |. n) ~5 n! @+ ?input axr0,7 u$ n/ Q, U' L3 m# b
, n9 f8 Y: L$ \, w- X5 P, y1 youtput mcasp_afsr,
* D) m" G/ I* J* k" L) @2 P0 Boutput mcasp_ahclkr,( `/ y; X0 a& b7 t# h( B$ Z
output mcasp_aclkr,# A7 \1 M7 _# G. i
output axr1,7 J3 \) e; P+ x2 s% \
assign mcasp_afsr = mcasp_afsx;
\) O0 K5 z8 x5 l5 L6 M2 s6 gassign mcasp_aclkr = mcasp_aclkx;
5 a) B; g$ y& x% ~! z( ?/ Eassign mcasp_ahclkr = mcasp_ahclkx;/ ?/ V& o8 s( O0 V+ G; s
assign axr1 = axr0; % I/ M% M" `4 a6 r
& l8 k- K- {( Q( l: c0 w' R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 {: L7 y5 F# H2 Dstatic void McASPI2SConfigure(void)4 O5 m9 ^- O6 @& _2 J4 {
{
& c6 F# j2 n0 m5 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 P! e( Z3 i$ b* \: P% Z7 JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 Z+ T% n* {1 K1 c; _2 Y1 y4 \0 q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) h3 m0 N, e* S! M0 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* c# X6 `/ K: C$ P: x. w/ r$ v) xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 p+ r+ s! P/ B# Q3 w
MCASP_RX_MODE_DMA);
. ^. C% X/ e0 ^' y1 K% KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ c% p6 `2 f9 J* x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) T: Z5 f$ u% m$ U+ t$ o5 D l4 O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' e7 I" W$ D1 G8 ]$ u! {9 k4 D9 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
r0 [* @5 J7 I3 o8 BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 R. }8 ~7 o" ~2 VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 i R/ Z& ~% o5 B! @; IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& ~/ h: V; e. K( Z* PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - D# R2 D* N# l9 P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 M! @9 B4 G8 u7 e4 x9 X1 Y
0x00, 0xFF); /* configure the clock for transmitter */2 o# _( \# @0 c. K. y( u. O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. {7 ?, \( G# }& m! R% W4 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
l/ I6 J" b9 q" F+ _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) x2 q3 }0 j& V
0x00, 0xFF);
$ l& q+ l/ T9 u; [! y' m; E
7 G h0 f( A" }" \/* Enable synchronization of RX and TX sections */
6 D4 ?0 y8 S, Q( u8 A6 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ Y' e. ]) o a& h" h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* U% x+ X/ W# g# N7 b- TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- K9 ?- g. l7 U* {. Y
** Set the serializers, Currently only one serializer is set as4 a1 J) S4 C% j% {: P! ^
** transmitter and one serializer as receiver./ P$ C! o2 P J2 `! s
*/7 t+ W% ]7 V* X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 @& }+ E) A% p" c2 m4 ]' B8 f% R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; o- _4 B0 j; w2 g( m** Configure the McASP pins
, K' B3 A3 L0 ~ ~** Input - Frame Sync, Clock and Serializer Rx. ^0 W$ c" a( j) m, u9 e) W
** Output - Serializer Tx is connected to the input of the codec 3 T9 j. a3 R5 @4 d+ Q( b% q+ H
*/9 n0 G8 f% g2 Q- U- z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# j- o7 I/ K3 F% w$ dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 Z" z- `! B3 [1 H; {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX Q) w3 R+ p# M, f! \
| MCASP_PIN_ACLKX0 u% O+ S9 _) g6 G
| MCASP_PIN_AHCLKX
8 |1 o) ]. i1 c, m O( @; z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" W" O9 M% N9 d* D8 O6 B+ A D; Q$ yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # q* B( y4 u4 I2 ]* H' {3 A
| MCASP_TX_CLKFAIL
+ y/ {' g% q5 i| MCASP_TX_SYNCERROR
7 J% m" N) Q% r3 v. Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' B. j8 r4 E6 o/ N
| MCASP_RX_CLKFAIL3 v2 T2 c5 M% x' L8 u' {
| MCASP_RX_SYNCERROR 8 a" r3 ~. n7 S; }: l; @
| MCASP_RX_OVERRUN);" k2 O. w0 U4 I1 U. [, K
} static void I2SDataTxRxActivate(void): J4 [* g& { H$ f" G3 g6 L5 N- l
{
. d. [) B5 L& H9 z4 G4 i/* Start the clocks */. \5 \* Q. M4 X# @6 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 \5 Q) L! |- P2 E2 Y5 ]7 T) U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! r$ B* c0 I- Z* }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 ~: |: v! V* e% J2 lEDMA3_TRIG_MODE_EVENT);
1 T3 k7 Q/ ?. h3 }3 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 O1 n- a! L1 o0 }- D' u, }' E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, |2 u. l" F1 {5 fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 R# V- [2 e' p) IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 W5 A" ?: ?: i- j$ w7 z7 ~; D {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 j# o+ U' Q. \6 t# o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 z+ L+ e) Z. y: bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ I+ ?6 @3 g+ K+ a1 [9 M+ T. V. `}
" N- O* |9 J4 a; [% E# H' P1 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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