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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 r) R$ X; [; _- F6 r/ z J" Z
input mcasp_ahclkx,6 }+ @. c1 k9 X7 E7 W# V/ p
input mcasp_aclkx,) z- u" K' `7 A7 f% u$ p5 g( j
input axr0,( D, [' u* {9 l7 ?
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output mcasp_afsr,
; ]2 E" O0 \8 b3 _4 \; Z. boutput mcasp_ahclkr,2 O4 m! W$ P* ]) G! E ?7 n0 U' ~% w
output mcasp_aclkr,* ?9 @* q E6 M8 M" E3 F
output axr1,
8 b5 L( Z8 Z3 _$ L8 g, _ I assign mcasp_afsr = mcasp_afsx;% t4 [7 ]1 P9 _+ f
assign mcasp_aclkr = mcasp_aclkx;
( y0 _4 j( s5 C2 b$ Gassign mcasp_ahclkr = mcasp_ahclkx;; m0 L( V5 `8 H- T4 n5 M
assign axr1 = axr0; ) A( U- d* }2 T) p, M) X
; K% T9 x7 O) ~& k" p& h$ Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( [; s1 Q+ O, m, T0 Dstatic void McASPI2SConfigure(void)
2 S2 F+ i* T: c3 k, U0 b: `3 w{
C# h+ q! @7 d5 F% X3 O% lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 i. B$ V! V& Q7 {6 U6 M) S ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 r2 x# o; ^& E. W3 L/ Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 d, Y3 G `' CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 a2 L1 i. u5 c( Y1 N$ L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 b. D6 B5 D1 w" N/ G2 `MCASP_RX_MODE_DMA);9 ?2 t- g. l# K- R; K. O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- M) S: {* f# y1 V- f$ E" |7 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% t; U, _% i- f5 l6 K8 {. V5 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 y2 J% j1 u, W9 f. ^: iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 g$ c' l9 U- KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ s+ Z. |6 _9 T0 g/ }$ m" i. p, wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* L6 T; {/ V: A/ P# Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); e* W/ p3 a6 f0 T+ S6 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . V t( e. `) L4 R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, }0 ~( s: S: d( f. p- v0x00, 0xFF); /* configure the clock for transmitter */6 @, J j; h) ~& D5 o, g" X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 w; X( G0 P4 h- O9 b& tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 C3 I! q t8 b0 M1 i: FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ z1 I7 f5 q" N2 O! L- N3 r0 [0x00, 0xFF);$ F, \% I- E+ ]" {2 V& S" B
# v* Q; K6 n/ X" ~% J+ o/* Enable synchronization of RX and TX sections */
* E# Z q" f0 I3 z4 L, LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ s+ m2 Y" c9 h, ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: J% J. S* \! C9 \8 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 i" p8 W; t1 ?. Q+ I7 H. b
** Set the serializers, Currently only one serializer is set as
# y3 s' g* X/ D# }$ D! D; _** transmitter and one serializer as receiver.2 y( V, h1 j7 `* f5 ~! x
*/( l; f2 c0 V8 y# z0 U0 O* O! Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 x l* x' \3 o' W- A4 {1 X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! [9 A$ J/ f% g
** Configure the McASP pins 1 `' {4 C) _/ g' s4 S. m6 o/ x/ Z1 E7 g2 r
** Input - Frame Sync, Clock and Serializer Rx, f/ b5 {7 G4 p! f# S" _! M
** Output - Serializer Tx is connected to the input of the codec * H. M2 l# J3 E9 G( j
*/2 c2 ]5 ?# u6 K. V8 ~8 C) C4 Z5 X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ x+ {3 v; y; `! zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- r% |5 M, r3 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 a$ I% D6 ]+ m {
| MCASP_PIN_ACLKX/ y8 v2 |. m1 W2 G
| MCASP_PIN_AHCLKX
$ {; Y6 P* E* \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 M0 Y/ k: d R. D4 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # u" r+ K- C( N6 J0 C$ s
| MCASP_TX_CLKFAIL
7 f' ?5 {* i4 F" H| MCASP_TX_SYNCERROR
1 n+ V) w4 U1 u l M( b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& v- d, U: S- e6 K| MCASP_RX_CLKFAIL
2 s, t1 o" a3 [0 S2 Q# G* P| MCASP_RX_SYNCERROR * Z1 i) A, D0 b8 v6 p3 ?$ a# g
| MCASP_RX_OVERRUN);
8 ^/ R3 G" t, @9 j/ j} static void I2SDataTxRxActivate(void)* Q6 D Q. e7 T. c. o9 q
{- }& J4 {9 N, V, v; ~$ ~( [
/* Start the clocks */
8 V; l0 q/ c& j4 O3 C' X, B/ nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; e: Y7 @. p/ f9 `" S) c- g& d+ N( OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. G' r& s; k* G) M+ q% w1 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 Y; P5 t1 }! E5 {
EDMA3_TRIG_MODE_EVENT);
* M$ Z& E; z5 w4 N$ V8 f' }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 Z4 J9 ?' Y. ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# w( ]( D0 F+ x, ~ V- pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 [' `/ r) m4 o' F0 G* S/ ~4 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, z1 }9 j/ c, {% N$ a9 |, |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& E" b9 _7 e2 |2 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, v3 A8 T9 c6 u* c K) Z$ d9 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, s6 t7 e& F! P% N
} ; B2 s$ [) ? d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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