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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 t4 O* p+ l+ z1 C
input mcasp_ahclkx,
5 r5 B6 g- c* m* w8 B, e- i1 oinput mcasp_aclkx,7 j8 X3 }- C4 s7 B. \% W( U
input axr0,
$ s. e% o9 V) G" K+ x6 r8 O( V
) @. N8 I. b) i( z! Voutput mcasp_afsr,
+ C: N+ v, Q z5 x' { e0 qoutput mcasp_ahclkr,
8 ]; G% R9 u; y d5 Aoutput mcasp_aclkr,7 L+ E! h1 b8 Z6 Z7 {9 H
output axr1,
) |) [- F" }5 c7 m2 E; ] assign mcasp_afsr = mcasp_afsx;
+ K/ m r+ n5 f9 X9 Rassign mcasp_aclkr = mcasp_aclkx;
- G9 P9 X& W9 C) s, W2 Oassign mcasp_ahclkr = mcasp_ahclkx;2 a! Z' d7 B% g8 _; b5 j A
assign axr1 = axr0; % d2 O2 u' R+ [" u( y4 p
+ F8 ?4 [! ~) J9 u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 o4 I) V9 V3 S% _- q* }5 K3 G2 jstatic void McASPI2SConfigure(void)
/ K f6 S1 d. ?{7 Q! s; P1 o5 w2 c$ q+ H' p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
l# W/ w6 u. V! LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 `8 ]9 G+ h. L' M* |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& n9 z0 p6 X, F, D" IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 w0 @- F& J# i! i0 K% Z4 o; @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; X) ^3 G7 q- pMCASP_RX_MODE_DMA);5 g- |$ M5 m( V6 d. n" m! f) g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* d; K* d+ `# `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 c; L( m1 x, }5 q8 A5 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 ?1 y4 F" Q9 |. K( D, X7 y9 FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" V7 T- w3 N# o6 r: \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, P$ l5 G& ?8 O4 |5 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, D( }6 \9 l" A- o$ d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( `/ N$ Y$ [5 ]8 k) P+ M uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 W a u, z# T3 z+ qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! h% V6 K* {0 G2 [% E0x00, 0xFF); /* configure the clock for transmitter */
: M9 S( J% c6 p3 c! u/ B3 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, r5 b2 H+ L- E" D4 o Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 E$ W" P) `2 R. F6 t5 h9 {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, o# k4 g2 b8 M$ M
0x00, 0xFF);; ?4 E+ a0 }( f S
3 Y _( K) g: S9 ^
/* Enable synchronization of RX and TX sections */ 0 T- Y! G$ ]5 Z& m2 x. N6 {+ `! O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ K2 w$ p7 U6 d/ L6 U. `+ B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. G4 B& D" E, Z( B! Q. {* XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. t# g% L5 j8 |5 D# X# L) b** Set the serializers, Currently only one serializer is set as9 J- }. v) Y" q; h) j; y0 l+ G
** transmitter and one serializer as receiver.0 ~- o, T5 G; h/ t, ], O
*/
; M& d I) m6 N9 H$ M( {$ b# hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 v; b- `$ f& NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 G/ c! ]/ O5 A5 ~$ {; c b
** Configure the McASP pins
( T* D$ ~/ L7 C8 q& x6 p a** Input - Frame Sync, Clock and Serializer Rx
! w8 C% r8 ?4 H8 k4 w** Output - Serializer Tx is connected to the input of the codec & d1 E7 S0 Y; M4 }8 i
*/# B* e7 ~" O8 i4 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# U8 D' E, M4 d5 e0 r7 k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 H4 A) v2 C# c1 D% ]+ {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& v& N8 Z8 K+ w' U$ b3 W) e0 x
| MCASP_PIN_ACLKX& l4 L. M* D4 k6 [, G
| MCASP_PIN_AHCLKX/ c q3 S. W+ N2 m h L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 R8 r. G. d& H" g5 q: t1 \/ x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; F7 ~# l# k. e1 ?
| MCASP_TX_CLKFAIL
) r# G" ]9 P5 A. A| MCASP_TX_SYNCERROR" i/ e( a B, f, E7 S7 o, c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ m* m3 v, r1 b| MCASP_RX_CLKFAIL
3 `. o; r& z, t U N9 H; I| MCASP_RX_SYNCERROR
5 E# F ^* \+ R| MCASP_RX_OVERRUN);
( Y4 y1 ^9 _1 G: a0 \6 I; x! D% g} static void I2SDataTxRxActivate(void)& O7 F, g A ]& r ^2 u
{, _* n+ n0 i$ x) B4 Z
/* Start the clocks */
0 f; G2 R0 }8 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 a* j; k+ Q7 v# R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: X' b, O: [0 N8 i, _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' I% I" n1 a0 n7 _: @; dEDMA3_TRIG_MODE_EVENT);3 v. z$ l. X; N0 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 {; N5 A4 g ~0 i! U5 }; QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! l1 Y/ f: r1 Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 H6 O. ?7 h. @4 d8 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 x6 x) ^& k% u' L+ a; Q6 V5 o; E9 @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( w" N9 A$ F8 h+ ~* eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; u/ L u+ [8 I u+ R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 C, \7 A9 s/ \+ g R, B
}
( @! d# Z* K$ R% e# E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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