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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; n/ e X! \6 B; k
input mcasp_ahclkx,& b* c2 w4 @8 W+ F# `' M4 u
input mcasp_aclkx,
2 c7 D. W. x" i. ^1 @! {8 yinput axr0,
& [$ K1 p- e9 ?$ i& d) Q1 r( |
@+ |* s5 d1 o* c7 j! `output mcasp_afsr,6 L5 w; ?2 h$ i% P: F0 _
output mcasp_ahclkr,( O i c6 e7 Z
output mcasp_aclkr,! C. |8 E5 y& C7 ]1 L
output axr1,5 e# k9 }# E3 c+ `7 i
assign mcasp_afsr = mcasp_afsx;2 `) [; C0 }- Y. ~% y) b* p* q
assign mcasp_aclkr = mcasp_aclkx;/ U: c, j5 e) G
assign mcasp_ahclkr = mcasp_ahclkx;
0 A. d7 O$ ?7 c3 S- R) |. O* Kassign axr1 = axr0;
3 W# u5 j0 A5 D7 `1 u9 B' m6 T) H8 o! r8 L( o1 ~% c0 g3 m8 B Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% y H7 B; N" istatic void McASPI2SConfigure(void)
7 V+ F" ~2 q' ~* Q' |{
$ X2 v n3 r& x( F9 P1 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! B( c' ]4 w' \" N3 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 [8 f7 F" o, n6 R& J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 D# E" T5 G4 x, l7 o' @7 D. cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ b$ _& W. I/ R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% o' @' U* o V& l1 RMCASP_RX_MODE_DMA);6 T$ L8 U% i! t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# y1 Z$ I0 [1 ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 J7 G6 u3 X, f. b b# A( P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ W) w) G6 W+ w, X. t( z6 d) s2 s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, Q; H2 B% r( D* t# e6 D' F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 I, N- w" a+ {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! k+ O1 W) p- E; c; y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 L) p, @! t, A; O1 X) j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / |. \3 |0 o0 o9 E4 O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 h1 j6 |/ T/ @4 c
0x00, 0xFF); /* configure the clock for transmitter */
- o7 M7 `! `% x" P* f; aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
n! k8 a: y# e8 J9 fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. _7 ]9 t8 ]- U* a d2 c, jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ }3 C7 S- z; D0 ]% q5 |7 p
0x00, 0xFF);
; J c9 I2 t6 ~3 c% ~8 x+ T( p8 k2 A& v
/* Enable synchronization of RX and TX sections */ / G' Q: K5 L& ~# Y/ F8 C# n1 Q3 T) V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* [1 d2 ^! s: X# g) @/ b7 |. F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 o5 x0 Q9 b/ F. J% R3 P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# N6 Z- u8 h$ @ S) b# s2 ~** Set the serializers, Currently only one serializer is set as% z+ \' G5 m: T" v3 Q
** transmitter and one serializer as receiver./ C9 R! R/ T( o% B
*/
- L- h m b0 n% [$ ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); @0 w+ o1 L9 H, L B0 V" {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) \4 ?& E+ t" t4 O7 x7 s- F# Z& L** Configure the McASP pins
`0 R/ U8 U, E9 {2 [! o6 g! }** Input - Frame Sync, Clock and Serializer Rx
1 [, O7 ~) m1 q/ @" C. K$ q/ J/ l0 P0 B** Output - Serializer Tx is connected to the input of the codec
3 M4 X9 n" P7 ~# n( ~* ^*/, R" V& S- ?5 W9 `1 J( U, E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: z6 p0 i) b) wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! n9 o, y0 S6 z5 P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 }! J/ e" ^5 l4 c9 A| MCASP_PIN_ACLKX. L2 f. [, [9 C' u/ ~5 P
| MCASP_PIN_AHCLKX' \( ?& P M* {* W' J" l% D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; H8 n% ~% ~. G0 s" k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 B8 q, V( b+ E- J0 h1 L
| MCASP_TX_CLKFAIL
. E9 Z/ x7 j& Y7 i" {| MCASP_TX_SYNCERROR
) V6 x3 n- \6 O4 b* ]3 z# O# z$ `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 O1 K1 u% s' W9 {* J6 J' n( a| MCASP_RX_CLKFAIL% I4 Z3 }8 u) K9 D/ ^0 o T2 J
| MCASP_RX_SYNCERROR
+ K) v" u& X+ X* j! B! Y| MCASP_RX_OVERRUN);
+ u0 G B* e9 p, X0 V3 q1 d8 i! e} static void I2SDataTxRxActivate(void)$ H' L) \) G" }8 F' l: [; u* M
{
8 c$ b& X6 g$ h1 l2 A9 {/* Start the clocks */; O6 _6 m( X. s6 h4 ]& F, p, ~ V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" z N+ {$ Z( L- m8 G$ ~1 F! J9 eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; E/ C0 t6 M* E& x# O& K+ XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! c |9 T/ `! {! m# i
EDMA3_TRIG_MODE_EVENT);
+ t* E ]. a+ D) K$ aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' ?! i: p. P' D }! HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 N3 N" [) ?1 t9 |6 J g' D- zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ O2 ?& X- E9 k, f. W2 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 F3 o+ A6 I% U5 M t6 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 X7 U D' Q, x1 Y$ c8 E; s! YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* m- Z$ d; X3 T7 |( p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 V2 Y% n( a; P) b6 w& H
}
4 F+ n" _: c7 i8 y5 R, H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + O8 M- f' U& w
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