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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! c- o7 h$ W w4 Z9 \3 sinput mcasp_ahclkx,
! B& Q& x3 @$ Vinput mcasp_aclkx,+ ^+ F, b2 `4 [( C) n: ~$ K- V0 c
input axr0,, s+ o% \3 j5 y$ n
+ A2 g& a& U P1 youtput mcasp_afsr,/ K ^* g" s4 L+ O
output mcasp_ahclkr,
' L5 x5 _. L `( d* q2 i; c% Ooutput mcasp_aclkr,+ @3 o6 \- h& F" s, _) e. r$ V
output axr1,5 ?. p h F% _/ |+ @4 n
assign mcasp_afsr = mcasp_afsx;" d9 n' L, v- z6 I- x. |/ S
assign mcasp_aclkr = mcasp_aclkx;
0 Q, \) ^* h' z, |assign mcasp_ahclkr = mcasp_ahclkx;/ [( T# `, d7 I% n L7 Z
assign axr1 = axr0;
' @8 m( u( ^5 H5 t' G6 ^0 \
4 T1 m1 T" A8 u$ H! J; A& A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# A# P$ W. h5 ]static void McASPI2SConfigure(void). h1 x& @8 r5 s; a& w1 j/ d* Q/ o
{
& m( a0 q% V5 f- A# b! ^: s; ?- wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) r$ R: ?, u& T; o( x6 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 P1 e" _8 N' h8 M0 v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& L$ H9 W+ H1 Z% o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ g9 e8 V5 W! G p' c* w/ iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) i- @, W) N" a& C5 C" MMCASP_RX_MODE_DMA);
6 e& c/ T, D! {' H0 t5 g9 o% nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ v% k7 K6 ^" f+ DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- e# M% D* _" } W1 A" @( c1 o JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# w- `) ~2 W" ]) k% NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# A0 D) {4 a: c _+ l4 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- Y* X4 M6 F4 n1 Q: F, g5 rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 G7 x! r9 K7 Q% N' T* m9 C( T* a ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 I' Y+ w1 R% d; L, z- U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 G( k# |8 R! w9 W+ G0 r% w" C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 y; Y' Z7 A8 o) y7 S2 e6 q
0x00, 0xFF); /* configure the clock for transmitter */
, m# h" H) ]% zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 e. z7 h* v( E6 J$ g7 |& S- hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 m- l2 V {" K+ H/ V( UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! B& [( K0 t: y+ Y. A* b0x00, 0xFF);
2 v2 n( r6 {7 y1 R, _
; o7 z) h: `: ~/* Enable synchronization of RX and TX sections */ & O. i& g0 t2 ^+ N& J) L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// ^. r3 R" q% s% X) e) e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 n0 _* w, z' A" D$ a3 N( Z3 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) Q% Z9 z( l: ^
** Set the serializers, Currently only one serializer is set as x7 H; I4 \6 X) ~; n: I. G. \, k
** transmitter and one serializer as receiver.
8 X+ c3 B! R1 r- Z- A*/
) k* O% M/ o5 d3 ]. |' cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ E" O$ L% `% h9 T/ }, o: J& P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ j/ F/ ]# {* L# o# H% Z K1 Y+ a** Configure the McASP pins $ z! i9 m$ y0 f- {: ?
** Input - Frame Sync, Clock and Serializer Rx4 ~: }* X! k3 @8 T
** Output - Serializer Tx is connected to the input of the codec
. m7 a' A0 w( j \4 O*/; O" Q i) ]* f; }& z1 e( v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" [3 b4 J& f; gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) _! z0 f! @+ t! v( oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' l: z3 ~3 C( E2 J j
| MCASP_PIN_ACLKX2 H0 K" |+ }$ Q2 A c) k0 \
| MCASP_PIN_AHCLKX
+ L6 H; G0 D. K: \5 o. g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// l$ ~% e( Z' H& m6 m h1 N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 I$ q! k) \+ x; G5 M8 u
| MCASP_TX_CLKFAIL " O/ W6 b/ E& {; `+ a# B& f5 F* l
| MCASP_TX_SYNCERROR
2 s2 @1 z4 e- y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) o6 X: K! C5 Y: L
| MCASP_RX_CLKFAIL
' w6 G" L- F. r| MCASP_RX_SYNCERROR
1 O& ~; a$ j0 }2 g* c| MCASP_RX_OVERRUN);+ ?6 ~, _2 m% U4 Z% I. i2 s
} static void I2SDataTxRxActivate(void)1 X2 U: ~, P! W9 V7 Z( Z7 v f
{, L0 R! `- q: N' o7 N! `
/* Start the clocks */& q, a9 i! B' J$ b. R) x1 o/ k7 O \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( n2 X2 o: V/ [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 _$ z/ z) d( [; Y7 g# \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! G6 ^# \; y5 n/ v- E# q7 }EDMA3_TRIG_MODE_EVENT); q& i" F" p# K7 ?+ I1 ]* h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 E( C5 c( g$ X8 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. a5 t6 `% j! D+ \. t6 G2 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! K8 E, z4 ], J1 c% J1 o% \5 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! q* A$ f5 w; c6 A- w ]3 |2 zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 F. \9 D) R' O/ t( G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* F; ?5 m( l* Q; v8 F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 ?5 {$ o9 s/ Q1 s: t) @0 O}
" C, w% [( i! B/ H# z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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