|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 n# k" B( r& vinput mcasp_ahclkx,
) |" l6 m3 n& k( X6 w6 v4 binput mcasp_aclkx,
+ w1 ~ F% t; x. Q( D, jinput axr0,4 ?9 K- V9 S- r
q, f# P1 S: b1 R6 aoutput mcasp_afsr,; H; X% N( i' t4 d5 X, S8 q3 B
output mcasp_ahclkr,; E, Q1 p: N, c- e- Q9 `
output mcasp_aclkr,
6 E9 X0 @3 u; W0 e8 y# \output axr1,/ Q; e+ Q5 y4 c7 p7 K+ {- a' b
assign mcasp_afsr = mcasp_afsx;5 \: `" D( w3 s, W, C( R; C8 {
assign mcasp_aclkr = mcasp_aclkx;
* N6 @# [/ u4 k$ p! D: Dassign mcasp_ahclkr = mcasp_ahclkx;* B$ t+ E3 Q( k0 L' s# B% b
assign axr1 = axr0;
; T0 y3 R/ l1 i$ b4 @: g/ x7 ?* b% X/ Y) r9 H, T" R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( c6 w2 H" g2 F/ r Kstatic void McASPI2SConfigure(void)
% |9 B5 K6 [, C{
! x! A! Y$ S) @% J4 s; V& TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 _. u* B! E7 l5 j0 k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 ]: ]% ?* U2 a" f' M$ l# ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( x$ e" K4 {' o! Q0 P; K, C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 E2 d$ G0 }' ~* M0 ]- Q3 ?/ _( L5 OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 s+ N+ ], K* R7 V- ^1 L3 a
MCASP_RX_MODE_DMA);8 ^& _$ f" s* f* z: }+ W2 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# Q+ f/ `: d3 Y# ~8 Z: E5 u8 y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* Z- J- K3 E0 `5 n0 v' O- F6 B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 ]& Q) L. g$ M2 x% T3 k+ jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ E1 @2 o C! }* ~2 N8 y: |8 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! A1 `$ P# B. eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' _. v5 c4 n4 b- M7 V! E j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 K5 @+ [# i/ S9 p% fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % b! G; Y% b% d3 t9 J9 i2 i0 M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, m& U1 D2 {8 O- X' B) x- B
0x00, 0xFF); /* configure the clock for transmitter */, E/ L$ }/ C1 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( r9 q' M! ^* |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 B0 W$ J; x# e/ yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& F n# c& u* v% F. U1 O& P
0x00, 0xFF);. C7 w! @3 |8 Y$ q7 F
# M$ s& a' t+ y+ u+ y/* Enable synchronization of RX and TX sections */
7 U; e; E0 s6 ]' R' p1 VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" j) |& }3 c/ s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* P+ A" C9 L7 b: N/ G. t3 A. [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 T) ~; B/ m) i** Set the serializers, Currently only one serializer is set as7 [) B* ^* d2 D' v% }5 |
** transmitter and one serializer as receiver.
! {; T$ v+ W2 D% T3 X- D" y*/$ N# \( q9 |, r/ }6 [/ I; x( t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ u. i7 F, I6 D1 \4 \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* s0 `+ b6 N- v @$ p& F& K1 t# O** Configure the McASP pins
) `$ x+ r+ M3 @+ K8 y% ?** Input - Frame Sync, Clock and Serializer Rx7 ~/ S/ ]. S) @' Z9 ^' P( K3 S
** Output - Serializer Tx is connected to the input of the codec + n1 i+ H* @2 y4 W* j
*/
8 N& q! e, S; MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; C; S5 t7 i8 x; m( u) \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* O9 V$ i3 k l* M# O6 m+ x$ Y4 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) q% @' n6 _5 Z, K* T% l7 V| MCASP_PIN_ACLKX
1 {& J; ?1 o8 k4 ?: F, [| MCASP_PIN_AHCLKX
$ q6 Y6 s2 A' m7 j* D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* V+ d8 Y0 `2 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ T, ?+ }% Y) L/ w$ y) O| MCASP_TX_CLKFAIL ( [& m. N; l/ F* `1 T2 Z
| MCASP_TX_SYNCERROR! ^( X! w0 L+ ^! g5 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 U8 N# E* I6 _, }: H# s0 x' j
| MCASP_RX_CLKFAIL
) P. v9 l2 d: y8 F/ F| MCASP_RX_SYNCERROR 5 O. X) n" z3 F9 t4 _+ L+ `
| MCASP_RX_OVERRUN);
4 u0 E4 c w" @6 q0 K9 c} static void I2SDataTxRxActivate(void)# B7 S" a" u1 E) k
{
0 D' f, P0 c7 V. [/* Start the clocks */
. j2 N2 j8 f% Y8 b1 M! IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) V- V! q( ^" J4 K& {: ]& `+ X8 l/ f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 K, [% { H% qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) \6 l- T& s, s9 P* e9 V, @EDMA3_TRIG_MODE_EVENT);
( {% H: i; a4 ~8 R3 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' ?# {4 Z: `8 ^- S9 P: R3 D- Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ R# ^, {' t9 m! D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ T8 P5 t+ r) o, O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 ~& s/ Q6 k! j. E2 @% a. W& P( h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; d6 B/ m) \& k9 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- v M( H d8 \* X9 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS); v1 R g3 d! Q8 r( p4 N
}
7 ~5 [; I9 @( A% ~ T) W1 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " n4 \" Y! D" E, v8 a' r+ c' X
|