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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 p! f2 [, h) g8 M7 jinput mcasp_ahclkx,9 s: D. O9 ]0 z0 K* Z/ u
input mcasp_aclkx,9 Z# ? ]" H5 k+ X. S, u
input axr0,+ J+ ^: K( d! A# y7 \8 l- p, c
1 h( S' r+ r- D3 z6 L( F4 Koutput mcasp_afsr,! [% n, N" b0 I# O' @
output mcasp_ahclkr,2 h2 C O0 w3 L! U
output mcasp_aclkr,
/ n# X: r( K l7 t3 Doutput axr1,
. d4 K! q! l- \( X Q assign mcasp_afsr = mcasp_afsx;# s( M$ x2 L8 q7 Y. N3 w
assign mcasp_aclkr = mcasp_aclkx;
- k$ u. U. L! G5 @assign mcasp_ahclkr = mcasp_ahclkx; v$ G/ ~2 I% w, B1 t3 \
assign axr1 = axr0;
" ]1 C- o9 ~. `& z& h- k7 i( ]4 w6 W, j" }- S% y0 M, A9 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . m' ^- j$ @+ r3 ?$ A! e; @
static void McASPI2SConfigure(void)& u3 F" N8 \, X: r( T: B& N4 R5 V
{: A. ^6 M7 o% S3 c# P5 s' q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! p4 Z+ {, h3 L$ }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 t, l) G, `. H& B+ J: S& Y8 bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ o! A- D) V$ {, Z9 ?" ?7 E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 F6 |4 f; m' uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. X; f, y/ S% B& f$ M/ C
MCASP_RX_MODE_DMA); S( C' M6 u1 a" r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: |0 [9 w; m# j% N( H N- KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, E- \% R! I5 s9 {; {5 dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % |. W7 V; h: l2 D" u, p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* u7 K- g* U- N! y8 E! y5 ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) \: h2 G6 A1 j$ ?* WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! j4 Y7 i0 _/ {) j9 d& ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& i& a) t) q7 \4 F" E! |, C0 R" U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , E( T: C4 W) u/ v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 U( I3 i# ? F$ R& k. M
0x00, 0xFF); /* configure the clock for transmitter */' X$ d: E3 R2 S7 @2 ?1 C' \6 V5 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. _# `& c% x" _7 mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 } c% P" P8 OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: R" n! |9 A I
0x00, 0xFF);7 [9 t( r9 i, D4 c) G9 g& [; w
; z. l1 X- i3 i3 o: Z/ b5 r
/* Enable synchronization of RX and TX sections */
# t: A: O. o8 r- W4 s+ M) p& bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" F5 r2 x9 [- Q# t: h7 C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) X Y* G$ e1 u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 R# \) m# e6 O9 U** Set the serializers, Currently only one serializer is set as
' \5 ]# j9 p+ k6 m** transmitter and one serializer as receiver.# p$ R; V* z) b0 b1 m
*/
* s+ o$ U9 w0 ^# d' f2 ^/ y% |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* a+ }' }# e7 lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. D1 J3 }& w8 s0 Y; m9 d) s6 N
** Configure the McASP pins / H; g& B$ j7 ^
** Input - Frame Sync, Clock and Serializer Rx4 p/ F* t6 x$ I) [) @1 Y$ h
** Output - Serializer Tx is connected to the input of the codec , A6 i% {" U/ M" X, P
*/0 | X6 m. b; X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 k: Z5 g, c1 U( [7 H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 E- j, r4 C+ f$ |. s, pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; M3 N: F- C8 E, l, h" d
| MCASP_PIN_ACLKX
9 [, `6 r6 D1 A+ A. I3 b| MCASP_PIN_AHCLKX
7 D: Y$ R' p/ j7 v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" E/ T/ ]& S6 j1 H5 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , P$ `; {% x. H0 [1 e9 c
| MCASP_TX_CLKFAIL
# n1 l1 X# ?0 V" \/ O* L. u| MCASP_TX_SYNCERROR
& Z2 I8 z" \1 w1 S! e! u* l$ @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 e3 T3 s* p/ z1 f! H9 d6 _1 z7 s
| MCASP_RX_CLKFAIL/ N3 o+ o7 c: r; N" p" j: U
| MCASP_RX_SYNCERROR
4 ]/ _0 ~7 h" l" `5 \5 {5 C) c4 y. R| MCASP_RX_OVERRUN);7 g |: o: l( c5 q6 b! C
} static void I2SDataTxRxActivate(void)7 F# s- n& ~; q5 g' g7 W* S
{
) H* L' r& z+ f/ V) P' s! J! q/* Start the clocks */# q/ e' Q8 Y4 f* y$ g T4 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. E z S, B2 M. V1 Y" {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ N8 d1 P, i2 ^ rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ g& e3 `8 @7 GEDMA3_TRIG_MODE_EVENT);
. ]: w# o1 D; O+ eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, G2 Q/ ~0 W# {# h5 K. f6 C6 j% ^$ `- Z! qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 D$ Y; ?* \- ^% QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# i' _8 X" j7 ]" D" S" h, MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( A& d( x- `$ ^/ P. e+ _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; ?; X9 p2 _- fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ l2 ~; g0 }! v1 N6 n! M4 o8 [% SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ t: [. q+ B, E0 \1 Z9 U} - Z! B: ^+ _& {' Y! O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : A* c/ G2 f4 c( W4 n; `( L
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