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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, C+ J# P4 l! j' ]4 r% V! F
input mcasp_ahclkx,/ @0 u9 k! K' ^3 x
input mcasp_aclkx,
6 x1 u8 O- f0 b% z' c7 f4 Winput axr0,
6 Z" t/ M7 R5 O- H6 G+ C& d9 t1 m/ D+ g7 G
output mcasp_afsr,
f$ H1 l, P3 K# I3 N$ Ooutput mcasp_ahclkr,4 d2 X" H+ x6 d' k; o/ l$ x
output mcasp_aclkr,
+ L/ _5 H& H, e2 ?' S6 s! A7 ?& H$ |output axr1,' w, J4 f4 s) ~; v3 h2 s# p' i- O. f
assign mcasp_afsr = mcasp_afsx;
2 G2 r" Y% w( z- X# r) O. x3 z$ Uassign mcasp_aclkr = mcasp_aclkx;9 O1 Y1 {- d3 L2 q
assign mcasp_ahclkr = mcasp_ahclkx;$ A: \6 ?5 l! P4 P6 D
assign axr1 = axr0; : M; h8 @# l; ~, F3 |% R$ P6 i
$ g$ P% i" X! l, m4 x+ a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 ?/ W& \2 p7 S9 U; h: Rstatic void McASPI2SConfigure(void)$ O5 w4 L* V) v! Z6 N
{% J$ w( m* T, R+ t( f4 m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: c3 {( u1 I: O2 t0 x, ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ o' H2 i9 Z" [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, u% ^2 |; @3 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 @. P; j+ F" a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* d4 I! g7 o+ e$ V# [; [! l$ HMCASP_RX_MODE_DMA);
% f+ I, |% ?0 [- F+ Q3 L1 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) B2 F4 f7 ~1 X$ F" e/ n/ G; P' yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; \0 O# T% b# p8 t( c+ X- SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, [9 p9 F5 k! \/ |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 G ?# i: J/ X- G D% Y- n, R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 t. P. o/ H3 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 M% S8 }6 N8 b* z7 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( A0 p$ h+ f7 v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. }" Y+ F6 s G* S+ n+ RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) o& @) T6 Z. C: C3 _. Q0x00, 0xFF); /* configure the clock for transmitter */
3 C4 I9 G' D, E+ I* qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: L- ~9 @* k* }( K" s8 ^/ A8 Y+ M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & `7 n0 F2 w0 M% f( |' M* C9 t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- u8 G& u+ D5 ^% |3 B& d0x00, 0xFF);% T4 r6 E1 y& Q( e$ `
& u( n% P# Y$ f a; M8 L* x; Y/ L/* Enable synchronization of RX and TX sections */
& D" V: X& c, Y( zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 y1 T) G+ O; M3 D) t. g5 _& AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. D7 L: i0 }# {" T w5 R8 Q9 {- v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% a+ P, I$ I9 d* Z, A$ \5 e- P/ @** Set the serializers, Currently only one serializer is set as+ K$ W7 r% \3 n+ u4 V: o6 u
** transmitter and one serializer as receiver.
. s* E) a! @2 @7 L# [+ S/ Y3 O*/3 X$ a& p4 Y9 Y6 E7 X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ K2 K& @+ m+ \5 J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ c. G. C- ?9 ]; |8 I% ?$ _: Y
** Configure the McASP pins / p% f2 j0 ^4 q! _% N/ Y1 H9 Y
** Input - Frame Sync, Clock and Serializer Rx7 ~& |; k; U1 [% }
** Output - Serializer Tx is connected to the input of the codec 4 I; \! e) e5 k* a, z/ g7 e
*/
5 ~3 J' g; }+ K5 x, v& B, a8 FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 a A$ Z" ]4 z7 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# U! M9 m; ~4 s6 a o9 j2 vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 f# ^% H8 ?) Y! g+ q
| MCASP_PIN_ACLKX
3 \7 W" d o3 Y+ g' O( }| MCASP_PIN_AHCLKX
. e: o: F$ `. X2 H/ Q1 @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! C5 L$ O' e+ r+ r! \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # W$ H1 `9 c9 m3 F1 A6 f
| MCASP_TX_CLKFAIL $ A- Y4 u# O2 n5 {9 K
| MCASP_TX_SYNCERROR( s0 t: z6 P' ~. R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" ]/ x; W4 K2 S| MCASP_RX_CLKFAIL
! _, D+ V9 j2 t0 W: ^7 d% @3 X! ~| MCASP_RX_SYNCERROR
# T& {4 l1 Q: h. w4 e| MCASP_RX_OVERRUN);; ~: b9 u9 v9 N+ A$ [; k! u
} static void I2SDataTxRxActivate(void)
" F7 T# u6 a) Y' _1 E{
7 }% N$ b i7 p1 O8 t( `/* Start the clocks */7 C' D' X6 `. k+ ^8 x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: W+ m) [: z8 B; N/ ]3 mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 s* M5 a4 s+ vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. z& z( q! q& l3 c& X
EDMA3_TRIG_MODE_EVENT);
. H- \& [5 s9 y8 Q) p; I. a+ j' wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 ?$ f0 T6 W7 k& u7 w& B% u& m: wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: H* W# ]& b s& {' M5 v$ gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! ~+ ` C; S" o1 E- `3 |3 I/ JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" I7 u4 Z& T" f" C- b5 C, N" W0 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. U# M2 r! f' QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" o5 L/ \, F2 E1 W% I4 M$ m" c+ IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; i2 z7 f/ z6 s+ G" L( }1 ~8 P
} + n. p+ J* V$ S4 S/ ?" H5 ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " ]# Y$ G3 i' g+ g J, l
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