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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ {0 n. R* _1 E' S$ Y
input mcasp_ahclkx,
) Y9 u6 S8 Y- H1 }" minput mcasp_aclkx,
6 ~, I9 q$ N9 r, Binput axr0,! k4 C4 W+ H2 p; T
9 _: N' i; ~) Ioutput mcasp_afsr,8 f3 c1 ^$ w! |9 a# i# |/ }8 t9 S
output mcasp_ahclkr,- {9 R! C6 R2 d ]5 S. s" J
output mcasp_aclkr,1 _0 G/ b+ p: M2 g0 R* v
output axr1,
3 B O& g; ` Y; r s0 ^- R assign mcasp_afsr = mcasp_afsx;2 D! w: q. t5 z, ~# [* e+ K
assign mcasp_aclkr = mcasp_aclkx;8 F8 k5 z* B4 \. t$ |
assign mcasp_ahclkr = mcasp_ahclkx;
' n% A1 ^% B9 ~/ \. L2 Y `assign axr1 = axr0;
& `: `; m( h& |5 D" u8 t9 t1 B1 ` s2 ~2 b$ p5 v% }# Q: c* }1 f! C$ l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 B& `; C9 G4 N. V; Hstatic void McASPI2SConfigure(void)8 i1 s$ x- ]6 A
{
* o) i" [" `# \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( W* w+ e- K q: FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// J# H$ }7 O% T6 V6 c- ~7 F# e% O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 f& T; ^3 ?) D: X; V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" q9 p/ a3 e) O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 p0 `- A( O" \9 X# h: iMCASP_RX_MODE_DMA);
; i% F# ]/ A) E2 j* H+ i1 z7 GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, S# Y6 Y# N, n6 x6 s- g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 F0 z' n6 v) I0 Y7 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % D: m- }* j* y) N& p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, L* h6 G* s1 V+ M# z0 X2 q* t# ^ VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 W! e: x+ M5 E9 AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* b* T9 `" s1 `9 n+ z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 ^6 X% R" E+ ]8 Q; S! q, {% D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! s+ l: Q( e" A1 s) v% M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 Y) A( v) T1 a5 m& i6 x& ^
0x00, 0xFF); /* configure the clock for transmitter */' M; G% e% U9 O& e- w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" i+ x0 b, p" P0 E2 P+ N) bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . o" @' r5 _7 A* k5 b& u* F" C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ t4 _) I2 _6 g0x00, 0xFF);) n8 q5 u, l( ]1 _( s) M0 _
7 S+ C q0 B4 }. R/* Enable synchronization of RX and TX sections */
1 j3 n5 C1 \" E; P0 v5 M! JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& `* C" K. P, K4 A6 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ U4 O9 x. Q3 T, q" c qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) i) |% ^$ x% `5 N- k0 z
** Set the serializers, Currently only one serializer is set as) B# h( K2 f, o1 g4 E$ q# L
** transmitter and one serializer as receiver.3 K5 p; Z* \% o: D+ g2 D/ R+ C
*/
4 j& A# ?3 R4 b# a0 [$ v4 ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, ` S1 `3 t, j3 h- D3 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ K5 C1 J7 Z1 }. Z- o** Configure the McASP pins P/ n3 | X4 P T2 I7 A& i: [) b
** Input - Frame Sync, Clock and Serializer Rx
! N8 R1 ^- i2 \& Y- q** Output - Serializer Tx is connected to the input of the codec
9 V4 ]# r5 a1 i) m% }. G# H) A/ M*/
6 n7 _' N: ?" z7 L. j$ zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 L$ b: f5 l5 U) a( _* ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( P g! n$ e2 ?8 \% G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' B+ J7 m: T6 j! |) e| MCASP_PIN_ACLKX, |* X) T% {" G8 m: l) g8 s
| MCASP_PIN_AHCLKX) b8 c* f! n& z, Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( ]0 S9 \ I A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 C: k( G* x7 Z/ H. d6 y) Y| MCASP_TX_CLKFAIL / o% l% u+ _. ]0 G6 \# X
| MCASP_TX_SYNCERROR t& ^" k( g5 e1 q6 H# e3 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( N" N0 \4 C# p
| MCASP_RX_CLKFAIL6 n/ X5 h0 ?0 l; W7 K/ M
| MCASP_RX_SYNCERROR
" N' N0 C. Q6 P& `: I6 Q$ U| MCASP_RX_OVERRUN);7 C1 J. r: k, S1 e4 k& b1 ]
} static void I2SDataTxRxActivate(void)
- M( ~6 W! B# N, Z{) O$ x8 H, _4 \1 z9 }+ D1 Q
/* Start the clocks */. n3 B1 ~( I: P& E3 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" U9 B( i( d4 ]0 ?6 G- g# v) HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ n% W: |8 t, d) S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 d* y$ T2 V1 E' |' Y' F( w1 l( v
EDMA3_TRIG_MODE_EVENT);& Q, g1 ]2 t8 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, |4 f% e( X q8 d# e/ kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// j, G, M: a5 ~8 h, V5 y, r) V: M0 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! o. q5 q+ y' W( A# g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; `3 x( N$ R- R9 ^2 b7 `# @' X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' Q* Y: C) ?( D h$ [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% p. N+ ?! ]) f' w( |( A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: u/ }% Q! B1 {
}
9 O1 N3 O+ N7 I3 N/ |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
5 ~& z' X+ N! `- j* i T |