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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 i" S2 d! @7 z1 V0 F
input mcasp_ahclkx,
+ h8 y1 Z% G: _& r5 S* Y& O4 Binput mcasp_aclkx,2 j( ?0 f: ^9 w( [9 O; g
input axr0,
; @# d3 ?& V. o+ R$ y
|5 L5 s( {, q! noutput mcasp_afsr,9 C j5 |0 A1 ?' }) [% [
output mcasp_ahclkr," _1 f! O, o. G9 b* Z" ^
output mcasp_aclkr,
+ A j9 O- J' woutput axr1,
. u& i8 B9 B9 t4 B) Z8 _6 { assign mcasp_afsr = mcasp_afsx;- N5 J$ R9 C0 ~: W; W7 Y
assign mcasp_aclkr = mcasp_aclkx;
$ b/ H/ l* m0 Z6 m9 M8 \( u Rassign mcasp_ahclkr = mcasp_ahclkx;8 C% N0 J* @7 @; H3 I: ]
assign axr1 = axr0;
4 L! l5 L1 ~' {6 G2 A+ {: n( m; c {4 m; S3 L! ^4 ^5 @* d- [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * ~; i2 c9 H+ n0 Q5 s* `, R
static void McASPI2SConfigure(void)7 r& d! E/ L! Z2 O" G- _
{
6 Y( @- z {( [, e8 T! DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; {1 j7 i5 ?9 ~( z( }* l- \! lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) m7 K6 i( k# e" L5 R6 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' ?& l3 W& S' EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; a: ^# K+ e& Z4 N, B! i1 u% H0 w% S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* t" q& M, g# y) lMCASP_RX_MODE_DMA);
, G* Y0 J2 n$ n/ oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 U2 A& q5 C+ u+ M, ^$ L# b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. S$ x7 i$ B* `$ O) [! bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % s( J0 n$ N/ L5 x+ \7 e; q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 d& A+ Y4 R8 M& LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( X' A7 ?, I- l& E: w+ aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 i$ m7 ]: |4 r3 z+ jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 \1 z/ A" [ F: y+ L; ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 {- ]# E( u7 W$ Y3 d6 U7 p( {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! u/ C D" G9 ]- q! B5 i3 Z4 K0x00, 0xFF); /* configure the clock for transmitter */
9 v' V, N' \: }1 o! ? CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 M" U7 X+ o" _- N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! C* H4 `7 |0 D. x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 C7 H5 z) T& x7 W: F" R0x00, 0xFF);1 B3 Z j6 Y) X6 l+ q
) ?8 _9 r6 u' l9 h* u- {/* Enable synchronization of RX and TX sections */
9 {, \) f! U* c* x' jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# P( T% V: B! c0 z$ l9 f1 UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ a4 b+ s" ~& c2 E5 @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 j6 |3 U" z5 j: \# V** Set the serializers, Currently only one serializer is set as
7 J! b! t+ A% u x** transmitter and one serializer as receiver.
4 j7 g+ P$ l, [*/
6 R9 D1 L+ b5 K# j8 ` ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' W4 S n: T% Y: h# ^, oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 a6 O/ N( h& Y q7 R; k** Configure the McASP pins
# |9 \. z1 b) U$ s0 B** Input - Frame Sync, Clock and Serializer Rx( G/ @# i2 U0 Z+ j( i7 q
** Output - Serializer Tx is connected to the input of the codec
1 X& }/ Z/ c1 f& u*/
% `! i k# d! a) j: eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
^, a6 K: F2 c f1 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 e, O/ T% H/ g1 e7 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 ?" F/ Z, K& ~$ t- G| MCASP_PIN_ACLKX3 y K/ x# {4 j+ l5 v7 d5 K
| MCASP_PIN_AHCLKX
* h' }/ }& {5 {# X5 K9 \ A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 M. F$ D# o& i; kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. l. r L6 K3 w$ L$ ^| MCASP_TX_CLKFAIL , n2 v0 T# N9 _* u2 b
| MCASP_TX_SYNCERROR7 m! `" \4 O) f8 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" h( z* S/ `. w| MCASP_RX_CLKFAIL! {: G$ ]' H3 I. @9 c; @, O
| MCASP_RX_SYNCERROR % ? C4 }" Y7 m8 k% [& E
| MCASP_RX_OVERRUN);
4 @. |8 s! ?4 m; T7 t' Q} static void I2SDataTxRxActivate(void)
/ n' t8 V9 V2 P; p2 r8 V0 B{
4 F" X- b; u0 m; o/* Start the clocks */$ Z4 L# {6 j l4 D/ z$ U7 w e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 h( Z. B e. r1 T2 |+ A1 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ d& _+ E! z. w1 d5 A, v3 [ C$ d' `+ `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 ^ g* Q4 C U3 H2 vEDMA3_TRIG_MODE_EVENT);9 s5 [- z/ S* l! S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 m" i; J# D. y9 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 D3 A5 [6 g! w w1 m# P" s" Z* \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ N0 I' g9 C! A0 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ a2 c6 P- v. D1 M4 t/ U! z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; \7 a0 n+ B$ ~! Y- L& `& R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 m6 P; A/ {9 lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 @& y+ q$ \& _) _/ a}
7 X3 S5 i% L% ]' `* H" }' K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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