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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 z. t6 T) O. T9 t8 @. N$ x: X
input mcasp_ahclkx,# }9 ?, t; N1 ?# N
input mcasp_aclkx,
' Y" B; c! t! ?7 K/ ^input axr0,
/ {0 a" {' V2 ^ N! V6 _6 [# X, o* k9 o
output mcasp_afsr,# H7 |. ]9 O8 @7 m+ g
output mcasp_ahclkr,
! h7 v: p$ ~5 j9 J7 h c% Routput mcasp_aclkr,5 |0 s$ o" W! m/ G* F* G
output axr1,: e! K" B% `7 n5 o( {* s( J5 S) n
assign mcasp_afsr = mcasp_afsx;! u. O) b& x W6 E
assign mcasp_aclkr = mcasp_aclkx;" B6 F4 l: o3 H. A
assign mcasp_ahclkr = mcasp_ahclkx; e; e0 P: k/ U" \4 `( k+ y' l
assign axr1 = axr0; ( w! e N" O) D2 i5 H
7 }$ Y6 b# G7 I) ?5 o: a0 \" Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 D& R0 N4 f+ `3 Xstatic void McASPI2SConfigure(void)% B, |( U1 z- z* c3 Z; d
{
9 R; l1 T* q ` _6 c: YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 }) }1 T3 |5 I! |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; k. e$ t" R, Q+ D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ a2 O% P7 y- k" h( q5 t: x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 S# f0 I( a! _0 \$ Y! JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, D- d7 R0 `' L. X
MCASP_RX_MODE_DMA);
% p; h+ E9 H5 Z+ C2 {6 NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 P" [# [5 W, j% l# dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( |( [, b4 I( nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 Z+ s3 w2 E/ i( |% S' S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 @; J: G$ I# I. r) r' n" mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 f1 S' } x! f) G% M$ BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. r2 M/ D n1 S1 q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); o4 A1 ~/ {2 u/ J# D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . B& R, l' U( Q3 r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ U5 i5 X" V. p( L: O' L R
0x00, 0xFF); /* configure the clock for transmitter */& M: ~ }3 N" H- C2 U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 D: T/ L/ C1 Q7 m- R/ @) b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, I: f/ ]4 Q! m/ D+ p3 d% lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ F' c) A% N1 L# c/ g0x00, 0xFF);
! V- ?. U- w% m3 H
1 C. h4 c' E- Y! J) Q/ F& D$ n/* Enable synchronization of RX and TX sections */ $ Z$ g* `5 b' x* r: f/ R7 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ }8 @2 ?3 a/ K! V4 M, P1 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" c+ Q! C1 j# E2 Y+ l" _' S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* N" E7 A- I% A0 K** Set the serializers, Currently only one serializer is set as8 g/ K3 l0 ]4 g+ n& H3 V& j) P
** transmitter and one serializer as receiver.
: m+ F* v7 }" B$ n W2 N*/
, n' }6 y5 x3 ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 ~8 w9 M) K; B( ]( I- {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 C- e$ b# d0 I
** Configure the McASP pins - H9 X( ~, ~% {, Y) S
** Input - Frame Sync, Clock and Serializer Rx
5 Y; O# r2 i& Z+ _ Y0 Z** Output - Serializer Tx is connected to the input of the codec
1 w- s3 h; @0 X+ L*/
" q; D& a! @8 `+ p* A# \, \( cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
Y6 c* j( ]3 R2 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* |# d; N. u8 c+ K* `: }) `6 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# ~, S. x" Y) I8 U| MCASP_PIN_ACLKX3 A% T* o% K9 _& F& m6 Q2 z
| MCASP_PIN_AHCLKX
. j2 |9 i5 n, M& h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& T2 ?* g2 U6 [' C) U8 W& i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # H% N! }( D Y: g1 E; r4 {/ w
| MCASP_TX_CLKFAIL . i9 F2 s) d- N( S% j, _
| MCASP_TX_SYNCERROR0 U6 U) l; A; _9 J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : y+ h* U1 K/ G! Y
| MCASP_RX_CLKFAIL
o) L9 V4 H0 Y$ s& a1 J| MCASP_RX_SYNCERROR
( {8 A% y/ \' y9 x| MCASP_RX_OVERRUN);3 h0 Z8 q% u" L% A- Y
} static void I2SDataTxRxActivate(void)" r6 P# q% w3 m# Z) I
{
W" ~8 h6 F% Z) C/* Start the clocks */% r7 D% Y, x; b/ g' _# a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 H* b; w& L: iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 m* ~4 p, [2 b- N' ]' u8 P0 L2 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 A8 |. D6 L; a4 C8 c* rEDMA3_TRIG_MODE_EVENT);
- t+ K0 K. _& o, Y& LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& l6 j5 v! Z9 J7 G" ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! s8 x$ F# p# B- t0 c" d1 L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ W* [/ K7 I0 Y. pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" y. ~7 C' _9 o+ F: P; N5 @! U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// V H1 Y' I8 `5 d j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( b4 Y _. x5 H* q, Z h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 [+ H& c$ }/ Y% P( e/ Q0 q
}
) ?8 d V8 j: e0 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. Q3 K) i8 p8 d' \$ Z2 p$ _
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