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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( p" M9 V) X0 W5 ?, @input mcasp_ahclkx,
+ e; Q" q1 e, E# w, V- yinput mcasp_aclkx,
/ L5 ]4 ^# P' ~( r9 {* i% r5 `input axr0,
$ l/ Q& z9 z1 g9 B2 G
3 C5 ]! i+ r v h1 j2 |+ G6 Uoutput mcasp_afsr,
6 [+ h5 ]7 ]* \" n& S1 ]7 S9 H, Ioutput mcasp_ahclkr,& P) R3 E* B3 N8 g0 v8 ^2 i
output mcasp_aclkr,
& ]* l: c! a7 P2 M2 foutput axr1,
" J! j! Q9 B9 D# W8 [ ?* c+ A5 I assign mcasp_afsr = mcasp_afsx;. s d0 K6 T- G/ T# C9 ?# T
assign mcasp_aclkr = mcasp_aclkx;
: H. q5 D5 c' I( D' d( zassign mcasp_ahclkr = mcasp_ahclkx;3 }. l& p0 ]! v/ Z- }
assign axr1 = axr0;
k5 u! p# x) w; C. ~4 j
7 _/ L5 T, R8 X3 \2 ?6 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 @' I1 n0 j, o4 b9 C: G! vstatic void McASPI2SConfigure(void)7 P9 u, o& b- [
{; C0 ]/ V% f+ b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 E* p8 x' G) i6 K) B9 `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 a+ N1 f `* w7 [# i8 W6 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% t1 q1 E F6 C0 `+ h4 @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ [& s+ m! w, o* r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 q7 R3 w; q( `8 G/ a0 h
MCASP_RX_MODE_DMA);* T$ N: N O8 ]$ V' t* E2 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 V3 r! F" j4 B. d" g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
o% Z: s0 w; G. rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : @7 t7 T, p' D; ~: k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! p8 `+ r4 V2 ?) y. K: _4 g3 N2 bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 o6 |; ~1 ]$ U. I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 x3 C7 ?' J7 w$ iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 F# r" }3 E6 v K5 \, HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % ]3 W; H5 E1 s6 s' G! o" T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 J; o( D, C% X1 k0x00, 0xFF); /* configure the clock for transmitter */
' n! D. p' \7 z3 ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% w" o7 t% e5 ^) L" \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # F& C) I% G7 J9 Z. `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 o0 O7 C" C; A
0x00, 0xFF);% @" t y( L( \3 @; U9 s6 q9 a
" @) o1 T2 ^7 R5 ~+ B( j) N
/* Enable synchronization of RX and TX sections */
) ]( n( Q0 o- T" W n, R0 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
_) m$ S' `" b6 {, GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# S5 O( u0 W* o) N. o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% V9 z2 e2 |2 s( j
** Set the serializers, Currently only one serializer is set as
* p( U D q8 ~** transmitter and one serializer as receiver.
: _& K( p6 I3 o% R0 f*/* a4 u" B" T1 N+ W( }& t2 O/ p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& ?! K; T8 ?& dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# Q5 t5 j1 s+ c1 A* ~" k' j
** Configure the McASP pins 6 F5 H# y, D# k3 N |8 S% e
** Input - Frame Sync, Clock and Serializer Rx
3 }7 L' F) M ~3 L** Output - Serializer Tx is connected to the input of the codec 0 z! G6 }9 B; s* ]* |
*/
% G* `# i1 K* q+ t3 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 \& u, T/ k Z+ QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- ?# D6 }' D/ bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 u8 b( |: U% p* G& h
| MCASP_PIN_ACLKX
) M$ f% a/ A @9 g4 h. l9 ~| MCASP_PIN_AHCLKX3 o R% f) b+ p; O; _( h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. {' c8 _; m: W: aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " i; i6 [# t, m1 w" [
| MCASP_TX_CLKFAIL 0 M$ x) T3 D2 q8 t, _
| MCASP_TX_SYNCERROR
- F( H5 u- A2 e" P# b) ~! K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 p- _# t5 T' |8 ~6 |
| MCASP_RX_CLKFAIL+ z- p+ y% d4 e, w0 t1 x
| MCASP_RX_SYNCERROR * ~* h0 A) k5 G5 c) I3 s2 ~
| MCASP_RX_OVERRUN);
1 h1 o P& e4 m0 Z7 C& M( a} static void I2SDataTxRxActivate(void)6 a! |/ e. I) o, p5 v4 L6 |2 ^
{1 e" |/ ?7 z# R- F6 K
/* Start the clocks */, R5 e- E* Q* T& G& g' [ b* n! @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" K `: Z1 W. W5 VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& t, L& k& X1 S, t- D* F7 S5 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 J5 g0 P, v" F3 p* Y. xEDMA3_TRIG_MODE_EVENT);$ W' b1 ^8 ]: O8 M7 ~ _: L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 B4 e5 l+ |( m' F' aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. X# V; ?3 H& d+ T$ [. f1 G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 N3 k' }: t( ^5 J6 {! t4 e$ o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( h4 E5 G9 c* l& N0 ~0 m+ u1 jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 m, b1 K8 U1 N. v0 B, P; kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& i" I. L; \3 R. E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' y) N, E! O3 K) g G0 i% R: v9 d
} 0 u7 E6 P! F& A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / E7 x% ~, X: I8 r f% Q# [$ X
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