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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: D6 {0 p# E+ B+ ~
input mcasp_ahclkx,
+ X3 @- y; k3 h% N) l0 ?) D6 cinput mcasp_aclkx,# x r g* W$ l( ]
input axr0,* K, d4 F2 m. [" J/ A% v+ p9 n$ J
$ }4 V% P" J; ooutput mcasp_afsr,3 v/ S+ q, o& D0 S# i
output mcasp_ahclkr,( v j* H$ P, ?2 P
output mcasp_aclkr,
: u* a% k8 p& f! a* k/ Foutput axr1,
& a7 U& u1 ^# @3 W/ H) m assign mcasp_afsr = mcasp_afsx;; e6 ~1 [9 W+ y
assign mcasp_aclkr = mcasp_aclkx;
2 X& d+ ]. R7 zassign mcasp_ahclkr = mcasp_ahclkx;
0 V Q$ y" X2 ]* ]* c3 T* Eassign axr1 = axr0; ! X2 L7 ]( l! R
$ P8 p% v/ p1 ^7 Q- n! |: P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. p7 u% K6 l9 V& lstatic void McASPI2SConfigure(void)- w* l2 u, Q1 f' R8 \
{
! \0 |" U* ?7 a1 _9 N7 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( E: i5 c. Y* T* K3 s3 V/ _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 B- }$ W, M; [9 U$ u; {5 o( O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& E7 R: i3 i4 {- e. j9 O. A3 T' M9 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" d3 J! R! @4 L$ c' J7 v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 H0 y( L }0 D J: k5 `2 R- O. |4 M# q- I
MCASP_RX_MODE_DMA);
) D" Z( }0 |' t" n4 {* w& hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& G# @) z ?& |3 E, yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' x; e Y; r( \9 [. H5 ]9 t; {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # p: V& w1 T: ~+ [+ A" O. D9 h0 p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* z) j# d& C6 b* F. ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 T' k" l( Y u5 Z" U, RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 {! f8 B5 m2 e; X3 ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# C) \, i" F& Z' l ?4 C4 l: CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 c6 r0 p+ A( K& TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 H1 y8 ^# b' G! c( }' ^0x00, 0xFF); /* configure the clock for transmitter */& V# z4 n- t) P }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) X @' p4 x0 c7 E* I8 x( }- f! U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ E# w; x# Z5 u: m6 f3 p- R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: X4 `+ C) }4 V0 S, Q1 n- x) e; b0x00, 0xFF);
H4 p K8 W; C' z' }# [6 T: Z( ^/ h9 g& s1 `: L1 R9 Q4 T% x
/* Enable synchronization of RX and TX sections */ 5 Z9 A% B* M8 L/ W5 s2 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ ]' T# {! Q) ~8 N. E( p0 [6 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 w4 i& Y2 e+ NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 }& B2 ]' ?, Y; G** Set the serializers, Currently only one serializer is set as
8 |( n* w" u/ C. g6 {4 b' K** transmitter and one serializer as receiver.
2 Y; v5 ?) F# E x3 T7 g5 _9 M*/
; W2 d/ S1 t# ]: a1 [5 ~0 pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 r k5 ?8 ~! m2 dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, n( v8 |% b/ J" y** Configure the McASP pins 6 K; ?( s2 W, e$ D
** Input - Frame Sync, Clock and Serializer Rx W: B1 {, r) ]
** Output - Serializer Tx is connected to the input of the codec 0 n: @# [% m& _/ c0 x" f6 ^/ l
*/1 F* G# D9 f# j& ^5 A8 g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' e3 m: ]! P' ?7 w" uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% s! y- V# E7 X3 |- w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 e6 e9 _8 Z* p% \! [) i# a
| MCASP_PIN_ACLKX3 p- ?+ v# K) t# @5 \- y1 c
| MCASP_PIN_AHCLKX( Y+ r# T; k4 R* Z$ ` ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' M# Y2 e5 D5 Q7 u3 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 b0 b8 U2 R2 m- Y( h| MCASP_TX_CLKFAIL
) B- ~' e% U( J$ ]! b9 v& M- X, l| MCASP_TX_SYNCERROR6 _; G$ f! Z+ K# D! m9 t( e& Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 }/ b& }1 O: x- U) U! G| MCASP_RX_CLKFAIL
1 x, D6 E& c9 q: G0 t: Q( m& W| MCASP_RX_SYNCERROR
1 d Q" H; z$ ^1 j: i4 r| MCASP_RX_OVERRUN);
9 R* e8 z6 m! G: Z1 h" l} static void I2SDataTxRxActivate(void)
5 J6 t6 y) s; V; ]{
* S, a- D r- I/ d" N6 e/* Start the clocks */
0 k3 S7 G+ B: q- ~7 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; y8 A$ d; y' K( ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 {# ^- @* [+ b4 c. O- I+ t( G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ s6 |$ w8 H4 X8 N5 k, o- \
EDMA3_TRIG_MODE_EVENT);1 G: R! F/ c8 f1 e& ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( r4 k5 ]- g; W4 @: v5 i/ I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. s* K$ D9 |9 H' U* cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% o- z' H- X3 ~3 {7 A( RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* e/ T7 p6 {9 @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 R7 g2 i" }; l6 C" }! ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, N( M& U" l5 C9 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: T% v; L- q, u8 w5 ?3 Q} " G4 i! ?) R+ q {$ S1 ~+ U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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