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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 H2 o: w; r! M! ~2 j
input mcasp_ahclkx,6 ^! E" R& z' D% d
input mcasp_aclkx,5 {) `; c' b8 F: Y# h, e8 l! b
input axr0,6 h- O- E. ^) ^5 o4 W
( i7 t2 f/ T& ?0 H! Boutput mcasp_afsr, P- h( {+ P9 U3 M" ^/ G
output mcasp_ahclkr,2 s/ a8 x0 ?* f$ I$ u2 j u
output mcasp_aclkr,
( `" s+ r% A9 Q- moutput axr1,& ~2 {8 y* u8 x. ]& q
assign mcasp_afsr = mcasp_afsx;5 ?. t9 ^5 l% }% U
assign mcasp_aclkr = mcasp_aclkx;3 C% _& a/ R0 e" H
assign mcasp_ahclkr = mcasp_ahclkx;% r' V8 C7 X) {* u x
assign axr1 = axr0;
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+ W: y# {. _; J- E3 R: J+ b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( k# d! M1 V/ V K
static void McASPI2SConfigure(void)( M6 a2 U5 O! k" v% l. Y1 j! J
{
- d: z: N5 s. }) E6 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' H- f. r* [/ a: q4 A, |+ _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" ?3 U. S: S6 l$ N, l+ pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ p) B) q6 s0 t6 a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% q' }! e' K/ l, `% G4 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" @% H) }7 y9 B, G3 f# q" _MCASP_RX_MODE_DMA);
) E/ U! e9 s2 d: U+ aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 O# P; z; V' EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" ?" F+ \% N" O3 A2 ]4 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) e$ O. ?! h5 Y8 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) i0 E8 i Q; H. N& p6 z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 I8 W2 ^* x1 c! _5 n0 L% AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 \( w+ |* B! l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" r( ~0 `; ^$ u) J+ ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 R/ b2 t6 ^" P2 g2 _* U. D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! h, p. `- R/ R/ o4 T0x00, 0xFF); /* configure the clock for transmitter */
_$ @( e G! sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) r$ [3 Y* w3 f" g" R4 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 x: L% u* g$ b: e. _: EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! R( O2 Y. I5 T% h% M) s/ F3 k0x00, 0xFF);
& A% q7 P6 l+ Z0 B+ R) x4 {- V) V( S. N( C! p9 ~; s6 c# P* N
/* Enable synchronization of RX and TX sections */
! f# u, I9 z! [* [* l( }4 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 Y) g; \! c$ I+ j ^: K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ v! m8 Y* m. \$ X' X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 j4 v0 O# Q+ x# X: }2 E** Set the serializers, Currently only one serializer is set as
2 l; v" u4 t# \* \6 W. E2 [** transmitter and one serializer as receiver.0 U& b7 M. v9 F7 a9 u% B. q
*/
" l5 G1 g# a! UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- c0 c, s1 ~/ g" F M# U' V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 U! `! |& W' e/ S! G* R+ ^
** Configure the McASP pins
, y# O7 q* W7 J/ U2 U7 T** Input - Frame Sync, Clock and Serializer Rx
3 k7 j: ^# }+ g** Output - Serializer Tx is connected to the input of the codec
9 J( \5 {3 |2 ^* L/ K*/& n$ ?; W1 q+ z9 v. E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" ?; f! U5 e; d9 g3 v$ a1 N6 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 n3 D$ S2 X2 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% j3 a4 f' `+ O s
| MCASP_PIN_ACLKX& P; k! ?9 Y$ r# G
| MCASP_PIN_AHCLKX
9 ~2 q3 }6 {' d5 H' n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 ^& t n. t2 F3 m, p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- V( g2 a. W! v+ H2 R6 y( E| MCASP_TX_CLKFAIL
W- I- N2 E% p+ `/ I% v0 B| MCASP_TX_SYNCERROR( @5 s# B7 ^- x3 z0 G& B3 B5 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 K+ [: t& O4 L( m. ?
| MCASP_RX_CLKFAIL
: G8 p1 e" A' p% n! Q4 F3 o2 e| MCASP_RX_SYNCERROR ; s0 O) j! s* ?! W. @! Y5 x
| MCASP_RX_OVERRUN);+ a7 a* J; v# d# k0 n
} static void I2SDataTxRxActivate(void)
3 q, M, t6 `6 l. ]0 d7 y6 ]6 _{
* i3 {" L; x4 `! m: ?5 J/* Start the clocks */: q8 j6 \! K w% R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ [( w3 @* P( m* y- `) cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 e& E @" @5 ^( Z( a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 r, H; l4 S& j
EDMA3_TRIG_MODE_EVENT);
$ ^! z, D% B# w. [# j) ^9 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : {3 m9 y( w# o, O7 K. I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 ~7 i5 C, E0 O/ A0 R' m E0 jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) [# j2 u4 g5 Z, {( gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' P1 i6 S% \+ M) Y; F! T* Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; D/ Q" H, ?' s$ C; ]. B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 R4 Y8 n4 O/ G# |1 U- ?9 L# aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 E/ r: ]7 W9 Z% T& }; d} % Z2 K& S6 l6 L& ]5 X4 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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