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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 p+ n& P: M V& T0 R! q! o: @
input mcasp_ahclkx,. O/ k: q% n3 P' A
input mcasp_aclkx,
) f/ d) D+ i" S5 E" F7 x. E. G5 }input axr0,
- ^! n" V% ]- p# H7 f
' q. v# r" @7 F4 t xoutput mcasp_afsr,* s; B; W3 v6 c! G7 n/ o) I
output mcasp_ahclkr,8 a+ J6 N5 Q( k6 Q0 O2 R* h
output mcasp_aclkr,# F9 U% h+ L) y2 ]1 C8 e" l
output axr1,* x8 j: ~- A! ]. z. @- l* w9 z
assign mcasp_afsr = mcasp_afsx;$ X( b9 b& w& B7 x: j2 Q
assign mcasp_aclkr = mcasp_aclkx;4 J7 g6 y" T* ?* p0 }& W* u% x
assign mcasp_ahclkr = mcasp_ahclkx;; j; V- X6 T" |9 l1 h9 w
assign axr1 = axr0; 6 m) t# x3 J3 Y
$ Q! z( @! R; Y7 d5 _, W8 i0 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 `5 P$ @2 k5 `$ O& }static void McASPI2SConfigure(void)! l! D0 n" A4 ]* G
{
/ d2 p3 |4 n4 _$ u; rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
` v- |+ p" e& H3 {' N# EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' e# ? G+ r7 |* CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 z8 k8 M6 u- y( AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ R5 d1 k# w* T9 B& L6 B2 V- q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: L! I$ V; Y& z: t# r5 ]* M+ DMCASP_RX_MODE_DMA);6 n" {: P8 N( a' D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; w' H, \+ J6 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 o8 {0 ]; ^% U( M5 v+ A( O, N8 O+ d! Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 G U5 m3 e( \+ |" ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: x5 D. c* ^! [2 M7 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 u2 ~; j0 U* YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; b4 U7 B9 `- U7 [' H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 d0 T+ V! t |- Q% ]0 @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & u, n$ q" T" M! T4 f4 ?+ R, @7 j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% K: E q, N0 v& j, t! {0x00, 0xFF); /* configure the clock for transmitter */
3 j ~1 R1 q. ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; C# W1 Z- G* f! I$ F# [5 @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; |) C5 P. p2 S/ ^: O3 y) Z- {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 c N4 h2 o$ ]
0x00, 0xFF);6 y% m# ~% O$ j: P& [0 _
1 Y. z+ j, e) v9 q. f( I
/* Enable synchronization of RX and TX sections */
& `. t7 D P* c6 I% e: Q+ H4 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* S& ]7 {( T! J$ j- uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 z7 Y) Z+ I1 h2 c+ j% k" \# Q$ P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 c Q( F: m; y+ V4 Z/ r
** Set the serializers, Currently only one serializer is set as
, F! `$ t( ^% d- ?6 f1 i/ p** transmitter and one serializer as receiver.) K: D& H# f8 |- P B
*/
& x J1 E+ e9 F \1 N2 {5 R XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" T6 q( B. S% K( ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 T* f7 v) i8 c/ @; Y; c6 ]
** Configure the McASP pins 6 ?8 n/ ?6 I; z5 [0 K8 c
** Input - Frame Sync, Clock and Serializer Rx
% X$ W* _( I$ ^( V) ^. \, Z** Output - Serializer Tx is connected to the input of the codec
0 p2 G6 c4 U: {( b/ I! F*/
4 N3 x8 k6 {- |8 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- p% k1 ~0 |" m0 s8 d* v1 YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' x7 r0 z7 P/ y8 r- T% XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 u9 j7 d- i' y/ q+ ?% ^' n
| MCASP_PIN_ACLKX# J( b6 h, b P t( f) T( @* h% N
| MCASP_PIN_AHCLKX
4 W6 H9 o, P, _8 `0 || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, |4 ^ o1 X; L0 b, JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 K$ m$ ~% u0 ?9 n) x
| MCASP_TX_CLKFAIL
) U" F* ?* I& z4 {$ K6 a( T| MCASP_TX_SYNCERROR- `! @3 M% ~3 q$ C$ ]) v0 \7 G" y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* `4 c2 P! f4 ?* }2 d- P& o7 n; q; T| MCASP_RX_CLKFAIL. Z0 S7 f3 G7 n4 `4 P& ]: U5 j- e
| MCASP_RX_SYNCERROR
7 @) G2 e/ T' w2 C. S8 B/ R3 ~5 O. o| MCASP_RX_OVERRUN);! x0 I& @, {3 w. E
} static void I2SDataTxRxActivate(void)3 E# O/ U% v7 Q9 i! k4 l
{5 X9 c5 i6 _! J( F
/* Start the clocks */
3 U& L# m1 S) V/ gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. o' W3 Y- m$ q) {* {1 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& e4 U' l8 u0 [+ ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' l7 z' _! u( u7 `" _5 `' fEDMA3_TRIG_MODE_EVENT);
# |* Y0 c8 {& z1 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 O# T4 u, V8 f0 f) X& I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" ]$ S2 Z5 c# y s" e$ k6 S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 O8 n0 o. J) GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 H0 v$ m- e' ?/ S n9 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! h$ S" v. t; W" X+ I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( _& \* N/ u! z% v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 i+ I- o4 U7 S7 T7 P9 Q' l8 H) }9 y
}
9 W( b% X8 Z2 }; g0 J: N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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