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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 b) e0 h% L, m6 D5 v0 a$ J# ^8 r: w
input mcasp_ahclkx,
$ G4 S& j; ^. Z, Uinput mcasp_aclkx,! o! D* x' |/ D9 Q
input axr0,4 |/ T _& [7 O, i! w& |
. F% m" D, m0 f7 ?3 V+ r4 @8 Boutput mcasp_afsr,
4 N9 z6 Z) d; }0 J9 coutput mcasp_ahclkr,. e. D$ T+ q9 j7 |' T! O" c
output mcasp_aclkr,
1 {1 d% ]! k+ f4 voutput axr1,
1 h: J4 v2 c) O2 I7 w assign mcasp_afsr = mcasp_afsx;& R0 y+ A6 L' I9 T" ?
assign mcasp_aclkr = mcasp_aclkx;+ x8 |* _1 `) A; }. i
assign mcasp_ahclkr = mcasp_ahclkx;
8 P6 Y; i# }+ Y lassign axr1 = axr0;
/ T0 J) z$ t) Z3 Y% y1 ^) M. b7 b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 V+ z$ j6 u; `' n; I
static void McASPI2SConfigure(void)4 C5 F. F8 W; u
{
, C) r7 g( S) ]; E7 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" j$ G; l' x: Z7 Z8 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. S3 I9 Z& q: rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* A( s+ U# P! D$ [& r- S, `/ o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 z! f# R# n0 P! J$ o- x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 R" J# P, t, m5 I4 f; U2 TMCASP_RX_MODE_DMA);$ g) z# O c+ ?: _' w$ F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. w3 e6 a( u5 h- _' {+ B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 k4 ?7 D0 A- }: AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 Z: W+ \# {: L u$ }% Z9 ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, N4 Y; v/ g' XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 u# t9 I4 x1 C; e1 k* V6 J# @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! B) u# w, m/ Z: I5 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( k' r2 R3 @: z$ ?9 c5 L6 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! }; y- }5 o: t/ `6 v G6 J) r9 oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 A0 Z/ P! S. ~% h0x00, 0xFF); /* configure the clock for transmitter */
) G- w7 l3 |- X3 M+ G2 l# zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 c0 e' _* q6 ^/ Q7 z6 q. S& m1 S1 bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ R7 O8 P- `: C+ w @- @% U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 G+ d8 P+ D- V' @6 z/ T# F
0x00, 0xFF);$ p: Q7 {6 t. W* f) Z+ c: i
: x _* ]! ^' s6 T; W/* Enable synchronization of RX and TX sections */ * n6 G( O: P! C: n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( O. D6 x* i% D, p2 f+ T7 \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" s* e6 S- |+ V7 x! ?1 P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: g! P4 I3 H- X9 x8 S** Set the serializers, Currently only one serializer is set as9 s: L5 W5 b+ [ ]
** transmitter and one serializer as receiver.
5 }- M8 C# l+ ?! c% J: B+ M*/
7 c$ j/ p& l" }3 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. b6 `- F. o" `( m$ p CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 R( M0 \5 G+ E3 r1 i: P+ c
** Configure the McASP pins
, q6 w7 V/ c+ J3 F** Input - Frame Sync, Clock and Serializer Rx
5 h- ~( ]+ W9 ?3 c! @** Output - Serializer Tx is connected to the input of the codec
$ `5 q- O) z$ r) M9 i/ c/ i*/
6 g9 m k- Y& J0 a7 C- pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 ~! v4 {. F, Z4 z0 t! N& n3 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' k- q/ A# |7 D4 n- m1 YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 l, x* C9 {9 Z" ?$ k( T" F3 m. t" _| MCASP_PIN_ACLKX
. ~% p* K& B+ \, B8 ~: k3 y| MCASP_PIN_AHCLKX: g# H {! ?& I* t; G+ R; \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( B' [2 [8 L f6 e, MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* A- s$ c/ u+ ^; c9 K5 i; g| MCASP_TX_CLKFAIL 3 @( G# r1 [" T2 T5 \/ B
| MCASP_TX_SYNCERROR5 q6 D' t8 k. S' l; @/ i% Q# O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ k, W* }7 o, F2 z1 `8 R
| MCASP_RX_CLKFAIL
- z' K o( k0 E9 o| MCASP_RX_SYNCERROR
5 I [$ r5 G7 ^: \# B5 s! s| MCASP_RX_OVERRUN);1 ~5 e+ d+ _5 {
} static void I2SDataTxRxActivate(void)4 J# d, F" h- V. L1 {
{
) h7 \9 b0 |2 T/ e# _2 K/* Start the clocks */
) R5 W4 ]% Y, F/ S3 E7 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 c1 r" G5 `4 G# S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 f0 y9 y0 T; z0 g* {+ L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ a2 y% o$ U, b. z( _$ D! U" _
EDMA3_TRIG_MODE_EVENT);
* t# c* x) b3 u9 ^1 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# A/ w& D7 z, @: m* GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, g: @3 I% t' ?5 X' O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' J/ A8 N3 F! W( E, [+ TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( j- z* }5 O9 `6 M" [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 b$ a' V6 b- x8 @- Z; D8 i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' s; A4 ]% `; z( g/ P& a$ [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 Q) r5 T' J, q+ c& F}
# ?. J7 x4 l- T4 j0 O1 M1 S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 B% X3 _% b( f2 ~1 z, r8 ?
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