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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' V7 c+ g* k+ e, r+ m( O |input mcasp_ahclkx,0 v* \ M6 r2 l4 P% U
input mcasp_aclkx,
% {: f- Z X* K4 H; p3 H& Ginput axr0,9 y- `% M3 {0 d5 w4 h7 j' R! s1 q: G
! M! N' y3 M) ?9 b! S toutput mcasp_afsr,
5 o7 a4 N- v* b# ^; n0 G0 Soutput mcasp_ahclkr,9 E4 c) t6 U. o: b! W& @; I
output mcasp_aclkr,
. a) X% a8 @: ^output axr1,& _$ @" I$ Z& x- m( n7 g0 ?
assign mcasp_afsr = mcasp_afsx;
4 ^( ~+ y+ X6 @/ Vassign mcasp_aclkr = mcasp_aclkx;
/ t+ D+ D0 ^; B) e [7 G" Iassign mcasp_ahclkr = mcasp_ahclkx;' K$ z/ V4 t$ Z+ h# N: g; n7 h0 [. r
assign axr1 = axr0; % ] ^& t, v5 o% t2 @0 V
! g8 M5 o. h Y2 C) T8 r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 O) g/ m+ o3 I: m8 ~5 V
static void McASPI2SConfigure(void)
. g5 |& \" X* F3 ?. g( z; Y{
% M" u$ P0 V$ KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 {4 n+ z) v7 t: J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" `3 b: S7 a9 F! ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ F$ \% l% `8 B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 o1 C4 K* j3 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" H% j7 E" S+ _) l; f! CMCASP_RX_MODE_DMA);
4 N$ X ]) R3 k s' p3 f2 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ B0 ~% x" L$ lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( X& F' Q: ^4 G2 v( F8 a) P6 W, b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" U. m8 \( I% J/ n( z5 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 R3 ~4 S! n1 X: W. `) x% {# C# v7 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 N' d: n/ _" ~7 p7 b$ [0 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 V/ x A0 I7 ^# L, AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, q( |0 a1 L' g$ N8 h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + \7 t# ~6 Y2 s& {5 [" n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& D( x1 s1 i1 K @ Q# @* d' F! m0x00, 0xFF); /* configure the clock for transmitter */! |8 ^" f7 n' `/ e( [) \6 ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 d$ l6 L' J' h2 `# }0 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 s0 h2 c& c, R4 `7 }$ e! QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 s8 |& M8 b0 k' Y
0x00, 0xFF);' J* g" a7 V# t( V, w6 Q
1 `1 @. [8 s2 g& I
/* Enable synchronization of RX and TX sections */ % W4 Y6 ~, }7 _. `) v8 J& Y' ?) F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( R$ c# G1 b, o3 b: Z# u, H- \+ NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 s, E( i, ?9 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: M8 q; F# j8 h/ \4 _$ G8 d8 N$ y
** Set the serializers, Currently only one serializer is set as
( q; v& ^! }1 s! D2 y** transmitter and one serializer as receiver.
) ~* I* }( i0 h% l" U7 j5 [ {*/0 s2 P# L, v: _7 F& g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 a9 t' ^0 ^. T2 {2 o! NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. e2 Z) q& b9 b4 G** Configure the McASP pins , h: @/ I2 U8 L3 |
** Input - Frame Sync, Clock and Serializer Rx
& x* \+ J w5 G( o$ y v** Output - Serializer Tx is connected to the input of the codec
$ X; c2 r, U2 J6 ?7 [*/
* u4 `- \8 V' U+ lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ u2 t! s* e, RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( T& z) s: ]9 W0 g: BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* u; ~: A4 K! \& U- W9 `: z! p| MCASP_PIN_ACLKX
; a! ] H* N# |1 q6 A| MCASP_PIN_AHCLKX% s2 `6 R3 \3 R/ W# r( w) J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 f! B! S* _5 E" d) y6 j0 Z+ M0 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* T2 z c5 p2 ^5 f. f- z8 T8 v) a| MCASP_TX_CLKFAIL $ G a4 Z7 q+ `# R! X% _# n/ {
| MCASP_TX_SYNCERROR" r7 m) V4 u z3 A" [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : R/ r, A a, o' o: \
| MCASP_RX_CLKFAIL
. _( @9 q9 f$ x8 T9 P3 H0 b| MCASP_RX_SYNCERROR
# ^6 r4 t; \7 b; E' W| MCASP_RX_OVERRUN);
2 A1 c: { |* L1 q: p, [) l} static void I2SDataTxRxActivate(void), Q6 b: Q# Z* Q
{
/ r- N9 k( e2 E) p7 z o) t; S/* Start the clocks */
6 p+ X, W/ u0 r; p, JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; I; r1 [5 H$ R; [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- X% j3 @# d$ a7 k$ X Z/ E2 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) i% S% B% R# \EDMA3_TRIG_MODE_EVENT);6 t+ g! l: F& S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 y# U$ X6 W8 ~/ g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& x& j' h: c0 f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- r- E" i9 H4 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* r W' S) ?: |. b% D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! y$ r* J! Z/ Y: CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' C1 q3 {" P5 S* @2 I8 { i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( W* n6 h! K1 W" ]$ P( l}
! E$ q; h+ o+ Q5 G9 z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 Q: `; K# X/ q" m% |/ `/ A
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