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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 O+ s7 j1 M) d! T
input mcasp_ahclkx,
2 K4 y6 C$ q/ `& A$ Rinput mcasp_aclkx,2 U% k/ ? }* R* P. A, y+ b. n+ f
input axr0,3 w6 e0 a/ W5 \% }1 g S W
4 U& b z0 T/ k* c4 F" l
output mcasp_afsr,
5 b9 W$ F9 F5 L/ u# i* _' ]output mcasp_ahclkr,% W. V# A# ?8 Z+ _$ }1 V
output mcasp_aclkr," i, {9 Z. |- s6 c( @) V
output axr1,
$ g7 X0 S) |7 T! _4 L$ | assign mcasp_afsr = mcasp_afsx;
% j3 P' D* |% yassign mcasp_aclkr = mcasp_aclkx;/ V) a7 ^- w+ c* h: \
assign mcasp_ahclkr = mcasp_ahclkx;/ L) W6 x7 L' E# i' M) j
assign axr1 = axr0; " x, v) ~" M& J, o% w$ s
: w4 C8 B4 z0 g+ M4 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
d: R9 s& d0 m4 Xstatic void McASPI2SConfigure(void)3 X- B' }$ \, {; U' K& x
{& b" k, Y) p! h; H Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 y% s+ \) M+ N8 r4 ]/ ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 A1 G8 e$ }8 P% [7 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) _9 N) M7 m6 w" Q$ x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 ~' d6 X' B; Q9 d7 t# @3 v' }5 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ }* L2 _% G) Y% o. v8 `MCASP_RX_MODE_DMA);
. s# i( G* _# c4 O9 w8 J4 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 }8 }0 g* T" }! z8 A* SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 ^5 r& w1 k1 l) e0 \; g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; W* C3 u9 r( g e5 [: n$ P( p" U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# D" E6 J1 O" oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 t& H/ f+ p4 k' Z5 M5 I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// K8 u' _# |/ ^. m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( E9 e% l2 V4 k( N+ y, [1 t$ J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : O8 }/ [- F; V$ ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: W; f1 F; ~# u0x00, 0xFF); /* configure the clock for transmitter */- }0 d1 @% b e. Y9 ~1 v* R0 x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# x) n8 `' ?/ N$ a. ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( d- b. U1 e% D7 I8 p/ eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 C& ]# L% w/ T0x00, 0xFF);3 L0 ?1 D6 M% `: O; n
* u I8 s) V1 r% Q/* Enable synchronization of RX and TX sections */
: t/ L1 @5 q8 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- t) o5 I! T' n' F B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# B/ U3 t" o& y/ j# b9 Y! \; }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. T, _1 x, r: }6 L; }
** Set the serializers, Currently only one serializer is set as
: |( o% |1 I; [2 X5 F# R9 h! l** transmitter and one serializer as receiver.9 S+ [" \% E, u1 e8 \# x! h
*/
, @8 e0 X; U# JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* Z; c8 J8 P! T6 ^3 oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! Z# h! B$ Q1 x% Z
** Configure the McASP pins
, j1 n( x' n @& [3 V* V** Input - Frame Sync, Clock and Serializer Rx
$ a, ^9 L! q: S9 v** Output - Serializer Tx is connected to the input of the codec
6 } s* b- ?- ~1 {5 R6 b' v*/
7 N7 R; P% `; m' {: [1 s- TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 q: ^3 v: u, ]: E0 S% b9 n$ [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( i# O" t; B0 f# NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 o) h/ D3 J" J' s| MCASP_PIN_ACLKX4 j' T; m. |: o! |! l
| MCASP_PIN_AHCLKX
" z3 h/ _6 @$ G9 {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" ^2 q1 u+ Z/ R4 A& Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! i# F+ M$ g% y, l| MCASP_TX_CLKFAIL 6 X: P4 @7 C+ s9 Y. [
| MCASP_TX_SYNCERROR: W/ n) r6 u' R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 Q# o) l" r0 [| MCASP_RX_CLKFAIL
) e, |) \1 D, d: T; l0 g% z+ L6 l| MCASP_RX_SYNCERROR
/ C; x) |7 ?: G5 v# c4 v| MCASP_RX_OVERRUN);2 E9 Q5 b; ^. D+ A/ ~4 M
} static void I2SDataTxRxActivate(void)* O8 [% K) ~, U/ Q! }
{# z5 A1 Z. t$ t
/* Start the clocks */
! W( ?- z2 k! A/ K, gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 O0 w+ P) I; V* ~1 q- {6 R/ F0 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ t4 k0 Q9 R) |# a9 L) u- y$ O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ I, m+ Z+ v& V, l4 b2 tEDMA3_TRIG_MODE_EVENT);! I, A* b! c/ `! g9 B& {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) ?- V( a: @4 e: R/ O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 q. i/ Y: s$ D% E1 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& r# o4 x4 i0 J( r/ \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 q5 w$ A5 S! {/ N/ y9 _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: E& f# A1 q6 I5 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 f9 M C' C2 j$ pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 f( n8 y/ i; n. L
}
: ~ l" l' Y4 {6 |: u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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