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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 |& y0 j' i, t( J8 O9 v2 n6 V* s$ } C
input mcasp_ahclkx,
& M! h; |9 n; s. D0 minput mcasp_aclkx,, J J5 j# }5 x& ^8 D9 n# ^. m; [! c. A
input axr0,
; l' M& V L2 S! {6 A$ `
* W( C% @& F# Z8 L: ^output mcasp_afsr,
+ o3 I$ Q' q' ^& l* ^' ^output mcasp_ahclkr,
' B% E" {4 v5 W8 xoutput mcasp_aclkr,
. B; v" {' n) i, g4 j4 P! P9 loutput axr1,
$ u, b$ X+ l6 {( ?7 J: ~ assign mcasp_afsr = mcasp_afsx;
- |: T" r1 a' ?5 f6 L$ |! S" Bassign mcasp_aclkr = mcasp_aclkx;- t! p% C. W* h, `' k
assign mcasp_ahclkr = mcasp_ahclkx;, ~ [6 q6 W( F- O' K
assign axr1 = axr0;
" y3 L' {; U5 p
# \3 y( Z/ G! Q( e0 ~( R+ R$ C# r5 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 ?# c' ~- l: H3 P; R& b
static void McASPI2SConfigure(void)
/ k' \3 a) N/ J x{
# M& Z3 i8 W+ D. K( _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- Q/ a5 e+ u0 ?/ hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 P1 @0 @* \- m* b; u7 Q! |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ i& Y8 \) S7 j/ k: UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! U$ [) m7 t7 R2 b; S& K4 w E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; W6 Z( V9 w5 C! k) M3 cMCASP_RX_MODE_DMA);
' G! D7 a C% E! i `7 k( a' D/ c" qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: M6 |: m. \; n1 \& A6 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 ^# w! C3 k8 C0 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 g+ [$ Y. M1 tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% Q: l9 A' ]. I/ y9 \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
Z1 x" _, ]4 h9 `; LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 j3 O. C/ D J( t# x- r+ U- p) aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 X% q& v; N# i. N: a8 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
}- Y. O+ X& X- ~) W7 r4 X% X0 Y) FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" Q' t7 u/ ?! D4 O0x00, 0xFF); /* configure the clock for transmitter */. k# p. C) A9 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% b% |# \% X9 L+ O! r& [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % O/ M. w3 A; O/ A R- k1 W6 H1 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ F" ~# H1 l/ J; o# T. M5 d- S$ w0x00, 0xFF);
3 S$ {% C& A' x# u# D
& K+ I0 m1 R9 `7 _/* Enable synchronization of RX and TX sections */ 2 G& Y3 o5 Z+ ? H4 A; H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 K5 q6 u0 e; P/ A( `( F% |/ KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; r3 g8 }" f$ g, x9 @4 O6 a; M5 a4 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 u9 \3 w5 m. M" V. D, k5 `** Set the serializers, Currently only one serializer is set as
* n1 P, i2 ^4 ^0 |; s) z4 u** transmitter and one serializer as receiver.2 T, X, |4 r0 G, y
*/
6 s$ R9 v5 G4 i I P: }! }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ Q# O, G4 W O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ M0 V3 t: ^9 I) |- \. b2 P** Configure the McASP pins ) W' K) |' c: A! X3 ~
** Input - Frame Sync, Clock and Serializer Rx* ~. P. n4 X3 L# j* U6 `: X
** Output - Serializer Tx is connected to the input of the codec
/ G; e" U$ d% D( y*/
# b7 E" h, P8 r2 r3 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' i e M& \( T& k) n" |, \0 ` mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# L O1 z7 Z. Q2 v. a! Q" b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 m& t3 Q: @9 J8 g6 n' }
| MCASP_PIN_ACLKX! u0 r! k+ c# S5 I! L
| MCASP_PIN_AHCLKX
! w: j K% H# C1 o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 u* P$ Q- l/ Y2 c4 `( G, TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 w/ U C7 I# j! s I9 m| MCASP_TX_CLKFAIL
, c& R4 p* v0 e- Y8 W8 I- G| MCASP_TX_SYNCERROR5 y: @, I( ~! n5 M2 y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 Y( S0 i+ u8 Z0 U| MCASP_RX_CLKFAIL3 T: o0 ^ ?6 m+ I# i
| MCASP_RX_SYNCERROR
- ~; O* `7 x T: S. c| MCASP_RX_OVERRUN);+ w5 G- G8 F i# v9 K- G
} static void I2SDataTxRxActivate(void)
) s1 h2 t4 E5 G2 u: J- R7 R6 \9 c{
; T- m9 D) p5 l, t/ v1 v/* Start the clocks */
* ^6 z* P2 ^( Y% H& x7 mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' D% s0 ?! u3 Q; w7 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. D% ?' p8 X* |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ w4 s$ t5 T: d6 U. N) L0 ?# ~
EDMA3_TRIG_MODE_EVENT);) o4 z( c m# j6 H" z/ J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ C' M. G0 M. L" o2 @ c; uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 ^) m' j6 B- |6 x) y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" h! O* C1 E/ e6 V- Y- FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 Y4 |& t( `8 t' o5 T) w( K. l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( \) Q d; h: I3 t1 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 U' Z2 n8 f- ]# m$ h( @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& \: q' E2 L+ _. \
}
$ s; o1 |3 @5 F* o. S- M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( ~9 f" n$ d+ Z
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