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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 c; _( V" s5 f/ U3 F
input mcasp_ahclkx,5 D& _# \* `( l+ i
input mcasp_aclkx,; ^+ z) I+ h& I; X( o( `6 @
input axr0,
7 L* S' j$ Z* b" S& W/ K% L. x6 [
' r3 q6 _4 ~8 \0 g6 Aoutput mcasp_afsr, O8 ?5 p0 g6 J" a) @
output mcasp_ahclkr,
3 J8 n$ |' e: M" W Houtput mcasp_aclkr,' P6 O4 [& Y! |" `9 @
output axr1,9 m A2 K2 w/ G4 ~
assign mcasp_afsr = mcasp_afsx;# e8 h1 l8 d m' @0 q. t- A
assign mcasp_aclkr = mcasp_aclkx;$ a; g& k& h' G( w8 q# B
assign mcasp_ahclkr = mcasp_ahclkx;
* P5 ]5 B+ m+ l. s) p9 V9 c4 kassign axr1 = axr0; , ~1 @ X% Y, h6 S3 \5 j
$ T& f& U* ^* T% c2 F; V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 T* |; S' Z" K( G6 q1 K
static void McASPI2SConfigure(void)
f5 K8 C. |8 Q; A7 d' x{2 V* {( D4 k% P4 n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ R* _/ R1 Z3 d( k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
w9 Q& S3 Q3 e$ ]+ \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) u, ?8 r1 w7 q+ t) E6 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 T0 \. n# }( R# g: t# A( s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 p1 u0 g/ f0 M! D7 PMCASP_RX_MODE_DMA);. U* ~; z* t: S* w6 n, c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; f, C7 H- {* G$ K* r: N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: E% \6 K3 `9 p/ R" r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 W+ \" f' B$ b7 | F5 P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 g3 T8 W! e1 |/ X) H" SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) X1 p! ?; m, L4 K0 H8 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% c3 |8 \5 J; k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! h r( h$ `" m8 w0 ~9 r: k# [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % u" _; n# m- J# h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 [7 h! F2 C6 j
0x00, 0xFF); /* configure the clock for transmitter */$ S- L8 F( G; ?- M% P! \) B, i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* ]# Z% U# ]: yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 _# }& S& ~/ J8 t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( _+ g7 s4 H& L% b
0x00, 0xFF);. w0 ?" y, Z8 I/ Q
: h3 I" a0 T1 O# H3 ~& ?
/* Enable synchronization of RX and TX sections */ # ~) U" U$ M+ w+ `' m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* b5 [ V& i$ Q) j- G+ M2 TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 s2 `3 o" q( z8 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: s5 ~! \+ A: `, v D" r** Set the serializers, Currently only one serializer is set as
" u9 c8 q, y5 O6 j** transmitter and one serializer as receiver.
' C" [8 X" T) s& ]; f8 J*/
; |& P+ l8 ^2 d% R) E$ k4 F* @/ q1 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
x) z$ `. |+ F5 K/ C- r' T' L3 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% X5 Z8 s; I6 B- s: }% Z: ?0 Y
** Configure the McASP pins 0 C5 ^' K8 L( F) C) ?+ I5 `6 `& w
** Input - Frame Sync, Clock and Serializer Rx
" i; ^6 ^, _: J- {3 @6 T: Z** Output - Serializer Tx is connected to the input of the codec
$ s. D# _' Y2 ?) q& W5 x# w*/) f/ e1 j$ |! M3 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: E, X. i/ j2 G p, x$ `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. W) y) r) ^1 O9 wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 C, a1 X0 k5 x! d$ A; i0 D& Y% j( }6 u| MCASP_PIN_ACLKX) _% v# \9 i! X V
| MCASP_PIN_AHCLKX. Q4 s( T% H* q: x2 h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 w3 q* e1 ]. j- h4 ~& B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
l: B" t. l, |: V$ F6 V( o' f" P| MCASP_TX_CLKFAIL
' j1 n4 z. c; R| MCASP_TX_SYNCERROR( p5 B0 K* b# N R2 b: [/ u' v# S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 G! B, E" |$ Z- @ o+ d
| MCASP_RX_CLKFAIL2 ~, O; \* t" }8 U' a4 c( |$ P6 E
| MCASP_RX_SYNCERROR
( a3 x& c4 [/ R+ J| MCASP_RX_OVERRUN);
8 Q( j5 z9 J/ D4 U1 q1 X} static void I2SDataTxRxActivate(void)+ |6 V( U' h" _2 z! B% T' C
{+ z5 w7 O; k( }' z7 I# Z
/* Start the clocks */
$ I8 s6 y# Q$ C" d3 w; q9 vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 ~6 L& l- y6 S/ B, aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' K5 b2 o' n. j k- v/ _1 F. A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 w* X' W% X* e+ n( j+ vEDMA3_TRIG_MODE_EVENT);& h/ d* o4 ~7 j2 w- ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* Z8 b! r/ z0 J5 V0 l. h9 Z, `/ eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 \& U' r# R, m0 z% AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) J, ]7 G5 H; b. Y/ [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 ?$ T1 C% ]) a7 x. l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- K# g( e8 h9 Q, b* A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 H7 v! ^% d' X0 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& f6 C% i2 L1 e& e6 A}
5 _% l" E: ]+ v9 k& u* a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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