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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 k2 E+ y( H8 f3 l, V
input mcasp_ahclkx,& z u( q# D+ F5 d
input mcasp_aclkx,, y! H5 D! d2 @6 f% s" k
input axr0,# Y f4 Q* b. i" \. { D( ?' l
! \/ d3 k- z) W) s
output mcasp_afsr,! h. O5 ]8 C/ x0 [! N8 c. t# @, D
output mcasp_ahclkr,
5 I; \* D; h' houtput mcasp_aclkr,
3 o, T- G; F; }output axr1,
- t8 V1 r9 N4 a* U: J% V0 Y( p- h( v- n assign mcasp_afsr = mcasp_afsx;
/ F9 Q. s& g7 b" K9 x9 massign mcasp_aclkr = mcasp_aclkx;+ a% V7 l8 _4 C' `
assign mcasp_ahclkr = mcasp_ahclkx;/ y: W7 ]9 \- I+ K5 |7 b
assign axr1 = axr0; 3 }/ X1 n: X$ A6 K8 K
5 i1 P; ?+ Y! V: E! V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , W6 m- R& k+ w
static void McASPI2SConfigure(void), _/ S9 |" u% M8 N
{# ^% @2 U" I% C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 k) A, s K8 e& W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; F4 [8 _3 D( nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 M( c3 ~7 i+ Q8 C+ w" ~0 p; y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ n, ?5 N" f! _; K4 _0 B- J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 J- \3 [6 D; @. B+ y: I# s7 c/ [% a
MCASP_RX_MODE_DMA);+ w3 o0 o! V& E" R" l
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% K# M% X" N7 ~, {) o p) w' v8 S) @. U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 W9 Y, i5 A4 f8 q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% @$ G! O9 `/ Z; p3 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: O# c, q H2 W I$ ]( kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 I B% U8 _. A3 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 K3 ]1 B5 a7 {0 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); }. m W/ e1 Z- n; L5 u: m! F8 C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' }5 r) |* H# lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 x' U: T& o9 X/ v, h0x00, 0xFF); /* configure the clock for transmitter */
0 m* U0 R5 _- P) Y" ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; M% i7 [: j: y8 g1 N8 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / l2 Y0 f2 J" M/ I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# g! v' h% J9 r8 a
0x00, 0xFF);$ P) X# y: j, K, k# {
6 L" k% s" l3 O# h8 J' m
/* Enable synchronization of RX and TX sections */ . e; ^" \& e, f% I% _9 W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// k, V9 l' h# q0 R+ J3 ?8 ~; H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) H7 P/ h' B# V" t0 R; \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% y( f$ m# l+ f, P** Set the serializers, Currently only one serializer is set as! C& y, Y: E& }
** transmitter and one serializer as receiver./ y4 K+ v9 P: R' H/ X0 U
*/
, Q6 L- ~3 u& O3 j, L3 _2 O: `$ EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) b1 m1 W) F" H6 a0 d* iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& _' @% x2 O; Z, u/ d9 J1 t+ l
** Configure the McASP pins , M. ]% L/ X+ [% ~
** Input - Frame Sync, Clock and Serializer Rx
* j! s( y7 j+ _& \8 m) I( m) E4 k** Output - Serializer Tx is connected to the input of the codec 0 e2 r( R8 w! y3 s2 a" [
*/
/ Q& e! |% d. k4 Q8 u: G$ N$ M0 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- T7 a6 V: R2 RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: _7 m4 ^ D" K; F. }) M7 D$ t/ NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: J" [7 J0 J) V& l
| MCASP_PIN_ACLKX' G8 E3 `3 ?3 z& [
| MCASP_PIN_AHCLKX/ u6 \( l" a# x4 ?* U- N% V% D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# X( S! B8 H" H! `- ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / j/ v7 G+ O6 E4 |5 a2 w( m
| MCASP_TX_CLKFAIL 7 a- S! m8 {( b1 T
| MCASP_TX_SYNCERROR: e4 w. e. P+ |- ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! E- z3 H0 ^3 [- i/ z' }% S/ u, h
| MCASP_RX_CLKFAIL! N v6 N, ~0 M8 l* t( [; J
| MCASP_RX_SYNCERROR
- M$ g# ^+ d) q0 v3 ^+ v| MCASP_RX_OVERRUN);) P7 _3 u3 W/ t! Y2 y
} static void I2SDataTxRxActivate(void)
: B9 G+ P8 ?4 s& {; _; G B{* B! ?( J& Z, k0 A& L# s
/* Start the clocks */
7 T. n! y3 k+ @+ t7 ?3 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 G& G1 S {* ^9 s4 j+ K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 Q% K, o s; n3 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 p! v$ k \. q1 p+ c
EDMA3_TRIG_MODE_EVENT);
+ I( t! Q+ q& u/ D0 \& F: W+ ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 t; S; T% U4 Q7 V& QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, P9 g. }7 \# e* C% B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. l+ w- n7 a& \% P8 _5 J1 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& L- k$ \4 ?: |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 k; w& A& h( s X6 Z- _* qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- i" M7 b% V/ v w, vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 S% h5 z. K2 H' i3 B9 ?! @} ! l+ t8 l; J# x, A1 A! V3 c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 I7 T( b% n7 H
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