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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 F1 p1 }1 v- ^; binput mcasp_ahclkx,
8 f9 T; x# v# w' Binput mcasp_aclkx," ~) y1 s9 h [: J
input axr0,
l0 k; ~% |8 o) }0 _; S P% x$ k' v* l5 }8 E" K6 q
output mcasp_afsr,
7 m/ k0 ] R7 @# zoutput mcasp_ahclkr,+ W* L% c; ?' w8 N4 T
output mcasp_aclkr,0 K5 A8 W) k6 B: w6 q% E
output axr1,1 ]1 Q' @" @ Y3 x) [
assign mcasp_afsr = mcasp_afsx;
& u1 ]! u' H5 r# N# s W$ Xassign mcasp_aclkr = mcasp_aclkx;" K- g9 Y2 ?$ ~9 `* I$ B7 d- g
assign mcasp_ahclkr = mcasp_ahclkx;9 D% N: }: y; N5 X* _' {- A
assign axr1 = axr0; 5 }, P! N* {: I( Z3 z; V1 v$ a* }
3 N& i7 `1 i- [" a/ l' _% B* @/ G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 @: [% z2 ?2 C. c+ E8 x+ _4 O
static void McASPI2SConfigure(void)1 f: U! h) y4 a0 K0 l2 l4 ~" o' P
{$ a) }9 Z* B- j' ?! C+ r; P/ A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) `$ y3 ]0 ]- _5 X! ~" y. c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 n! G0 j ~" s e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. S( r8 i" u; y4 M* |' H2 {5 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 O. e1 z1 m8 E# Q( @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. z$ x1 [7 R$ S1 q9 R4 S0 s+ nMCASP_RX_MODE_DMA);
/ w7 Z" ]( b+ h& j' c3 VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% \/ l: I1 n8 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" {9 Z0 l0 x: n \4 M& c1 aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 {# v' F/ U6 T' |4 ?6 OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- J/ y" u2 m" o, V9 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ _7 T: P( f) `4 P$ v, fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. |5 d3 M1 L* N! T% x# m$ UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) ?% w6 Q; O1 \; v( z# }' `, j$ VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& s) O* J" i3 w% L5 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* u4 G) w+ k' Q; E' s& |# ?6 \
0x00, 0xFF); /* configure the clock for transmitter */
8 O( y/ i5 ]/ YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
H! _6 ]# ]- ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: ~) u& ~$ `" f/ rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* }& p* g, a @2 l" }9 @; B4 ?0x00, 0xFF);7 F& A# t4 \2 q$ @" {' Q
1 ^: ~, {+ ]4 m/ Z
/* Enable synchronization of RX and TX sections */ 6 j7 b$ I9 |" x& M% S9 g& p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! \/ d8 L$ n. R/ U; W+ E- W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) P9 | X# t; V2 U- f. R# dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- b9 N I$ b6 i" Q- Z" _ S
** Set the serializers, Currently only one serializer is set as
: ?3 g1 X# I# u+ I9 B** transmitter and one serializer as receiver.5 R: @$ N+ h. n# R0 c+ Z
*/
: I7 f% D' F* z7 L% L/ FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" w2 _; s5 Z$ [* m5 b5 T% NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& B+ t( H% i* A, O& a** Configure the McASP pins
0 U: n; J3 d, L4 U** Input - Frame Sync, Clock and Serializer Rx
7 P6 X4 ?) e9 u d0 B# U& i+ f* [** Output - Serializer Tx is connected to the input of the codec
1 x3 Z! \. W, L; U3 H+ k*/
0 A2 t9 w( Y* Y* i5 z2 \! l! |- hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( }! b1 U* ?9 N; Z. J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 W b# ^' {1 c% Z5 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 X9 {+ E: x" f# m6 R* `' J: L- s
| MCASP_PIN_ACLKX% ?9 S$ n# z4 q0 Y9 z+ Y0 C
| MCASP_PIN_AHCLKX
% {& g1 U! |. P$ S7 ~) M' T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 _- E" q$ q2 D4 H3 P% _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 h2 u. m, L6 Y# h% J8 a% X% _( K
| MCASP_TX_CLKFAIL 1 o% f- x% |6 e H5 m4 ~& Z5 [
| MCASP_TX_SYNCERROR
" \+ F- s W% W+ ^$ x! b2 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : f8 i. y, E- \3 @: G' i
| MCASP_RX_CLKFAIL
4 P8 [- c( ?" Y( K+ d/ O; u| MCASP_RX_SYNCERROR 3 v/ ?2 N M% N, a3 t
| MCASP_RX_OVERRUN);
! o6 s' q+ }6 I3 n- }' C& r% |" |} static void I2SDataTxRxActivate(void); h$ Q) U; ~, f9 E4 V9 H) e; R) y$ ?
{+ P2 T, N- q3 }) D6 e2 M d+ U
/* Start the clocks */
, ^: o0 ]" N2 s7 M0 L% Q% UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ L; Z6 L/ b! F) ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 Q# b& l9 a, g- j' |6 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& b5 N, G7 J. y, K; u# m) }& EEDMA3_TRIG_MODE_EVENT);
7 k8 h: v- k0 o( vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : E# H3 s) ?: w V/ o7 ?8 |4 q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ I8 z9 d* @* [3 N! z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( L# ?+ I7 I/ U* O$ h% X. m }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 ?6 ~: l$ k) Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 R5 J. \9 m5 [# I! U2 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 X2 ?& j `9 x3 H6 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); v( d! O. e/ {% j
}
. b% `# c+ ^1 b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # F) W8 b9 z& |- w) R V+ n+ {
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