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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 H, r& F8 Q2 kinput mcasp_ahclkx,8 H9 |3 I5 N% A" T
input mcasp_aclkx,
) e; t; t6 ]/ J+ y! Winput axr0,
5 e4 Z3 q* ~5 C1 y6 i1 P2 d, {% E9 j/ Y& r/ }4 w" k. l5 b% a
output mcasp_afsr,; F8 N, I) w* C) m* E
output mcasp_ahclkr,: z5 n& g4 {5 F, T+ W" y, j M
output mcasp_aclkr,
7 O# c" z9 _ a a# I# E8 Xoutput axr1,- j4 t& q2 y- _0 h+ N* W/ S* C
assign mcasp_afsr = mcasp_afsx;% l1 E5 B3 H+ {) J+ K G
assign mcasp_aclkr = mcasp_aclkx;8 \- C4 n6 F: h# i% n8 b
assign mcasp_ahclkr = mcasp_ahclkx;
q2 r8 I! ~% @! P# V1 R# j- Yassign axr1 = axr0; , O2 u% q3 k9 P9 e" [
% ?3 d1 ?( v' m$ Z; c, s" {( Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) f; A) Z# u& e6 X1 _4 ]
static void McASPI2SConfigure(void)! O- G/ g6 q$ s1 n7 s q2 w& T8 B
{2 d; t1 u8 i2 F6 K; Z" o: K& z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 l5 e1 R" W/ x C1 _5 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* ~- o& H4 ?1 m8 _' J$ u. Z( [8 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 f0 ~+ j! z; O$ k' b$ @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 p" E6 m' h* N, U( B& R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& e: {1 @$ P) f% X) v- m% oMCASP_RX_MODE_DMA);% F- y7 W* R2 \6 r* C5 `* f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) G4 I' C$ M1 ]' }) ], t. tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, L) S5 C* |' cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; d: e: p# F5 C$ t- O: t/ K7 N; T uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- b8 H! A, T* n/ q m9 a+ @9 [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( R1 D. k- `4 G' d; NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ \$ }( p! I- z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ P# E" Q3 d. \# ]1 h2 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % Y6 C3 ]" S, K+ u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% ~3 q3 V9 I6 u( e$ s$ S
0x00, 0xFF); /* configure the clock for transmitter */6 U4 {$ ? u+ [+ |/ l7 n) d, B; r8 q% a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 v: _6 _" ]! S8 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 u: p5 l% Y! S! T* Y }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- w: O0 v; o, j& _ A& ?* M {
0x00, 0xFF); J$ B+ S8 g( y
; W( }8 x- t% \# q& T! V
/* Enable synchronization of RX and TX sections */ " w! ~* U# D0 F0 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" M! Z. `( p/ y. _4 E8 Z2 W4 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. T) u+ O0 g3 V; B! ]1 \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( V z' A% W* H
** Set the serializers, Currently only one serializer is set as# G" V8 W h7 U+ B: |3 G
** transmitter and one serializer as receiver.6 B( `" @- c/ j8 \' Y; i
*/& p# {- O- K, Z9 o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! t3 |* Z. w6 {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: e( C% u6 y( i! j- A** Configure the McASP pins
; K3 x: Q5 `1 m% M** Input - Frame Sync, Clock and Serializer Rx2 v: ^3 x! z. @7 V+ f# I5 ^
** Output - Serializer Tx is connected to the input of the codec 1 a; t4 G. P5 L
*/) P9 D- i' y: q# s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) T" x, y1 q# c! Y0 f* M' z2 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 B, `9 {8 H5 P0 j [/ I( KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% `. N$ Y3 W/ J4 V" s3 m1 `
| MCASP_PIN_ACLKX
2 q. c& F0 X' ^3 E2 i' O$ ~| MCASP_PIN_AHCLKX) {- D5 j: c1 x8 N3 @) A& F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( x; k% |# D: r9 y0 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 {5 p' P1 z6 b! m- t- d| MCASP_TX_CLKFAIL % g4 b# s% l: U" A
| MCASP_TX_SYNCERROR2 @. u$ f+ n6 M& L, r2 w: {2 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % O2 L$ M- V+ H! Y( I
| MCASP_RX_CLKFAIL
1 Z+ k; n$ M- F( r- K: r3 c| MCASP_RX_SYNCERROR % Y% ]" D0 n7 Y
| MCASP_RX_OVERRUN);
8 J% a6 u) g% X8 ?# h. T} static void I2SDataTxRxActivate(void)# I; p3 ^' h; W
{
Z! R; k D" U4 `4 _" ~7 I( e/* Start the clocks */ N; R3 d) R1 o. P) j j4 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' l) Q% [1 N; K" Y3 x+ ~- y( v$ YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 S; K: T. s U6 b6 k. `; T) nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' t0 i2 R, P+ Y" b: |9 a H# Q5 vEDMA3_TRIG_MODE_EVENT);
+ A F) s) F! K; T' v7 \ W5 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& R9 P$ g2 F2 a: t0 K" B; QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 a8 B4 E: M1 s& b. L. D6 dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% y! O' x( j. P4 XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 {- R4 ?" r+ O vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 [0 v8 w9 V' F$ D+ S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 y# J. {/ @. r8 x& C9 n* ^3 t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 F: n! z* J8 i: z4 q0 {% m} 7 O5 s- o3 p/ D' V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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