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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% q6 ?: Q9 y" b( ]# _- O
input mcasp_ahclkx,
9 C8 G8 w0 I: h1 Z' Y$ H ^/ {' oinput mcasp_aclkx,; y7 ~& e( x* A# W! d5 d R% D
input axr0,
, o W' K% Q6 b4 j! s* j. y2 a$ }$ d) T7 j8 U& h. f* H! J
output mcasp_afsr,/ q% C: a: K+ Y1 \7 \2 r
output mcasp_ahclkr,
! V. C, @6 s% K$ G( O+ S4 j. C/ o qoutput mcasp_aclkr,4 H4 ^/ V' V- b* X/ D
output axr1,9 G- v' C+ J S. W) T$ X
assign mcasp_afsr = mcasp_afsx;% I: {- J, D' k( d' ]" m
assign mcasp_aclkr = mcasp_aclkx;
) A. r& {# N, i% hassign mcasp_ahclkr = mcasp_ahclkx;
; r$ g: F1 g" i' ~4 _; ]8 Massign axr1 = axr0;
2 K2 [- I) R# }, h2 m+ Q/ ~
7 ?& t) A# v1 y" p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 U" [2 A& Z+ `; Z8 h* `8 Tstatic void McASPI2SConfigure(void): l, W$ S$ n( g3 Z) |# L
{4 \5 {3 U( ]5 [) q6 Z4 d* j
McASPRxReset(SOC_MCASP_0_CTRL_REGS); Y+ f; H& M2 c; s$ b0 c, R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ m+ f' j! y7 y4 l& w- U/ [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) ^) O( Z( t; `" E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 {5 O |9 n+ |' O: }/ sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, K9 e4 \8 Z! y$ ^ |3 a$ Q8 X1 d0 Z
MCASP_RX_MODE_DMA);7 C( f8 o; i R$ q8 g$ q8 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ e, M l3 V# mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ b1 ?; A: ?) X* v! [" c9 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ B# \/ ?$ l& M' NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. E6 u$ a+ R8 _6 O6 K# s% K0 s) f8 {; PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 z6 o9 a2 S& kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ Q' Y [% c) F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
I0 Q3 s4 i7 C( a% GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 `; i. p l1 w j* ?3 M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) k* m% z) ]4 b( h' _1 ]0x00, 0xFF); /* configure the clock for transmitter */
. i5 E1 {/ k, S2 i6 y) xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- X0 `1 L0 Q( @0 b$ }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * a7 ?; K j: R, F' c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 q2 @+ J0 C* X0x00, 0xFF);: t u! l( i. }/ _
. \* j- b0 Q# ~! j$ D6 z7 B0 }
/* Enable synchronization of RX and TX sections */ 9 B! I* J1 H! X( O5 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 }& L# l' I9 U" \" `$ c' ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. @( M3 o# p- ~9 R. q& L8 ?$ q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" p$ O- W0 Y/ _& k4 B
** Set the serializers, Currently only one serializer is set as
0 X U* X7 y: C8 _- z e3 R& j** transmitter and one serializer as receiver.0 \1 ] J( F) B
*/( B9 m/ | @. i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 \5 Z! B9 X! r9 V' p7 I& \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 f1 s+ e( ^/ `
** Configure the McASP pins
: E$ c- L& u* y7 d- b$ C** Input - Frame Sync, Clock and Serializer Rx9 e% E* p- @2 {2 ]: F
** Output - Serializer Tx is connected to the input of the codec 4 H7 _7 f: G. B% [$ K
*/
- x: t' I9 T7 c5 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' I! e# }; U- h! l5 iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ Q& Y$ o* a1 o& ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' R, l1 `+ d1 l Q$ V/ |- @& S
| MCASP_PIN_ACLKX
+ Q7 p* q6 l- y6 y3 d9 E" e| MCASP_PIN_AHCLKX9 a' ^" X; p6 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 `; s" g& A! F; E6 SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 n; @% N; G( l
| MCASP_TX_CLKFAIL . h3 B: q3 R% i* \# u0 L
| MCASP_TX_SYNCERROR
) k* {+ S6 `0 p) n- g2 }5 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' D" w, ?% o8 H- o# S$ T$ Q/ o| MCASP_RX_CLKFAIL& K1 q0 e$ f5 I
| MCASP_RX_SYNCERROR 3 z2 t% I1 J, F! C% @1 K
| MCASP_RX_OVERRUN);
2 \4 S$ H3 K3 Y' v* Y7 q4 b( P: q' \} static void I2SDataTxRxActivate(void)4 {% ^( p9 w3 p! b* _2 S
{
, v( g7 z. M* V: S/* Start the clocks */
# l6 l1 k# P8 K! oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ D# z/ e6 @0 k; x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 k1 n: X+ H1 n9 w+ FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 ^9 g/ ]6 v8 ^0 |. C
EDMA3_TRIG_MODE_EVENT);7 B5 F! M: g* @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, A( \' @; t1 h! i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ c* D8 Q8 V% L( A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' L- K0 d& u) Y( i. w' Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 ]0 i! H9 J- @$ u/ rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* X% ]* [( X$ Y! k" O* W" E! p8 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* a* v; z# Z" v- B# e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 \& F: y- U8 H: f8 |
}
# O1 c& `- e/ q! d. X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 \* L& x+ I5 N& s
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