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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# z6 H! ?# l# e% v6 Cinput mcasp_ahclkx,* t2 o% L0 N, E# _
input mcasp_aclkx,3 m* P# J: a2 u) U" s8 n+ }2 L: q
input axr0,
0 ], u0 ?: x# @+ L2 a4 e$ }. p
output mcasp_afsr,, N& V* N8 q) G& `2 d
output mcasp_ahclkr,
# }' Z) `: r9 R$ d: [% b& s. c! uoutput mcasp_aclkr,
8 W0 Q" A4 d7 N( p0 Koutput axr1,5 V8 i. o5 d: G8 L% ~
assign mcasp_afsr = mcasp_afsx;
' T! b, ?+ G% c' x- _7 Cassign mcasp_aclkr = mcasp_aclkx;, Z; G, A" H/ C0 ~. O2 S
assign mcasp_ahclkr = mcasp_ahclkx;) g0 |2 R9 u" C
assign axr1 = axr0;
0 K% S2 ?2 [# _8 H2 r4 x2 h% X# ]6 [, v/ q/ S s& T0 y. L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
F3 M. q" x1 Y, H O& V& Xstatic void McASPI2SConfigure(void)5 g7 L8 ~9 w) }4 ?
{
& n/ h: s$ ?1 q- aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 e/ A: L9 s8 O" BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* x+ m2 g) a) q; S2 O% `6 ^* `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! o0 D- s; O7 e$ N! p) {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ u( b* P. t3 u4 y6 k8 u+ jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ [' i: C3 V: z9 y0 M1 a3 a( rMCASP_RX_MODE_DMA);4 m( |$ s3 t8 l( \5 S3 O- A& r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ D( C; z! X2 R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 S8 l9 ]0 ^% i/ ]# F+ zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 V- Z+ h/ ?6 B _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 m: Q! { g7 s; `4 Z# v: _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 H/ `) T: Q( B, n7 \# R$ WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ a" k4 @; l1 h8 S, r1 J8 \- OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 }+ Y; T" n1 ^- P" B( @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! D) K8 f% L# } WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 a0 F- S& R5 G( }- C3 C+ Y$ W
0x00, 0xFF); /* configure the clock for transmitter */
; V& e) ]3 _7 P" W3 R* tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( y. F+ I9 d# o, QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, C0 Z$ B# M2 \* P3 j6 w9 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 j& h; N. o* C0 h9 L% e3 p) _0x00, 0xFF);0 U7 [$ N3 w, P9 N
' M9 u. X# Q3 D, b: z
/* Enable synchronization of RX and TX sections */
4 J' E I; k n! F5 v' B% vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" V: e; @: z B! A% Q1 d7 q1 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 z$ d" t: e) m6 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 e, a7 X1 D b2 Y$ N) V
** Set the serializers, Currently only one serializer is set as
& z- _* o) A9 {; V** transmitter and one serializer as receiver.
# m' z( V7 m" M }*/
* f. \& B( I6 M T0 W7 d1 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 I& ]% A! n* M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ [7 o$ m! _; s$ ]) ?1 K' N
** Configure the McASP pins 3 ~: Z. g* h" i* Y9 B) @3 M& M9 q/ }; ?
** Input - Frame Sync, Clock and Serializer Rx$ x" E( [, R# k# N* h( q! e
** Output - Serializer Tx is connected to the input of the codec
7 @" q+ X& {1 w l*/
3 v( o5 R8 i# X Z& VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, u' n$ r/ e/ d% |% _/ X& z3 B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 M& q/ N2 {0 L$ u1 q( dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ E( j- z3 K, w6 i+ W3 Y
| MCASP_PIN_ACLKX
7 g% L0 x1 f; ^/ V% i Y| MCASP_PIN_AHCLKX2 Q9 k8 L) k6 J" W0 G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 y+ r% B- @% ]2 W) k1 `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 a" q( M+ p/ K( ~2 T0 R| MCASP_TX_CLKFAIL
* j/ h. r+ i8 k1 l3 }9 a4 w8 Y$ Q7 `| MCASP_TX_SYNCERROR" L2 R0 q# F4 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 q/ \# g* x; p' `: {| MCASP_RX_CLKFAIL; a# @( [. ^0 i( K* F
| MCASP_RX_SYNCERROR
2 \; h% h* F) j1 q$ N7 n9 Y7 y5 ?| MCASP_RX_OVERRUN);
0 @* V `) E, _} static void I2SDataTxRxActivate(void)
# V5 c4 ?7 j. G5 c6 `# |) \6 w# }7 Y{ l |7 M3 @6 X+ F
/* Start the clocks */. w% a. a0 l9 _* v! L2 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* B/ m$ g v* F# _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, `8 I @0 W. ] O- u: m( a \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 V% F' r4 E9 a9 `1 r! r
EDMA3_TRIG_MODE_EVENT);6 V4 `- x( ]$ P# a" N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 S( z9 u4 W& g' \* t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ ~3 c U6 l, p. D3 q" W8 E8 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. p+ S/ t& p& C; g% u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) t( t8 h* P7 X9 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* S! h: S, V3 z. T! j2 k9 Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 }2 A( L1 C% c/ E% _: ~5 a- L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' [. n# W0 h$ N5 j. I}
" X, ~0 ^0 J) {9 h5 O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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