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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," X* l7 G% C2 g1 Z. q
input mcasp_ahclkx,
, [' V* K; S) z9 D9 ]5 uinput mcasp_aclkx,
- ], X1 o( R9 g& k! j8 X) O3 I+ ]* rinput axr0,
8 B) G% K$ s5 V4 o& `, o( p( r6 i' {* k( k- ?0 e. t- T, B
output mcasp_afsr,
' g# T: F# _1 woutput mcasp_ahclkr,
/ z/ _2 k# y1 c# l M* Z3 c! n$ |output mcasp_aclkr,5 A l! { T6 @. F8 |) y
output axr1,
- E4 J. z8 R: ]" B assign mcasp_afsr = mcasp_afsx;
! y3 I2 \6 l; x$ }; Aassign mcasp_aclkr = mcasp_aclkx;9 @; V2 b, s' c. K/ I- @
assign mcasp_ahclkr = mcasp_ahclkx;( p4 F$ {8 s2 D- r
assign axr1 = axr0;
+ }3 ]1 p# _& X% R8 h
X. b2 w! G3 ~" m8 G' n6 B+ c3 u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 I( P* F# m6 d! M" G$ ~. _( q8 D
static void McASPI2SConfigure(void)( G, h2 ` k- l) o# A0 ^! E
{
6 x) n3 t4 F* _# k/ E$ X% Y7 B7 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ p, a0 H# C$ o3 n7 x. N5 d6 |5 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) X' e. d" [$ G# d% v' dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 N0 M M" Q; K; A# {. i, ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, r1 ?0 F/ f. @( B- B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 {- `7 o: v- u+ u- g
MCASP_RX_MODE_DMA);+ X; J5 `/ a6 `9 q/ Z1 I9 E, ]7 S" ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ J! _( ^2 i2 B- H! W, O6 F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- D9 E6 o1 m# K$ M( w! W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 v* D, z: K% g( vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ ]* e0 X3 k0 z C" q5 @3 m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 @9 K; G8 d( @3 p" _6 \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 O+ x% l( _ {: h5 c: r) `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( g* ~5 Z+ v) B8 i6 T& v& \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! U* f' a2 f$ h2 c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ q+ d6 M3 F4 a8 ?, C3 ~( I( ~
0x00, 0xFF); /* configure the clock for transmitter */1 p1 X9 `4 {0 V1 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) Z2 h2 E: c! S& D/ x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , G" W( H/ F/ u" ]* i4 w$ L( c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 w+ K O- C, k% g
0x00, 0xFF); T# @9 e$ Z* I& r/ Z" g8 M6 R
U2 R7 k6 q9 ?0 \
/* Enable synchronization of RX and TX sections */
" M' J# b' z& d- AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 |, n5 z/ e/ u- e( ^+ D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 F. e6 l- d7 F+ a7 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 [6 M- K) f9 V/ r3 r3 p. X# J** Set the serializers, Currently only one serializer is set as. R4 `- d+ r* n( ]! X& o
** transmitter and one serializer as receiver.% t( }% t% x" G6 n* f, A
*/1 Q$ U% ^' |7 \2 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) C- A: `4 z( y4 @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* Z7 D" t5 {% \5 \! s4 q
** Configure the McASP pins
5 W# @0 S* T& p$ N, K** Input - Frame Sync, Clock and Serializer Rx- y; m t$ i% I6 q; D3 g' c
** Output - Serializer Tx is connected to the input of the codec
" Z# X2 {9 f4 Z# h) Z*/
A: a! R6 `) K4 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. P7 t$ _$ t. Z! _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 e4 ]1 z8 Y+ K8 F; E. c6 k9 G& HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: ]& G, v( V2 E( P
| MCASP_PIN_ACLKX) b4 c) k" l' _" q& j
| MCASP_PIN_AHCLKX
, s& k- y! [, Q/ a1 x5 w* t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! k9 e. J) ~% u3 iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 w" w- F) t+ h3 b9 W2 O; F( G
| MCASP_TX_CLKFAIL
0 E& f& H& c; _) ^9 E& ~| MCASP_TX_SYNCERROR. p& P5 D/ i4 V/ E- T% V* L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 ^# W, K5 P% I' G7 d
| MCASP_RX_CLKFAIL
. x9 H0 i+ U6 Y2 H: [ w9 M# q| MCASP_RX_SYNCERROR
6 G) v+ ^! _* y$ Z6 j| MCASP_RX_OVERRUN);
) L" c5 L4 {( I3 u} static void I2SDataTxRxActivate(void)
. }8 X% k- r6 a0 [' y{
* B. h5 x( G# M# }/ a3 \! C: r/* Start the clocks */) R1 T+ G4 R5 @2 h" o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ _) j" \6 N. W2 ]" B0 O- b* V7 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' Q7 k8 n9 k2 y2 p( ~0 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ @1 E' ^- l9 q
EDMA3_TRIG_MODE_EVENT);3 ?( S1 O* O% U$ u7 o+ X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" j6 N& y" x8 f4 O. `9 `( X3 C4 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 l- o0 F* C4 ^% x) q$ M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) E( \: B' ?& S' bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& G+ x+ q$ `( ?0 C8 ~) lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( t) {7 V' ^) [% zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% p7 { y; r1 ]0 @& K1 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ l& A! ?7 ]+ d' n} ! F* K& k; [6 B( a( q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 j; {/ `8 h' w& d8 a5 u
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