MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
- d. }+ K! g* d2 Einput mcasp_ahclkx,
* C8 Q9 {5 s6 I' G# t8 [input mcasp_aclkx,
input axr0,
. N0 d$ |# W9 l9 Z
0 x# y2 J2 K% C# a+ qoutput mcasp_afsr,
% `: s! ?. c! d- I0 M' d, k  @' voutput mcasp_ahclkr,
# _; a; z( t# z0 n1 Routput mcasp_aclkr,
output axr1,
. F  t4 \* o! X# c- S7 w# t5 x

assign mcasp_afsr = mcasp_afsx;
% d; ]* j8 D  t6 G. Jassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

2 ^8 i) ~- ^4 J# q% g# P3 Q
+ }, U" \% L' ^; m5 @* S( {/ a

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

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static void McASPI2SConfigure(void)
. m' {, h/ l* s{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# ?9 k# K7 D0 T. v+ ^8 j# yMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 }# ~! v! d+ MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# c, L1 s+ @9 G0 z7 L- W$ c5 l& rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, w' \4 ?) }9 x3 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
' U" N' O" P9 W7 q% Z# g4 w* G9 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 O! [  m4 E' ~& ~, y* ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 e4 J1 h+ m! ^6 v4 x0x00, 0xFF);

/* configure the clock for transmitter */
4 z% [0 T) d7 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; a" q" a1 M  Z' sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

: Q" [- n3 k( a- M/* Enable synchronization of RX and TX sections */
' g/ o6 C! \+ m( ]+ a$ ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
" J7 J: R2 v% S9 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( b' S& I# A7 B  S+ A7 V0 vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
! e% A( @+ S4 v! k6 J** Set the serializers, Currently only one serializer is set as
8 D1 Y: m0 H: l; f- b' k% e" e** transmitter and one serializer as receiver.
" G7 L" F* W0 J*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ ^/ F+ D: N0 W% E& L8 C. DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
4 e% x% y/ K+ r** Output - Serializer Tx is connected to the input of the codec
*/
" \: s2 i1 C# f+ }* b0 l. TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
7 d) K+ {) H# T6 G, n8 c$ GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
0 f9 C2 R, k0 _( {' |8 E| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) _5 V/ n$ w# w/ P| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
0 `& W9 q& f) z; e# n* L| MCASP_RX_OVERRUN);
* X) ^9 f. p' a9 Z, \9 |) s* b}

static void I2SDataTxRxActivate(void)
, @7 n+ `  ^: W) U5 @{
/* Start the clocks */
) k/ `8 q- y! \4 I; VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 ^( ]* H, {; y/ d* G4 GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
) G5 K* {4 z3 ~4 W: WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
; M% N  o8 f5 Q. H, G8 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% j6 |& u/ V+ z+ ~: \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% s, M6 t, {# OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

  l1 s' d& h3 X* w. k5 K# O. x

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

' |" b7 u- @* k) w: k