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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: s# p* A a, ], l) r: V
input mcasp_ahclkx,1 Y+ K1 ]) O! w8 t2 `+ C/ _
input mcasp_aclkx,
. Y2 d! J' Q+ Q* b0 ]input axr0,
9 x! S* @% Z9 c7 {; `8 x; i8 x
output mcasp_afsr,3 ]" ~3 G. s' K' C' D5 f% E
output mcasp_ahclkr, p8 Q" | P! H9 b/ e% g s
output mcasp_aclkr,8 p+ k6 j) j/ _8 Z1 T9 n+ q
output axr1,
- I5 c" i+ W: _ {: u assign mcasp_afsr = mcasp_afsx; X5 j6 _: d$ [) F- p: r1 [( m
assign mcasp_aclkr = mcasp_aclkx;: [) s6 s5 k! P/ z% ` t
assign mcasp_ahclkr = mcasp_ahclkx;: W$ A0 ^' l Y( t# X
assign axr1 = axr0; 9 Z- F1 a6 i2 ~9 V' f6 v9 Z/ C1 y/ W
' b$ h# o) ~# z: [9 G( W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 R1 B% Z' ^: \/ b1 j3 H$ hstatic void McASPI2SConfigure(void)
7 f. o# Z7 [* o7 X0 B{
% c5 J7 [* W3 x6 aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 [- S" |7 \6 N2 t& z2 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 t4 p4 ~: ?% R5 D3 ~2 O! \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 X+ O6 Q5 {" R8 ?& K8 D2 t1 r% {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 j2 _3 z: u# @/ M% @7 }) r7 e4 E3 RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! j V5 P7 |/ a6 c6 v* i7 m( F0 yMCASP_RX_MODE_DMA);; o4 F' L' j) j0 ^$ m$ _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( j% @6 y5 Y# }3 V' P$ Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' _. N3 y$ s5 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! k0 R9 J* u I7 P6 i$ L! E/ P8 L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! H$ q' o& f% U2 V. |* ~# `0 s* ^& {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( F- n7 p B0 O4 KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- T4 A# g [, E& |" G& t/ O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ R) y% [ I" ~! P/ pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 u5 ]5 k: m. m+ S! nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ W2 ]* n) X. [) B0 ]" y, _
0x00, 0xFF); /* configure the clock for transmitter */
! k7 w0 i, Y8 }8 c& @% ?6 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- U0 W, b) |3 ~4 C, v( t* PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 y7 H3 \9 Z, L' z2 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 f( u( b/ V( Z Y0 j0x00, 0xFF);
: ^: T9 N. \% U& B
6 L: s% ?* Z$ B* a+ A/ `$ P/* Enable synchronization of RX and TX sections */ * m6 i, {6 D+ V5 t: _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% o; G4 x i' ~( S' MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' V# y) d5 G( z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- u/ ?2 W; k- O z+ i7 l
** Set the serializers, Currently only one serializer is set as
- x; ^5 t o) `( o# w** transmitter and one serializer as receiver.! l/ q5 U5 w) y: C2 K# _
*/. x9 ]1 F* i/ Y" X" u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) n1 Z1 V3 a6 s) d, ]& N; mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( W2 F+ R4 M; l0 \# O
** Configure the McASP pins
7 A* w$ P: X3 S+ G: L** Input - Frame Sync, Clock and Serializer Rx* U6 k O n& Z q* ~6 R
** Output - Serializer Tx is connected to the input of the codec 0 U& {: {$ n( q! G% @, l
*/
' O2 Q' f. n/ p+ d S: S1 z2 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' m* X5 y# W+ M1 O- W, G8 z; @7 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 q/ N) U R- L: }: u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ B3 S `" v+ L$ h9 C
| MCASP_PIN_ACLKX! \, t4 m6 ^7 W; o G5 c
| MCASP_PIN_AHCLKX
! {/ K1 E8 j" q0 [: j' m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' e$ A3 m( e, Q$ G, J" O6 Y# W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ C. n( G+ W4 O, f
| MCASP_TX_CLKFAIL ) m; @8 s6 j- t! V: \
| MCASP_TX_SYNCERROR3 ?/ z8 U* W* f e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# p/ c7 a, a0 Q* s, m4 T| MCASP_RX_CLKFAIL
7 m- @9 R7 y4 X! v| MCASP_RX_SYNCERROR 9 j. c. B" P9 v# }+ |3 {7 f7 B1 B8 k
| MCASP_RX_OVERRUN);9 _2 M; F9 j. I) V) N9 n/ t1 B
} static void I2SDataTxRxActivate(void), L0 X. c2 _9 h! O0 a) B
{* R# v* o; }. k, r
/* Start the clocks */
' A. T0 d4 K$ w" O2 L4 z% sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 r, N+ }1 I. h# s; O$ aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& C* M* {. U9 K/ ^& B& G+ T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& Z; W5 h1 D; p$ H& u
EDMA3_TRIG_MODE_EVENT);
4 v: n9 o( q0 A+ o- r" @0 f+ zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 M. g" L9 s. K rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 ~% J$ [7 p5 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 h# c2 I5 k* n' q! H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" G- H% V7 U( z+ }9 [+ \! n4 qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) J" ?3 x3 L# S6 Y1 l0 nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( m, O9 c" D. V9 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* M: `& v* L: s. P) N, V% [}
! T1 \) [( I! r" A# d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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