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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 z8 z0 w8 B7 j" q6 {8 [input mcasp_ahclkx,2 h7 A; n g$ Q7 q' R! K/ W
input mcasp_aclkx,5 ?; ]/ [. G" d% d
input axr0,
: n& W+ g1 @- S
3 Z/ @: K0 Z# d; Loutput mcasp_afsr,
0 D C1 M. f0 g/ Loutput mcasp_ahclkr,1 l7 ]3 @+ i- n8 l* h. Q: U
output mcasp_aclkr,
5 @* _7 B& d. V7 Goutput axr1,- _4 p5 ~9 o! N
assign mcasp_afsr = mcasp_afsx;( x {7 ?/ m5 a4 K: S' R1 }. i- ~
assign mcasp_aclkr = mcasp_aclkx;
$ {. M" q% S, ^& i7 I5 eassign mcasp_ahclkr = mcasp_ahclkx;' t. s, R+ w) c, C8 |7 v* h) P% Z
assign axr1 = axr0; 6 }' P. V2 y' x" [ x
J/ K# s; }9 ]7 C0 _; r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 `% |5 Y5 o' v- J' _static void McASPI2SConfigure(void)6 {( I6 Z) B0 I O% {. D, |% C/ J
{
1 c9 Z2 v/ [% T X1 T1 l8 FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( w' V- x2 E9 `% a- UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 z) u3 C h) {" B, o, PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ M( t1 V; ?+ [! Y$ U: u7 x# w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 D7 M- |, y- e* O& s! VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. x" R, z' e; x! Q! N% bMCASP_RX_MODE_DMA);% E3 j# h& [8 N1 Y4 \7 h$ W- ~# J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' N$ Y H; P8 d$ RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 W' V# z5 p5 V% h) m& e1 {" e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , |1 C0 {% P1 t' Y8 C- j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& h3 P8 @! t. B5 @2 J5 X8 s# x$ C0 E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, U% ]/ S/ `$ I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 m0 r6 _: t* v& O$ ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- Y0 c: x, o" s9 }& Y/ S; EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 V8 H4 \/ w! RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ _/ |; t8 e0 f n
0x00, 0xFF); /* configure the clock for transmitter */
4 e- W3 A# f1 a5 F: w( R2 ]' [1 ~( ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" ?* ]8 c- F2 n) V" l) `" }5 a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* M4 `; Y( E: uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 k! Y: o) S# X5 Y. E0 i
0x00, 0xFF); G9 Y8 _ f8 v7 }/ L+ S4 B
% D- @% y9 x5 h" s# d5 V/* Enable synchronization of RX and TX sections */
$ |/ z' B5 q# z, c9 VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. O! R' F- e4 d& `1 m1 J! u; L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 _# k' ]) C4 e0 b6 s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( r- a7 e' F( z a9 W
** Set the serializers, Currently only one serializer is set as
6 \# ?+ L* x @2 i$ x# k** transmitter and one serializer as receiver.
- V; ~% A' n5 j7 N3 S# i*/3 a4 C2 k5 K/ r; i+ Q% W2 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 s) p$ v0 I- g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" M6 u6 p/ ]+ {
** Configure the McASP pins 2 Q1 J$ A ?3 I7 ]$ n- ^$ p
** Input - Frame Sync, Clock and Serializer Rx
1 x; r9 x7 l! c, t** Output - Serializer Tx is connected to the input of the codec ( j2 F8 [. t9 g9 K
*/- X9 Z: T6 X& [* X! f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! j' ~2 _/ z) Q, ]' q' e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 O$ w5 J) D9 n# R$ s2 sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% A4 F8 Z8 S1 ^8 m* }
| MCASP_PIN_ACLKX
2 l; Y, J5 e1 E; f O| MCASP_PIN_AHCLKX+ H8 X, S/ {5 a! b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: i/ N9 {# h) _/ Q, q3 L, r7 d0 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( ^5 N& G3 E4 b# m+ H; q! G( M* }| MCASP_TX_CLKFAIL 2 p9 x0 A$ ]5 s" F
| MCASP_TX_SYNCERROR
2 R& B: m2 z: Q5 c: l+ k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 G# v( ~; ^7 Z: n9 e
| MCASP_RX_CLKFAIL
/ W: _0 ?! b6 p! B. i| MCASP_RX_SYNCERROR
# _3 P9 z$ n# Z| MCASP_RX_OVERRUN);/ ]' o( u) q8 E: M: Q9 f
} static void I2SDataTxRxActivate(void)
' X) L6 z9 `2 }! A- s5 i! S{
5 m6 R7 t1 \3 {! G M/* Start the clocks *// \, @/ `- G8 n* L6 b: M5 A+ j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 B( a6 |3 U, Y6 U, h- O& EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' ]# o+ n. q5 y+ xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 z. }% V9 Z$ N) n; [
EDMA3_TRIG_MODE_EVENT);6 t- C0 \3 [/ |6 D9 P; ~4 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! [8 s) A$ O2 b" `3 z A2 r" g1 P6 p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 u1 ?. O: _; [, S" ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# x* T2 G- N7 d4 T6 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* C: z9 K) N5 T# R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( }& H8 |6 y, b$ N9 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, I, M* G2 |2 R& j8 gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, h/ _3 E5 r( i0 T* B9 a: o} 8 G* B [3 |0 y1 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. M; ~. U' R0 J
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