|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 y4 B1 Q3 y# N4 z& Iinput mcasp_ahclkx,
; V; S, k' [5 z0 f6 dinput mcasp_aclkx,
( H# X! V+ [( Y ]input axr0,6 C" B$ p& l2 J
) c' P+ f Y, coutput mcasp_afsr,
5 m% D7 j; M* [" Z9 e% Zoutput mcasp_ahclkr,
: N0 n% b7 P0 f9 A1 B8 poutput mcasp_aclkr,$ j: ~' @# Q2 E) O% w( d; H2 @
output axr1,
& V! v" W# C1 g assign mcasp_afsr = mcasp_afsx;
' \& Z% o6 n; r M. M3 M7 nassign mcasp_aclkr = mcasp_aclkx;% l9 c. L7 Q8 U2 m6 S
assign mcasp_ahclkr = mcasp_ahclkx;: U0 B) Y! \$ ]" Z
assign axr1 = axr0;
- ~& I, p3 Y2 a, o/ t$ r6 `7 w) F5 ~" C+ |4 ?0 \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . `, C5 K- a O2 H. Z% {
static void McASPI2SConfigure(void)
) O+ {( c C, e/ @* V o& {{: q; j% ~* g1 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! u m" a+ S2 X6 x" i C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( G5 p1 S" r/ ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) f h7 `+ G) i5 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 P5 v& t5 j$ u$ a4 v e1 j- iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' Y- p/ p' m, E0 Z
MCASP_RX_MODE_DMA);
* l/ a' S |8 qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, i. Z8 X9 h9 j8 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 x0 Y; ^, a4 g# ^8 S' J' k3 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( a# u2 I, U1 `6 N, m1 F; q5 u: P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* ~) d+ v* _; x! Y! Y0 p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) s9 Y' D8 ~/ }4 g5 sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 M& j. k/ w* t0 \) A* M" L) t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 b/ V3 g/ W+ O" a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + V. m4 f& E/ V" o4 W4 m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: Z2 J2 d! n5 {- ~: M0x00, 0xFF); /* configure the clock for transmitter */: t" r' Z5 D9 i+ B) Q6 k% \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ t) w0 w9 K# h5 X6 l: [+ GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + j0 c: W; @. V/ n' t8 k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 B" J0 Q9 n+ N! D* ~! R, i0x00, 0xFF);2 m, C6 Y2 S0 E& h' O: T. F
0 P( C' k! F8 A9 F2 s7 s$ ~
/* Enable synchronization of RX and TX sections */
( m9 l0 @' c2 J; |; MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; B' V/ x- m7 ^1 G4 V' r. U7 gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 i# P q- {4 Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 w' y4 \; v! z6 U+ F
** Set the serializers, Currently only one serializer is set as: t$ w4 s# G/ [
** transmitter and one serializer as receiver.
' L: G8 g7 l4 b: F. B6 q* i*/
! X3 B! X/ L ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 ^$ b7 V8 r& i* M& DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 p" c+ T3 D' w6 H# ~% a: {
** Configure the McASP pins 6 q% N b0 u; x
** Input - Frame Sync, Clock and Serializer Rx
% F1 |9 ]. u5 n& N2 @; s3 C: |9 X** Output - Serializer Tx is connected to the input of the codec
% T) k6 O3 S# i1 W6 O*/
+ g0 x; W1 N6 x6 ~: y8 _$ O, }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
l* P6 `( `5 V+ I* l \; Q# MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); v0 A5 ] f. e/ l+ | \$ J/ p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* Q- g; k& p% W2 {) u( `$ ^| MCASP_PIN_ACLKX
% n4 E2 u0 O1 S) H3 N5 P| MCASP_PIN_AHCLKX& S/ d. I8 q) e/ U2 \) K! N6 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// A7 z0 |& L$ k, @2 j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 y6 T( Y5 E e* c6 ^' B3 q| MCASP_TX_CLKFAIL , d! p7 o) w6 `+ E- F1 T. Q1 a' l
| MCASP_TX_SYNCERROR
! m0 `/ l7 b& b$ p4 W! z( u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 w3 F* }" [: P8 x& Q; z
| MCASP_RX_CLKFAIL2 m s& i. r6 \* k P
| MCASP_RX_SYNCERROR 7 s& \* @! G: s( E4 l
| MCASP_RX_OVERRUN);
/ h" W" {1 G1 A& y% z7 z; ^} static void I2SDataTxRxActivate(void)
]" q' c* l' `/ k* g$ X{
( U( p% X$ u* e" X: q {/* Start the clocks */$ \5 T: o) H$ Q: ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& A8 P. f( v+ C0 L+ ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# n( b; Q" `* n' O# PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ q2 G) p4 n7 d' r
EDMA3_TRIG_MODE_EVENT);
5 Y6 ~; M* `& G, B1 h- qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + K4 z6 h1 G7 _! E! b& D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# q- I- c; f3 Y5 F% fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 b: N7 q8 `7 {$ w2 ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; W2 H' v' ?% Q% ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 c Q- s( T# r4 S; EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 J3 n. R" \3 ~. lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, _- a9 w9 [0 D- H, I0 z5 o8 A/ R
}
7 s2 Q5 v; s, \4 N! m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
# S4 m' f) S' S1 @# D) L) t9 U( r" [4 b z |