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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 @- T) I5 }6 |- U4 b9 U
input mcasp_ahclkx,
& C! H7 S4 |; `+ _% @/ Binput mcasp_aclkx,# @3 x- @8 k! Q, P$ d# [ C q5 s
input axr0," U* Y5 E: I6 C- G* @ e6 X
7 ~& ?6 h3 e3 p. K
output mcasp_afsr,# {% Z4 r8 e6 C, b! k G
output mcasp_ahclkr,
" X) _' _$ N4 P: H. ?# O8 e: q/ }6 q# loutput mcasp_aclkr,
5 ?& s9 z& m+ `+ Goutput axr1,* @( i9 ?" j, i$ m. ~7 N) q7 _
assign mcasp_afsr = mcasp_afsx;8 K( M; i( y z" Y; w, Q
assign mcasp_aclkr = mcasp_aclkx;
* ~5 Z# u# ~: B* H8 Oassign mcasp_ahclkr = mcasp_ahclkx;4 a* @9 i- a3 E9 R' g. _; P
assign axr1 = axr0; 2 \6 c; l% m! t7 V8 h
8 Q7 c! R1 c' `6 Q7 g& `; P, p" ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * ^0 M2 {+ C/ q" v7 w" U
static void McASPI2SConfigure(void)6 b6 ]9 o" O+ q' J6 W* i* r4 K! X
{/ h+ n1 l& \; m+ f5 u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" W2 a- R5 m5 D3 L2 d( s: qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
b* H1 I" Z3 r8 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# v+ g/ y' q. E5 c4 g* JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ I5 S+ d8 m5 n/ p. o0 Y1 Z( ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 N+ {- z0 D$ p. {2 E( i i% pMCASP_RX_MODE_DMA);5 f4 R6 Z$ c5 @' ?- X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, J* M; {8 j/ rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& R/ e v( ^( q& j/ t9 aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % S, Q! r" {# H' U' q" F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 u" c$ I% A4 T$ ?6 f4 F: a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : E- H2 j4 O/ G1 m/ ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ ?0 x1 N- ?5 Q4 i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ h B) Z. W t8 R* S, \7 ]7 e! o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 j3 j9 L9 s9 @& \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 u+ m/ i; I: X9 n% X9 ?0x00, 0xFF); /* configure the clock for transmitter */
1 D5 e0 q% E) u& s& k# y5 ]2 cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 d9 H6 i% ~, Q- F$ u( ]0 ~& T. s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# K+ ^8 _9 r1 n, i( bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 f7 m% n5 p, @( [
0x00, 0xFF);
1 H* `3 p+ D* _9 M+ D6 V6 ]( u; ^
3 j0 G1 D0 a9 j+ D/* Enable synchronization of RX and TX sections */
& x" o1 N0 _! JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% P# y5 A+ }( ?% }+ H: q1 F& h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# F0 k: I; n1 L/ |# F, qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 x9 ~, ]7 ^5 _. E** Set the serializers, Currently only one serializer is set as
7 S- O5 ?% q7 l+ h+ q** transmitter and one serializer as receiver.) @0 b Y# k( x% S2 e
*/
& t' T& T8 T( H0 @9 b! G; }! W, s8 O6 v% A- `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 W: H6 J! @% r( D) k6 {( L) V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ ^. m2 D% n% Q2 Q- {. a- R, W8 d** Configure the McASP pins ) b2 @0 w6 @+ u# v q
** Input - Frame Sync, Clock and Serializer Rx; h' R, O' j1 p& ]: l
** Output - Serializer Tx is connected to the input of the codec ; p* @) G6 p! k$ D- a! F/ \3 w( B
*/
/ y/ L( i5 x; Q) @8 _' ?7 h3 GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" Z" E* h4 J( j4 c/ ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 _6 i% f2 m2 S1 P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: a6 g C3 m4 b+ p2 v. g3 Y& M
| MCASP_PIN_ACLKX
! b/ c9 Q7 J3 G$ j* ~" T b* r| MCASP_PIN_AHCLKX5 o+ t( k7 p0 p$ e7 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 Q) g& ~6 x, C+ q7 \: \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / F$ [& @5 t/ E: T9 y* X, b
| MCASP_TX_CLKFAIL
4 A0 T' c" s2 G. ] W9 n3 H) l- h3 C8 [| MCASP_TX_SYNCERROR' X' p2 E ^& K$ X4 U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 q I0 s" S( q% a& }8 E+ x7 r8 M
| MCASP_RX_CLKFAIL
0 o5 a- J. y, R) y/ O3 s| MCASP_RX_SYNCERROR 4 f( k" Q7 t0 J( a
| MCASP_RX_OVERRUN);
) L9 C/ m, F8 m3 b} static void I2SDataTxRxActivate(void)! p0 ?8 l: V- ~+ X
{# r5 g: v2 ?2 @- L+ c7 R# H$ c
/* Start the clocks */
8 w3 h3 Q& Q' n$ S4 J7 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# f9 |! m. n- ^5 z" d9 k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' @5 I- U- L, \9 ^0 [5 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 i; f+ h2 Q3 G. R S) ~- lEDMA3_TRIG_MODE_EVENT);
k, c) S; l0 @2 @# h4 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 p4 `1 E8 \& \1 ~% y" VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% Y7 o( e& X, [/ E+ D: d! Z" l* BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 L. }3 y" Z! L! Z7 z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 k9 h6 `$ L6 i- D: swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 w: F, C' q% y; d, g/ q7 pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 K- a; h; T$ ?) U( SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) }. ?' q. l$ A2 }}
2 x& D0 h' X! t$ e; T# V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 ?3 v9 g% O6 t& p: i% F# I6 v9 e
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