MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
' D, ^+ y9 s9 j" \8 zinput mcasp_aclkx,
0 `7 D, K- B4 Q, o/ C  Y: H# Oinput axr0,

* X2 E; m+ U6 W, Q! E; }# u" m9 R) ]output mcasp_afsr,
3 R4 o7 y, N8 N( uoutput mcasp_ahclkr,
. K" q  ^6 {& B8 Soutput mcasp_aclkr,
output axr1,
+ G( T- S- F3 g" l) `0 x

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

- I5 D, b8 G: M5 C3 _6 z# q5 G2 l- M

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
5 L& _& f# |9 m$ g+ ~4 e" S2 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
  K4 j& F* {2 s. Y/ o7 g) r% fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
5 A: T, K' r( {+ H, e0 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( W( o3 H6 E& pMCASP_RX_MODE_DMA);
, Y4 R% [  E- O2 V, x1 iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! Z5 X, P+ x% k/ b1 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
6 c/ ]7 z% h% B* a* xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 o# K" [3 u4 _1 T4 ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ c/ |, Y6 v' `1 _/ ]$ X* c# iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
! @* D. Y9 j8 F$ aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. J; ~, k6 O3 A% c' o, {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 ^! C$ T7 _" rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
4 A+ l) d0 o7 H8 G% x0 B5 \" [
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
$ b+ {2 ]* {$ Q7 M1 P9 V*/
* P) }3 |& V8 B; ~/ WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
0 Z5 W  S: J' M$ W** Output - Serializer Tx is connected to the input of the codec
1 G: \4 f9 j4 V*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
  p2 t2 F$ x& P' sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( K$ y2 S/ F% G2 z! ~/ Z, m- \| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
; a; W9 Z4 L2 X: |  y: ?| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% a( Q6 l5 R1 ~; _# z7 W; ]* k8 K# r" t| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
4 C! c2 @' p0 ~' c| MCASP_RX_OVERRUN);
3 P+ y5 o7 K3 c$ m0 t9 P1 |% k  `* Y}

static void I2SDataTxRxActivate(void)
{
/ t- y. h* V) V" z/* Start the clocks */
/ ]& I  T: R! D4 j' q9 j& a0 c( o; VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
; v  d4 O/ X; [" _; C2 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 T% I) W7 A  C9 {3 k. ^EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
1 O7 E9 a/ |1 e( _2 f. |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
9 E2 }# Y3 `/ `4 {, d2 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" I0 y$ R) g7 ^2 K. R: vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) m0 L5 u( a1 ~- [* M7 T}

- R4 y) I) _6 s- P% l

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

0 L: r0 w3 [- F: i' m; J& W6 G